Semiconductor processing system and semiconductor processing method thereof

Abstract

The invention discloses a semiconductor processing system and a semiconductor processing method thereof, and the system comprises a semiconductor processing device which comprises a first chamber part and a second chamber part, the chamber part is provided with a groove channel which is recessed from the inner wall surface of the corresponding chamber part, a first through hole and a second through hole, the surface of the semiconductor wafer abuts against the surface of the inner wall forming the groove channel to form a closed channel; the wafer conveying device comprises a manipulator and a control device, and under the control of the control device, the manipulator carries out angle adjustment operation on the semiconductor wafer; and the driving and valve assembly is used for controlling fluid to enter the closed channel so as to process a partial region of the surface of the semiconductor wafer. As the manipulator performs angle adjustment operation on the semiconductor wafer, pollution impurities in more selected areas of the semiconductor wafer can be extracted and detected.

Description

[Technical field]

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor processing system and a semiconductor processing method thereof. [Background technology]

[0002] As the size of semiconductors continues to decrease, impurities contained in the wafer silicon material itself become a requirement that needs to be detected and monitored in quality control. However, current wafer contamination detection technology is limited to extracting and detecting impurity contamination on the wafer surface or performing destructive testing on the entire wafer material.

[0003] Chinese patents with application numbers 201210171681.9 and 201210088237.0 disclose a micro-chamber processing device for wafer processing, the micro-chamber processing device includes a first chamber part and a second chamber part, the first chamber part and the second chamber part can be relatively moved between an open position for loading and / or removing the wafer and a closed position for accommodating and processing the wafer under the drive of a driving device. When the first chamber part and the second chamber part are in the closed position, a micro-chamber is formed, the wafer is placed in the micro-chamber, and the first chamber part and / or the second chamber part include one or more inlets for the processing fluid to enter the micro-chamber and one or more outlets for the processing fluid to discharge the micro-chamber.

[0004] When the processing fluid enters the microchamber through the entrance of the microchamber to process the wafer, the direction of the processing fluid flow is generally in a fixed direction, but there is a lack of corresponding control mechanism to ensure the degree of reaction between the processing fluid and the wafer. Although the existing technology can ensure the extraction efficiency of surface pollutants when extracting and detecting wafer surface contamination as long as a sufficient reaction time is given, when extracting and detecting impurities inside the wafer material, since the liquid is required to corrode the wafer material, different reaction degrees will cause the corrosion depth of the processing fluid on the wafer surface to have a large error and be difficult to control. In this way, when the impurities inside the wafer material are detected for contamination, the processing fluid collected after the reaction can only obtain the qualitative situation of the overall impurity contamination inside the wafer material, and cannot accurately obtain the quantitative situation of impurity contamination within a given depth range inside the wafer material, and further cannot obtain the distribution of impurity contamination at different depths inside the wafer.

[0005] To this end, Chinese patent application number 201710078489.8 discloses a wafer local processing method. However, this wafer local processing method can only extract and detect contaminants in a few local areas of the wafer, and there are many areas where contaminants cannot be extracted and detected.

[0006] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. [Summary of the invention]

[0007] An object of the present invention is to provide a semiconductor processing system and a semiconductor processing method thereof, which can extract and detect contaminant impurities in more selected areas of a semiconductor wafer.

[0008] To achieve the above object, the present invention provides a semiconductor processing system, comprising:

[0009] A semiconductor processing device, comprising a first chamber portion, and a second chamber portion movable between an open position and a closed position relative to the first chamber portion, wherein when the second chamber portion is located at the closed position relative to the first chamber portion, a micro chamber is formed between the first chamber portion and the second chamber portion, and a semiconductor wafer can be accommodated in the micro chamber, and when the second chamber portion is located at the open position relative to the first chamber portion, the semiconductor wafer can be taken out or put in, the first chamber portion and / or the second chamber portion has a groove channel formed by a depression from the inner wall surface of the corresponding chamber portion, a first through hole passing through the corresponding chamber portion from the outside to communicate with the first position of the groove channel, and a second through hole passing through the corresponding chamber portion from the outside to communicate with the second position of the groove channel, when the second chamber portion is located at the closed position relative to the first chamber portion and the semiconductor wafer is accommodated between the first chamber portion and the second chamber portion, the surface of the semiconductor wafer abuts against the inner wall surface forming the groove channel, and at this time, the groove channel forms a closed channel by blocking the surface of the semiconductor wafer, and the closed channel communicates with the outside through the first through hole and the second through hole;

[0010] A wafer conveying device, comprising a robot and a control device, wherein under the control of the control device, the robot performs an angle adjustment operation on a semiconductor wafer located between a first chamber portion and a second chamber portion, wherein the angle adjustment operation comprises: picking up the semiconductor wafer located between the first chamber portion and the second chamber portion when the second chamber portion is located at the open position relative to the first chamber portion and adjusting the angle of the semiconductor wafer, re-placing the semiconductor wafer after the angle adjustment between the first chamber portion and the second chamber portion, and rotating the re-placed semiconductor wafer by a predetermined angle relative to the previously placed semiconductor wafer;

[0011] A drive and valve assembly controls the fluid to enter the closed channel through one of the first through hole and the second through hole when the second chamber portion is located at the closed position relative to the first chamber portion and the semiconductor wafer is accommodated between the first chamber portion and the second chamber portion. The fluid entering the closed channel can move along the guidance of the closed channel. At this time, the fluid can contact a partial area of ​​the surface of the semiconductor wafer. The fluid flowing through the surface of the semiconductor wafer flows out through the other through hole of the first through hole and the second through hole and is extracted.

[0012] According to another aspect of the present invention, the present invention provides a semiconductor processing method based on the semiconductor processing system described above, comprising: making the second chamber part in an open position relative to the first chamber part; under the control of the control device, the manipulator performs an angle adjustment operation on the semiconductor wafer located between the first chamber part and the second chamber part, and the angle adjustment operation includes: picking up the semiconductor wafer located between the first chamber part and the second chamber part when the second chamber part is in the open position relative to the first chamber part and adjusting the angle of the semiconductor wafer, re-placing the semiconductor wafer after the angle adjustment between the first chamber part and the second chamber part, and rotating the re-placed semiconductor wafer by a predetermined angle relative to the previously placed semiconductor wafer; making the second chamber part in a closed position relative to the first chamber part; injecting fluid into the groove channel through one of the first through hole and the second through hole, and the fluid travels along the closed channel until the other through hole of the first through hole and the second through hole, and extracting the fluid from the other through hole.

[0013] Compared with the prior art, in the present invention, since the robot can perform angle adjustment operations on the semiconductor wafer, contaminant impurities in more selected areas of the semiconductor wafer can be extracted and detected.

[0014] It should therefore be understood that this overview is provided only for the purpose of summarizing some embodiments in order to provide a basic understanding of some aspects of the present invention. Therefore, the above-described embodiments are merely examples and should not be interpreted as narrowing the scope or ideas of the present invention in any way. The features, appearances, and advantages of the various embodiments will become apparent by reading the following detailed description and the accompanying drawings, which illustrate the principles of some embodiments by way of example.

Brief Description of the Drawings

[0015] The present invention will be more easily understood with reference to the accompanying drawings and the following detailed description, wherein like reference numerals correspond to like structural components, wherein:

[0016] Figure 1a is a cross-sectional schematic diagram of a semiconductor processing device in one embodiment of the present invention;

[0017] Figure 1b for Figure 1a An enlarged schematic diagram of circle A in FIG.

[0018] Figure 1c for Figure 1a An enlarged schematic diagram of circle B in FIG.

[0019] Figure 2a is a top view of the second chamber portion in one embodiment of the present invention;

[0020] Figure 2b for Figure 2a An enlarged schematic diagram of circle C in FIG.

[0021] Figure 2c for Figure 2a An enlarged schematic diagram of circle D in FIG.

[0022] Figure 2d For along Figure 2a A schematic cross-sectional view of the section line AA in FIG.

[0023] Figure 2e for Figure 2d An enlarged schematic diagram of circle E in FIG.

[0024] Figure 2f for Figure 2a An enlarged schematic diagram of circle F in FIG.

[0025] Figure 3a is a top view of the first chamber portion in one embodiment of the present invention;

[0026] Figure 3b for Figure 3a An enlarged schematic diagram of circle G in FIG.

[0027] Figure 3c for Figure 3a An enlarged schematic diagram of circle H in FIG.

[0028] Figure 3d For along Figure 3a A schematic cross-sectional view of the section line BB in FIG.

[0029] Figure 3e for Figure 3d An enlarged schematic diagram of circle I in FIG.

[0030] Figure 3f for Figure 3a An enlarged schematic diagram of circle J in FIG.

[0031] Figure 4a is a cross-sectional schematic diagram of a semiconductor processing device in another embodiment of the present invention;

[0032] Figure 4b Figure 4aAn enlarged schematic diagram of circle K in FIG.

[0033] Figure 5a is a top view of the first chamber portion in one embodiment of the present invention;

[0034] Figure 5b For along Figure 5a A schematic cross-sectional view of the section line CC in FIG.

[0035] Figure 5c for Figure 5a An enlarged schematic diagram of circle L in FIG.

[0036] Figure 6a is a top view of the second chamber portion in another embodiment of the present invention;

[0037] Figure 6b For along Figure 6a An enlarged schematic diagram of circle M in FIG.

[0038] Figure 7 FIG. 1 is a flow chart of a semiconductor processing method in one embodiment of the present invention.

[0039] Figure 8 is a schematic structural diagram of a semiconductor processing system in another embodiment of the present invention;

[0040] Fig. 9 FIG. 4 is a flow chart of a semiconductor processing method in another embodiment of the present invention. [Specific embodiment]

[0041] Some embodiments of the present invention will be described more fully below with reference to the accompanying drawings, in which some, but not all, embodiments are listed. In fact, various embodiments of the present invention can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; on the contrary, these embodiments are provided to make the present invention thorough and complete and will fully convey the scope of the present invention to those skilled in the art. For example, unless otherwise stated, referring to something as first, second, etc. should not be construed as implying a particular order. In addition, something may be described as being higher than something (unless otherwise stated) when it is actually lower than something, and vice versa; similarly, something described as being on the left may be on the right, and vice versa. The same reference figure number always represents the same element.

[0042] The details of the present invention can be more clearly understood by combining the accompanying drawings and the description of the specific embodiments of the present invention. However, the specific embodiments of the present invention described herein are only used for the purpose of explaining the present invention and cannot be understood as limiting the present invention in any way. Under the guidance of the present invention, technicians can conceive of any possible variations based on the present invention, which should be regarded as belonging to the scope of the present invention. It should be noted that when an element is referred to as "arranged on" another element, it can be directly on another element or there can also be a central element. When an element is considered to be "connected" to another element, it can be directly connected to another element or there may be a central element at the same time. The terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a mechanical connection or an electrical connection, or it can be the internal communication of two elements, it can be directly connected, or it can be indirectly connected through an intermediate medium. For ordinary technicians in the field, the specific meanings of the above terms can be understood according to the specific circumstances. The terms "vertical", "horizontal", "up", "down", "left", "right" and similar expressions used herein are only for illustrative purposes and do not represent the only implementation method.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0044] Part I

[0045] In order to better extract and detect contaminants in the wafer, a semiconductor processing device is also proposed in the present application.

[0046] Figure 1a FIG. 1 is a schematic cross-sectional view of a semiconductor processing device 100 in one embodiment of the present invention. Figure 1b for Figure 1a An enlarged schematic diagram of circle A in FIG. Figure 1c for Figure 1a An enlarged schematic diagram of circle B in FIG. Figure 1a As shown, the semiconductor processing device 100 includes a first chamber portion 110 and a second chamber portion 120. In this embodiment, the first chamber portion 110 is a chamber portion located at the top, and the second chamber portion 120 is a chamber portion located at the bottom. In other embodiments, the bottom chamber portion may be defined as the first chamber portion, and the top chamber portion may be defined as the second chamber portion.

[0047] The first chamber portion 110 includes an upper chamber plate 111 and a first flange 112 extending downward from the periphery of the upper chamber plate. The second chamber portion 120 includes a lower chamber plate 121 and a first groove 122 recessed downward from the periphery of the lower chamber plate 121 .

[0048] The first chamber part 110 can be moved between an open position and a closed position relative to the second chamber part 120. When the first chamber part 110 is in the open position relative to the second chamber part 120, a semiconductor wafer can be placed on the inner wall surface of the second chamber part 120, or the semiconductor wafer can be taken out from the inner wall surface of the second chamber part 120. When the first chamber part 110 is in the closed position relative to the second chamber part 120, the first flange 112 cooperates with the first groove 122 to form a sealed micro chamber between the upper chamber plate and the lower chamber plate, and the semiconductor wafer can be accommodated in the micro chamber to wait for subsequent processing.

[0049] Figure 2a FIG. 1 is a top view of the second chamber portion 120 in one embodiment of the present invention. Figure 2b for Figure 2a An enlarged schematic diagram of circle C in FIG. Figure 2c for Figure 2a An enlarged schematic diagram of circle D in FIG. Figure 2d For along Figure 2a Schematic diagram of the cross-sectional view of section line AA. Figure 2e for Figure 2d An enlarged schematic diagram of circle E in FIG. Figure 2f for Figure 2a An enlarged schematic diagram of circle F in FIG.

[0050] Combination Figure 2a-2f As shown, the second chamber portion 120 has a groove channel 124 formed by a depression from the inner wall surface 123 of the second chamber portion 120 facing the micro chamber, a first through hole 125 passing through the second chamber portion from the outside to communicate with the first position of the groove channel 124, and a second through hole 126 passing through the second chamber portion from the outside to communicate with the second position of the groove channel 124. The cross section of the groove channel 124 can be U-shaped, V-shaped or semicircular, and can also be other shapes. The number of through holes in the groove channel 124 can be greater than or equal to 1.

[0051] like Figure 1a , 1bAs shown in FIG. 1c, when the first chamber portion 110 is located at the closed position relative to the second chamber portion 120 and the semiconductor wafer 200 is accommodated in the microchamber, one surface (lower surface) of the semiconductor wafer 200 abuts against the inner wall surface 123 forming the groove channel 124. At this time, the groove channel 124 forms a closed channel by blocking the surface of the semiconductor wafer 200. The closed channel communicates with the outside through the first through hole 125 and the second through hole 126. When used, the processing fluid can enter the closed channel through the first through hole 125, and the fluid entering the closed channel can move forward along the guidance of the closed channel. At this time, the processing fluid can contact and process a partial area of ​​the surface of the semiconductor wafer 200, and the fluid that has processed the surface of the semiconductor wafer 200 can flow out through the second through hole 126 and be extracted. In this way, not only can the flow direction and flow speed of the processing fluid be accurately controlled, but also the amount of processing fluid can be greatly saved.

[0052] In one embodiment, Figure 2a , 2b As shown in Figures 2 and 2c, the groove 124 is spirally formed, wherein the first through hole 125 is located in the central area of ​​the spiral groove (the area of ​​circle D), and the second through hole 126 is located in the peripheral area of ​​the spiral groove 124 (the area of ​​circle C). The first through hole 125 can be used as an entrance, and the second through hole 126 can be used as an exit. In other embodiments, the first through hole 125 can also be used as an exit, and the second through hole 126 can be used as an entrance.

[0053] In one embodiment, Figure 2d , 2e As shown in Figures 2 and 2f, the first through hole 125 includes a first buffer port 125a that is directly connected to the groove channel 124 and is deeper and wider than the groove channel 124, and a first through hole portion 125b that is directly connected to the first buffer port 125a. Due to the provision of the first buffer port 125a, it is possible to avoid the central area of ​​the semiconductor wafer being over-processed due to the excessive initial velocity of the processing fluid entering through the first through hole 125. The second through hole 126 includes a second buffer port 126a that is directly connected to the groove channel 124 and is deeper and wider than the groove channel 124, and a second through hole portion 126b that is directly connected to the second buffer port 126a. Due to the provision of the second buffer port 126a, it is possible to prevent the processing fluid from being unable to be discharged from the second through hole 126 in time and overflowing. Preferably, the first buffer port 125a can be a conical groove, and the second buffer port 126a can be a cylindrical groove.

[0054] Figure 3ais a top view of the first chamber portion 110 in one embodiment of the present invention; Figure 3b for Figure 3a An enlarged schematic diagram of circle G in FIG. Figure 3c for Figure 3a An enlarged schematic diagram of circle H in FIG. Figure 3d For along Figure 3a A schematic cross-sectional view of the section line BB in FIG. Figure 3e for Figure 3d An enlarged schematic diagram of circle I in FIG. Figure 3f for Figure 3a An enlarged schematic diagram of circle J in FIG.

[0055] Combination Figures 3a to 3f As shown, the first chamber portion 110 includes an upper chamber plate 111 and a first flange 112 extending downward from the periphery of the upper chamber plate 111. The first chamber portion 110 has a groove channel 113 formed by being recessed from an inner wall surface 113 of the first chamber portion facing the micro chamber, and the groove wall of the groove channel 114 formed on the inner wall surface 113 of the first chamber portion (the portion between adjacent groove channels 114) corresponds to the groove wall of the groove channel 124 formed on the inner wall surface 123 of the second chamber portion 120 (the portion between adjacent groove channels 124). Figure 1b , Figure 1c ). In this way, when the first chamber portion 110 is located at the closed position relative to the second chamber portion 120 and the semiconductor wafer 200 is accommodated in the microchamber, the groove wall of the groove channel 114 of the first chamber portion 110 can press against the corresponding position of the semiconductor wafer 200, and enable the semiconductor wafer 200 to be more tightly pressed against the groove wall of the groove channel 124 of the second chamber portion 120, so that the sealing performance of the finally formed closed channel is better. In addition, the groove wall of the groove channel 114 formed on the inner wall surface 113 of the first chamber portion (the portion between adjacent groove channels 114) and the groove wall of the groove channel 124 formed on the inner wall surface 123 of the second chamber portion 120 (the portion between adjacent groove channels 124) can also be arranged in an interlaced manner.

[0056] In another modified embodiment, the structures of the first chamber part 110 and the second chamber part can be interchangeable or have the same structure, in which case the upper surface of the semiconductor wafer 200 will form a closed channel together with the groove of the first chamber part 110. The processing fluid flowing in the closed channel can process the upper surface or the lower surface of the semiconductor wafer 200, or process the upper and lower surfaces simultaneously.

[0057] Figure 4a is a cross-sectional schematic diagram of another embodiment 200 of a semiconductor processing device according to the present invention; Figure 4b Figure 4aFIG. 4 is an enlarged schematic diagram of circle K in FIG. As shown in FIG. 4a , the semiconductor processing device 400 and Figure 1a The difference compared with the semiconductor processing equipment in the Figure 4a The first chamber portion 410 and Figure 1a The structure of the first chamber portion 110 is different. Figure 5a FIG. 4 is a top view of the first chamber portion 410 in one embodiment of the present invention; Figure 5b For along Figure 5a A schematic cross-sectional view of the section line CC in FIG. Figure 5c for Figure 5a An enlarged schematic diagram of circle L in FIG. Figures 5a to 5c As shown, the first chamber part 410 includes an upper chamber plate 411, a first flange 412, a first inner wall surface 413 facing the micro chamber, a second groove 414, a second flange 415 located between the first inner wall surface 413 and the second groove 414, and a channel 416 located at the center of the first inner wall surface 413. The second flange 415 abuts against the semiconductor wafer 200 and the first inner wall surface 413 to form a closed space, which is connected to the outside through the channel 416. Fluid can enter this closed space through the channel 416 to generate pressure, and enable the semiconductor wafer 200 to abut more tightly against the groove wall of the groove channel 124 of the second chamber part 120, so that the sealing performance of the finally formed closed channel is better.

[0058] Figure 6a is a top view of the second chamber portion in another embodiment 620 of the present invention; Figure 6b For along Figure 6a The enlarged schematic diagram of the circle M in FIG. There are multiple grooves 624 formed by the inner wall surface 623 of the second chamber portion 620 facing the micro chamber. Figure 6a There are five grooves 624, and in other embodiments, there may be other numbers, and each groove channel 624 corresponds to a first through hole 625 and a second through hole 626. Different groove channels 624 of the second chamber portion 620 are located in different areas of the inner wall surface 623. In this way, different treatments can be performed on different areas, and they are independent of each other.

[0059] The present invention also provides a semiconductor processing method using the semiconductor processing device. Figure 7 As shown, the semiconductor processing method 700 includes the following steps.

[0060] Step 710, placing the second chamber portion 120 in an open position relative to the first chamber portion 110;

[0061] Step 720 , placing the semiconductor wafer between the second chamber portion 120 and the second chamber portion 110 ;

[0062] Step 730 , placing the second chamber portion 120 in a closed position relative to the first chamber portion 110 ;

[0063] Step 740, injecting fluid into the groove channel 124 through the first through hole 125;

[0064] Step 750 , driving the fluid to travel along the closed channel until reaching the second through hole 126 ;

[0065] In step 760 , the fluid is extracted from the second through hole 126 .

[0066] In one embodiment, element detection may be performed based on the extracted fluid, so that the elements remaining on the surface of the semiconductor wafer and their concentrations may be obtained.

[0067] In one embodiment, the fluid is a liquid or a gas, and the fluid is a reaction fluid or an extraction fluid. The reaction fluid can react with the surface of the semiconductor wafer in contact with it. The extraction fluid can extract contaminants from the surface of the semiconductor wafer in contact with it.

[0068] The fluid may be driven to move in the closed channel by a driving fluid, or by air pressure, such as vacuum pump, to drive the fluid to move in the closed channel. The driving fluid is an ultrapure gas or ultrapure liquid that is not easy to react, such as nitrogen, helium, argon, ultrapure water, acetone, tetrachloromethane, etc.

[0069] In another embodiment, the first through hole 125 may also serve as a fluid outlet, and the second through hole 126 may serve as a fluid inlet.

[0070] Part 2

[0071] Figure 8 FIG. 6 is a schematic diagram of the structure of a semiconductor processing system 600 in another embodiment of the present invention. Figure 8 As shown, the semiconductor processing system 600 includes a semiconductor processing device 810 , a wafer transfer device 820 , and a drive and valve assembly 830 .

[0072] The semiconductor processing device 810 may be the semiconductor processing device described in the above embodiments. Figure 6a shown.

[0073] The wafer conveying device 820 includes a robot and a control device. Under the control of the control device, the robot can perform an angle adjustment operation on the semiconductor wafer located between the first chamber part and the second chamber part. The angle adjustment operation includes: picking up the semiconductor wafer located between the first chamber part and the second chamber part when the second chamber part is located at the open position relative to the first chamber part and adjusting the angle of the semiconductor wafer, re-placing the semiconductor wafer after the angle adjustment between the first chamber part and the second chamber part, and rotating the re-placed semiconductor wafer by a predetermined angle relative to the previously placed semiconductor wafer.

[0074] The drive and valve assembly 830 controls the fluid to enter the closed channel through one of the first through hole and the second through hole when the second chamber portion is located in the closed position relative to the first chamber portion and the semiconductor wafer is accommodated between the first chamber portion and the second chamber portion. The fluid entering the closed channel can move along the guidance of the closed channel. At this time, the fluid can contact a partial area of ​​the surface of the semiconductor wafer. The fluid flowing through the surface of the semiconductor wafer flows out through the other through hole of the first through hole and the second through hole and is extracted.

[0075] In one embodiment, there are multiple grooves, each of which corresponds to a first through hole and a second through hole, and different grooves are located in different areas of the inner wall surface, wherein the center of at least one groove is spaced a predetermined distance from the center of the inner wall surface where the at least one groove is located. More specifically, the centers of multiple grooves are spaced a predetermined distance from the center of the inner wall surface where the multiple grooves are evenly distributed around the center of the inner wall surface where the multiple grooves are located, and the center of one groove coincides with the center of the inner wall surface where the other groove is located. Specifically, as Figure 6a and 6b As shown, there are five grooves 624, namely 6241, 6242, 6243, 6244 and 6245. The centers of the grooves 6241, 6242, 6244 and 6245 are spaced a predetermined distance from the center of the inner wall surface where they are located. The center of the groove 6243 coincides with the center of the inner wall surface where the groove is located.

[0076] In another embodiment, the groove may be one, the center of which is spaced a predetermined distance from the center of the inner wall surface, and the groove is located in a local area of ​​the inner wall surface. Figure 6a and 6b As shown, in a modified embodiment, only one of the five groove tracks 624 may be retained, such as retaining any one of the groove tracks 6241 , 6242 , 6244 , and 6245 .

[0077] Combination Figure 6aAs shown, after the manipulator performs an angle adjustment operation on the semiconductor wafer located between the first chamber part and the second chamber part, the areas on the semiconductor wafer corresponding to the grooves 6241, 6242, 6244 and 6245 will change. For example, the control device sets the predetermined angle to 45 degrees, then after the manipulator performs an angle adjustment operation on the semiconductor wafer located between the first chamber part and the second chamber part, the grooves 6241, 6242, 6244 and 6245 respectively correspond to the areas after the semiconductor wafer rotates 45 degrees along the center. At this time, the grooves 6241, 6242, 6244 and 6245 are used again to extract and detect contaminated impurities on the surface of the semiconductor wafer, so that more selected areas (even any areas) of the semiconductor wafer can be extracted and detected as needed.

[0078] Obviously, the control device can set the predetermined angle as needed. The predetermined angle can be any angle, for example, the predetermined angle can be 2 degrees, 5 degrees, 45 degrees, 135 degrees, etc. In one embodiment, under the control of the control device, the robot can perform multiple angle adjustment operations on the semiconductor wafer located between the first chamber part and the second chamber part. For example, if Figure 6a In the second chamber part, there is only the groove channel 6241, and the predetermined angle can be set to 45 degrees. By repeating the angle adjustment operation 8 times, the groove channel 6241 can traverse all peripheral areas of the semiconductor wafer. After each angle adjustment operation, the drive and valve assembly 830 uses the groove channel 6241 to perform a fluid extraction and detection, so that the fluid is processed on different selected areas of the semiconductor wafer using one groove channel 6241. In addition, if the area of ​​the groove channel 6241 is small, the predetermined angle can be reduced, such as 10 degrees, so that the groove channel 6241 can traverse all peripheral areas of the semiconductor wafer. In other embodiments, the groove channel may not traverse all areas of the semiconductor wafer.

[0079] In one embodiment, under the control of the control device, the robot also performs a semiconductor wafer loading operation, and the semiconductor wafer loading operation includes: the robot picks up a semiconductor wafer from the outside (such as an external wafer box), and places the semiconductor wafer between the first chamber part and the second chamber part when the second chamber part is located in the open position relative to the first chamber part; under the control of the control device, the robot also performs a semiconductor wafer unloading operation, and the semiconductor wafer unloading operation includes: when the second chamber part is located in the open position relative to the first chamber part, the robot picks up the semiconductor wafer in the semiconductor processing device and places it outside (such as an external wafer box).

[0080] In one embodiment, different semiconductor wafers can be placed in the micro-chamber at different angles by a robot, and the same groove corresponds to different areas of the different semiconductor wafers. When processing each semiconductor wafer, the drive and valve assembly drives the fluid to flow through each groove and extract it. The detection data of each semiconductor wafer is obtained based on the extracted fluid, and the uniformity detection data of the semiconductor wafer is obtained by integrating the detection data of different semiconductor wafers. Specifically, Figure 6a Taking the second chamber part shown as an example, the same batch of semiconductor wafers are processed, and the first part of the semiconductor wafers are placed in the semiconductor processing device at the same angle in turn for contamination impurity extraction and detection, and the second part of the semiconductor wafers are rotated 45 degrees and placed in the semiconductor processing device in turn for contamination impurity extraction and detection. The uniformity detection data of this batch of semiconductor wafers can be obtained by combining the detection data of the first part of the semiconductor wafers and the detection data of the second part of the semiconductor wafers. This can reduce the extraction area of ​​each semiconductor wafer by nearly 1 half, but the detection data of more than 2 semiconductor wafers can be combined to obtain the uniformity detection data.

[0081] In one embodiment, a plurality of grooves are selected, and when a semiconductor wafer is processed, the drive and valve assembly drives the same fluid to flow through the selected plurality of grooves in sequence. Figure 6a Taking the second chamber portion shown as an example, groove channels 6241, 6243, and 6244 are selected for extraction and detection of contaminated impurities, and the drive and valve assembly can drive the same fluid to flow through the selected multiple groove channels 6241, 6243, and 6244 in sequence. Specifically, after the fluid flows out of groove channel 6241, it is driven to groove channel 6243 again, and then after flowing out of groove channel 6243, it is driven to groove channel 6244 again, and finally the fluid is extracted and detected to obtain detection data. In this way, the same fluid can flow through more and selected surface areas of the semiconductor wafer, improve the detection accuracy and detection rate, and provide more options.

[0082] In another embodiment, at least one of the plurality of groove channels is selected, and when processing different semiconductor wafers, the drive and valve assembly drives the same fluid to repeatedly flow through the selected at least one groove channel. Figure 6aTaking the second chamber portion shown as an example, the groove channel 6241 is selected, and then the drive and valve assembly drives the same fluid to flow through the groove channel 6241 to extract contaminated impurities from the first semiconductor wafer, and then replaces it with the second semiconductor wafer, and uses the same fluid to flow through the groove channel 6241 again to extract contaminated impurities from the second semiconductor wafer, and then replaces it with the third semiconductor wafer, and uses the same fluid to flow through the groove channel 6241 again to extract contaminated impurities from the third semiconductor wafer, and repeats this process, and the fluid finally obtained is tested to obtain test data. In this way, the same area of ​​different semiconductor wafers can be repeatedly tested to improve the detection accuracy and detection rate.

[0083] In another embodiment, the above-mentioned extraction and detection schemes may also be mixed.

[0084] Fig. 9 The figure is a flow chart of another embodiment of a semiconductor processing method based on the semiconductor processing system of the present invention. The semiconductor processing method comprises the following steps.

[0085] Step 910, bringing the second chamber portion into an open position relative to the first chamber portion;

[0086] Step 920, under the control of the control device, the robot performs an angle adjustment operation on the semiconductor wafer located between the first chamber part and the second chamber part, the angle adjustment operation comprising: picking up the semiconductor wafer located between the first chamber part and the second chamber part when the second chamber part is located at the open position relative to the first chamber part and adjusting the angle of the semiconductor wafer, re-placing the semiconductor wafer after the angle adjustment between the first chamber part and the second chamber part, and rotating the re-placed semiconductor wafer by a predetermined angle relative to the previously placed semiconductor wafer;

[0087] Step 930, bringing the second chamber portion into a closed position relative to the first chamber portion;

[0088] Step 940 , injecting a fluid into the groove channel through one of the first through hole and the second through hole, the fluid traveling along the closed channel to the other through hole of the first through hole and the second through hole, and extracting the fluid from the other through hole.

[0089] In one embodiment, the semiconductor processing method further includes: under the control of the control device, the robot also performs a semiconductor wafer loading operation, and the semiconductor wafer loading operation includes: the robot picks up an external semiconductor wafer and places the semiconductor wafer between the first chamber part and the second chamber part when the second chamber part is located in the open position relative to the first chamber part; under the control of the control device, the robot also performs a semiconductor wafer unloading operation, and the semiconductor wafer unloading operation includes: when the second chamber part is located in the open position relative to the first chamber part, the robot picks up the semiconductor wafer in the semiconductor processing device and places it outside.

[0090] For the same contents of the semiconductor processing method and the semiconductor processing system, please refer to the introduction of the semiconductor processing system, which will not be repeated here.

[0091] The above description is intended to be illustrative rather than restrictive. Although the present invention has been described with reference to specific illustrative examples, it should be understood that the present invention is not limited to the described embodiments. The scope of the present invention should be determined with reference to the claims and the full scope of equivalents authorized by the claims.

[0092] "An example (embodiment)" or "an example (embodiment)" referred to herein means that the specific features, structures or characteristics related to the embodiment may be included in at least one implementation of the present invention. The "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor does it necessarily refer to a separate or selected embodiment that is mutually exclusive with other embodiments. "Multiple" and "several" in the present invention mean two or more. "And / or" in the present invention means "and" or "or". In addition, the terms "first", "second", "third", "fourth", etc. used here are intended to be used as labels to distinguish different elements, and may not necessarily have sequential meanings according to their numerical designations. Therefore, the terms used here are only used for the purpose of describing specific implementations and are not intended to be limiting.

[0093] It should also be noted that in some alternative embodiments, the functions / actions noted may not occur in the order noted in the figures. For example, two figures shown in succession may actually be performed substantially simultaneously or may sometimes be performed in reverse order, depending on the functions / actions involved.

[0094] Although the method operations are described in a particular order, it should be understood that other operations may be performed between the operations described. The described operations may be adjusted so that they occur at slightly different times, or the described operations may be distributed throughout the system. The system allows multiple unrelated programs to be processed simultaneously.

[0095] Many modifications and other implementations of the present invention involve those skilled in the art who have relevant industry knowledge and some original data. Therefore, it should be understood that the present invention is not limited to the specific embodiments disclosed, but also includes other embodiments modified within the scope of the attached claims. In addition, although the foregoing description and related drawings describe the implementation of specific embodiment combinations of elements and functions, within the scope of the attached claims, elements and functions that are implemented in different combinations by substitution are also included. The attached claims also include combinations of elements and functions that are different from the elements and functions explicitly described above. Although specific terms are used herein, they are intended to be generally descriptive only and are not used for limiting purposes.

Claims

1. A semiconductor processing system, characterized in that: It includes: A semiconductor processing device, comprising a first chamber portion, and a second chamber portion movable between an open position and a closed position relative to the first chamber portion, wherein when the second chamber portion is located at the closed position relative to the first chamber portion, a micro chamber is formed between the first chamber portion and the second chamber portion, and a semiconductor wafer can be accommodated in the micro chamber, and when the second chamber portion is located at the open position relative to the first chamber portion, the semiconductor wafer can be taken out or put in, the first chamber portion and / or the second chamber portion has a groove channel formed by a depression from the inner wall surface of the corresponding chamber portion, a first through hole passing through the corresponding chamber portion from the outside to communicate with the first position of the groove channel, and a second through hole passing through the corresponding chamber portion from the outside to communicate with the second position of the groove channel, when the second chamber portion is located at the closed position relative to the first chamber portion and the semiconductor wafer is accommodated between the first chamber portion and the second chamber portion, the surface of the semiconductor wafer abuts against the inner wall surface forming the groove channel, and at this time, the groove channel forms a closed channel by blocking the surface of the semiconductor wafer, and the closed channel communicates with the outside through the first through hole and the second through hole; A wafer conveying device, comprising a robot and a control device, wherein under the control of the control device, the robot performs an angle adjustment operation on a semiconductor wafer located between a first chamber portion and a second chamber portion, wherein the angle adjustment operation comprises: picking up the semiconductor wafer located between the first chamber portion and the second chamber portion when the second chamber portion is located at the open position relative to the first chamber portion and adjusting the angle of the semiconductor wafer, re-placing the semiconductor wafer after the angle adjustment between the first chamber portion and the second chamber portion, and rotating the re-placed semiconductor wafer by a predetermined angle relative to the previously placed semiconductor wafer; A drive and valve assembly controls the fluid to enter the closed channel through one of the first through hole and the second through hole when the second chamber portion is located at the closed position relative to the first chamber portion and the semiconductor wafer is accommodated between the first chamber portion and the second chamber portion. The fluid entering the closed channel can move along the guidance of the closed channel. At this time, the fluid can contact a partial area of ​​the surface of the semiconductor wafer. The fluid flowing through the surface of the semiconductor wafer flows out through the other through hole of the first through hole and the second through hole and is extracted.

2. The semiconductor processing system according to claim 1, wherein: There is one groove, the center of which is spaced a predetermined distance from the center of the inner wall surface, and the groove is located in a local area of ​​the inner wall surface; or There are multiple grooves, each of which corresponds to a first through hole and a second through hole. Different grooves are located in different areas of the inner wall surface, and the center of at least one groove is separated from the center of the inner wall surface where the at least one groove is located by a predetermined distance.

3. The semiconductor processing system according to claim 2, characterized in that The centers of the plurality of grooves are spaced a predetermined distance from the center of the inner wall surface, wherein the plurality of grooves are evenly distributed around the center of the inner wall surface. The center of one groove track coincides with the center of the inner wall surface where the groove track is located.

4. The semiconductor processing device according to claim 2, wherein: Each groove track is spirally formed, wherein the first through hole is located in the central area of ​​the spiral groove track, and the second through hole is located in the peripheral area of ​​the spiral groove track.

5. The semiconductor processing system according to claim 1, wherein: Under the control of the control device, the robot also performs a semiconductor wafer loading operation, the semiconductor wafer loading operation comprising: the robot picks up an external semiconductor wafer and places the semiconductor wafer between the first chamber part and the second chamber part when the second chamber part is located at the open position relative to the first chamber part; Under the control of the control device, the robot also performs a semiconductor wafer unloading operation, and the semiconductor wafer unloading operation includes: when the second chamber part is located at the open position relative to the first chamber part, the robot picks up the semiconductor wafer in the semiconductor processing device and places it outside.

6. The semiconductor processing system according to claim 1, wherein: The control device is capable of setting the predetermined angle, Under the control of the control device, the robot performs one or more angle adjustment operations on the semiconductor wafer located between the first chamber part and the second chamber part.

7. The semiconductor processing system according to claim 2, wherein: Different semiconductor wafers are placed in the micro-chamber at different angles by a robot, and the same groove corresponds to different areas of the different semiconductor wafers. When processing each semiconductor wafer, the drive and valve assembly drives the fluid to flow through each groove channel and extract it, and obtains the detection data of each semiconductor wafer based on the extracted fluid, and obtains the uniformity detection data of the semiconductor wafer by combining the detection data of different semiconductor wafers.

8. The semiconductor processing system according to claim 2, wherein: Selecting a plurality of groove channels, wherein the drive and valve assembly drives the same fluid to flow through the selected plurality of groove channels in sequence when processing a semiconductor wafer; or At least one of the plurality of groove channels is selected, and when processing different semiconductor wafers, the drive and valve assembly drives the same fluid to flow through the selected at least one groove channel repeatedly.

9. The semiconductor processing system according to claim 1, wherein: The fluid is a liquid or a gas, the fluid is a reaction fluid or an extraction fluid, The reactive fluid is capable of reacting with the surface of the semiconductor wafer in contact with it, The extraction fluid is capable of extracting contaminants from the surface of the semiconductor wafer with which it comes into contact.

10. A semiconductor processing method based on the semiconductor processing system according to any one of claims 1 to 9, characterized in that: It includes: causing the second chamber portion to be in an open position relative to the first chamber portion; Under the control of the control device, the robot performs an angle adjustment operation on the semiconductor wafer located between the first chamber part and the second chamber part, and the angle adjustment operation includes: picking up the semiconductor wafer located between the first chamber part and the second chamber part when the second chamber part is located at the open position relative to the first chamber part and adjusting the angle of the semiconductor wafer, re-placing the semiconductor wafer after the angle adjustment between the first chamber part and the second chamber part, and rotating the re-placed semiconductor wafer by a predetermined angle relative to the previously placed semiconductor wafer; bringing the second chamber portion into a closed position relative to the first chamber portion; A fluid is injected into the recessed channel through one of the first through hole and the second through hole, and the fluid travels along the closed channel to the other through hole of the first through hole and the second through hole, from which the fluid is extracted.

11. The semiconductor processing method according to claim 10, characterized in that: It also includes: Under the control of the control device, the robot also performs a semiconductor wafer loading operation, the semiconductor wafer loading operation comprising: the robot picks up an external semiconductor wafer and places the semiconductor wafer between the first chamber part and the second chamber part when the second chamber part is located at the open position relative to the first chamber part; Under the control of the control device, the robot also performs a semiconductor wafer unloading operation, and the semiconductor wafer unloading operation includes: when the second chamber part is located at the open position relative to the first chamber part, the robot picks up the semiconductor wafer in the semiconductor processing device and places it outside.

Images