Method of manufacturing semiconductor device

Abstract

A low thermal budget dielectric material deposition process is provided. The dielectric material may be deposited using spin coating and treated with microwave plasma treatment. In some embodiments, a dielectric material is used adjacent to a contact feature of the CFET device, such as a contact feature that provides a connection to a source / drain region of a bottom transistor of the CFET device. The embodiment of the invention also relates to a method for manufacturing the semiconductor device.

Description

Technical Field

[0001] Embodiments of the present application relate to methods of manufacturing semiconductor devices. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, each with smaller and more complex circuits than the previous generation. In the course of IC development, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs. Such shrinking has also increased the complexity of processing and manufacturing ICs.

[0003] For example, semiconductor manufacturing inevitably involves depositing dielectric materials. In some instances, such dielectric materials are deposited in high aspect ratio regions. And in some instances, such dielectric materials must be etched back or planarized after deposition. For device performance and also for uniformity of subsequent processing, it is desirable to increase the quality of dielectric materials. Although methods of forming dielectric materials are suitable in some aspects, improvements in dielectric quality and / or ease of formation are desirable. Summary of the invention

[0004] Some embodiments of the present application provide a method for manufacturing a semiconductor device, comprising: providing a semiconductor structure; depositing a dielectric material over the semiconductor structure; treating the dielectric material with microwave (MW) plasma; and after the treatment, removing a portion of the treated dielectric material.

[0005] Other embodiments of the present application provide a method for manufacturing a semiconductor device, comprising: receiving a device including at least one metal component disposed on a substrate; forming a trench above the substrate, wherein the trench has a depth-to-width aspect ratio greater than 1; using a spin-on deposition process to provide a dielectric material above the substrate and within the trench; and performing microwave (MW) processing of the dielectric material.

[0006] Still other embodiments of the present application provide a method for manufacturing a semiconductor device, comprising: forming a first transistor of a transistor stack on a substrate; forming a second transistor of the transistor stack, wherein the second transistor is disposed above the first transistor; etching an opening extending through a dielectric layer disposed on the substrate, wherein the opening extends vertically adjacent to the first transistor and the second transistor; filling the opening with a conductive material; etching back the conductive material to form another opening; using spin coating deposition to fill the other opening with a dielectric material; and treating the dielectric material with microwave plasma treatment. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The disclosed embodiments are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustration purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 A flow chart illustrating an embodiment of a method of forming a dielectric material according to one or more aspects of the embodiments of the present disclosure is shown.

[0009] Figure 2 A partial top view of a complementary field effect transistor (CFET) 200 having a gate-all-around structure is shown according to one or more aspects of the embodiments of the present disclosure.

[0010] Figures 3 to 18 Each shows a partial cross-sectional view of a device 200 along respective cross-sectional cutting lines according to one or more aspects of an embodiment of the present disclosure.

[0011] Figures 19 to 26 A partial cross-sectional view of another device 2300 according to one or more aspects of an embodiment of the present disclosure is shown.

[0012] Fig. 27 A partial cross-sectional view of a device 3100 according to one or more aspects of an embodiment of the present disclosure is shown.

[0013] Fig.28 and Fig.29 The chemical structures of embodiments of dielectric materials before and after plasma treatment according to various aspects of embodiments of the present disclosure are shown. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0015] For ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0016] In addition, when "about," "approximately," or the like is used to describe a numerical value or a range of numerical values, as understood by one of ordinary skill in the art, the term is intended to encompass numerical values ​​within a reasonable range that takes into account variations that inherently occur during manufacturing. For example, based on known manufacturing tolerances associated with manufacturing components having properties associated with the numerical values, the numerical value or range of numerical values ​​encompasses a reasonable range that includes the described numerical value, such as within + / - 10% of the described numerical value. For example, a material layer having a thickness of "about 5 nm" may include a size range from 4.25 nm to 5.75 nm, where the manufacturing tolerance associated with the deposited material layer known to one of ordinary skill in the art is + / - 15%. Further, the disclosed embodiments may repeat reference numerals and / or characters in various instances. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0017] Dielectric materials are used for various isolation features in semiconductor devices. One semiconductor device that commonly implements dielectric materials is a stacked multi-gate device, where a top multi-gate device is disposed above a bottom multi-gate device. When the top multi-gate device and the bottom multi-gate device have different conductivity types, the stacked multi-gate device can be a complementary field effect transistor (CFET). The formation of some dielectric isolation features in the stacked multi-gate device can occur after the formation of the metal gate or metal interconnect.

[0018] After the dielectric material is deposited, some processes may implement an annealing process to improve the quality and / or density of the dielectric material. Annealing may be performed at elevated temperatures. Annealing processes (including exposure to high temperatures) may pose risks to the performance or integrity of other components of the device (such as metal gate structures and metal lines). In some instances, annealing may cause undesirable threshold voltage shifts or on-state current degradation. Therefore, there may be processes and devices that can benefit from dielectric materials formed in methods that provide dielectric materials with low thermal budgets.

[0019] The present disclosure provides a method for forming a dielectric material for use in a semiconductor device such as a CFET. However, the present disclosure is not limited thereto. Those skilled in the art will recognize that various aspects of the present disclosure are also applicable to the formation of dielectric materials in other device types.

[0020] In an exemplary process, the dielectric material is deposited by spin coating deposition. After the spin coating deposition, a microwave treatment process is performed. These steps can be performed at low process temperatures, reducing the risk to existing structures (including metal gate structures). In addition, the method forms a dielectric layer with uniform quality (e.g., no seams) and high density.

[0021] Figure 1 1 is a flow chart illustrating a method 100 for forming a dielectric layer. The method 100 is merely an example and is not intended to limit the disclosed embodiments to those explicitly shown in the method 100. Additional steps may be provided before, during, and after the method 100, and some of the steps described may be replaced, eliminated, or moved around for additional embodiments of the method. For the sake of simplicity, not all steps are described in detail herein. The method 100 may be used to Figures 2 to 27 In the process described in Figures 2 to 27 200, 2300, or 3100 at different stages of manufacture. It should be noted that although device 200, device 2300, and device 3100 include some different reference numerals, they may be the same workpiece or different regions of the same workpiece. In addition, throughout this application, the same reference numerals represent the same components unless otherwise specified.

[0022] The method 100 includes a block 102, in which a substrate is provided. The substrate may include: an elemental (single element) semiconductor, such as silicon (Si), germanium (Ge), and / or other suitable materials; a compound semiconductor (i.e., an alloy semiconductor), such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), gallium indium arsenide phosphide (GaInAsP), and / or other suitable materials. The substrate may be a single layer of material having a uniform composition. Alternatively, the substrate may include multiple material layers having similar or different compositions suitable for IC device manufacturing. In one example, the substrate may be a silicon-on-insulator (SOI) substrate having a silicon layer formed on a buried silicon oxide (BOX) layer. In some embodiments, the substrate includes various doped regions, such as an n-type well or a p-type well. The doped region may be doped with an n-type dopant (such as phosphorus (P) or arsenic (As)) and / or a p-type dopant (such as boron (B) or BF2), depending on design requirements. The doped region may be formed by implantation of dopant atoms, in-situ doping epitaxial growth, and / or other suitable techniques.

[0023] The substrate of block 102 may include various semiconductor devices or portions thereof at various stages of fabrication. Some components that have been formed in whole or in part on the substrate may include, for example, active regions, dielectric isolation components, metal gate structures, dielectric gate spacers, contact structures, epitaxial source / drain components, contact structures, and / or other components. In an embodiment, at least one metal component (e.g., a metal gate structure) is provided on the substrate prior to implementing blocks 106 and 108 of method 100 discussed below.

[0024] In block 104, an area where a dielectric material is to be deposited is defined or prepared. The area may have an aspect ratio (height: width) greater than 1:1. In an embodiment, the area may have an aspect ratio greater than 4. In some embodiments, the area may be located between metal lines or vias, such as between contact elements. In some embodiments, the area may be adjacent to other conductive features, such as a gate structure or a source / drain feature.

[0025] In block 106 of method 100, a dielectric layer is deposited over the substrate and within the region defined in block 104. In an embodiment, the dielectric layer includes a dielectric material including silicon (Si) and oxygen (O). The dielectric layer may also include additional elements such as carbon (C) and / or hydrogen (H).

[0026] Exemplary dielectric materials for forming the dielectric layer include the following materials in Table 1:

[0027]

[0028]

[0029] Or a combination thereof. In some embodiments, two, three, four, or more of the materials in Table 1 may be provided together to form the dielectric material deposited in block 106. In an embodiment, the dielectric materials of Table 1 are present in a material provided in preparation for deposition and / or when deposited (e.g., deposited by spin coating). However, after deposition, in some embodiments, the dielectric material may become SiO or SiOC with a varying composition, including SiOC having an atomic percentage of carbon greater than 0% and less than 30%. In an embodiment, the atomic percentage of carbon is provided after a baking process.

[0030] The deposition of frame 106 can be implemented by a spin coating deposition process also known as spin coating. The spin coating deposition process may include a first step of deposition of a dielectric material, such as discussed above. In some embodiments, the dielectric material is accompanied by a solvent, which then evaporates. Then, the spin coating deposition includes spinning up to a desired rotation speed, and spinning off. The spin coating deposition also includes evaporation of the solvent. The spin coating deposition can be implemented at a speed of about 1000 and 8000 revolutions per minute (rpm). The spin coating deposition can be implemented for about 30 seconds to about 60 seconds. In an embodiment, the spin coating deposition is implemented at about room temperature. In some embodiments, a soft baking process is implemented after spin coating. The soft baking can be, for example, a low temperature bake of about 100° C. or less. Other drying processes may also be implemented.

[0031] In an embodiment, spin-on deposition allows the dielectric regions of frame 104 to be filled with dielectric material without forming seams in the dielectric regions. Instead, the dielectric material is filled in the dielectric regions (eg, within the trenches) uniformly and / or in a bottom-up manner.

[0032] In an embodiment, deposition is provided at a temperature between about 120° C. and 250° C. In some implementations, deposition is a spin-on deposition as discussed above, and the temperature is selected based in part on solvent evaporation requirements. Thus, using spin-on deposition allows for a relatively low impact on the thermal budget.

[0033] Then, the method 100 proceeds to block 108, where a treatment is applied to the dielectric material. In an embodiment, the treatment is a microwave (MW) plasma. The MW plasma treatment can be used to restructure the dielectric material. In an embodiment, the restructuring prepares an amorphous network. In some embodiments, the restructuring forms certain bonds (e.g., O-Si-O). In an embodiment, the MW plasma treatment can be used to densify the dielectric material. Densification can increase the density per cm of the dielectric layer. 3MW plasma treatment may also remove impurities. Block 108 provides MW plasma treatment with high plasma density and low ion energy to provide one or more of the previously discussed features in some embodiments. Fig.28 The dielectric material is shown after deposition. Fig.29 The dielectric material is shown after plasma treatment.

[0034] In an embodiment, the box 108 treatment includes a MW plasma using an inert gas such as helium, argon, or other suitable gas. In an embodiment, the box 108 treatment includes a MW frequency having radiation centered at about 2.45 GHz. In an embodiment, box 108 includes implementing the MW plasma at a temperature between about 300°C and about 500°C. In an embodiment, the MW plasma treatment is implemented at a temperature less than about 500°C. Therefore, in some embodiments, the thermal impact on the device does not exceed 500°C; that is, the structure (e.g., metal gate and / or other metal components) is not exposed to temperatures greater than 500°C. In an embodiment, the impact on the thermal budget for box 108 (and box 106) is less than about 450°C. In an embodiment, box 108 has a MW plasma implemented at a source power between about 1000 watts (W) and about 4000 W. In some embodiments, materials after box 108 are provided, such as Fig.29 as shown in .

[0035] In an embodiment, annealing of the dielectric material after deposition is not required. In addition, the dielectric material can be formed to have sufficient quality (e.g., dielectric properties) and / or consistency (e.g., no seams) to benefit device performance and / or provide more controlled subsequent processes (e.g., such as removing portions of the dielectric material by etch-back or planarization). That is, in an embodiment, a process to remove the thickness of the dielectric layer, such as an etch-back process of the dielectric material or a chemical mechanical polishing (CMP) of the dielectric material, is performed without annealing or other high temperature processes for the dielectric material. In an embodiment, a process to thin the dielectric material is performed without further densification processes of the dielectric material in addition to the MW plasma treatment.

[0036] The method 100 is now described with respect to various embodiments of forming a semiconductor device, such as being performed during the formation of a CFET device. Specifically, in a first exemplary embodiment, Figures 2 to 18 The method 100 is shown applied to an isolation feature adjacent to a vertical contact feature of a CFET device.The vertical contact feature may be an L-shaped contact feature extending from above the upper device of the CFET to the terminals (source / drain features) of the lower device of the CFET.

[0037] Figure 2A simplified partial top view of a CFET device 200 is shown. For ease of reference, referring first to the top view, the device 200 includes an active region 220 extending longitudinally along the Y direction and a gate structure 216 extending longitudinally along the X direction. In addition to the active region 220 and the gate structure 216, Figure 2 200 is shown with a contact feature 208 extending to the source / drain region of the upper transistor of the device 200. In some embodiments, the contact feature 208 is referred to as MD and is part of a middle-end or MEOL feature that provides contact to the source / drain terminals of a transistor formed in the front-end of the line (FEOL). Another contact shown is a vertical contact feature 202 and a region 204 adjacent to the vertical contact feature 202. The region 204 is filled with a dielectric material, which can be formed using one or more of the steps of the method 100, including, for example, spin-on deposition and MW plasma treatment.

[0038] The active region may include a vertical stack of nanostructures 214 (or channel members) stacked along the Z direction. Figure 3 . Each of the gate structures 216 includes a bottom segment 216P and a top segment 216N above the bottom segment. The top segment and the bottom segment may include different work function layer arrangements or different dipole components. In the device 200, the bottom segment 216P is a gate structure for a PMOS transistor and the top segment 216N is a gate structure for an NMOS transistor, but other arrangements are possible. The active region includes corresponding source / drain regions - a top source / drain region (e.g., an epitaxial material doped with a second type of dopant) 216N and a bottom source / drain region (e.g., an epitaxial material doped with a second type of dopant) 216P. That is, the device 200 includes: a bottom transistor device 200B, including, for example, a gate 216P and a source / drain component 206P forming a PFET; and an upper transistor device 200A, including, for example, a gate 216N and a source / drain component 206N forming an NFET.

[0039] Transistors of a stacked transistor structure, such as stacked transistors 200A and 200B of device 200, can be manufactured individually, monolithically, or sequentially. When manufactured individually, the top transistor and the bottom transistor can be manufactured individually, and then the top transistor is joined / attached to the bottom transistor. When manufactured monolithically, the top transistor and the bottom transistor are manufactured from an initial device precursor. For example, a first semiconductor layer group can be joined / attached to a second semiconductor layer group and then processed to form a top transistor and a bottom transistor, respectively. When manufactured sequentially, the first semiconductor layer group can be processed to form a bottom transistor, and then the second semiconductor layer group is attached / joined to the bottom transistor and processed to form a top transistor (i.e., the top transistor is manufactured on the bottom transistor).

[0040] Device 200 also shows contact features. The bottom contact is interfaced with the source / drain feature 206P of the bottom transistor 200B. The contact 208 is interfaced with the source / drain feature 206N of the upper transistor 200A. A metallization layer (M0) connected to the contact 208 through a via 210 is formed above the contact 208. In the illustrated embodiment, the L-shaped contact 202 extends to the bottom contact to provide an interconnection to the source / drain feature 206P of the bottom device 200B. In some embodiments, a contact to a source / drain feature 206N of the upper device 200A is connected to a source / drain feature 206P of the bottom device 200B through the L-shaped contact 202. The L-shaped contact 202 includes a vertically extending portion (z direction) and a lower, horizontally extending portion (y direction). Region 204 is filled with a dielectric material. Region 204 has dielectric material located on top of the horizontally extending portion and abutting the sidewalls of the vertically extending portion. In effect, the L-shape is filled. Region 204 may be fabricated using one or more aspects of method 100 as discussed below.

[0041] Figure 3 A partial cross-sectional view of a CFET device 200 is shown. The device 200 includes a substrate 402. The substrate 402 is similar to the above-mentioned Figure 1 The substrate 402 is a substrate as described in the method 100 of the present invention. The substrate 402 includes: an elemental semiconductor such as silicon and / or germanium; a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or a combination thereof; an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or a combination thereof; or a combination thereof. In the depicted embodiment, the substrate 402 is a silicon substrate. In some embodiments, the substrate 402 is a semiconductor-on-insulator substrate such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The substrate 402 may include various doped regions such as a p-type doped region (e.g., a p-well), an n-type doped region (e.g., an n-well), or a combination thereof. The n-type doped region includes an n-type dopant such as phosphorus, arsenic, other n-type dopant, or a combination thereof. The p-type doped region includes a p-type dopant such as boron, indium, other p-type dopant, or a combination thereof. In some embodiments, the doped region includes a combination of a p-type dopant and an n-type dopant.In some embodiments, the device 200 includes a bottom silicon germanium layer over a base substrate, and the bottom silicon layer is disposed over the bottom silicon germanium layer.

[0042] Figure 3200B, 200A is shown in the channel member 214 of the active region 220. It should be noted that the number of channel members 214 for each of the transistors 200B, 200A is merely exemplary, and there may be more or fewer channel members 214. In some embodiments, in order to form the channel member 214, the sacrificial semiconductor layer and the channel semiconductor layer (which form the channel member 214) are vertically stacked (e.g., along the z direction) in a staggered and / or alternating configuration from the top surface of the substrate 402. The composition of the sacrificial semiconductor layer is different from that of the channel semiconductor layer to achieve etching selectivity and / or different oxidation rates during subsequent processing. The sacrificial semiconductor layer and the channel semiconductor layer include different materials, component atomic percentages, component weight percentages, thicknesses, or combinations thereof to achieve desired etching selectivity during an etching process (such as an etching process implemented to form a floating channel layer, here the channel member 214, collectively referred to and annotated as 214P, 214N). In an embodiment, the channel member 214 includes silicon. The channel member 214 of the upper device 200A is annotated as channel member 214N, and the channel member 214 of the lower device 200B is annotated as channel member 214P.

[0043] An intermediate dielectric isolation feature 406 is disposed between a topmost one of the bottom channel members 214P and a bottommost one of the top channel members 214N. The intermediate dielectric isolation feature 406 may include silicon oxide, silicon nitride, or a combination thereof.

[0044] The gate structure of CFET 200 includes a bottom segment 216P associated with device 200A and a top segment 216N associated with device 200B. In some embodiments, bottom segment 216P includes a p-type work function metal layer, and top segment 216N includes an n-type work function metal layer. In some alternative embodiments, bottom segment 216P includes an n-type work function metal layer, and top segment 216N includes a p-type work function metal layer. Gate structure 216P wraps around bottom channel member 214P, and gate structure 216N wraps around top channel member 214N. Figure 2, the cross section EE' shown in the figure, the cross section EE' extends along the active area, and the channel area of ​​the channel member 214 is interlaced with the source / drain area (e.g., the source / drain components 206P and 206N of the bottom device 200B and the top device 200A, respectively). In some embodiments, the bottom source / drain component 206P includes a p-type dopant, and the top source / drain component 206N includes an n-type dopant. In some embodiments, the bottom source / drain component 206P includes silicon germanium (SiGe) and a p-type dopant, and the top source / drain component 206N includes silicon (Si) and an n-type dopant. The doped region (e.g., an epitaxial region) can provide isolation and is disposed below the source / drain component 206P. The gate spacer layer 408 extends along the sidewalls of the gate structure 216. The gate structure 216 (including the bottom segment 216P and the top segment 216N) is insulated from the bottom source / drain feature 206P and the top source / drain feature 206N by the inner spacer feature 410 .

[0045] An interlayer dielectric (ILD) 414 and a contact etch stop layer (CESL) 412 are formed over the substrate 402. In an embodiment, the CESL 412 may include silicon nitride, and the ILD layer 414 may include silicon oxide. Other exemplary compositions of the CESL 412 include silicon carbonitride or silicon carbon oxynitride. Other exemplary compositions of the ILD layer 414 include, for example, silicon oxide, carbon-doped silicon oxide, silicon nitride, silicon oxynitride, oxide formed from tetraethyl orthosilicate (TEOS), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), Black (Applied Materials, Santa Clara, CA), xerogel, aerogel, amorphous fluorinated carbon, parylene, benzocyclobutene-based (BCB) dielectric materials, silk (The Dow Chemical Company, Midland, MI), polyimide, other suitable dielectric materials, or combinations thereof. In yet another embodiment, the ILD 414 may be formed according to the method 100, including dielectric materials deposited as discussed above with reference to the MW processing of blocks 106 and 108. The ILD 414 and CESL 412 are formed for the bottom device 200B (i.e., above the bottom source / drain feature 206P), and are formed for the top device 200A (i.e., above the top source / drain feature 206N).

[0046] Figure 3The device 200 shown in FIG. 2 shows a first hard mask layer 416 deposited over the ILD layer 414 and gate structure 216 of the upper device 200A. A second hard mask layer 418 is disposed on the first hard mask layer 416. In some embodiments, a photoresist layer for patterning openings to be etched for the device is deposited over the hard mask layer. In some embodiments, the first hard mask layer 416 includes silicon nitride and the second hard mask layer 418 includes silicon oxide. The portion ( Figure 3 ), such as to source / drain features 206N.

[0047] As noted above, in an embodiment, the ILD 414 may be configured to Figure 1 That is, the ILD 414 can be deposited using blocks 106 and / or 108 of the method 100, including spin-on deposition and subsequent MW plasma treatment using one or more of the materials discussed above (including materials as provided in Table 1). As shown below, the ILD 414 and CESL 412 are formed as the lower device 200B and the upper device 200A for the CFET 200. Any one or both of these ILD layers can be formed according to various aspects of the method 100.

[0048] Reference now Figures 4 to 18 To show Figure 2 The top view of the device 200 shows the formation of a vertical contact feature 202. Figure 2 , a first cross section is provided along the gate structure 216 (i.e., through the channel region) indicated as a cut A-A'; a second cross section and a third cross section are provided along the source / drain regions BB' and CC', respectively. Cut CC' passes through an area where there is a contact feature extending to the top of the top device 200A, i.e., a vertically extending portion of the contact feature 202. Cut BB' passes through an area where there is a contact feature only adjacent to a portion of the bottom device 200B, i.e., a horizontally extending "leg" portion of the contact feature 202 (see FIG. Figure 2 , wherein region 204 is located above a portion of contact feature 202).

[0049] Figure 4 , Figure 5 and Figure 6 Each shows a device 200 at a transition stage of manufacture. Figure 2 2 . The opening 504 is shown, which is provided to define an area for the contact element 202 of the device 200 . Figure 5An opening 504 is shown extending from the top of the first device 200A through the second device 200B. The opening 504 extends through the gate structure 216, including the top segment 216N and the bottom segment 216P. The opening 504 corresponds to the contact 202 and the region 204. Figure 2 .

[0050] like Figure 4 As shown in , the gate structure 216 includes a gate dielectric layer formed under the gate electrode of the gate structure 216. The gate dielectric layer may include an interfacial layer and / or a high-k dielectric layer. High-k dielectric materials generally refer to dielectric materials having a dielectric constant greater than the dielectric constant of silicon dioxide (k≈3.9), such as HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlO x , ZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, LaO3, La2O3, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3 (BTO), (Ba, Sr)TiO3 (BST), Si3N4, HfO2-Al2O3, other high-k dielectric materials or combinations thereof.

[0051] It should be pointed out that Figures 4 to 6 Also shown are the isolation regions between active regions. Isolation components 404 electrically isolate active device regions and / or passive device regions of the device from each other. Isolation components 404 include silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (including, for example, silicon, oxygen, nitrogen, carbon, other suitable isolation components, etc.) or combinations thereof. Isolation components 404 may have a multilayer structure. For example, isolation components 404 include bulk dielectrics (for example, oxide layers) above dielectric pads (including, for example, silicon nitride, silicon oxide, silicon oxynitride, carbon oxynitride silicon or combinations thereof). In another example, isolation components 404 include dielectric layers above doped pads, such as borosilicate glass (BSG) pads and / or phosphosilicate glass (PSG) pads. The size and / or characteristics of isolation components 404 are configured to provide shallow trench isolation (STI) structures, deep trench isolation (DTI) structures, local oxidation of silicon (LOCOS) structures, other suitable isolation structures or combinations thereof. In an embodiment, isolation feature 404 is a STI between portions of the substrate.

[0052] Figure 5 and Figure 6Each shows an opening 504 extending through the source / drain region of the device 200. The opening 504 extends between adjacent upper source / drain regions 206 of adjacent devices and extends vertically through the upper device 200A and the lower device 200B of the device 200. The opening 504 can be formed by suitable photolithography and etching processes. In some embodiments, the etching is an anisotropic etching that provides the opening 504 with substantially linear sidewalls. In an embodiment, the aspect ratio of the opening 504 is greater than about 4:1 (depth to width). As shown in FIG. Figure 5 and Figure 6 As shown in , the bottom source / drain feature 206 is covered by the bottom CESL 412 and the bottom ILD layer 414 , and the top source / drain feature 206 is covered by the top CESL 412 and the top ILD layer 414 .

[0053] After forming the opening 504, the opening is filled with a dielectric liner layer and a conductive material over the dielectric liner layer. Figure 7 , Figure 8 and Fig. 9 As shown in , a dielectric liner layer 802 is conformally formed on the sidewalls of the opening 504. In an embodiment, the dielectric liner layer 802 is a silicon nitride composition. A conductive material 804 is filled in the opening 504 above the dielectric liner layer 802. In an embodiment, the conductive material 804 is ruthenium (Ru). In other embodiments, other conductive materials are possible, such as, for example, nickel (Ni), cobalt (Co), copper (Cu), or a combination thereof. In some embodiments, the deposition of materials 802, 804 can be implemented by ALD, PVD, CVD, high density plasma CVD (HDPCVD), metal organic CVD (MOCVD), remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), low pressure CVD (LPCVD), atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), plating, other suitable processes, or a combination thereof. In an embodiment, after deposition, a planarization process such as chemical mechanical polishing (CMP) is implemented to remove the deposited material from the top surface of the device. The hard mask layers 416 and 418 may also be removed, as shown in FIG. Figure 7 , Figure 8 , Fig. 9 as shown in .

[0054] In some portions of the device 200, the conductive material is etched back. And portions of the conductive material remain to form contact structures. Fig.10 In the example of FIG. 1 , the conductive material 804 is etched back to form an etched back conductive material 804 ′ and an opening 1102 thereover. Fig.10 Also shown is an area where conductive material 804 is retained. Fig.10 , Fig.11 , Fig.12and Fig.13 After patterning as shown in FIG. , the conductive materials 804, 804' form an L-shaped contact structure, as discussed above. Figure 2 As shown in the contact structure 202. Fig.14 Shows when along Figure 2 The vertical contact member 202 comprises an L-shape of conductive material 804, 804' when viewed in cross section DD' of FIG. The contact member 202 is vertically spaced apart from the substrate 402 by a spacer 802.

[0055] In some embodiments, etching back the conductive material 804 and forming the opening 1102 is provided by patterning additional hard mask layers 416, 418 and layer 1104. In an embodiment, layer 1104 is a hard mask material. In an embodiment, layer 1104 is a photosensitive material. Layers 416, 418, 1104 can be patterned by suitable photolithography and etching processes to define openings over respective portions of the conductive material 804.

[0056] The opening 1102 is oriented in at least one direction (e.g., Figure 3 The opening 1102 may have an aspect ratio (height: width) greater than 1 in the CC' and AA' cross-sectional directions. In an embodiment, the opening 1102 may have an aspect ratio (height: width) greater than 4:1. The opening 1102 may be defined as an area for a dielectric material, as described above with reference to Figure 1 As discussed in block 104 of method 100 and as Figure 2 As shown in area 204.

[0057] Fig.11 , Fig.12 , Fig.13 and Fig.14 Shown according to Figure 1 FIG. 1 is a partial cross-sectional view of the device 200 after various aspects of block 106 of the method 100 have then been deposited with a dielectric material. In particular, a dielectric material 1502 is formed on the device 200 (including within the opening 1102). Fig.11 A partial cross-sectional view along line AA′ is shown, wherein a dielectric material 1502 is deposited over the device 200 (including in the opening 1102 over the etched-back conductive material 804 ′), which provides a horizontal extension of the L-shaped conductive structure 202 . Fig.12 A partial cross-sectional view along line BB′ is shown, wherein dielectric material 1502 is deposited over device 200 (including in opening 1102 over etched-back conductive material 804 ′), which provides a horizontal extension of L-shaped conductive structure 202 . Fig.13 A partial cross-sectional view along line CC′ is shown, with the conductive material 804 remaining extended to the top surface of the device 200 , providing a vertical extension of the L-shaped conductive structure 202 .

[0058] In an embodiment, the dielectric material 1502 is deposited by spin coating deposition, as described above with reference to Figure 1 In an embodiment, the dielectric material 1502 may be substantially similar to the dielectric material 1502 of the embodiment described above with reference to FIG. Figure 1 The materials discussed in block 106 of method 100 include, for example, one or more of the components of Table 1. In another embodiment, the dielectric material may be silicon oxide, a nitride such as silicon nitride, a low-k dielectric material, and / or other suitable materials. The low-k dielectric material includes a material having a dielectric constant of less than about 2.5 (i.e., an extremely low-k (ELK) dielectric material), such as porous silicon oxide, silicon carbide (SiC), a carbon-doped oxide (e.g., a SiCOH-based material (having, for example, Si-CH3 bonds)), and / or other suitable materials.

[0059] After the dielectric material is deposited, as described above with reference to Figure 1 As discussed in block 108 of method 100, the deposited dielectric material is subjected to microwave plasma treatment. The microwave plasma treatment may include reconstructing and / or densifying the dielectric material by introducing a MW plasma. Fig.15 , Fig.16 , Fig.17 and Fig.18 The dielectric material 1502 is shown to have been processed, resulting in processed dielectric material 1502'.

[0060] By spin-on deposition and processing of dielectric material 1502, in an embodiment, no seam exists in dielectric material 1502' within opening 1102. In some embodiments, processing of dielectric material 1502' can be performed before removing the hard mask layer and / or the underlying planarization process. In other embodiments, processing of dielectric material 1502' can be performed after removing the hard mask layer and / or the underlying planarization process.

[0061] The device 200 may be further processed, including providing a planarization process. In some embodiments, the device 200 is planarized using chemical mechanical polishing (CMP). Fig.15 , Fig.16 , Fig.17 and Fig.18 As shown in FIG. 4 , planarization removes excess dielectric material 1502 (or 1502 ′) and any hard mask layers (eg, 416 and 418 ) remaining on the top surface of device 200 . In some embodiments, after planarization, the top surface of top ILD layer 414 is exposed.

[0062] It should be noted that when the dielectric material 1502' is formed (e.g., deposited and processed), the gate structure 216 is disposed on the device. In an embodiment, the gate structure 216 includes a metal. If a process such as an annealing process with a high temperature (greater than 500° C.) is implemented to prepare the dielectric material, the high heat may damage the gate structure 216 in terms of threshold voltage shift or degradation of on-state current. Because the dielectric material 1502' is formed according to various aspects of the method 100 that allow temperatures less than 400° C., the thermal budget can be reduced and damage to the gate structure 216 can be mitigated.

[0063] refer to Figures 19 to 26 Another embodiment of implementing the method 100 during the formation of a CFET device is described. Specifically, the method 100 is applied to form a dummy material when patterning a gate stack of a CFET device.

[0064] Fig.19 shows a basically similar Figure 3 A partial cross-sectional view of a view. Fig. 20 23. The transition structure provided during the manufacture of the CFET device 2300, in particular during the gate stack formation cycle, is shown. The bottom device 2300B of the CFET device 2300 includes a gate structure 216P formed to wrap around the channel member 214P. An isolation region 406 is disposed between the bottom device 2300B and the top device 2300A. The CFET device 2300 is substantially similar to the device 200.

[0065] exist Fig. 20 In the transition phase of the top device 2300B, the gate structure of the top device 2300A has not yet been formed. Therefore, the top device 2300A includes a dummy plug 2302 between the channel components 214N. And the top device 2300A includes a hard mask layer 2306. In an embodiment, the dummy plug 2302 includes a dielectric material such as aluminum oxide. In an embodiment, the hard mask layer 2306 includes a dielectric material such as silicon nitride, silicon carbonitride and / or other suitable materials. The dummy plug 2302 and the hard mask layer 2306 can protect the channel component 214N of the top device 2300A during the processing of the gate structure 216P of the bottom device 2300B.

[0066] An opening 2304 is provided in the gate region of the upper device 2300A. In some embodiments, the opening 2304 is provided as a region defined by a dielectric material, such as provided in block 104 of method 100.

[0067] Continuing with the application of method 100 to exemplary device 2300 , in some implementations to form CFET 2300 , a dummy layer is deposited in opening 2304 at this stage of fabrication, according to block 106 of method 100 . Fig. 20 Provides along Fig.19 A partial cross-sectional view of the cut FF′ of FIG. 2 , wherein a dummy material 2402 has been formed in the opening 2304 .

[0068] exist Fig. 20 In a transition device, one or more layers of a metal gate may be formed on the bottom transistor surrounding the lower active layer 214P. At this stage, epitaxial source / drain components may have been formed. In some embodiments, the metal gate 216P may have a work function adjusted to the first device type (e.g., a p-type work function) and is located above the gate dielectric. A dummy material 2402 is then formed over the one or more layers of the metal gate of the bottom transistor. In some embodiments, the dummy material 2402 is used to protect the bottom gate components (e.g., the gate dielectric and the gate electrode) from being processed while the upper gate components are formed as discussed below.

[0069] In an embodiment, the dummy material 2402 is formed according to various aspects of the method 100. That is, in some embodiments, according to Figure 1 In various aspects of block 106 of method 100, dummy material 2402 is deposited in opening 2304. For example, in some embodiments, dummy material 2402 is deposited by a spin-on deposition process. As another example, in an embodiment, dummy material 2402 can include one or more dielectric materials of Table 1 discussed above.

[0070] After depositing the dummy material 2402 into the opening 2304, the dummy material may be subjected to a MW plasma treatment, as described above with reference to Figure 1 The microwave plasma treatment may include reconstructing and / or densifying the deposited dummy material by introducing a MW plasma. Fig.21 MW treated dummy material 2402' is shown. The treated dummy material 2402' is formed by spin coating deposition and treatment of the dummy material. In an embodiment, there is no seam in the dummy material. Therefore, during a subsequent etching process, for example, Fig. 22 The etch-back process of the dummy material 2402' shown in FIG. 1 provides uniform removal of the dummy material 2402'. In an embodiment, etching back the dummy material 2402' is performed at a temperature between about -10°C and about 250°C. In an embodiment, the reaction gas and carrier gas for the etchant (e.g., plasma etching) may include HF, NH3, Ar, N2, and / or other suitable gases. In an embodiment, the etch-back process is performed at a pressure between about 100 mTorr and about 3500 mTorr.

[0071] After etching back the dummy material 2402', the exposed portion of the metal gate 216P can be removed. In some embodiments, the metal gate 216P can have a work function adjusted to a first device type (e.g., a p-type work function), which is associated with the bottom device 2300B. Since a second device type (e.g., an n-type work function) is desired for the top device 2300A, it is desirable to remove the metal gate 216P. The metal gate 216P can be removed at a temperature between about 20°C and about 75°C. In an embodiment, the metal gate 216P is removed by an etching process (e.g., plasma etching) including an etching gas of H2O, H2O2, NH4OH and / or other suitable gases. The etching process can be a selective etching process for the conductive material of the metal gate 216P. Fig.23 The metal gate 216P is shown having been removed.

[0072] After removing the metal gate 216P, the etched-back, processed dummy material 2402' is removed from the device 2300, as shown in FIG. Fig.24 . In an embodiment, the removal of the dummy material 2402' is performed at a temperature between about -10°C and about 250°C. In an embodiment, the dummy material 2402' is removed by an etching process that implements a reactive gas (and carrier gas) of HF, NH3, Ar, N2, and / or other suitable gases. In an embodiment, the dummy material 2402' is removed at a process pressure between about 10 mTorr and about 3500 mTorr.

[0073] The process of forming CFET 2300 may continue by removing hard mask 2306 and dummy plug 2302 from device 2300A, as shown in FIG. Fig.25 In an embodiment, the removal is performed by a selective etching process. In an embodiment, the removal is a wet etching process. After removing the hard mask 2306 and the dummy plug 2302, the upper channel member 214P is released and has an exposed surface. A metal gate is then deposited, such as Fig.26As shown in , a metal gate 216N is formed over the device 2300 and the channel member 214P. The metal gate 216N can provide a different work function than the metal gate 216P. In one embodiment, the first work function layer 216P is a p-type work function layer, and the second work function layer 216N is an n-type work function layer. In another example, the first work function layer 216P is an n-type work function layer, and the second work function layer 216N is a p-type work function layer. Exemplary n-type work function materials include Ti, Al, Ag, Mn, Zr, TiAl, TiAlC, TaC, TaCN, TaSiN, TaAl, TaAlC, or TiAlN. Exemplary p-type work function materials include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, or WN. In some embodiments, the metal gate 216N is substantially similar to that discussed above with reference to the device 200, including the attached Figure 3 Forming the metal gate 216N provides, in some embodiments, forming an interfacial layer, a gate dielectric layer such as a high-k gate dielectric, and a gate electrode layer.

[0074] Processing of the device 2300 may then proceed to forming MEOL contacts, including those contact features such as the L-shaped contacts 202 discussed above.

[0075] As described above, the top device of the CFET and the bottom device of the CFET have different composition requirements to affect different performance. Therefore, they need to be processed differently. One way to provide differentiated processing is to use a dummy layer, such as the dummy material 2402 described in the embodiment of the CFET device 2300. As described in detail above, according to Figure 1 The method 100 forms the dummy fill material 2402 to provide deposition of a different work function layer for the top device 2300A. Other uses of the dummy fill layer may also be implemented, depositing and patterning or etching back the dummy fill layer to cover the bottom channel component 214P or bottom device features, such as source / drain regions or gate structures, while materials or processes are applied around the top channel component 214N. Figure 1 The method 100 may fabricate any or all of these dummy layers.

[0076] For another example, dummy materials can also be used to form different dipole layers. In particular, different dipole layers are introduced into the top channel member (nanostructure) and the bottom channel member (nanostructure) in different device regions. As described above, in the manufacture of devices such as devices, dummy materials are formed to cover the bottom channel member (e.g., 214P) and the top channel member (e.g., 214N), and then etched back to expose the top channel member (e.g., 214N). Because the dummy material is formed after depositing some gate layers including metals, and because the dummy material is subjected to an etch-back process, it is beneficial to form a dummy layer using a process that does not strain the thermal budget, or in other words, provide a relatively low temperature, but form the dummy layer with uniform quality (e.g., no seams) and high density.

[0077] refer to Fig. 27 , to provide an exemplary device 3100. The device 3100 includes three device regions—a first region 1300A, a second region 1300B, and a third region 1300C. The workpiece 400 includes a substrate 402 substantially similar to that discussed above with reference to the embodiment of the device 200. For example, an isolation feature 404 is formed on the substrate 402. Like the active region of the device 200 described above, a plurality of bottom channel components 214P and a plurality of top channel components 214N are provided. An intermediate dielectric isolation feature 406 is disposed between the topmost one of the bottom channel components 214P and the bottommost one of the top channel components 214N.

[0078] like Fig. 27 As shown in , an interfacial layer 1302 is formed over the surface of the channel member 214. In an embodiment, the interfacial layer 1302 is formed by thermal oxidation to form, for example, silicon oxide. A gate dielectric layer 1304 is then deposited over the top surface of the interfacial layer 1302 and the isolation member 404 using CVD or ALD. The gate dielectric layer 1304 may include, for example, HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, HfO2-Al2O3, TiO2, Ta2O5, La2O3, Y2O3, other suitable high-k dielectric materials, or combinations thereof. Over the first region 1300A, a first dipole material 1306A is conformally deposited over the gate dielectric layer 1304 using ALD or CVD. Over the second region 1300B, a second dipole material 1306B is conformally deposited over the gate dielectric layer 1304 using ALD or CVD. The first region 1300A is free of the second dipole material 1306B. The second region 1300B is free of the first dipole material 1306B. The third region 1300C is free of the first dipole material 1306A and the second dipole material 1306B. In some embodiments, the dipole materials 1306A, 1306B are both n-type dipole materials and differ in composition or thickness.

[0079] A dummy material 1308 is deposited over the first region 1300A, the second region 1300B, and the third region 1300C. Figure 1 dummy material 1308 is formed according to various aspects of method 100. For example, in an embodiment, according to one or more aspects of block 106 of method 100, dummy material 1308 is deposited, for example, by spin coating of a dielectric material and / or includes a material selected from Table 1. In further embodiments, according to Figure 1 In various aspects of block 108 of method 100 , dummy material 1308 is subjected to a MW plasma treatment.

[0080] In some embodiments, the dummy fill material 1308 after the MW plasma treatment can then be reduced in thickness, or etched back, so that the treatment of one or more regions of the device 3100 can be implemented. In some embodiments, the dummy fill material 1308 remains above the channel member 214P of the bottom device 1300L, and the treatment of the material above the channel member 214N of the top device 1300T is implemented. For example, additional dipole materials can be selectively deposited and / or selectively removed. After providing a suitable configuration of dipole materials above the corresponding channel members 214P, 214N of the regions 1300A, 1300B and 1300C, a drive-in process is implemented. The process can continue to manufacture the device 3100, including forming a gate electrode for the bottom device 1300L and the top device 1300T.

[0081] In one exemplary aspect, the disclosed embodiments are directed to a method. The method includes providing a semiconductor substrate, depositing a dielectric material over a semiconductor structure, treating the dielectric material with a microwave (MW) plasma, and after the treating, removing a portion of the treated dielectric material.

[0082] In an embodiment of the method, depositing the dielectric material is performed by a spin coating process. In some embodiments, depositing the dielectric material comprises introducing at least one of the following compounds into the semiconductor structure:

[0083] And wherein, R, R1, R2, R3 are each an alkyl series, and each of n, l and m is greater than 0.

[0084] In an embodiment, the introduced compound is

[0085] and wherein the ratio of l to m is between about 0.05 and about 0.95. In a further embodiment, the introduced compound is

[0086] and n is between about 10 and about 20. And in an embodiment, the dielectric material becomes at least one of silicon oxide or silicon oxycarbide. In an embodiment of the method, processing the dielectric material is performed at a temperature less than 500° C. In some embodiments, depositing the dielectric material includes forming the dielectric material in an opening having a depth to width aspect ratio greater than 1.

[0087] In one exemplary aspect, a method is provided, comprising: receiving a device comprising at least one metal feature disposed on a substrate; and forming a trench over the substrate, wherein the trench has a depth to width aspect ratio greater than 1. A spin-on deposition process is used to provide a dielectric material over the substrate and within the trench. The method continues by performing microwave (MW) treatment of the dielectric material.

[0088] In a further embodiment, wherein the spin-on deposition process comprises introducing into the substrate at least one of the following compounds:

[0089] and wherein R, R1, R2, R3 are each alkyl groups, and n, l and m are each greater than 0. In some embodiments, the treatment performed on the dielectric material is performed on a silicon oxide or silicon oxycarbide material produced from at least one compound (eg, those listed previously).

[0090] In an embodiment, the spin-on deposition process fills a trench disposed above and adjacent to the contact feature, and the contact feature has an L-shape in the first cross-sectional view. In an embodiment, the at least one metal feature is a metal gate structure surrounding a channel region of the first transistor. In some implementations, the at least one metal feature includes another metal feature that extends to an L-shaped contact feature of a source / drain region of the first transistor.

[0091] In another exemplary aspect, a method is provided, the method comprising forming a first transistor of a transistor stack on a substrate. Forming a second transistor of the transistor stack above the first transistor. Etching an opening extending through a dielectric layer disposed on the substrate. And the opening extends vertically adjacent to the first transistor and the second transistor. Filling the opening with a conductive material. And etching back the conductive material to form another opening. Performing a spin-on deposition to fill the other opening with a dielectric material. And treating the dielectric material with a microwave plasma treatment.

[0092] In some embodiments, the method further comprises etching back the conductive material, leaving an L-shaped conductive component in at least one cross-sectional view. The first transistor comprises a gate structure extending in a first direction in the top view. In an embodiment, the treated dielectric material is disposed on a bottom region of the L-shaped conductive component and borders a sidewall of a vertically extending region of the L-shaped conductive component. The method may comprise providing a dielectric material of at least one of the following compounds onto the substrate by spin coating deposition:

[0093] And wherein, R, R1, R2, R3 are each an alkyl series, and each of n, l and m is greater than 0.

[0094] In an embodiment, the deposition and microwave plasma treatment are performed at a temperature of less than 500° C. In an embodiment, the microwave plasma treatment is performed with a radiation frequency centered at about 2.45 GHz.

[0095] Some embodiments of the present application provide a method for manufacturing a semiconductor device, comprising: providing a semiconductor structure; depositing a dielectric material over the semiconductor structure; treating the dielectric material with a microwave (MW) plasma; and after the treatment, removing a portion of the treated dielectric material. In some embodiments, depositing the dielectric material is performed by a spin coating process. In some embodiments, depositing the dielectric material comprises introducing at least one of the following compounds into the semiconductor structure:

[0096] And wherein, R, R1, R2, R3 are each alkyl series, and each of n, l and m is greater than 0. In some embodiments, the introduced compound is and wherein the ratio of l to m is between about 0.05 and about 0.95. In some embodiments, the introduced compound is and n is between about 10 and about 20. In some embodiments, after the depositing, the dielectric material becomes at least one of silicon oxide or silicon oxycarbide. In some embodiments, processing the dielectric material is performed at a temperature less than 500° C. In some embodiments, depositing the dielectric material includes forming the dielectric material in an opening having a depth to width aspect ratio greater than 1.

[0097] Some other embodiments of the present application provide a method of manufacturing a semiconductor device, comprising: receiving a device including at least one metal component disposed on a substrate; forming a trench above the substrate, wherein the trench has a depth-to-width aspect ratio greater than 1; using a spin-on deposition process to provide a dielectric material above the substrate and within the trench; and performing microwave (MW) treatment of the dielectric material. In some embodiments, the spin-on deposition process includes introducing at least one of the following compounds into the substrate:

[0098] and wherein each of R, R1, R2, R3 is an alkyl series, and each of n, l and m is greater than 0. In some embodiments, the treatment performed on the dielectric material is performed on a silicon oxide or silicon oxycarbide material produced by the at least one compound. In some embodiments, the spin-on deposition process fills the trench disposed above and adjacent to a contact feature, wherein the contact feature has an L shape in the first cross-sectional view. In some embodiments, the at least one metal feature is a metal gate structure surrounding a channel region of the first transistor. In some embodiments, the at least one metal feature includes another metal feature of an L-shaped contact feature extending to a source / drain region of the first transistor.

[0099] Still other embodiments of the present application provide a method for manufacturing a semiconductor device, comprising: forming a first transistor of a transistor stack on a substrate; forming a second transistor of the transistor stack, wherein the second transistor is disposed above the first transistor; etching an opening extending through a dielectric layer disposed on the substrate, wherein the opening extends vertically adjacent to the first transistor and the second transistor; filling the opening with a conductive material; etching back the conductive material to form another opening; using spin coating deposition to fill the other opening with a dielectric material; and treating the dielectric material with microwave plasma treatment.

[0100] In some embodiments, the method further comprises: wherein etching back the conductive material leaves an L-shaped conductive feature in at least one cross-sectional view, and wherein the first transistor comprises a gate structure extending in a first direction in a top view. In some embodiments, the treated dielectric material is disposed on a bottom region of the L-shaped conductive feature and borders a sidewall of a vertically extending region of the L-shaped conductive feature. In some embodiments, the spin-on deposition provides the dielectric material of at least one of the following compounds onto the substrate:

[0101] and wherein each of R, R1, R2, R3 is an alkyl group, and each of n, l and m is greater than 0. In some embodiments, the deposition and the microwave plasma treatment are performed at a temperature of less than 500° C. In some embodiments, the microwave plasma treatment is performed with a radiation frequency centered at about 2.45 GHz.

[0102] The features of several embodiments are summarized above so that those of ordinary skill in the art can better understand the various aspects of the embodiments of the present disclosure. Those of ordinary skill in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those of ordinary skill in the art should also be aware that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, comprising: Providing a semiconductor structure; depositing a dielectric material over the semiconductor structure; treating the dielectric material with a microwave (MW) plasma; as well as After the processing, portions of the processed dielectric material are removed.

2. The method according to claim 1, wherein: Depositing the dielectric material is performed by a spin coating process.

3. The method according to claim 1, wherein: Depositing the dielectric material includes introducing at least one of the following compounds into the semiconductor structure: And wherein, R, R1, R2, R3 are each an alkyl series, and each of n, l and m is greater than 0.

4. The method according to claim 3, wherein: The introduced compound is And wherein the ratio of l to m is between about 0.05 and about 0.

95.

5. The method according to claim 3, wherein: The introduced compound is And n is between about 10 and about 20.

6. The method according to claim 3, wherein: After the deposition, the dielectric material becomes at least one of silicon oxide or silicon oxycarbide.

7. The method according to claim 1, wherein: Processing the dielectric material is performed at a temperature less than 500°C.

8. The method according to claim 1, wherein: Depositing the dielectric material includes forming the dielectric material in an opening having a depth to width aspect ratio greater than one.

9. A method for manufacturing a semiconductor device, comprising: receiving a device including at least one metal feature disposed on a substrate; forming a trench over the substrate, wherein the trench has an aspect ratio of depth to width greater than 1; using a spin-on deposition process to provide a dielectric material over the substrate and within the trench; and Microwave (MW) treatment of the dielectric material is performed.

10. A method for manufacturing a semiconductor device, comprising: forming a first transistor of a transistor stack on a substrate; forming a second transistor of the transistor stack, wherein the second transistor is disposed above the first transistor; etching an opening extending through a dielectric layer disposed on the substrate, wherein the opening extends vertically adjacent to the first transistor and the second transistor; filling the opening with a conductive material; Etching back the conductive material to form another opening; using spin-on deposition to fill the other opening with a dielectric material; and The dielectric material is treated with a microwave plasma treatment.

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