Semiconductor device

Abstract

A semiconductor device includes: a substrate; the first insulating film is arranged on the substrate and is provided with at least one guide hole; and a second insulating film disposed on the first insulating film. The semiconductor device further includes: a first adhesive layer provided on the first insulating film; the first conductive structure is arranged in the at least one guide hole and is provided with an extension part extending to the top surface of the first insulating film; and a second adhesive layer disposed on the first conductive structure. The first adhesive layer covers at least a portion of a bottom surface of the extension, and the second adhesive layer covers at least a portion of a top surface of the first conductive structure.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, and more particularly to an adhesive layer of the semiconductor device. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. During the evolution of integrated circuits, functional density (i.e., the number of interconnected devices per unit chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be produced using a process) has decreased. This process of miniaturization generally provides benefits by increasing production efficiency and reducing associated costs. However, this miniaturization is also accompanied by more complex designs and processes for incorporating integrated circuits into devices. Corresponding advances in technology have enabled more complex designs to be manufactured in a precise and reliable manner.

[0003] However, these advances have increased the complexity of manufacturing integrated circuits. As feature sizes continue to decrease, processes become more difficult to perform. Therefore, forming reliable semiconductor devices at smaller sizes is a difficult challenge. Summary of the invention

[0004] In one embodiment, a semiconductor device includes: a substrate; a first insulating film disposed on the substrate and having at least one guide hole; and a second insulating film disposed on the first insulating film. The semiconductor device further includes: a first adhesive layer disposed on the first insulating film; a first conductive structure disposed in the at least one guide hole and having an extension extending from the top surface of the first insulating film; and a second adhesive layer disposed on the first conductive structure. The first adhesive layer covers at least a portion of the bottom surface of the extension, and the second adhesive layer covers at least a portion of the top surface of the first conductive structure.

[0005] In another embodiment, a semiconductor device includes: a III-V compound semiconductor substrate; a first insulating film disposed on the III-V compound semiconductor substrate and having at least one guide hole; and a second insulating film disposed on the first insulating film. The semiconductor device further includes: a first adhesive layer disposed on the first insulating film; a conductive structure disposed in the at least one guide hole and on the top surface of the first insulating film; and a second adhesive layer disposed on the conductive structure. At least a portion of the conductive structure is sandwiched between the first adhesive layer and the second adhesive layer.

[0006] The invention inserts an adhesive layer between the insulating film of benzocyclobutene and the electroplated conductive structure to minimize moisture entering into the material of benzocyclobutene, thereby improving the reliability of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The following will be described in detail with reference to the accompanying drawings. It is worth noting that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various components can be arbitrarily enlarged or reduced to clearly show the features of the present disclosure.

[0008] Figure 1 is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0009] Figure 2 According to some embodiments of the present disclosure, Figure 1 An enlarged schematic diagram of the semiconductor device shown.

[0010] Figure 3 is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0011] Figure 4 is a cross-sectional schematic diagram of a semiconductor device according to another embodiment of the present disclosure.

[0012] Figure 5 is a cross-sectional schematic diagram of a portion of a semiconductor device according to another embodiment of the present disclosure.

[0013] Exemplary embodiments will be described in detail with reference to the accompanying drawings. In the drawings, like reference characters generally indicate identical, functionally similar, and / or structurally similar elements.

[0014] Description of Figure Numbers:

[0015] 10: Semiconductor devices

[0016] 10D: Drain region

[0017] 10G: Gate area

[0018] 10S: Source region

[0019] 20: Semiconductor devices

[0020] 20D: Drain region

[0021] 20G: Gate area

[0022] 20S: Source region

[0023] 30: Semiconductor devices

[0024] 30D: Drain region

[0025] 30G: Gate area

[0026] 30S: Source region

[0027] 40: Semiconductor device

[0028] 100: Base

[0029] 200: epitaxial layer

[0030] 320: Ohm layer

[0031] 340: Gate structure

[0032] 360:Metal layer

[0033] 380: Dielectric layer

[0034] 400: Insulation film

[0035] 420:Metal layer

[0036] 440: Dielectric layer

[0037] 460:Metal layer

[0038] 480: Dielectric layer

[0039] 500: Insulation film

[0040] 500V:Through hole

[0041] 520: Adhesive layer

[0042] 540: Seed layer

[0043] 540A:Connection

[0044] 540B: ​​Extension

[0045] 540B-1: Complete Segment

[0046] 540B-2: Incomplete segment

[0047] 550: Gap

[0048] 560:Metal layer

[0049] 560A:Connection

[0050] 560B: Extension

[0051] 580: Adhesive layer

[0052] 590: Adhesive layer

[0053] 600: Insulation film

[0054] 600V:Through hole

[0055] 620: Adhesive layer

[0056] 640: Seed layer

[0057] 660:Metal layer

[0058] 680: Adhesive layer

[0059] 700: Insulation film

[0060] X: Area DETAILED DESCRIPTION

[0061] The following disclosure provides many different embodiments or examples for implementing different components of the present invention. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to limit the present disclosure. For example, the description of a first component formed on a second component may include an embodiment in which the first and second components are in direct contact, and may also include an embodiment in which an additional component is formed between the first and second components so that the first and second components are not in direct contact.

[0062] It should be understood that additional operating steps may be implemented before, during or after the method, and in some embodiments of the method, some operating steps may be replaced or omitted.

[0063] Additionally, spatially relative terms such as "below," "beneath," "lower," "above," "above," "upper," and the like may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. These spatial terms are intended to encompass different orientations of the device in use or operation, as well as the orientations depicted in the figures. When the device is otherwise oriented (rotated 90 degrees or at other orientations), the spatially relative descriptors used herein may be interpreted in accordance with that rotated orientation.

[0064] In the present disclosure, the terms "about", "approximately", and "generally" generally mean within ±20%, or within ±10%, or within ±5%, or within ±3%, or within ±2%, or within ±1%, or even within ±0.5% of the value or range of a given quantity. The value of a given quantity is an approximate amount. That is, in the absence of specific description of "about", "approximately", and "generally", the meaning of "about", "approximately", and "generally" can still be implied.

[0065] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as those commonly understood by those skilled in the art. It should be understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the present disclosure.

[0066] The different embodiments disclosed below may repeatedly use the same reference symbols and / or marks. Such repetition is for the purpose of simplicity and clarity, and is not intended to limit the relationship between the various embodiments and / or structures discussed.

[0067] In high-power and high-frequency semiconductor devices (such as high electron mobility transistors (HEMTs)), complex circuit layouts can be designed on the front side of the wafer. Specifically, when stacking various metal layers, a planarization process needs to be included between the metal layers to avoid cracking or breaking of the traces. In some embodiments, after the layout of the first metal layer is deposited on the epitaxial surface, an insulating layer with a flat surface should be introduced to cover the entire epitaxial surface and the first metal layer. Thereafter, a second metal layer with a different layout can be deposited on the flat surface of the insulating layer without being affected by the structural contour of the first metal layer below. When making a micro-strip line transmission line structure, a large area of ​​electrode is required to establish electrical grounding on the front side of the wafer, so proper planarization is a key factor in ensuring that the semiconductor device can operate effectively.

[0068] Conventional semiconductor devices may employ insulating layers formed from benzocyclobutene (BCB). Benzocyclobutene is a benzene ring fused to cyclobutane. Applications of benzocyclobutene may include insulation between redistribution lines (as mentioned above), interlayer dielectrics (ILDs), barrier layers between sensitive integrated circuit (IC) devices, or lamination adhesives in packaging structures. The material properties of benzocyclobutene may exhibit external curing behavior in a temperature range between 220°C and 270°C. Cured benzocyclobutene may exhibit excellent thermal stability, a high glass transition temperature, and a low dielectric constant. The above-mentioned properties make benzocyclobutene an ideal choice for forming a planar platform.

[0069] Despite the above advantages, benzocyclobutene has high solubility in a wide range of solvents at room temperature. In some embodiments, benzocyclobutene can absorb aqueous solutions by nature, resulting in moisture (or impurities) entering the benzocyclobutene material layer. During reliability testing, semiconductor devices including benzocyclobutene are prone to failure due to moisture absorption. In some embodiments, biased highly accelerated stress test (bHAST) can combine the parameters of voltage bias, high temperature, high humidity, high pressure, and time to test the reliability of semiconductor devices. In a specific case, the semiconductor device can be tested at a voltage bias between 3V and 6V, a temperature of 130°C, a relative humidity of 85%, a pressure of 33.3 psia, and a time of 96 hours. In short, biased highly accelerated stress test can be used as a corrosion failure test, which reveals defects in package seals, materials, or connections in a very short time. Therefore, semiconductor devices containing benzocyclobutene may often encounter reliability issues.

[0070] Conventionally, for the prior art known to those skilled in the art, the application of benzocyclobutene materials may lead to reliability failure (such as bias high accelerated stress test). According to some embodiments of the present disclosure, an adhesive layer may be introduced and inserted between the insulating film of benzocyclobutene and the electroplated conductive structure. The placement of the adhesive layer can minimize the moisture entering the benzocyclobutene material. As a result, the reliability of the semiconductor device (such as bias high accelerated stress test) can be improved.

[0071] Figure 1FIG. 1 is a schematic cross-sectional view of a semiconductor device 10 according to some embodiments of the present disclosure. In some embodiments, the semiconductor device may include any number of active components and passive components. The active components may include metal-oxide semiconductor (MOS) transistors, complementary metal-oxide semiconductor (CMOS) transistors, laterally diffused metal-oxide semiconductor (LDMOS) transistors, bipolar complementary metal oxide semiconductor-double diffused metal oxide semiconductor (BCD) transistors, bipolar junction transistors (BJT), planar transistors, fin field-effect transistors (FinFET), gate-all-around field-effect transistors (GAA FET), other similar devices, or combinations thereof. The passive components may include metal traces, capacitors, inductors, resistors, diodes, bonding pads, or other similar structures. For simplicity, FIG. 1 only illustrates one transistor structure. According to some embodiments of the present disclosure, the transistor structure may be a high electron mobility transistor. The semiconductor device 10 may be divided into a source region 10S, a drain region 10D, and a gate region 10G of the transistor structure (such as a high electron mobility transistor). The source region 10S and the drain region 10D may be located at opposite sides of the gate region 10G.

[0072] Reference Figure 1, the semiconductor device 10 may include a substrate 100, an epitaxial layer 200, an ohmic layer 320, a gate structure 340, a metal layer 360, a dielectric layer 380, an insulating film 400, a metal layer 420, a dielectric layer 440, a metal layer 460, a dielectric layer 480, an insulating film 500, an adhesive layer 520, a seed layer 540, a metal layer 560, an adhesive layer 580, and an insulating film 600. The substrate 100, the epitaxial layer 200, the dielectric layer 380, the insulating film 400, the dielectric layer 440, the dielectric layer 480, the insulating film 500, the adhesive layer 520, the adhesive layer 580, and the insulating film 600 may extend across the source region 10S, the drain region 10D, and the gate region 10G. The ohmic layer 320, the metal layer 360, the metal layer 420, the metal layer 460, and the seed layer 540 may be disposed in the source region 10S and the drain region 10D, and the gate structure 340 may be disposed in the gate region 10G. The metal layer 560 may extend beyond the source region 10S or the drain region 10D. The seed layer 540 and the metal layer 560 may be considered together as a first conductive structure, which is electrically connected to the metal layer 460 through the via 500V.

[0073] Continue to refer to Figure 1The substrate 100 may be, for example, a wafer or a die, but the disclosed embodiment is not limited thereto. In some embodiments, the substrate 100 may be a semiconductor substrate, such as a silicon (Si) substrate. In addition, in some embodiments, the semiconductor substrate may also be: an elemental semiconductor, including germanium (Ge); a compound semiconductor, including gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); an alloy semiconductor, including silicon germanium (SiGe) alloy, gallium arsenide phosphide (GaAsP) alloy, aluminum indium arsenide (AlInAs) alloy, aluminum gallium arsenide (AlGaAs) alloy, gallium indium arsenide (GaAs) alloy, and / or indium antimonide (InSb). In certain embodiments of the present disclosure, the substrate 100 may be formed of any suitable III-V compound semiconductor material.

[0074] In other embodiments, the substrate 100 may also be a semiconductor on insulator (SOI) substrate. The semiconductor on insulator substrate may include a base plate, a buried oxide (BOX) layer disposed on the base plate, and a semiconductor layer disposed on the buried oxide layer. In some embodiments, the buried oxide layer may encapsulate the base plate and may be a film layer with high thermal stability at high temperatures.

[0075] In some embodiments, the substrate 100 may be of N-type or P-type conductivity. In some embodiments, the N-type dopant may include phosphorus (P), arsenic (As), silicon, selenium (Se), and tellurium (Te), and the P-type dopant may include boron (B), indium (In), aluminum (Al), carbon (C), magnesium (Mg), zinc (Zn), calcium (Ca), beryllium (Be), strontium (Sr), barium (Ba), and radium (Ra).

[0076] Reference Figure 1 , an epitaxial layer 200 may be disposed on the substrate 100. According to some embodiments of the present disclosure, the epitaxial layer 200 may include various compound semiconductor film layers (not shown for simplicity). In some embodiments, the epitaxial layer 200 may include a channel film layer, which provides an electron transmission path between the source region 10S and the drain region 10D, and the gate region 10G controls the electron flow. The material of the epitaxial layer 200 may include gallium nitride, aluminum nitride (AlN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), other similar materials, or a combination thereof. The epitaxial layer 200 may be formed by metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), other suitable methods, or a combination thereof.

[0077] Continue to refer to Figure 1, an ohmic layer 320 may be disposed on the epitaxial layer 200. According to some embodiments of the present disclosure, the ohmic layer 320 in the source region 10S and the drain region 10D may serve as the source terminal and the drain terminal of the transistor structure (eg, high electron mobility transistor) of the semiconductor device 10, respectively. The material of the ohmic layer 320 may include amorphous silicon, polysilicon, polycrystalline silicon germanium (poly-SiGe), metal nitride (such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), or other similar materials), metal silicide (such as nickel silicide (NiSi), cobalt silicide (CoSi), tantalum silicon nitride (TaSiN), or other similar materials), metal carbide (such as tantalum carbide (TaC), tantalum carbonitride (TaCN), or other similar materials), metal oxide (such as titanium oxide (TiO) or other similar materials), metal, other suitable materials, or combinations thereof, but the present disclosure is not limited thereto. The metal may include cobalt (Co), ruthenium (Ru), aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), silver (Ag), gold (Au), platinum (Pt), nickel (Ni), palladium (Pd), zinc, chromium (Cr), molybdenum (Mo), niobium (Nb), other similar materials, combinations thereof, or multiple layers thereof, but the present disclosure is not limited thereto.

[0078] The ohmic layer 320 may be formed by depositing a metal layer on the epitaxial layer 200 and then patterning the metal layer. The deposition process may include chemical vapor deposition (CVD), atomic layer deposition, physical vapor deposition (PVD), evaporation, plating, other suitable processes, or a combination thereof, but the present disclosure is not limited thereto. The patterning process may include a lithography process and an etching process, other suitable processes, or a combination thereof.

[0079] In other embodiments, a patterned photoresist layer may be first formed on the epitaxial layer 200, and then a metal layer may be deposited. During the removal of the photoresist layer, the portion of the metal layer disposed on the photoresist layer may be removed together with the photoresist layer, and the remaining portion of the metal layer becomes the ohmic layer 320 disposed in the source region 10S and the drain region 10D.

[0080] It should be understood that the ohmic layer 320 may also constitute a diode structure (not shown). In some embodiments, in addition to forming the ohmic layer 320 in the source region 10S and the drain region 10D, the ohmic layer 320 may be further provided as a P-type metal and an N-type metal in the diode structure. Before forming the ohmic layer 320, a predetermined area of ​​the epitaxial layer 200 may be recessed. The P-type metal may stand on the area of ​​the epitaxial layer 200 that is not recessed, and the N-type metal may stand on the area of ​​the epitaxial layer 200 that is recessed.

[0081] Reference Figure 1 , a gate structure 340 may be disposed on the epitaxial layer 200. According to some embodiments of the present disclosure, the gate structure 340 in the gate region 10G may serve as a gate terminal of a transistor structure (such as a high electron mobility transistor) of the semiconductor device 10. The material and formation method of the gate structure 340 may be similar to the material and formation method of the ohmic layer 320, and the details thereof will not be repeated here.

[0082] In some embodiments, the epitaxial layer 200 in the gate region 10G may be etched back to form a wide groove. The wide groove may be formed by an etching process (e.g., a wet etching process). After the wide groove is formed, a photoresist layer (not shown) may be applied. The photoresist layer may include a polymethylmethacrylate (PMMA) film layer and a polymethacrylic acid (PMAA) film layer stacked in sequence on the epitaxial layer 200 (including the wide groove) and the ohmic layer 320. For the exposure step, electron beam lithography (EBL) may be used. Electron beam lithography may write patterns of the polymethylmethacrylate film layer and the polymethacrylic acid film layer with greater spatial resolution. Due to the different material properties between polymethylmethacrylate and polymethacrylic acid, the pattern of the polymethylmethacrylate film layer may be different from the pattern of the polymethacrylic acid film layer.

[0083] After patterning the polymethyl methacrylate film layer and the polymethacrylic acid film layer, a gate groove may be formed below the wide groove. The size of the gate groove may be smaller than the size of the wide groove. The gate groove may be formed by a wet etching process. Next, a metal layer may be deposited, which may follow the profile of the patterned polymethyl methacrylate film layer and the patterned polymethacrylic acid film layer. The metal layer may be further extended through the wide groove and the gate groove, and may stand on the bottom surface of the gate groove. The metal layer having the desired profile becomes the gate structure 340, and a Schottky contact may be formed between the bottom surface of the gate structure 340 and the bottom surface of the gate groove.

[0084] like Figure 1 As shown, the lower portion of the gate structure 340 may correspond to the patterned polymethyl methacrylate film layer, and the upper portion of the gate structure 340 may correspond to the patterned polymethyl methacrylate film layer. In some embodiments, the size of the upper portion of the gate structure 340 may be designed to be larger than the size of the lower portion of the gate structure 340. The relatively larger upper portion of the gate structure 340 allows the electron flow in the channel film layer to be more effectively controlled. The size of the gate structure 340 at the Schottky contact may be defined as the gate length. A relatively small gate length may enable the semiconductor device 10 to operate at higher power and higher frequency. However, a smaller gate length may affect the breakdown performance, so a wide groove may compensate for the breakdown voltage. The gate groove may be used to reduce the gate resistance.

[0085] Continue to refer to Figure 1 , a metal layer 360 may be disposed on the ohmic layer 320. The metal layer 360 may serve as a connection between other metal layers. The material and formation method of the metal layer 360 may be similar to the material and formation method of the ohmic layer 320, and the details thereof will not be repeated here.

[0086] Reference Figure 1, a dielectric layer 380 may be conformally formed on the epitaxial layer 200, the ohmic layer 320, the gate structure 340, and the metal layer 360. In some embodiments, the dielectric layer 380 may also fill the wide groove and any remaining portion of the gate groove. According to some embodiments of the present disclosure, the dielectric layer 380 may provide mechanical protection and electrical insulation for the underlying structure. The dielectric layer 380 may be an inorganic film layer, and its material may include zirconium oxide (ZrO2), aluminum oxide (Al2O3), silicon dioxide (SiO2), silicon oxynitride (SiON), silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), aluminum nitride, titanium oxide (TiO2), hafnium oxide (HfO2), tantalum oxide (Ta2O5), other similar materials, or a combination thereof. The dielectric layer 380 may be formed by chemical vapor deposition, high-density plasma chemical vapor deposition (HDP-CVD), plasma-enhanced chemical vapor deposition (PECVD), flowable chemical vapor deposition (FCVD), sub-atmospheric chemical vapor deposition (SACVD), low-pressure chemical vapor deposition (LPCVD), atomic layer deposition, other similar methods, or a combination thereof.

[0087] Continue to refer to Figure 1, an insulating film 400 may be disposed on the dielectric layer 380. In some embodiments, the insulating film 400 may cover the epitaxial layer 200, the ohmic layer 320, the gate structure 340, and the metal layer 360. According to some embodiments of the present disclosure, the insulating film 400 may provide insulation and planarization for the intermediate structure of the semiconductor device 10. The insulating film 400 may be an organic insulating film, and its material may include benzocyclobutene. The insulating film 400 may be formed by spin-on coating, chemical vapor deposition, atomic layer deposition, other similar methods, or a combination thereof. The insulating film 400 may be subjected to a planarization process (such as chemical mechanical polishing (CMP) or other similar methods). In addition to forming a flat surface of the insulating film 400, a portion of the dielectric layer 380 on the upper portion of the metal layer 360 may be removed, and the upper portion of the metal layer 360 may protrude beyond the flat surface of the insulating film 400. This ensures a more effective electrical connection between the metal layer 360 and the subsequently formed metal layer 420.

[0088] Reference Figure 1 , a metal layer 420 may be disposed on the flat surface of the insulating film 400. In some embodiments, the metal layer 420 may cover the protruding portion of the metal layer 360. According to some embodiments of the present disclosure, the metal layer 420 may serve as a metal transmission line. The material and formation method of the metal layer 420 may be similar to the material and formation method of the ohmic layer 320, and the details thereof will not be repeated here.

[0089] Continue to refer to Figure 1 , a dielectric layer 440 may be conformally formed on the insulating film 400 and the metal layer 420. According to some embodiments of the present disclosure, the dielectric layer 440 may provide mechanical protection and electrical insulation for the underlying structure. The material and formation method of the dielectric layer 440 may be similar to the material and formation method of the dielectric layer 380, and the details thereof will not be repeated here.

[0090] Reference Figure 1 , a metal layer 460 may be disposed on the dielectric layer 440. In some embodiments, the metal layer 460 may be located above the metal layer 420. In addition, the metal layer 460 may extend through the dielectric layer 440, thereby establishing an electrical connection between the metal layer 460 and the metal layer 420. According to some embodiments of the present disclosure, the metal layer 460 may serve as a capacitor electrode and a metal transmission line. The material and formation method of the metal layer 460 may be similar to the material and formation method of the ohmic layer 320, and the details thereof will not be repeated here.

[0091] In some embodiments, a via may be formed in the dielectric layer 440 before depositing the metal layer 460. According to some embodiments of the present disclosure, a via may be considered as an opening in the dielectric layer 440 that allows electrical connections to be established between components below and above the dielectric layer 440. In a specific embodiment of the present disclosure, the via may allow the metal layer 420 and the metal layer 460 to be electrically connected for signal transmission. From a top view, the via may be arranged on the metal layer 420 in the source region 10S and the drain region 10D, respectively. From a top view, the critical dimension (CD) of the via may be between 1 μm and 500 μm. If the critical dimension of the via is too large, misalignment may occur between the via and the structure below or above. If the critical dimension of the via is too small, electrical connection may not be properly established. The via may be formed by patterning the dielectric layer 440, which includes a lithography process and an etching process.

[0092] It should be understood that the metal layer 420, the dielectric layer 440, and the metal layer 460 may also constitute a capacitor structure (not shown). In some embodiments, in addition to forming the metal layer 420, the dielectric layer 440, and the metal layer 460 in the source region 10S and the drain region 10D, the metal layer 420, the dielectric layer 440, and the metal layer 460 may be further configured as the bottom electrode, the insulating layer, and the top electrode in the capacitor structure, respectively. It should be understood that for the capacitor structure, since the bottom electrode (or metal layer 420) and the top electrode (or metal layer 460) of the capacitor structure should be insulated from each other, there may be no through hole formed in the dielectric layer 440.

[0093] Continue to refer to Figure 1 , a dielectric layer 480 may be conformally formed on the dielectric layer 440 and the metal layer 460. According to some embodiments of the present disclosure, the dielectric layer 480 may provide mechanical protection and electrical insulation for the underlying structure. The material and formation method of the dielectric layer 480 may be similar to the material and formation method of the dielectric layer 380, and the details will not be repeated here.

[0094] Reference Figure 1 , an insulating film 500 may be disposed on the dielectric layer 480. In some embodiments, the insulating film 500 may cover the insulating film 400, the metal layer 420, and the metal layer 460. According to some embodiments of the present disclosure, the insulating film 500 may provide insulation and planarization for the intermediate structure of the semiconductor device 10. The thickness of the insulating film 500 may be adjusted to improve the performance of the semiconductor device 10. The material and formation method of the insulating film 500 may be similar to the material and formation method of the insulating film 400, and the details thereof will not be repeated here.

[0095] Continue to refer to Figure 1, an adhesive layer 520 may be disposed on the insulating film 500. According to some embodiments of the present disclosure, the adhesive layer 520 may bond the insulating film 500 to the extension portion (refer to Figure 2 The thickness of the adhesive layer 520 may be, for example, The thickness of the adhesive layer 520 may be adjusted to improve the performance of the semiconductor device 10. The material and formation method of the adhesive layer 520 may be similar to the material and formation method of the dielectric layer 380, and the details will not be repeated here.

[0096] As mentioned previously, benzocyclobutene can absorb aqueous solutions in nature, which causes moisture (or impurities) to enter the insulating film 500. The first conductive structure (including the seed layer 540 and the metal layer 560) is different from the ohmic layer 320, the metal layer 360, the metal layer 420, and the metal layer 460, and can be specifically formed by an electroplating process. When the insulating film 500 is directly exposed to the electroplating process of the first conductive structure, the electroplating solution may be absorbed by the insulating film 500. As a result, the reliability of the semiconductor device 10 may suffer from serious failure.

[0097] According to some embodiments of the present disclosure, an adhesive layer 520 may be inserted between the insulating film 500 and the extension of the first conductive structure. Placing the adhesive layer 520 can minimize moisture entering the insulating film 500 and the first conductive structure. As a result, the reliability of the semiconductor device 10 (such as a bias high acceleration stress test) can be improved.

[0098] Reference Figure 1, a through hole 500V may be formed in the insulating film 500. In some embodiments, the through hole 500V may pass through the adhesive layer 520, the insulating film 500, the dielectric layer 480, and a portion of the metal layer 460. According to some embodiments of the present disclosure, the through hole 500V may be regarded as an opening in the adhesive layer 520, the insulating film 500, and the dielectric layer 480, allowing components below and above the insulating film 500 to establish electrical connections. In a specific embodiment of the present disclosure, the through hole 500V allows the metal layer 460 and the first conductive structure (including the seed layer 540 and the metal layer 560) formed subsequently to be electrically connected for signal transmission. From a top view, the through hole 500V may be arranged on the metal layer 460 in the source region 10S and the drain region 10D, respectively. From a top view, the critical dimension of the through hole 500V may be between 1μm and 500μm. If the critical dimension of the via 500V is too large, misalignment may occur between the via 500V and the structure below or above. If the critical dimension of the via 500V is too small, electrical connection may not be properly established. The via 500V may be formed by patterning the adhesive layer 520, the insulating film 500, and the dielectric layer 480 (which includes a lithography process and an etching process). The via 500V may be over-etched to remove a portion of the metal layer 460 near the top surface to form a more effective contact between the metal layer 460 and the first conductive structure.

[0099] Conventionally, forming a via through an insulating film may involve sequentially depositing a dielectric layer and a photoresist layer. The photoresist layer may be used to pattern the dielectric layer below, and the patterned dielectric layer may be used as a hard mask to form the via. The advantage of forming the via by a hard mask is that the profile of the via is more effectively controlled. However, after forming the via, both the dielectric layer and the photoresist layer may be removed, and the insulating film may be exposed to subsequent processes (such as electroplating solutions). In order to form an adhesion layer 520 on the insulating film 500, only the photoresist layer may be used to pattern the via 500V.

[0100] Continue to refer to Figure 1 , a seed layer 540 may be conformably formed on the adhesion layer 520 and into the through hole 500V. Initially, the seed layer 540 may be deposited on the entire wafer of the semiconductor device 10. According to some embodiments of the present disclosure, the seed layer 540 may make the entire wafer of the semiconductor device 10 conductive, which allows the metal layer 560 to be electroplated thereon. The thickness of the seed layer 540 may be adjusted to improve the performance of the semiconductor device 10. The material and formation method of the seed layer 540 may be similar to the material and formation method of the ohmic layer 320, and the details will not be repeated here. In a specific embodiment of the present disclosure, the seed layer 540 may include titanium tungsten (TiW), and the seed layer 540 may be formed by an electroplating process.

[0101] Reference Figure 1, a metal layer 560 may be disposed on the seed layer 540. In some embodiments, the metal layer 560 may be filled in the through hole 500V and may extend above the surface of the adhesive layer 520. According to some embodiments of the present disclosure, the first conductive structure (including the seed layer 540 and the metal layer 560) may be used as a metal trace for signal transmission. The thickness of the metal layer 560 may be adjusted to improve the performance of the semiconductor device 10. The material and formation method of the metal layer 560 may be similar to the material and formation method of the ohmic layer 320, and the details will not be repeated here. In a specific embodiment of the present disclosure, the metal layer 560 may include gold, and the metal layer 560 may be formed by an electroplating process.

[0102] In some embodiments, a patterned photoresist layer may first be formed on the seed layer 540, and the through hole 500V is exposed through the patterned photoresist layer. Afterwards, the entire wafer of the semiconductor device 10 may be immersed in a plating solution (which serves as a precursor) and a bias voltage may be applied so that a target material (such as gold) may be electroplated on the exposed seed layer 540 through redox. During the photoresist removal process, the portion of the electroplating material disposed on the photoresist layer may be removed together with the photoresist layer, and the remaining portion of the electroplating material becomes the metal layer 560 disposed in the source region 10S and the drain region 10D.

[0103] It should be understood that the photoresist removal process cannot remove the underlying seed layer 540. An additional de-plating process is required to remove the portion of the seed layer 540 that is not covered by the metal layer 560. To ensure that the seed layer 540 is completely removed, the de-plating process may over-etch to form an undercut under the metal layer 560. Figure 1 As shown, the portion of the seed layer 540 near the edge of the metal layer 560 can be partially etched away, leaving a gap vertically located between the adhesive layer 520 and the metal layer 560 (refer to Figure 2 details).

[0104] Continue to refer to Figure 1, an adhesive layer 580 may be disposed on the adhesive layer 520 and the metal layer 560. In some embodiments, the adhesive layer 580 may be deposited on the exposed portion of the adhesive layer 520 and on the top surface of the metal layer 560. The exposed portion of the adhesive layer 520 represents a portion of the adhesive layer 520 that is not covered by the first conductive structure (including the seed layer 540 and the metal layer 560). In this embodiment, the adhesive layer 580 may be formed only on the exposed horizontal surface. In some embodiments, the adhesive layer 580 does not exist on the sidewalls of the metal layer 560 and does not fill the gap vertically located between the adhesive layer 520 and the metal layer 560. According to some embodiments of the present disclosure, the adhesive layer 580 may allow the insulating film 500 to have a more excellent adhesion with the insulating film 600 formed subsequently. Although the adhesive layer 580 cannot extend on the sidewalls of the metal layer 560, the overall performance of the semiconductor device 10 will not be significantly affected. The thickness of the adhesive layer 580 may be adjusted to improve the performance of the semiconductor device 10. The material and formation method of the adhesive layer 580 may be similar to the material and formation method of the dielectric layer 380 , and the details thereof will not be repeated herein.

[0105] Reference Figure 1 , an insulating film 600 may be disposed on the adhesive layer 580. In some embodiments, the insulating film 600 may cover the metal layer 560 and the adhesive layer 580. According to some embodiments of the present disclosure, the insulating film 600 may provide insulation and planarization for the intermediate structure of the semiconductor device 10. The thickness of the insulating film 600 may be adjusted to improve the performance of the semiconductor device 10. The material and formation method of the insulating film 600 may be similar to the material and formation method of the insulating film 400, and the details thereof will not be repeated here.

[0106] Figure 2 According to some embodiments of the present disclosure, Figure 1 An enlarged schematic diagram of the marked area X. The seed layer 540 may include a connecting portion 540A and an extending portion 540B. The extending portion 540B may further include a complete segment 540B-1 and an incomplete segment 540B-2. The metal layer 560 may include a connecting portion 560A and an extending portion 560B. The gap 550 may be vertically disposed between the adhesion layer 520 and the metal layer 560. For illustrative purposes, the substrate 100, the epitaxial layer 200, the ohmic layer 320, the gate structure 340, the metal layer 360, and the dielectric layer 380 are omitted. The features of the insulating film 400, the metal layer 420, the dielectric layer 440, the metal layer 460, the dielectric layer 480, the insulating film 500, the adhesion layer 520, the seed layer 540, the metal layer 560, the adhesion layer 580, and the insulating film 600 are similar to those of the embodiment of the present invention. Figure 1 The details are similar to those shown, and will not be repeated here.

[0107] Reference Figure 2The connection portion 540A of the seed layer 540 and the connection portion 560A of the metal layer 560 may be disposed in the through hole 500V (refer to Figure 1 ). From another point of view, the connection portion 540A and the connection portion 560A can be considered as a via structure together, which electrically connects the extension portion of the first conductive structure (including the extension portion 540B and the extension portion 560B) and the metal layer 460. Since the adhesion layer 520 does not extend into the through hole 500V, the connection portion 540A of the seed layer 540 is in direct contact with the insulating film 500. The connection portion 540A of the seed layer 540 can cover the sidewall and bottom surface of the connection portion 560A of the metal layer 560. In some embodiments, the connection portion 540A of the seed layer 540 can be disposed between the insulating film 500 and the connection portion 560A of the metal layer 560.

[0108] Continue to refer to Figure 2 , the extension 540B of the seed layer 540 and the extension 560B of the metal layer 560 may be disposed on the top surface of the insulating film 500. The extension 540B of the seed layer 540 may be disposed between the top surface of the insulating film 500 and the bottom surface of the extension 560B of the metal layer 560. As previously mentioned, since the stripping process of the seed layer 540 may over-etch, the extension 540B may include a complete segment 540B-1 and an incomplete segment 540B-2. The complete segment 540B-1 may be located between the through-holes 500V, and the incomplete segment 540B-2 may be located between the through-holes 500V and the edge of the metal layer 560. Since the stripping process may etch the seed layer 540 inward from the edge of the metal layer 560, the extension 540B of the seed layer 540 may not maintain its integrity. Therefore, the adhesive layer 520 may cover and directly contact a portion of the bottom surface of the extension portion (such as the extension portion 540B) of the first conductive structure. The adhesive layer 520 may be exposed to the gap 550, which is the space generated by forming the incomplete segment 540B-2. In some embodiments, the gap 550 may be isolated from the insulating film 500 by the adhesive layer 520.

[0109] Reference Figure 2, the adhesive layer 520 may be disposed between the insulating film 500 and the insulating film 600. The adhesive layer 520 may be disposed between the insulating film 500 and the extension 540B of the seed layer 540. The adhesive layer 580 may cover and directly contact the top surface of the first conductive structure (more specifically, the top surface of the extension 560B). The adhesive layer 520 may be disposed between the insulating film 500 and the adhesive layer 580. The adhesive layer 580 may be disposed between the top surface of the first conductive structure (more specifically, the top surface of the extension 560B) and the insulating film 600. The extension of the first conductive structure (including the extension 540B and the extension 560B) may be sandwiched between the adhesive layer 520 and the adhesive layer 580. The placement of the adhesive layer 520 and the adhesive layer 580 may minimize moisture entering the insulating film 500, the insulating film 600, and the first conductive structure. As a result, the reliability of the semiconductor device 10 (eg, bias highly accelerated stress test) can be improved.

[0110] Figure 3 is a cross-sectional view of a semiconductor device 20 according to some embodiments of the present disclosure. Figure 1 , the semiconductor device 20 may further include an adhesion layer 620, a second conductive structure (including a seed layer 640 and a metal layer 660), an adhesion layer 680, and an insulating film 700. The semiconductor device 20 may be divided into a source region 20S, a drain region 20D, and a gate region 20G of a transistor structure (such as a high electron mobility transistor). The features of the substrate 100, the epitaxial layer 200, the ohmic layer 320, the gate structure 340, the metal layer 360, the dielectric layer 380, the insulating film 400, the metal layer 420, the dielectric layer 440, the metal layer 460, the dielectric layer 480, the insulating film 500, the adhesion layer 520, the seed layer 540, the metal layer 560, the adhesion layer 580, and the insulating film 600 are similar to those ... Figure 1 The details are similar to those shown, and will not be repeated here.

[0111] Reference Figure 3 , an adhesive layer 620 may be disposed on the insulating film 600. According to some embodiments of the present disclosure, the adhesive layer 620 may isolate the insulating film 600 from an extension of a second conductive structure (including a seed layer 640 and a metal layer 660) formed subsequently. The thickness of the adhesive layer 620 may be adjusted to improve the performance of the semiconductor device 20. The material and formation method of the adhesive layer 620 may be similar to the material and formation method of the adhesive layer 520, and the details thereof will not be repeated here.

[0112] According to some embodiments of the present disclosure, an adhesive layer 620 may be inserted between the insulating film 600 and the extension of the second conductive structure. Similar to the adhesive layer 520, the placement of the adhesive layer 620 may also minimize moisture entering the insulating film 600 and the second conductive structure. As a result, the reliability of the semiconductor device 20 (such as bias high acceleration stress test) may be improved.

[0113] Continue to refer to Figure 3 , a through hole 600V may be formed in the insulating film 600. In some embodiments, the through hole 600V may pass through the adhesive layer 620, the insulating film 600, the adhesive layer 580, and a portion of the metal layer 560. According to some embodiments of the present disclosure, the through hole 600V may be regarded as an opening in the adhesive layer 620, the insulating film 600, and the adhesive layer 580, allowing components below and above the insulating film 600 to establish electrical connections. In a specific embodiment of the present disclosure, the through hole 600V allows the first conductive structure (including the seed layer 540 and the metal layer 560) to be electrically connected to the second conductive structure (including the seed layer 640 and the metal layer 660) formed subsequently for signal transmission. From a top view, the through hole 600V may be arranged on the first conductive structure in the source region 20S and the drain region 20D, respectively. From a top view, the critical dimension of the through hole 600V may be between 1 μm and 500 μm. If the critical dimension of the via 600V is too large, misalignment may occur between the via 600V and the structure below or above. If the critical dimension of the via 600V is too small, electrical connection may not be properly established. The method of forming the via 600V may be similar to the method of forming the via 500V, and the details will not be repeated here.

[0114] Reference Figure 3 , a seed layer 640 may be conformably formed on the adhesive layer 620 and into the through hole 600V. Initially, the seed layer 640 may be deposited on the entire wafer of the semiconductor device 20. According to some embodiments of the present disclosure, the seed layer 640 may make the entire wafer of the semiconductor device 20 conductive, which allows the metal layer 660 to be electroplated thereon. The thickness of the seed layer 640 may be adjusted to improve the performance of the semiconductor device 20. The material and formation method of the seed layer 640 may be similar to the material and formation method of the seed layer 540, and the details will not be repeated here.

[0115] Continue to refer to Figure 3 , a metal layer 660 may be disposed on the seed layer 640. In some embodiments, the metal layer 660 may be filled in the through hole 600V and may extend above the surface of the adhesive layer 620. Furthermore, the metal layer 660 may extend beyond the source region 20S or the drain region 20D. According to some embodiments of the present disclosure, the second conductive structure (including the seed layer 640 and the metal layer 660) may be used as a bonding pad connected to an external circuit, such as a printed circuit board (PCB). The thickness of the metal layer 660 may be adjusted to improve the performance of the semiconductor device 20. The material and formation method of the metal layer 660 may be similar to the material and formation method of the metal layer 560, and the details thereof will not be repeated here.

[0116] It should be understood that the photoresist removal process cannot remove the underlying seed layer 640. An additional stripping process is required to remove the portion of the seed layer 640 that is not covered by the metal layer 660. To ensure that the seed layer 640 is completely removed, the stripping process may over-etch to form a groove under the metal layer 660. Figure 3 As shown, a portion of the seed layer 640 near the edge of the metal layer 660 may be partially etched away, leaving a gap vertically located between the adhesive layer 620 and the metal layer 660. The characteristics of the gap are similar to Figure 2 The gap 550 shown is similar and its details will not be repeated here.

[0117] Reference Figure 3 , an adhesive layer 680 may be disposed on the adhesive layer 620 and the metal layer 660. In some embodiments, the adhesive layer 680 may be deposited on the exposed portion of the adhesive layer 620 and on the top surface of the metal layer 660. The exposed portion of the adhesive layer 620 represents a portion of the adhesive layer 620 that is not covered by the second conductive structure (including the seed layer 640 and the metal layer 660). In this embodiment, the adhesive layer 680 may be formed only on the exposed horizontal surface. In some embodiments, the adhesive layer 680 does not exist on the sidewalls of the metal layer 660 and does not fill the gap vertically located between the adhesive layer 620 and the metal layer 660. According to some embodiments of the present disclosure, the adhesive layer 680 may allow the insulating film 600 to have a more excellent adhesion with the insulating film 700 formed subsequently. Although the adhesive layer 680 cannot extend on the sidewalls of the metal layer 660, the overall performance of the semiconductor device 20 will not be significantly affected. The thickness of the adhesive layer 680 may be adjusted to improve the performance of the semiconductor device 20. The material and forming method of the adhesive layer 680 may be similar to the material and forming method of the adhesive layer 580 , and the details thereof will not be repeated here.

[0118] Continue to refer to Figure 3 , an insulating film 700 may be disposed on the adhesive layer 680. In some embodiments, the insulating film 700 may cover the metal layer 660 and the adhesive layer 680. According to some embodiments of the present disclosure, the insulating film 700 may provide insulation and planarization for the intermediate structure of the semiconductor device 20. The thickness of the insulating film 700 may be adjusted to improve the performance of the semiconductor device 20. The material and formation method of the insulating film 700 may be similar to the material and formation method of the insulating film 400, and the details thereof will not be repeated here.

[0119] Reference Figure 3, the adhesive layer 620 may be disposed between the insulating film 600 and the insulating film 700. The adhesive layer 620 may be disposed between the insulating film 600 and the seed layer 640. The adhesive layer 680 may cover and directly contact the top surface of the second conductive structure. The adhesive layer 620 may be disposed between the insulating film 600 and the adhesive layer 680. The adhesive layer 680 may be disposed between the top surface of the second conductive structure and the insulating film 700. The extension of the second conductive structure may be sandwiched between the adhesive layer 620 and the adhesive layer 680. The placement of the adhesive layer 620 and the adhesive layer 680 can minimize moisture entering the insulating film 600, the insulating film 700, and the second conductive structure. As a result, the reliability of the semiconductor device 20 (such as a bias high acceleration stress test) can be improved.

[0120] Figure 4 is a cross-sectional view of a semiconductor device 30 according to another embodiment of the present disclosure. Figure 1 , the semiconductor device 30 may include an adhesion layer 590 that continuously extends on the sidewall of the metal layer 560 and fills the gap vertically located between the adhesion layer 520 and the metal layer 560. The semiconductor device 30 can be divided into a source region 30S, a drain region 30D, and a gate region 30G of a transistor structure (such as a high electron mobility transistor). The characteristics of the substrate 100, the epitaxial layer 200, the ohmic layer 320, the gate structure 340, the metal layer 360, the dielectric layer 380, the insulating film 400, the metal layer 420, the dielectric layer 440, the metal layer 460, the dielectric layer 480, the insulating film 500, the adhesion layer 520, the seed layer 540, the metal layer 560, and the insulating film 600 are similar to Figure 1 The details are similar to those shown, and will not be repeated here.

[0121] Reference Figure 4 , the adhesion layer 590 may cover the sidewalls of the extension of the first conductive structure (including the seed layer 540 and the metal layer 560). Furthermore, the adhesion layer 590 may cover and directly contact the bottom surface of the metal layer 560. In a specific embodiment of the present disclosure, the adhesion layer 590 may be formed by atomic layer deposition. Compared to the adhesion layer 580, the adhesion layer 590 may exhibit a more excellent coverage. The placement of the adhesion layer 590 may more effectively minimize moisture entering the insulating film 600 and the first conductive structure. As a result, the reliability of the semiconductor device 30 (such as a bias high acceleration stress test) may be improved.

[0122] According to some embodiments of the present disclosure, an adhesive layer 520 may be inserted between the insulating film 500 and the extension of the first conductive structure. Placing the adhesive layer 520 can minimize moisture entering the insulating film 500 and the first conductive structure. As a result, the reliability of the semiconductor device 30 (such as a bias high acceleration stress test) can be improved.

[0123] Figure 5is a cross-sectional view of a portion of a semiconductor device 40 according to another embodiment of the present disclosure. Figure 2 , the seed layer 540 of the semiconductor device 40 does not include an incomplete segment. The features of the insulating film 400, the metal layer 420, the dielectric layer 440, the metal layer 460, the dielectric layer 480, the insulating film 500, the adhesive layer 520, the seed layer 540 (including the connecting portion 540A and the extending portion 540B), the gap 550, the metal layer 560 (including the connecting portion 560A and the extending portion 560B), the adhesive layer 580, and the insulating film 600 are similar to those ... adhesive layer 580, and the insulating film 600. Figure 2 The details are similar to those shown, and will not be repeated here.

[0124] Reference Figure 5 , an extension 540B of the seed layer 540 and an extension 560B of the metal layer 560 may be disposed on the top surface of the insulating film 500. The extension 540B of the seed layer 540 may be disposed between the top surface of the insulating film 500 and the bottom surface of the extension 560B of the metal layer 560. In the present embodiment, the stripping process of the seed layer 540 may be over-etched, and the section of the extension 540B located between the through hole 500V and the edge of the metal layer 560 is completely removed. The resulting extension 540B may only remain between the through holes 500V. In some embodiments, the stripping process may etch the seed layer 540 inward from the edge of the metal layer 560 to the through hole 500V. Therefore, the adhesion layer 520 may cover and directly contact a portion of the bottom surface of the extension (such as the extension 540B) of the first conductive structure. The adhesive layer 520 may be exposed to the gap 550 , which is the space laterally located between the edge of the via 500V and the metal layer 560 .

[0125] Continue to refer to Figure 5 , the adhesive layer 520 may be disposed between the insulating film 500 and the insulating film 600. The adhesive layer 520 may be disposed between the insulating film 500 and the extension portion 540B of the seed layer 540. The adhesive layer 580 may cover and directly contact the top surface of the first conductive structure (more specifically, the top surface of the extension portion 560B). The adhesive layer 520 may be disposed between the insulating film 500 and the adhesive layer 580. The adhesive layer 580 may be disposed between the top surface of the first conductive structure (more specifically, the top surface of the extension portion 560B) and the insulating film 600. The extension portion of the first conductive structure (including the extension portion 540B and the extension portion 560B) may be sandwiched between the adhesive layer 520 and the adhesive layer 580.

[0126] According to some embodiments of the present disclosure, an adhesive layer 520 may be inserted between the insulating film 500 and the extension of the first conductive structure. Placing the adhesive layer 520 can minimize moisture entering the insulating film 500 and the first conductive structure. As a result, the reliability of the semiconductor device 40 (such as a bias high acceleration stress test) can be improved.

[0127] Conventional semiconductor devices utilize an insulating film including benzocyclobutene as an intermediate stage of planarization so that the subsequently formed conductive structure can be deposited on a flat surface. If the conductive structure directly disposed on the insulating film is formed by an electroplating process, the electroplating solution can be absorbed by the insulating film, which causes reliability failure. The disclosed embodiment incorporates an adhesive layer between the insulating film and the conductive structure. The adhesive layer can minimize the moisture of the electroplating solution that enters the insulating film and the conductive structure. As a result, the reliability of the semiconductor device can be improved.

[0128] The features of several embodiments are summarized above so that those skilled in the art can better understand the viewpoints of the present disclosure. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the present disclosure to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also understand that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and various changes, substitutions and replacements can be made without violating the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be subject to the claims. In addition, although the present disclosure has been disclosed as above with several preferred embodiments, it is not intended to limit the scope of the present disclosure.

[0129] References throughout this specification to features, advantages, or similar language do not imply that all features and advantages that may be realized using the present disclosure should or may be realized in any single embodiment of the present disclosure. Rather, language referring to features and advantages is understood to mean that a particular feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, discussions of features and advantages and similar language throughout this specification may, but do not necessarily, refer to the same embodiment.

[0130] Furthermore, in one or more embodiments, the described features, advantages, and characteristics of the present disclosure may be combined in any suitable manner. Based on the description herein, one skilled in the art will appreciate that the present disclosure may be implemented without one or more of the specific features or advantages of a particular embodiment. In other cases, additional features and advantages may be identified in certain embodiments that may not be present in all embodiments of the present disclosure.

Claims

1. A semiconductor device, characterized in that: include: a base; a first insulating film disposed on the substrate and having at least one guide hole; a second insulating film disposed on the first insulating film; a first adhesive layer disposed on the first insulating film; a first conductive structure disposed in the at least one guide hole and having an extension portion extending from a top surface of the first insulating film; and A second adhesive layer is disposed on the first conductive structure, wherein the first adhesive layer covers at least a portion of the bottom surface of the extension portion, and the second adhesive layer covers at least a portion of the top surface of the first conductive structure.

2. The semiconductor device according to claim 1, wherein The semiconductor device includes a high electron mobility transistor.

3. The semiconductor device according to claim 1, wherein: The first conductive structure includes a seed layer and a metal layer.

4. The semiconductor device according to claim 3, wherein: The seed layer is disposed in the at least one guide hole and covers the side wall of the metal layer.

5. The semiconductor device according to claim 3, wherein: The seed layer is disposed between the top surface of the first insulating film and the bottom surface of the metal layer.

6. The semiconductor device according to claim 1, wherein: The first adhesive layer is disposed between the first insulating film and the second insulating film.

7. The semiconductor device according to claim 1, wherein The second adhesive layer is disposed between the top surface of the first conductive structure and the second insulating film.

8. The semiconductor device according to claim 1, wherein The second adhesive layer covers the sidewall of the extension portion.

9. The semiconductor device according to claim 1, wherein: The first adhesive layer directly contacts the bottom surface of the extension portion, and the second adhesive layer directly contacts the top surface of the first conductive structure.

10. The semiconductor device according to claim 1, wherein The first adhesive layer and the second adhesive layer are inorganic films.

11. The semiconductor device according to claim 10, wherein: The first adhesion layer and the second adhesion layer include zirconium oxide, aluminum oxide, silicon dioxide, silicon oxynitride, silicon nitride, silicon carbonitride, silicon oxycarbonitride, aluminum nitride, titanium oxide, hafnium oxide, or tantalum oxide.

12. The semiconductor device according to claim 1, wherein The first insulating film and the second insulating film are organic insulating films.

13. The semiconductor device according to claim 12, wherein: The first insulating film and the second insulating film include benzocyclobutene.

14. The semiconductor device according to claim 1, wherein: It further includes a second conductive structure disposed on the first conductive structure.

15. A semiconductor device, characterized in that: include: A III-V compound semiconductor substrate; a first insulating film disposed on the III-V compound semiconductor substrate and having at least one guide hole; a second insulating film disposed on the first insulating film; a first adhesive layer disposed on the first insulating film; a conductive structure disposed in the at least one guide hole and on a top surface of the first insulating film; as well as A second adhesive layer is disposed on the conductive structure, wherein at least a portion of the conductive structure is sandwiched between the first adhesive layer and the second adhesive layer.

16. The semiconductor device according to claim 15, wherein: The conductive structure includes a seed layer and a metal layer.

17. The semiconductor device according to claim 16, wherein: A connecting portion of the seed layer and a connecting portion of the metal layer are disposed in the at least one guide hole, and an extending portion of the seed layer and an extending portion of the metal layer are disposed on a top surface of the first insulating film.

18. The semiconductor device according to claim 17, wherein: The connection portion of the seed layer is disposed between the first insulating film and the connection portion of the metal layer.

19. The semiconductor device according to claim 17, wherein: The first adhesive layer is disposed between the first insulating film and the extending portion of the seed layer.

20. The semiconductor device according to claim 15, wherein The first adhesive layer is disposed between the first insulating film and the second adhesive layer.

Images