Semiconductor device

Abstract

A semiconductor device includes an interconnect line, an insulating layer on the interconnect line and having an opening exposing a top surface of the interconnect line, and a redistribution pattern extending into the opening and electrically connected to the interconnect line at a bottom surface of the opening. The interconnect line is configured to provide a current path in the first direction in a region adjacent to the redistribution pattern. The opening includes a first side surface facing a first direction. A corner region of the opening protrudes away from the opening or is recessed toward the opening at an end of the first side surface of the opening when viewed in a plan view.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device including a redistribution pattern. Background Art

[0002] Semiconductor devices are widely used in the electronics industry due to their small size, multifunctional characteristics and / or low manufacturing cost. Semiconductor devices can be classified into semiconductor memory devices for storing logic data, semiconductor logic devices for processing logic data, and hybrid semiconductor devices having the functions of both semiconductor memory devices and semiconductor logic devices.

[0003] As the demand for high-speed and / or low-power electronic devices increases, the demand for high-speed and / or low-voltage semiconductor devices used therein also increases, and highly integrated semiconductor devices have been developed to miniaturize electronic devices. Therefore, various technologies for highly integrating semiconductor devices and improving electrical characteristics and reliability of semiconductor devices have been studied. Summary of the invention

[0004] Embodiments of the inventive concepts may provide a semiconductor device having improved electrical characteristics and reliability.

[0005] In one aspect, a semiconductor device may include an interconnect, an insulating layer on the interconnect and having an opening exposing a top surface of the interconnect, and a redistribution pattern extending into the opening and electrically connected to the interconnect at a bottom surface of the opening. The interconnect may be configured to provide a current path in a first direction in an area adjacent to the redistribution pattern. The opening may have a first side surface facing the first direction. When viewed in a plan view, a first corner region of the opening may protrude away from the opening at a first end of the first side surface of the opening or be recessed toward the opening.

[0006] In one aspect, a semiconductor device may include an interconnection line, an insulating layer on the interconnection line and having an opening exposing a top surface of the interconnection line, and a redistribution pattern extending into the opening and electrically connected to the interconnection line at a bottom surface of the opening. The opening may have a first side surface facing a first direction and a second side surface opposite to the first side surface. When viewed in a plan view, a first thickness of a first portion of the redistribution pattern on the first side surface may be greater than a second thickness of a second portion of the redistribution pattern on the second side surface.

[0007] In one aspect, a semiconductor device may include an interconnection line, an insulating layer on the interconnection line and having an opening exposing a top surface of the interconnection line, and a redistribution pattern extending into the opening and electrically connected to the interconnection line at a bottom surface of the opening. The opening may have a first side surface facing a first direction and a second side surface opposite to the first side surface. When viewed in a plan view, a first portion of the redistribution pattern on the first side surface and a second portion of the redistribution pattern on the second side surface may be asymmetric about an axis extending in a second direction intersecting the first direction.

[0008] In one aspect, a semiconductor device may include a semiconductor layer on a substrate and an interconnection layer on the semiconductor layer. The interconnection layer may include a lower insulating layer and a lower interconnection line in the lower insulating layer, an upper interconnection line on the lower interconnection line, an upper insulating layer on the upper interconnection line and having a first opening exposing the top surface of the upper interconnection line, a redistribution pattern extending into the first opening and electrically connected to the upper interconnection line at the bottom surface of the first opening, and a passivation layer on the redistribution pattern and having a second opening exposing the top surface of the redistribution pattern. The upper interconnection line may be configured to provide a current path in a first direction in an area adjacent to the redistribution pattern. The first opening may have a first side surface facing the first direction. When viewed in a plan view, a corner area of ​​the first opening may protrude away from the first opening or be recessed toward the first opening at an end of the first side surface of the first opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a plan view illustrating a semiconductor device according to some embodiments of the inventive concept.

[0010] Figure 2 is along Figure 1 A cross-sectional view taken along line AA'.

[0011] Figure 3 Some embodiments of the present invention are shown in FIG. Figure 2 Cross-sectional view of a semiconductor layer.

[0012] Figure 4A , Figure 5A , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14A , Fig.15 and Fig.16 is corresponding to Figure 1 Magnified view of the “P1” portion of the image.

[0013] Figure 4B , Figure 5B and Fig. 14B It is shown separately Figure 4A , Figure 5A and Fig.14A An enlarged view of the first opening.

[0014] Fig. 14C is along Fig.14A A cross-sectional view taken along line BB'.

[0015] Fig.17 is a plan view illustrating a semiconductor device according to some embodiments of the inventive concept.

[0016] Fig.18 It is shown Fig.17 Enlarged view of the “P2” portion of the image. DETAILED DESCRIPTION

[0017] Example embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings. The terms "first", "second", etc., may be used herein only to distinguish one component, layer, direction, etc. from another component, layer, direction, etc. When used herein, the terms "include", "includes ...", "includes" and / or "includes ..." specify the presence of the elements described, but do not exclude the presence of additional elements. The term "and / or" includes any and all combinations of one or more associated listed items. The term "connected" may be used herein to refer to physical and / or electrical connections. When a component or layer is referred to herein as being "directly" on it or "in direct contact" or "directly connected", there are no intervening components or layers. Similarly, when components are "close to" each other, there may be no intervening components.

[0018] Figure 1 is a plan view illustrating a semiconductor device according to some embodiments of the inventive concept. Figure 2 is along Figure 1 A cross-sectional view taken along line AA'. Figure 3 Some embodiments of the present invention are shown in FIG. Figure 2 Cross-sectional view of a semiconductor layer.

[0019] refer to Figures 1 to 3 , a substrate 10 may be provided. The substrate 10 may be a semiconductor substrate, such as a silicon substrate, a germanium substrate, or a silicon germanium substrate.

[0020] The semiconductor layer 20 may be provided on the substrate 10. The semiconductor layer 20 may include one or more field effect transistors (FETs). For example, the field effect transistor may be a metal oxide semiconductor FET (MOSFET), but embodiments of the inventive concept are not limited thereto.

[0021] The semiconductor layer 20 may include a semiconductor device, such as a semiconductor memory device configured to store logic data, a semiconductor logic device configured to process logic data, or a hybrid semiconductor device including a memory element and a logic element. Figure 3 As shown in , the semiconductor layer 20 may include a dynamic random access memory (DRAM) device corresponding to a semiconductor memory device. The DRAM device may include an active pattern ACT, a bit line BL, a bit line node contact DC electrically connecting the bit line BL to the active pattern ACT, a capacitor CAP, a storage node contact BC electrically connecting the capacitor CAP to the active pattern ACT, and a word line (not shown).

[0022] The interconnection layer 30 may be provided on the semiconductor layer 20. The interconnection layer 30 may include a lower insulating layer 320, a lower interconnection layer, an upper insulating layer 340, an upper interconnection layer, a redistribution pattern 350, a protective layer 360, and a passivation layer 370.

[0023] The lower insulating layer 320 may cover the semiconductor layer 20. The lower insulating layer 320 may include an insulating material. For example, the lower insulating layer 320 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, tetraethyl orthosilicate (TEOS), or a low-k dielectric material. In this specification, a low-k dielectric material may be defined as a material having a dielectric constant lower than that of silicon oxide, and may include, for example, SiCOH. For example, the lower insulating layer 320 may be a single layer formed of one of the above materials, or a composite layer formed of two or more of the above materials.

[0024] A lower interconnect layer may be provided in the lower insulating layer 320. The lower interconnect layer may include a lower interconnect line 310 and a lower via 315. The lower interconnect line 310 may be electrically connected to the semiconductor layer 20 and / or the upper interconnect layer through the lower via 315. In some embodiments, the lower interconnect line 310 may include a plurality of lower interconnect lines 310 located at different levels (i.e., at different distances relative to the substrate 10), and the lower via 315 may include a plurality of lower vias 315 that electrically connect the plurality of lower interconnect lines 310 to each other. For example, the lower interconnect line 310 and the lower via 315 may include a metal material (e.g., Ti, Mo, W, Co, Cu, Al, Ta, Ru, Ir, etc.).

[0025] An upper insulating layer 340 may be provided on the lower insulating layer 320. The upper insulating layer 340 may cover the lower insulating layer 320. The upper insulating layer 340 may include a first upper insulating layer 341, a second upper insulating layer 342, and a third upper insulating layer 343 sequentially stacked. The first upper insulating layer 341, the second upper insulating layer 342, and the third upper insulating layer 343 may include different insulating materials. For example, the second upper insulating layer 342 may have an etching selectivity relative to the first upper insulating layer 341 and the third upper insulating layer 343. For example, the first upper insulating layer 341 may be a high density plasma (HDP) oxide layer, the second upper insulating layer 342 may be a silicon nitride layer, and the third upper insulating layer 343 may be a TEOS layer, but embodiments of the inventive concept are not limited thereto.

[0026] An upper interconnect layer may be provided in the upper insulating layer 340. The upper interconnect layer may include an upper interconnect line 330. In the present specification, the upper interconnect line 330 may be defined as the uppermost interconnect line of the interconnect lines 310 and 330. A portion of the top surface of the upper interconnect line 330 may contact the redistribution pattern 350 through the first opening 40 to be described below, so the upper interconnect line 330 may be electrically connected to the redistribution pattern 350. Another portion of the top surface of the upper interconnect line 330 may be covered with an upper insulating layer 340 (e.g., a first upper insulating layer 341). For example, the top surface of the upper interconnect line 330 may be located at a lower level (e.g., closer to the substrate 10) than the top surface of the first upper insulating layer 341. For example, the upper interconnect line 330 may include a metal material (e.g., Ti, Mo, W, Co, Cu, Al, Ta, Ru, Ir, etc.).

[0027] The upper insulating layer 340 may include a first opening 40. The first opening 40 may penetrate the upper insulating layer 340 provided on the upper interconnect line 330. The first opening 40 may extend from the top surface of the upper insulating layer 340 to the top surface of the upper interconnect line 330. As used herein, a "top" surface may be a surface facing away from or opposite to a reference layer or surface (e.g., substrate 10), while a "bottom" surface may be a surface facing or adjacent to a reference layer or surface. The top surface and the bottom surface may be (but not necessarily are) the uppermost surface or the lowermost surface of a particular element or layer. In some embodiments, the top surface of the upper interconnect line 330 below the first opening 40 may be partially recessed, but embodiments of the inventive concept are not limited thereto.

[0028] Redistribution patterns 350 may be provided on the upper interconnection lines 330 and the upper insulating layer 340. The redistribution patterns 350 may cover inner surfaces of the first openings 40 and may extend from the inner surfaces of the first openings 40 to cover the top surface of the upper insulating layer 340. The terms "covering" or "surrounding" or "filling" as may be used herein may not require completely covering or surrounding or filling the described element or layer, but may, for example, refer to partially covering or surrounding or filling the described element or layer.

[0029] The redistribution pattern 350 may include a first portion 351, a second portion 352, and a third portion 353. The first portion 351 of the redistribution pattern 350 may be a portion of the redistribution pattern 350 provided in a region vertically overlapping with the first opening 40. The second portion 352 of the redistribution pattern 350 may be another portion of the redistribution pattern 350 provided in a region vertically overlapping with the second opening 50 to be described below. The third portion 353 of the redistribution pattern 350 may be another portion of the redistribution pattern 350 provided in a region that does not vertically overlap with the first opening 40 and the second opening 50. When viewed along a line extending in a specific direction or in a plane perpendicular to the specific direction, components or layers described as “overlapping” in a specific direction may be at least partially blocked from each other.

[0030] The first portion 351 of the redistribution pattern 350 may be provided on the inner surface of the first opening 40. Since the first portion 351 is provided along the inner surface of the first opening 40, the redistribution pattern 350 may have a recess 350r provided on the bottom surface of the first opening 40. When viewed in a plan view, the recess 350r of the redistribution pattern 350 may be surrounded by the first opening 40. When viewed in a plan view, the recess 350r may have a symmetrical or asymmetrical shape with respect to a line passing through the center of the recess 350r and perpendicular to the first direction D1.

[0031] The first portion 351 may contact the top surface of the upper interconnection line 330 at the bottom surface of the first opening 40, and thus the redistribution pattern 350 may be electrically connected to the upper interconnection line 330. Therefore, the upper interconnection line 330 may have a current path. In this specification, the current path of the upper interconnection line 330 may be defined as a path in the upper interconnection line 330 in which the current flows when the current flows between the upper interconnection line 330 and the redistribution pattern 350.

[0032] The upper interconnection line 330 may have a current path in a direction parallel to the bottom surface of the substrate 10 in a region adjacent to the redistribution pattern 350, and the parallel direction may be defined as a first direction D1. In some embodiments, the conductive contact 380 may be electrically connected to the upper interconnection line 330, and the upper interconnection line 330 may electrically connect the conductive contact 380 to the redistribution pattern 350. Here, as Figure 1 As shown, the conductive contact 380 may be spaced apart from the redistribution pattern 350 in the first direction D1, and the upper interconnection line 330 may extend in the first direction D1. Therefore, the upper interconnection line 330 may have a current path in the first direction D1 in a region adjacent to the redistribution pattern 350. In some embodiments, the conductive contact 380 may be displaced from the redistribution pattern 350 in a second direction D2 parallel to the bottom surface of the substrate 10 and intersecting the first direction D1, but the upper interconnection line 330 may extend in the first direction D1 in a region adjacent to the redistribution pattern 350 to have a current path in the first direction D1. In some embodiments, the conductive contact 380 may be a lower via 315 or another redistribution pattern, but embodiments of the inventive concept are not limited thereto.

[0033] The second portion 352 of the redistribution pattern 350 may be located below the second opening 50, which will be described in detail below, and may be exposed to the outside at the bottom surface of the second opening 50. The third portion 353 of the redistribution pattern 350 may connect the first portion 351 to the second portion 352. In some embodiments, the third portion 353 may extend in a direction parallel to the current path (i.e., the first direction D1), but embodiments of the inventive concept are not limited thereto.

[0034] In some embodiments, the redistribution pattern 350 may be formed using a physical vapor deposition (PVD) process having a poor step coverage characteristic, and thus the redistribution pattern 350 may include portions having different thicknesses.

[0035] When viewed in a cross-sectional view, the thickness of the first portion 351 on the side surface of the first opening 40 in the horizontal direction (e.g., the first direction D1) may vary according to the level. For example, the minimum thickness T1 of the first portion 351 on the side surface of the first opening 40 in the horizontal direction may be in the range of 0.1 μm to 0.5 μm. If the minimum thickness T1 is less than 0.1 μm, the current density in the first portion 351 of the redistribution pattern 350 may be too high, which may deteriorate the electrical characteristics and reliability of the semiconductor device. If the minimum thickness T1 is greater than 0.5 μm, the thickness of another portion of the redistribution pattern 350 may be too large, making it difficult to form a fine pattern of the semiconductor device.

[0036] When viewed in a cross-sectional view, a thickness T2 of the redistribution pattern 350 on the top surface of the upper insulating layer 340 in the third direction D3 (which is perpendicular to the bottom surface of the substrate 10) may be greater than a thickness T3 (in the third direction D3) of the redistribution pattern 350 on the top surface of the upper interconnection line 330. For example, the thickness T3 of the redistribution pattern 350 on the top surface of the upper interconnection line 330 may be in a range of 50% to 95% of the thickness T2 of the redistribution pattern 350 on the top surface of the upper insulating layer 340.

[0037] The protective layer 360 may cover the redistribution pattern 350 and the upper insulating layer 340. The protective layer 360 may cover the redistribution pattern 350 and the upper insulating layer 340 with a substantially uniform thickness. For example, the protective layer 360 may include at least one of silicon nitride or silicon oxynitride.

[0038] The passivation layer 370 may cover the protective layer 360. For example, the passivation layer 370 may be formed using a spin coating process. For example, the passivation layer 370 may include a polyimide-based material such as photosensitive polyimide (PSPI).

[0039] The passivation layer 370 may include a second opening 50. The second opening 50 may be formed on the redistribution pattern 350 and may define a third portion 353 of the redistribution pattern 350. The second opening 50 may penetrate the passivation layer 370 and the protective layer 360 on the redistribution pattern 350. The second opening 50 may extend from the top surface of the passivation layer 370 to the top surface of the redistribution pattern 350. In some embodiments, the top surface of the redistribution pattern 350 below the second opening 50 may be partially recessed, but embodiments of the inventive concept are not limited thereto. The second portion 352 of the redistribution pattern 350 may be exposed to the outside through the second opening 50. The redistribution pattern 350 may be electrically connected to an external device through the exposed second portion 352. The term "exposed" may be used to describe the relationship between elements (e.g., when manufacturing a completed semiconductor device), but it may not necessarily be necessary to expose a specific region, layer, structure, or other element in the context of a completed device.

[0040] In the following, reference will be made to FIG. 4A to FIG. 16 Various shapes of the first opening 40 according to some embodiments of the inventive concept are described in more detail.

[0041] Figure 4A is corresponding to Figure 1 Magnified view of the “P1” portion of the image. Figure 4B It is shown Figure 4A An enlarged view of the first opening.

[0042] refer to Figure 4A and Figure 4B, the first opening 40 may have first to fourth side surfaces 41, 42, 43, and 44. The first side surface 41 may face the first direction D1, and the second side surface 42 may be opposite to the first side surface 41. The third side surface 43 may face the second direction D2, and the fourth side surface 44 may be opposite to the third side surface 43. The width of the first opening 40 in the second direction D2 may be defined as the distance between the third side surface 43 and the fourth side surface 44, and may be defined as a first length L1. The width of the first opening 40 in the first direction D1 may be defined as the distance between the first side surface 41 and the second side surface 42, and may be defined as a second length L2. The first length L1 and the second length L2 may be equal to each other or may be different from each other.

[0043] The first opening 40 may have a corner region 40e1. The corner region 40e1 may be provided in plural. For example, four corner regions 40e1 may be provided between the first side surface 41 and the third side surface 43, between the first side surface 41 and the fourth side surface 44, between the second side surface 42 and the third side surface 43, and between the second side surface 42 and the fourth side surface 44, respectively.

[0044] The four corner regions 40e1 may protrude from the first to fourth side surfaces 41, 42, 43, and 44 toward the outside of the first opening 40 (i.e., away from the first opening 40). For example, the corner region 40e1 between the first side surface 41 and the third side surface 43 may protrude from the first side surface 41 in the first direction D1, and may protrude from the third side surface 43 in the second direction D2.

[0045] Since the four corner regions 40e1 are provided at all corners of the first opening 40, the first opening 40 may have a shape symmetrical with respect to the first direction D1 and the second direction D2 when viewed in a plan view. For example, the first side surface 41 and the second side surface 42 may have substantially the same length and may be symmetrical with respect to a line extending in the second direction D2. For example, the third side surface 43 and the fourth side surface 44 may have substantially the same length and may be symmetrical with respect to a line extending in the first direction D1.

[0046] The first portion 351 of the redistribution pattern 350 may be provided on the first opening 40. The first portion 351 may cover the first to fourth side surfaces 41, 42, 43, and 44 and the corner region 40e1 of the first opening 40, and may have a recess 350r surrounded by the first to fourth side surfaces 41 to 44 and the corner region 40e1. The redistribution pattern 350 may have a corner pattern 350e filling the corner region 40e1 of the first opening 40.

[0047] When the redistribution pattern 350 is formed, due to the characteristics of the PVD process, in a plan view, the redistribution pattern 350 may have a non-uniform thickness on the side surfaces 41, 42, 43, and 44 of the first opening 40. For example, the thickness PT1 of the redistribution pattern 350 on the first side surface 41 may be substantially equal to the thickness PT2 of the redistribution pattern 350 on the second side surface 42. For example, the redistribution pattern 350 may have a maximum thickness in a region adjacent to a central portion of each of the side surfaces 41, 42, 43, and 44 of the first opening 40, and each of the thicknesses PT1 and PT2 may mean or may refer to a maximum thickness of the redistribution pattern 350 on each of the first side surface 41 and the second side surface 42.

[0048] If the corner region 40e1 is not provided, the thickness of the redistribution pattern 350 may be relatively thin at the corner where the side surfaces of the first opening 40 meet each other, and thus the current density in the redistribution pattern 350 may be too high. This may deteriorate the electrical characteristics and reliability of the semiconductor device. According to the inventive concept, the first opening 40 may include a corner region 40e1, and the redistribution pattern 350 may have a corner pattern 350e, so that the redistribution pattern 350 may have sufficient thickness in an area adjacent to the corner region 40e1. As used herein, sufficient thickness may refer to a thickness configured to reduce or prevent current density concentration relative to at least one other portion of the redistribution pattern 350. As a result, the concentration of current density in a specific area in the redistribution pattern 350 may be reduced or minimized to improve the electrical characteristics and reliability of the semiconductor device.

[0049] The width of the corner area 40e1 in the second direction D2 may be defined as a third length L3, and the width of the corner area 40e1 in the first direction D1 may be defined as a fourth length L4. The third length L3 may be in the range of 1% to 40% of the first length L1, and the fourth length L4 may be in the range of 1% to 40% of the second length L2. If each of the third length L3 and the fourth length L4 has a value less than the corresponding numerical range, the thickness reinforcement of the redistribution pattern 350 may not be effectively achieved. If each of the third length L3 and the fourth length L4 has a value greater than the corresponding numerical range, the corner area 40e1 may be excessively larger than the side surfaces 41, 42, 43, and 44. Therefore, the corner of the first opening 40 may have a structure substantially similar to that of an opening in which the corner area 40e1 is not provided, and the thickness reinforcement of the redistribution pattern 350 may not be effectively achieved.

[0050] The corner area 40e1 may protrude a fifth length L5 in the second direction D2 or a direction opposite thereto, and may protrude a sixth length L6 in the first direction D1 or a direction opposite thereto. The fifth length L5 may be in the range of 20% to 70% of the third length L3, and the sixth length L6 may be in the range of 20% to 70% of the fourth length L4. If the fifth length L5 or the sixth length L6 has a value less than or greater than the corresponding numerical range, thickness enhancement of the redistribution pattern 350 may not be effectively achieved for reasons similar to those described for the third length L3 and the fourth length L4. Therefore, in some embodiments, one or more of the widths or lengths L3, L4, L5, L6 may be critical to achieving thickness enhancement (and associated effects on current density and reliability) as described herein.

[0051] Figure 5A is corresponding to Figure 1 Magnified view of the “P1” portion of the image. Figure 5B It is shown Figure 5A An enlarged view of the first opening.

[0052] refer to Figure 5A and Figure 5B , the first opening 40 may have an asymmetric shape about an axis or a line extending in the second direction D2. For example, a pair of corner regions 40e1 may be provided at both ends of the first side surface 41, respectively, and the corner regions 40e1 may not be provided in an area adjacent to the second side surface 42. Therefore, the first side surface 41 and the second side surface 42 may have different lengths and may be asymmetric. Both ends of the second side surface 42 may intersect with the third side surface 43 and the fourth side surface 44, respectively.

[0053] Since the corner regions 40e1 are provided at the first side surface 41 but not at the second side surface 42, the thicknesses of the redistribution pattern 350 on the first side surface 41 and the second side surface 42 may be different from each other. For example, the pair of corner regions 40e1 may be provided at both ends of the first side surface 41, and thus the thickness PT1 of the redistribution pattern 350 on the first side surface 41 may be greater than the thickness PT2 of the redistribution pattern 350 on the second side surface 42. Therefore, the redistribution pattern 350 and its recessed portions 350r may also have an asymmetric shape about an axis or with respect to a line extending in the second direction D2.

[0054] Since the upper interconnection line 330 has a current path in the first direction D1, current density may be relatively high in the redistribution pattern 350 on the first side surface 41. Therefore, the first opening 40 may have only a corner region 40e1 adjacent to the first side surface 41.

[0055] Figure 6 is corresponding to Figure 1 Magnified view of the “P1” portion of the image.

[0056] refer to Figure 6 , the corner region 40e1 may protrude in the second direction D2 or the direction opposite thereto, but may not protrude in the first direction D1 or the direction opposite thereto. Since the corner region 40e1 protrudes in the second direction D2 or the direction opposite thereto, the thickness of the redistribution pattern 350 on the first side surface 41 and the second side surface 42 may be enhanced.

[0057] The first opening 40 may have four corner regions 40e1. Since the four corner regions 40e1 are provided at all corners of the first opening 40, the first opening 40 may have a symmetrical shape with respect to the first direction D1 and the second direction D2 when viewed in a plan view. For example, the first side surface 41 and the second side surface 42 may have substantially the same length and may be symmetrical about an axis or about a line extending in the second direction D2. For example, the third side surface 43 and the fourth side surface 44 may have substantially the same length and may be symmetrical about an axis or about a line extending in the first direction D1. Since the first opening 40 has a symmetrical shape, each of the redistribution pattern 350 and its recesses 350r may also have a symmetrical shape.

[0058] However, with Figure 6 In contrast, the corner region 40e1 may protrude in the first direction D1 or a direction opposite thereto, but may not protrude in the second direction D2 or a direction opposite thereto. More generally, the embodiments described herein may include protrusion configurations similar to those specifically shown in the figures (but in different directions).

[0059] Figure 7 is corresponding to Figure 1 Magnified view of the “P1” portion of the image.

[0060] refer to Figure 7 , the first opening 40 may have an asymmetric shape about an axis or a line extending in the second direction D2. For example, a pair of corner regions 40e1 may be provided at both ends of the first side surface 41, respectively, and the corner region 40e1 may not be provided in a region adjacent to the second side surface 42. Therefore, the first side surface 41 and the second side surface 42 may have different lengths and may be asymmetric.

[0061] Due to the asymmetric arrangement of the corner area 40e1, the thicknesses of the redistribution pattern 350 on the first and second side surfaces 41 and 42 may be different from each other. Therefore, the redistribution pattern 350 and its recesses 350r may also have an asymmetric shape about an axis or relative to a line extending in the second direction D2.

[0062] Figure 8 is corresponding to Figure 1 Magnified view of the “P1” portion of the image.

[0063] refer to Figure 8 , the first opening 40 may have a corner region 40e2 that is recessed from a side surface adjacent thereto into the first opening 40. For example, four corner regions 40e2 may be provided between the first side surface 41 and the third side surface 43, between the first side surface 41 and the fourth side surface 44, between the second side surface 42 and the third side surface 43, and between the second side surface 42 and the fourth side surface 44, respectively.

[0064] Since the four corner regions 40e2 are provided at all corners of the first opening 40, the first opening 40 may have a symmetrical shape with respect to the first direction D1 and the second direction D2 when viewed in a plan view. For example, the first side surface 41 and the second side surface 42 may have substantially the same length and may be symmetrical about an axis or about a line extending in the second direction D2. For example, the third side surface 43 and the fourth side surface 44 may have substantially the same length and may be symmetrical about an axis or about a line extending in the first direction D1. Since the first opening 40 has a symmetrical shape, each of the redistribution pattern 350 and its recesses 350r may also have a symmetrical shape.

[0065] The corner area 40e2 may have a stepped shape. For example, the corner area 40e2 may have a stepped shape and may connect two side surfaces adjacent to each other. The corner area 40e2 may include one or more stepped shapes.

[0066] When the redistribution pattern 350 is formed, the size of the angled portion of the redistribution pattern 350 in the first opening 40 can be reduced due to the corner area 40e2 recessed in the first opening 40. Therefore, the redistribution pattern 350 can be formed to have a relatively uniform thickness, and a phenomenon in which the current density is too high in a specific area due to the thin thickness can be prevented or avoided. As a result, the concentration of the current density in a specific area in the redistribution pattern 350 can be reduced or minimized to improve the electrical characteristics and reliability of the semiconductor device.

[0067] Fig. 9 is corresponding to Figure 1 Magnified view of the “P1” portion of the image.

[0068] refer to Fig. 9 , the first opening 40 may have an asymmetric shape with respect to the axis or with respect to a line extending in the second direction D2. For example, a pair of corner regions 40e2 having a stepped shape may be provided at both ends of the first side surface 41, respectively, but the corner regions 40e2 may not be provided in a region adjacent to the second side surface 42. Therefore, the first side surface 41 and the second side surface 42 may have different lengths and may be asymmetric.

[0069] Due to the asymmetric arrangement of the corner area 40e2, the redistribution pattern 350 and its recess 350r may also have an asymmetric shape about an axis or relative to a line extending in the second direction D2. The redistribution pattern 350 on the first side surface 41 may have a more uniform thickness than the redistribution pattern 350 on the second side surface 42.

[0070] Since the upper interconnection line 330 has a current path in the first direction D1, current density may be relatively high in the redistribution pattern 350 on the first side surface 41. Therefore, the first opening 40 may have only a corner region 40e2 adjacent to the first side surface 41.

[0071] Fig.10 is corresponding to Figure 1 Magnified view of the “P1” portion of the image.

[0072] refer to Fig.10 The first opening 40 may have a corner area 40e2 that is recessed from the side surface adjacent thereto into the first opening 40, and the corner area 40e2 may extend in a straight line shape, also referred to as a chamfered edge or a corner. The corner area 40e2 may extend in a direction that intersects the first direction D1 and the second direction D2.

[0073] For example, the four corner regions 40e2 may extend in a straight line shape between the first side surface 41 and the third side surface 43, between the first side surface 41 and the fourth side surface 44, between the second side surface 42 and the third side surface 43, and between the second side surface 42 and the fourth side surface 44, respectively. Here, each of the four corner regions 40e2 may form an obtuse angle with each of the two side surfaces adjacent thereto, and may connect the two side surfaces to provide a chamfered edge. For example, the corner region 40e2 between the first side surface 41 and the third side surface 43 may form an obtuse angle with each of the first side surface 41 and the third side surface 43, and may connect the first side surface 41 and the third side surface 43.

[0074] Since the four corner regions 40e2 are provided at all corners of the first opening 40, the first opening 40 may have a symmetrical shape with respect to the first direction D1 and the second direction D2 when viewed in a plan view. For example, the first opening 40 may have a polygonal shape (e.g., an octagonal shape). Since the first opening 40 has a symmetrical shape, each of the redistribution pattern 350 and its recesses 350r may also have a symmetrical shape.

[0075] When forming the redistribution pattern 350, since the corner region 40e2 is recessed into the first opening 40 and forms an obtuse angle with the side surface adjacent thereto, the redistribution pattern 350 can be formed to have a relatively uniform thickness. Therefore, it is possible to prevent or avoid excessive increase in current density due to thin thickness in a specific region in the redistribution pattern 350. As a result, concentration of current density in a specific region in the redistribution pattern 350 can be reduced or minimized to improve electrical characteristics and reliability of the semiconductor device.

[0076] Fig.11 is corresponding to Figure 1 Magnified view of the “P1” portion of the image.

[0077] refer to Fig.11 , the first opening 40 may have an asymmetric shape with respect to the axis or with respect to a line extending in the second direction D2. For example, a pair of corner regions 40e2 (i.e., a pair of chamfered edges) having a straight line shape may be provided at both ends of the first side surface 41, respectively, but the corner regions 40e2 may not be provided in a region adjacent to the second side surface 42. Therefore, the first side surface 41 and the second side surface 42 may have different lengths and may be asymmetric.

[0078] Due to the asymmetric arrangement of the corner area 40e2, the redistribution pattern 350 and its recess 350r may also have an asymmetric shape about an axis or relative to a line extending in the second direction D2. The redistribution pattern 350 on the first side surface 41 may have a more uniform thickness than the redistribution pattern 350 on the second side surface 42.

[0079] Fig.12 is corresponding to Figure 1 Magnified view of the “P1” portion of the image.

[0080] refer to Fig.12, the first opening 40 may have a corner region 40e2 that is recessed into the first opening 40 from a side surface adjacent thereto and has a curved surface that protrudes toward the outside of the first opening 40 or turns away from the first opening 40. For example, four corner regions 40e2 may have convex curved surfaces between the first side surface 41 and the third side surface 43, between the first side surface 41 and the fourth side surface 44, between the second side surface 42 and the third side surface 43, and between the second side surface 42 and the fourth side surface 44, respectively.

[0081] In the case where the size of the corner area 40e2 is increased, as shown in FIG. Fig.12 As shown, the first opening 40 may have a substantially circular shape when viewed in a plan view. Therefore, each of the first to fourth side surfaces 41 , 42 , 43 , and 44 may be a portion of a curved surface forming the first opening 40 .

[0082] Since the four corner regions 40e2 are disposed at all corners of the first opening 40, the first opening 40 may have a symmetrical shape with respect to the first direction D1 and the second direction D2 when viewed in a plan view. Since the first opening 40 has a symmetrical shape, each of the redistribution pattern 350 and its recesses 350r may also have a symmetrical shape.

[0083] Fig.13 is corresponding to Figure 1 Magnified view of the “P1” portion of the image.

[0084] refer to Fig.13 , the first opening 40 may have an asymmetric shape about an axis or with respect to a line extending in the second direction D2. For example, a pair of corner areas 40e2 having a convex curved surface may be provided at both ends of the first side surface 41, respectively, but the corner area 40e2 may not be provided in an area adjacent to the second side surface 42. Therefore, the first side surface 41 and the second side surface 42 may have different lengths and may be asymmetric. For example, the first side surface 41 may be a portion of a curved surface, and the second side surface 42 may have a straight line shape extending in the second direction D2.

[0085] Due to the asymmetric arrangement of the corner area 40e2, the redistribution pattern 350 and its recess 350r may also have an asymmetric shape about an axis or relative to a line extending in the second direction D2. The redistribution pattern 350 on the first side surface 41 may have a more uniform thickness than the redistribution pattern 350 on the second side surface 42.

[0086] Fig.14A is corresponding to Figure 1 Magnified view of the “P1” portion of the image. Fig. 14B It is shown Fig.14A An enlarged view of the first opening. Fig. 14C is along Fig.14A A cross-sectional view taken along line BB'.

[0087] refer to FIG. 14A to FIG. 14C , when viewed in a cross-sectional view, the gradient or inclination angle of the first side surface 41 may be different from the gradient of the second side surface 42. More specifically, the first side surface 41 may form a first angle a1 with the top surface of the upper interconnect line 330, and the second side surface 42 may form a second angle a2 with the top surface of the upper interconnect line 330. The first angle a1 may be smaller than the second angle a2.

[0088] Since the first angle a1 and the second angle a2 have different values, the thickness of the redistribution pattern 350 on the first side surface 41 may be different from the thickness of the redistribution pattern 350 on the second side surface 42. For example, when viewed in a plan view, the thickness PT1 of the redistribution pattern 350 on the first side surface 41 may be greater than the thickness PT2 of the redistribution pattern 350 on the second side surface 42. For example, when viewed in a cross-sectional view, the minimum thickness T1a of the redistribution pattern 350 on the first side surface 41 may be greater than the minimum thickness T1b of the redistribution pattern 350 on the second side surface 42.

[0089] Since the thicknesses of the redistribution pattern 350 on the first side surface 41 and the second side surface 42 are different from each other, the redistribution pattern 350 and the recess 350r thereof may have an asymmetric shape about an axis or with respect to a line extending in the second direction D2. For example, the redistribution pattern 350 on the first side surface 41 and the redistribution pattern 350 on the second side surface 42 may be asymmetric.

[0090] Since the upper interconnection line 330 has a current path in the first direction D1, the current density in the redistribution pattern 350 on the first side surface 41 may be relatively high. Therefore, the first side surface 41 may be relatively more inclined, and thus the thickness of the redistribution pattern 350 on the first side surface 41 may be enhanced. Although not shown in the drawings, the first opening 40 may further include at least one of the above-mentioned corner regions 40e1 and 40e2.

[0091] Fig.15 is corresponding to Figure 1 Magnified view of the “P1” portion of the image. Fig.16 is corresponding to Figure 1 Magnified view of the “P1” portion of the image.

[0092] refer to Fig.15 and Fig.16, the first opening 40 may have a strip shape extending longitudinally in the first direction D1 or the second direction D2. The first opening 40 having a strip shape may have at least one of the corner regions 40e1 and 40e2 according to the aforementioned embodiments. Fig.15 and Fig.16 As shown, the first opening 40 may have four protruding corner areas 40e1. Although not shown in the drawings, the first side surface 41 and the second side surface 42 may have different gradients, such as FIG. 14A to FIG. 14C shown.

[0093] Fig.17 is a plan view illustrating a semiconductor device according to some embodiments of the inventive concept. Fig.18 It is shown Fig.17 Enlarged view of the “P2” portion of the image.

[0094] refer to Fig.17 and 18 , the upper interconnection line 330 may have a current path in the first direction D1 in a region adjacent to the redistribution pattern 350. Here, Figure 1 Differently, the third portion 353 of the redistribution pattern 350 may extend in a direction (eg, the second direction D2 ) crossing the current path.

[0095] The first opening 40 may have at least one of the corner regions 40e1 and 40e2 according to the aforementioned embodiments. Fig.18 As shown, the first opening 40 may have four protruding corner areas 40e1. Although not shown in the drawings, the first side surface 41 and the second side surface 42 may have different gradients, such as FIG. 14A to FIG. 14C shown.

[0096] According to the inventive concept, the redistribution pattern can be provided with sufficient thickness along the current path of the upper interconnection line. As a result, the concentration of current density in a specific area in the redistribution pattern caused by the current path can be reduced or minimized, thereby improving the electrical characteristics and reliability of the semiconductor device.

[0097] While embodiments of the inventive concept have been particularly shown and described, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the scope of the appended claims.

[0098] This application claims the priority of Korean Patent Application No. 10-2023-0147183 filed on October 30, 2023, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device, comprising: Interconnection lines; an insulating layer on the interconnection line and having an opening exposing a top surface of the interconnection line; as well as a redistribution pattern extending into the opening and electrically connected to the interconnection line at a bottom surface of the opening, wherein the interconnection line is configured to provide a current path in a first direction in a region adjacent to the redistribution pattern, wherein the opening comprises a first side surface facing the first direction, and Wherein, when viewed in a plan view, a first corner region of the opening protrudes away from the opening or is recessed toward the opening at a first end of the first side surface of the opening. 2 . The semiconductor device according to claim 1 , wherein a second corner region of the opening protrudes away from the opening or is recessed toward the opening at a second end of the first side surface of the opening when viewed in a plan view.

3. The semiconductor device according to claim 1 , wherein the opening further includes a second side surface opposite to the first side surface, and The first side surface and the second side surface are symmetrical about an axis extending in the first direction. 4 . The semiconductor device according to claim 3 , wherein a corner region of the opening protrudes away from the opening or is recessed toward the opening at an end of the second side surface of the opening when viewed in a plan view.

5. The semiconductor device according to claim 1 , wherein the opening further includes a second side surface opposite to the first side surface, and The first side surface and the second side surface are asymmetric about an axis extending in a second direction intersecting the first direction. 6 . The semiconductor device according to claim 5 , wherein a corner region of the opening does not protrude away from the opening or is not recessed toward the opening at an end of the second side surface of the opening when viewed in a plan view.

7. The semiconductor device according to claim 1, wherein the opening further includes a second side surface opposite to the first side surface, wherein the first corner region protrudes in a second direction intersecting the first direction, and The width of the first corner area in the first direction is in a range of 1% to 40% of the distance between the first side surface and the second side surface in the first direction. 8 . The semiconductor device according to claim 1 , wherein a minimum thickness of the redistribution pattern on the first side surface is in a range of 0.1 μm to 0.5 μm when viewed in a cross-sectional view.

9. The semiconductor device according to claim 1, wherein the opening further includes a second side surface opposite to the first side surface, and Wherein, when viewed in a plan view, a first thickness of a first portion of the redistribution pattern on the first side surface is substantially equal to or greater than a second thickness of a second portion of the redistribution pattern on the second side surface. 10 . The semiconductor device according to claim 1 , wherein the first corner region comprises a stepped shape when viewed in a plan view. 11 . The semiconductor device of claim 1 , wherein the first corner region comprises a chamfered edge when viewed in a plan view. 12 . The semiconductor device according to claim 1 , wherein the first corner region includes a curved surface that bulges toward an outside of the opening when viewed in a plan view.

13. The semiconductor device according to claim 1, wherein the opening further includes a second side surface opposite to the first side surface, and Wherein, when viewed in a plan view, the redistribution pattern on the first side surface and the redistribution pattern on the second side surface are asymmetric about an axis extending in a second direction intersecting the first direction.

14. The semiconductor device according to claim 1, wherein the redistribution pattern includes a recess on the bottom surface of the opening, and Wherein when viewed in a plan view, the recess has an asymmetric shape relative to an axis extending perpendicular to the first direction.

15. A semiconductor device comprising: Interconnection lines; an insulating layer on the interconnection line and having an opening exposing a top surface of the interconnection line; as well as a redistribution pattern extending into the opening and electrically connected to the interconnection line at a bottom surface of the opening, wherein the opening comprises a first side surface facing a first direction and a second side surface opposite to the first side surface, and Wherein, when viewed in a plan view, a first portion of the redistribution pattern on the first side surface and a second portion of the redistribution pattern on the second side surface are asymmetric about an axis extending in a second direction intersecting the first direction. 16 . The semiconductor device of claim 15 , wherein a first thickness of the first portion of the redistribution pattern on the first side surface is greater than a second thickness of the second portion of the redistribution pattern on the second side surface when viewed in a cross-sectional view. 17 . The semiconductor device according to claim 15 , wherein the redistribution pattern extends in the first direction when viewed in a plan view. 18 . The semiconductor device according to claim 15 , wherein the redistribution pattern extends in a second direction intersecting the first direction when viewed in a plan view.

19. A semiconductor device comprising: a semiconductor layer on a substrate; as well as an interconnect layer on the semiconductor layer, Wherein the interconnect layer comprises: a lower insulating layer and a lower interconnection line in the lower insulating layer; an upper interconnection line on the lower interconnection line; an upper insulating layer on the upper interconnect line and having a first opening exposing a top surface of the upper interconnect line; a redistribution pattern extending into the first opening and electrically connected to the upper interconnection line at a bottom surface of the first opening; and a passivation layer on the redistribution pattern and having a second opening exposing a top surface of the redistribution pattern, wherein the upper interconnection line is configured to provide a current path in a first direction in a region adjacent to the redistribution pattern, wherein the first opening comprises a first side surface facing the first direction, and Wherein, when viewed in a plan view, a corner region of the first opening protrudes away from the first opening or is recessed toward the first opening at an end of the first side surface of the first opening.

20. The semiconductor device of claim 19, wherein the semiconductor device comprises a DRAM device.

Images