Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a substrate which comprises a device region and an interconnection region, forming a device on the substrate in the device region, forming a dielectric layer covering the device and the substrate, forming the dielectric layer penetrating through the interconnection region and a through hole interconnection structure located in the substrate, and carrying out the thinning processing along one surface, opposite to the dielectric layer, of the substrate, and the through hole interconnection structure is exposed. According to the invention, more device functions can be realized, and the circuit diversity of the semiconductor structure is improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor packaging technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Packaging technology came into being with the invention of integrated circuits. Its main functions are to complete power distribution, signal distribution, heat dissipation and protection. With the development of chip technology, packaging technology has been continuously innovated, the packaging interconnection density has been continuously improved, the packaging thickness has been continuously reduced, and the three-dimensional packaging and system packaging methods have been continuously evolved. With the diversification of integrated circuit applications, emerging fields such as smart phones, the Internet of Things, automotive electronics, high-performance computing, 5G, and artificial intelligence have put forward higher requirements for advanced packaging. Packaging technology has developed rapidly, and innovative technologies have continued to emerge. In order to solve the problem of insufficient wiring density of organic substrates, silicon interposers (Intermolecular through-holes (TSVs) with vertical interconnects and high-density metal wiring have been developed. 2.5D packaging technology is also called wafer-level packaging. The 2.5D packaging technology is to package the chip on the silicon transfer board and use the high-density wiring on the silicon transfer board for interconnection. With the development of the semiconductor industry, the chip in the package is bonded to the bottom package body on the substrate through gold wire. Similarly, the chip in the upper package is bonded to the substrate between the two packaging layers through gold wire, and then the whole package is packaged into an integral package. 2.5D packaging is an advancement of traditional 2DIC packaging technology, which can achieve more sophisticated line and space utilization. Summary of the invention

[0003] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure.

[0004] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate, including a device area and an interconnection area; a device, located on the substrate in the device area; a dielectric layer, covering the substrate and the device; and a through-hole interconnection structure, penetrating the dielectric layer and the substrate in the interconnection area.

[0005] Optionally, some devices are electrically connected to the through-hole interconnect structure, and other devices are electrically isolated from the through-hole interconnect structure.

[0006] Optionally, the semiconductor structure further includes: a first interconnect structure, which penetrates the dielectric layer on the top of the device and is electrically connected to the device.

[0007] Optionally, the semiconductor structure further includes: a mask layer covering the first interconnect structure and the dielectric layer;

[0008] The through-hole interconnect structure also penetrates the mask layer.

[0009] Optionally, the semiconductor structure further includes: a second interconnect structure, which penetrates the mask layer on top of the first interconnect structure and is electrically connected to the first interconnect structure.

[0010] Optionally, the semiconductor structure also includes: an interconnection layer located on the mask layer, part of the interconnection layer electrically connecting the second interconnection structure with the through-hole interconnection structure, part of the interconnection layer electrically connecting the second interconnection structure on different devices, part of the interconnection layer only electrically connected to the second interconnection structure, and the remaining part of the interconnection layer only electrically connected to the through-hole interconnection structure.

[0011] Optionally, the semiconductor structure further includes: an isolation layer covering the sidewalls of the through-hole interconnection structure.

[0012] Optionally, the device comprises a transistor structure.

[0013] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a device region and an interconnection region; forming a device on the substrate in the device region; forming a dielectric layer covering the device and the substrate; forming a through-hole interconnection structure that penetrates the dielectric layer in the interconnection region and is located in the substrate; and performing a thinning process along a side of the substrate that is opposite to the dielectric layer until the through-hole interconnection structure is exposed.

[0014] Optionally, after forming a device on the substrate in the device area and before forming a dielectric layer penetrating the interconnection area and a through-hole interconnection structure located in the substrate, the formation method further includes: forming a first interconnection structure penetrating the dielectric layer on top of the device, the first interconnection structure being electrically connected to the device.

[0015] Optionally, after forming the first interconnect structure and before forming the through-hole interconnect structure, the formation method further includes: forming a first mask layer covering the dielectric layer and the first interconnect structure; in the step of forming the dielectric layer that penetrates the interconnect area and is located in the substrate, the dielectric layer and the substrate are patterned using the first mask layer as a mask.

[0016] Optionally, the step of forming a through-hole interconnection structure that penetrates the dielectric layer and the substrate in the interconnection area includes: patterning the first mask layer to form a first mask opening located in the interconnection area, the first mask opening exposing the top surface of the dielectric layer; patterning the dielectric layer and the substrate along the first mask opening to form a first opening that penetrates the dielectric layer and is located in the substrate; and forming a through-hole interconnection structure in the first opening and the first mask opening.

[0017] Optionally, the step of forming a through-hole interconnection structure in the first opening and the first mask opening includes: forming a first interconnection material layer filling the first opening and the first mask opening and covering the top of the first mask layer; removing the first interconnection material layer above the top of the first mask layer, and retaining the first interconnection material layer located in the first opening and the first mask opening as a through-hole interconnection structure.

[0018] Optionally, before forming a first interconnect material layer filling the first opening and covering the top of the first mask layer, the formation method also includes: forming an isolation layer covering the top and side walls of the first opening and the top of the first mask layer; the step of removing the first interconnect material layer above the top of the first mask layer also includes: removing the isolation layer covering the top of the first mask layer.

[0019] Optionally, thinning is performed along a side of the substrate facing away from the dielectric layer until the through-hole interconnection structure is exposed, and the formation method further includes: forming a second interconnection structure of the first mask layer penetrating the top of the first interconnection structure, the second interconnection structure being electrically connected to the first interconnection structure.

[0020] Optionally, the step of forming a second interconnect structure of the first mask layer that passes through the top of the first interconnect structure includes: forming a second mask layer covering the first mask layer; patterning the second mask layer to form a second mask opening that passes through the second mask layer and is located above the first interconnect structure; patterning the first mask layer along the second mask opening to form a second opening that passes through the first mask layer, and the second opening exposes the top of the first interconnect structure; and forming the second interconnect structure in the second opening.

[0021] Optionally, the step of forming a second interconnect structure in the second opening includes: forming a second interconnect material layer filling the second mask opening and the second opening and covering the second mask layer; removing the second interconnect material layer and the second mask layer that are higher than the first mask layer, and retaining the second interconnect material layer located in the second opening as the second interconnect structure.

[0022] Optionally, after forming the second interconnect structure of the first mask layer that passes through the top of the first interconnect structure, the formation method also includes: forming an interconnect layer covering the first mask layer and the second interconnect structure, part of the interconnect layer electrically connecting the second interconnect structure with the through-hole interconnect structure, part of the interconnect layer electrically connecting the second interconnect structure on different devices, part of the interconnect layer only electrically connected to the second interconnect structure, and the remaining part of the interconnect layer only electrically connected to the through-hole interconnect structure.

[0023] Optionally, after forming an interconnection layer covering the first mask layer and the second interconnection structure, the forming method further comprises: forming a capacitor structure on the interconnection layer electrically connected to the device.

[0024] Optionally, in the step of forming a device on the substrate in the device region, the device includes a transistor structure.

[0025] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0026] In the semiconductor structure provided by the embodiment of the present invention, the substrate includes a device area and an interconnection area, the device is located on the substrate in the device area, the dielectric layer covers the substrate and the device, and the through-hole interconnection structure runs through the dielectric layer and the substrate in the interconnection area; in the embodiment of the present invention, the substrate and the dielectric layer constitute a silicon interposer, which is used to realize interconnection with other chips during packaging. The silicon interposer composed of the substrate and the dielectric layer has a through-hole interconnection structure for realizing vertical interconnection with the outside, and also has a device for forming a circuit structure with other devices or with the outside, which is conducive to enabling the silicon interposer composed of the substrate and the dielectric layer to realize vertical interconnection while also having a device operation function, which is conducive to realizing more device functions and improving the circuit diversity of the semiconductor structure.

[0027] In the method for forming a semiconductor structure provided by an embodiment of the present invention, a substrate is provided, the substrate includes a device area and an interconnection area, a device is formed on the substrate in the device area, a dielectric layer covering the device and the substrate is formed, a through-hole interconnection structure penetrating the dielectric layer in the interconnection area and located in the substrate is formed, and a thinning process is performed along a side of the substrate facing away from the dielectric layer until the through-hole interconnection structure is exposed; in the embodiment of the present invention, the substrate and the dielectric layer constitute a silicon interposer, which is used to realize interconnection with other chips during packaging, and the silicon interposer constituted by the substrate and the dielectric layer has both a through-hole interconnection structure for realizing vertical interconnection with the outside and a device for forming a circuit structure with other devices or with the outside, which is conducive to enabling the silicon interposer constituted by the substrate and the dielectric layer to realize vertical interconnection while also having a device operation function, which is conducive to realizing more device functions and improving the circuit diversity of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a structural schematic diagram corresponding to an embodiment of a semiconductor structure of the present invention;

[0029] Figures 2 to 13 It is a schematic structural diagram corresponding to each step of an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0030] As can be seen from the background technology, the current silicon interposer only has the function of interconnection to achieve electrical connection between different chips. However, due to area size and process limitations, it can usually only inherit a system chip (SOC) and a small number of memory chips (HBM). For applications with relatively large requirements for computing power, one SOC can no longer meet the demand. Therefore, the current silicon interposer is difficult to provide computing power and it is difficult to improve the circuit diversity of the semiconductor structure.

[0031] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a device region and an interconnection region; forming a device on the substrate in the device region; forming a dielectric layer covering the device and the substrate; forming a through-hole interconnection structure that penetrates the dielectric layer in the interconnection region and is located in the substrate; and performing a thinning process along a side of the substrate that is opposite to the dielectric layer until the through-hole interconnection structure is exposed.

[0032] In the method for forming a semiconductor structure provided by an embodiment of the present invention, the substrate and the dielectric layer constitute a silicon interposer, which is used to realize interconnection with other chips during packaging. The silicon interposer composed of the substrate and the dielectric layer has a through-hole interconnection structure for realizing vertical interconnection with the outside, and also has a device for forming a circuit structure with other devices or with the outside. This is beneficial for the silicon interposer composed of the substrate and the dielectric layer to realize vertical interconnection while also having a device operation function, which is beneficial for realizing more device functions and improving the circuit diversity of the semiconductor structure.

[0033] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0034] Figure 1 It is a structural schematic diagram corresponding to an embodiment of a semiconductor structure of the present invention.

[0035] refer to Figure 1 The semiconductor structure includes: a substrate 100, including a device area 100d and an interconnection area 100t; a device 300, located on the substrate 100 in the device area 100d; a dielectric layer 200, covering the substrate 100 and the device 300; and a through-hole interconnection structure 520, penetrating the dielectric layer 200 and the substrate 100 in the interconnection area 100t.

[0036] The substrate 100 is used as a process platform for forming a semiconductor structure.

[0037] In this embodiment, the substrate 100 includes a device region 100 d and an interconnection region 100 t , wherein the device region 100 d is used as a region for forming the device 300 , and the interconnection region 100 t is used as a region for forming a through-hole interconnection structure 520 .

[0038] In this embodiment, the material of the substrate 100 is silicon, so that the substrate 100 and the dielectric layer 200 constitute a silicon interposer.

[0039] In this embodiment, a shallow trench isolation structure 110 is formed in the substrate 100 in the interconnection region 100t.

[0040] The through-hole interconnect structure 520 penetrates the shallow trench isolation structure 110 , which is beneficial for better isolation of the through-hole interconnect structure 520 from the substrate 100 .

[0041] The device 300 is used to electrically connect to an external device when the silicon interposer formed by the substrate 100 and the dielectric layer 200 is electrically connected to the outside to form a circuit structure and provide computing power.

[0042] Specifically, in this embodiment, the device 300 includes a transistor structure.

[0043] The dielectric layer 200 is used to isolate adjacent devices 300 and to isolate adjacent devices 300 from the through-hole interconnect structure 520 . The dielectric layer 200 is also used to provide a process platform for forming the through-hole interconnect structure 520 .

[0044] The material of the dielectric layer 200 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

[0045] The through hole interconnect structure 520 is used to realize the electrical connection between the substrate 100 and the dielectric layer 200 constituting the silicon interposer in the vertical direction.

[0046] In this embodiment, the substrate 100 and the dielectric layer 200 constitute a silicon interposer, which is used to realize interconnection with other chips during packaging. The silicon interposer composed of the substrate 100 and the dielectric layer 200 has a through-hole interconnection structure 520 for realizing vertical interconnection with the outside, and also has a device 300 for forming a circuit structure with other devices or with the outside. This is beneficial for the silicon interposer composed of the substrate 100 and the dielectric layer 200 to realize vertical interconnection while also having device operation functions, which is beneficial for realizing more device functions and improving the circuit diversity of the semiconductor structure.

[0047] Specifically, the through-hole interconnect structure 520 penetrates the substrate 100 and the dielectric layer 200, so that the substrate 100 and the dielectric layer 200 can be vertically connected to the circuits at both ends of the silicon interposer through the through-hole interconnect structure 520, that is, electrical connection can be achieved with other circuits through the surface of the dielectric layer 200 facing away from the substrate 100 and the surface of the substrate 100 facing away from the dielectric layer 200.

[0048] In this embodiment, the through-hole interconnect structure 520 is a through-silicon-via (TSV) structure.

[0049] The TSV structure enables the semiconductor structure to be stacked in three dimensions with a higher density and smaller dimensions, and greatly improves chip speed and reduces chip power consumption.

[0050] In this embodiment, the material of the through-hole interconnection structure 520 includes Cu, Co or W.

[0051] In this embodiment, the semiconductor structure further includes an isolation layer 500 covering the sidewalls of the through-hole interconnect structure 520 .

[0052] The isolation layer 500 is used to isolate the through-hole interconnect structure 520 from the substrate 100, thereby reducing the electrical interference between the through-hole interconnect structure 520 and the substrate 100 during the operation of the semiconductor structure. In particular, since the substrate 100 is made of silicon material and has a conductive function, it is necessary to form an isolation layer 500 to electrically isolate the through-hole interconnect structure 520 from the substrate 100.

[0053] In this embodiment, the material of the isolation layer 500 includes silicon oxide.

[0054] In this embodiment, some devices 300 are electrically connected to the through-hole interconnection structure 520 , and the remaining devices 300 are electrically isolated from the through-hole interconnection structure 520 .

[0055] Some devices 300 are electrically connected to the through-hole interconnection structure 520, so that some devices 300 are electrically connected to the outside through the through-hole interconnection structure 520, and the remaining through-hole interconnection structure 520 only realizes the electrical connection of the semiconductor structure in the vertical direction. Therefore, the remaining devices 300 are electrically isolated from the through-hole interconnection structure 520, so that the remaining devices 300 and the through-hole interconnection structure 520 do not interfere with each other.

[0056] In this embodiment, the semiconductor structure further includes: a first interconnect structure 310 that penetrates the dielectric layer 200 on the top of the device 300 and is electrically connected to the device 300 .

[0057] The first interconnect structure 310 is used to be electrically connected to the device 300 , thereby achieving electrical connection between the device 300 and the outside.

[0058] In this embodiment, the semiconductor structure further includes: a mask layer 400 covering the first interconnect structure 310 and the dielectric layer 200 .

[0059] The mask layer 400 is used as an etching mask for forming the through-hole interconnection structure 520 when forming the through-hole interconnection structure 520 , and is also used as a process platform for forming the second interconnection structure.

[0060] In this embodiment, the mask layer 400 includes a silicon nitride layer and a silicon oxide layer located on the silicon nitride layer.

[0061] Correspondingly, in this embodiment, the through-hole interconnect structure 520 also penetrates the mask layer 400 .

[0062] The through hole interconnect structure 520 also penetrates the mask layer 400 , so that the through hole interconnect structure 520 completely penetrates the silicon interposer formed by the substrate 100 and the dielectric layer 200 , thereby realizing electrical connection in the vertical direction.

[0063] In this embodiment, the semiconductor structure further includes: a second interconnect structure 320 , which penetrates the mask layer 400 on the top of the first interconnect structure 310 and is electrically connected to the first interconnect structure 310 .

[0064] The second interconnect structure 320 is electrically connected to the first interconnect structure 310 to achieve electrical connection between the first interconnect structure 310 and the outside, and accordingly achieve electrical connection between the device 300 and the outside.

[0065] In this embodiment, the semiconductor structure further includes: an interconnection layer 600, which is located on the mask layer 400, part of the interconnection layer 600 electrically connects the second interconnection structure 320 and the through-hole interconnection structure 520, part of the interconnection layer 600 electrically connects the second interconnection structure 320 on different devices 300, part of the interconnection layer 600 is only electrically connected to the second interconnection structure 320, and the remaining part of the interconnection layer 600 is only electrically connected to the through-hole interconnection structure 520.

[0066] The interconnection layer 600 is used to realize the electrical connection between the second interconnection structure 320 and the outside. Specifically, part of the interconnection layer 600 is used to realize the electrical connection between the second interconnection structure 320 and the outside in the longitudinal direction, part of the interconnection layer 600 is used to realize the electrical connection between the second interconnection structure 320 and the through-hole interconnection structure 520, and then electrically connected to the outside through the through-hole interconnection structure 520, part of the interconnection layer 600 is used to realize the electrical connection between different devices 300, and the remaining part of the interconnection layer 600 is used to realize the electrical connection of the through-hole interconnection structure 520 in the longitudinal direction.

[0067] In this embodiment, the semiconductor structure further includes: a capacitor structure located on the interconnection layer 600 electrically connected to the device 300 .

[0068] The capacitor structure is used to filter signals when the two devices 300 are transmitting signals during operation of the semiconductor structure, which is beneficial to improving the stability of signal transmission.

[0069] Figures 2 to 13 It is a schematic structural diagram corresponding to each step of an embodiment of a method for forming a semiconductor structure of the present invention.

[0070] refer to Figure 2 , providing a substrate 100, the substrate 100 includes a device region 100d and an interconnection region 100t.

[0071] The substrate 100 is used as a process platform for forming a semiconductor structure.

[0072] In this embodiment, the substrate 100 includes a device region 100 d and an interconnection region 100 t , wherein the device region 100 d is used as a region for forming the device 300 , and the interconnection region 100 t is used as a region for forming a through-hole interconnection structure 520 .

[0073] In this embodiment, the material of the substrate 100 is silicon, so that the substrate 100 and the dielectric layer 200 constitute a silicon interposer.

[0074] In this embodiment, a shallow trench isolation structure 110 is formed in the substrate 100 in the interconnection region 100t.

[0075] The subsequently formed through-hole interconnect structure penetrates the shallow trench isolation structure 110 , which is beneficial for better isolation of the through-hole interconnect structure from the substrate 100 .

[0076] Continue to refer Figure 2 , a device 300 is formed on the substrate 100 in the device region 100d.

[0077] The device 300 is used to electrically connect with external devices to form a circuit structure and provide computing capabilities when the silicon interposer formed by the substrate 100 and the subsequently formed dielectric layer is electrically connected to the outside.

[0078] Specifically, in the present embodiment, in the step of forming the device 300 on the substrate 100 in the device region 100 d , the device 300 includes a transistor structure.

[0079] Continue to refer Figure 2 , forming a dielectric layer 200 covering the device 300 and the substrate 100 .

[0080] The dielectric layer 200 is used to isolate adjacent devices 300 and to isolate adjacent devices 300 from a subsequently formed through-hole interconnection structure. The dielectric layer 200 is also used to provide a process platform for subsequently forming a through-hole interconnection structure.

[0081] The material of the dielectric layer 200 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

[0082] In this embodiment, after forming the device 300 on the substrate 100 in the device area 100d, and before subsequently forming the dielectric layer 200 penetrating the interconnection area 100t and the through-hole interconnection structure located in the substrate 100, the formation method further includes: forming a first interconnection structure 310 penetrating the dielectric layer 200 at the top of the device 300, and the first interconnection structure 310 is electrically connected to the device 300.

[0083] The first interconnect structure 310 is used to be electrically connected to the device 300 , thereby achieving electrical connection between the device 300 and the outside.

[0084] In this embodiment, after forming the first interconnect structure 310 and before subsequently forming the through-hole interconnect structure, the forming method further includes: forming a first mask layer 400 covering the dielectric layer 200 and the first interconnect structure 310 .

[0085] The first mask layer 400 is used as an etching mask for forming a through-hole interconnection structure when a through-hole interconnection structure is subsequently formed, and is also used as a process platform for subsequently forming a second interconnection structure.

[0086] In this embodiment, the first mask layer 400 includes a silicon nitride layer and a silicon oxide layer located on the silicon nitride layer.

[0087] Combined with reference Figures 3 to 6 , forming a through-hole interconnection structure 520 penetrating the dielectric layer 200 of the interconnection region 100t and located in the substrate 100.

[0088] Subsequently, the substrate 100 will be thinned along the side facing away from the dielectric layer 200 until the through-hole interconnection structure 520 is exposed. The through-hole interconnection structure 520 is used to realize the electrical connection between the substrate 100 and the silicon interposer formed by the dielectric layer 200 in the vertical direction.

[0089] In this embodiment, the substrate 100 and the dielectric layer 200 constitute a silicon interposer, which is used to realize interconnection with other chips during packaging. The silicon interposer composed of the substrate 100 and the dielectric layer 200 has a through-hole interconnection structure 520 for realizing vertical interconnection with the outside, and also has a device 300 for forming a circuit structure with other devices or with the outside. This is beneficial for the silicon interposer composed of the substrate 100 and the dielectric layer 200 to realize vertical interconnection while also having device operation functions, which is beneficial for realizing more device functions and improving the circuit diversity of the semiconductor structure.

[0090] Specifically, a thinning process is subsequently performed along a side of the substrate 100 facing away from the dielectric layer 200 until the through-hole interconnect structure 520 is exposed. The through-hole interconnect structure 520 penetrates the substrate 100 and the dielectric layer 200, so that the substrate 100 and the dielectric layer 200 can be vertically connected to the circuits at both ends of the silicon interposer through the through-hole interconnect structure 520. In other words, electrical connection can be achieved with other circuits through the side of the dielectric layer 200 facing away from the substrate 100 and the side of the substrate 100 facing away from the dielectric layer 200.

[0091] In this embodiment, the through-hole interconnect structure 520 is a through-silicon-via (TSV) structure.

[0092] The TSV structure enables the semiconductor structure to be stacked in three dimensions with a higher density and smaller dimensions, and greatly improves chip speed and reduces chip power consumption.

[0093] In this embodiment, the material of the through-hole interconnection structure 520 includes Cu, Co or W.

[0094] In this embodiment, in the step of forming the through-hole interconnection structure 520 penetrating the dielectric layer 200 and located in the substrate 100 and penetrating the interconnection region 100 t , the dielectric layer 200 and the substrate 100 are patterned using the first mask layer 400 as a mask.

[0095] Specifically, refer to Figure 3 The step of forming a through-hole interconnection structure 520 penetrating the dielectric layer 200 and the substrate 100 in the interconnection region 100t includes: patterning the first mask layer 400 to form a first mask opening 410 located in the interconnection region 100t, wherein the first mask opening 410 exposes the top surface of the dielectric layer 200.

[0096] The first mask opening 410 is used as a mask opening for patterning the dielectric layer 200 , exposing the top surface of the dielectric layer 200 in preparation for patterning the dielectric layer 200 .

[0097] In this embodiment, the dielectric layer 200 and the substrate 100 are patterned along the first mask opening 410 to form a first opening 420 penetrating the dielectric layer 200 and located in the substrate 100 .

[0098] The first opening 420 is used to provide a space for forming a through-hole interconnection structure 520 .

[0099] refer to Figure 4 Before subsequently forming a first interconnect material layer filling the first opening 420 and covering the top of the first mask layer 400 , the formation method further includes: forming an isolation layer 500 covering the top and sidewalls of the first opening 420 and the top of the first mask layer 400 .

[0100] The isolation layer 500 is used to isolate the through-hole interconnect structure 520 from the substrate 100, thereby reducing the electrical interference between the through-hole interconnect structure 520 and the substrate 100 during the operation of the semiconductor structure. In particular, since the substrate 100 is made of silicon material and has a conductive function, it is necessary to form an isolation layer 500 to electrically isolate the through-hole interconnect structure 520 from the substrate 100.

[0101] In this embodiment, the material of the isolation layer 500 includes silicon oxide.

[0102] Combined with reference Figure 5 and Figure 6 , a through-hole interconnect structure 520 is formed in the first opening 420 and the first mask opening 410 .

[0103] A through hole interconnection structure 520 is formed in the first opening 420 and the first mask opening 410 , so that the formed through hole interconnection structure 520 penetrates the silicon interposer formed by the substrate 100 and the dielectric layer 200 .

[0104] Specifically, refer to Figure 5The step of forming the through hole interconnect structure 520 in the first opening 420 and the first mask opening 410 includes: forming a first interconnect material layer 510 filling the first opening 420 and the first mask opening 410 and covering the top of the first mask layer 400 .

[0105] The first interconnect material layer 510 is used to directly form a through-hole interconnect structure 520 .

[0106] refer to Figure 6 , the first interconnect material layer 510 above the top of the first mask layer 400 is removed, and the first interconnect material layer 610 located in the first opening 420 and the first mask opening 410 is retained as the through-hole interconnect structure 520 .

[0107] In this embodiment, the first interconnect material layer 510 is planarized to remove the first interconnect material layer 510 above the top of the first mask layer 400, so that the top surface flatness of the first mask layer 400 and the through-hole interconnect structure 520 is better, providing a better process platform for subsequent process steps.

[0108] In this embodiment, the step of removing the first interconnect material layer 510 above the top of the first mask layer 400 further includes: removing the isolation layer 500 covering the top of the first mask layer 400 .

[0109] Combined with reference Figures 7 to 10 Subsequently, a thinning process is performed along a side of the substrate 100 facing away from the dielectric layer 200 until the through-hole interconnection structure 520 is exposed. The formation method also includes: forming a second interconnection structure 320 of the first mask layer 400 that penetrates the top of the first interconnection structure 310, and the second interconnection structure 320 is electrically connected to the first interconnection structure 310.

[0110] The second interconnect structure 320 is electrically connected to the first interconnect structure 310 to achieve electrical connection between the first interconnect structure 310 and the outside, and accordingly achieve electrical connection between the device 300 and the outside.

[0111] Specifically, refer to Figure 7 The step of forming the second interconnect structure 320 penetrating the first mask layer 400 on the top of the first interconnect structure 310 includes: forming a second mask layer 430 covering the first mask layer 400 .

[0112] The second mask layer 430 is used as an etching mask for forming the second interconnect structure 320 .

[0113] refer to Figure 8 , patterning the second mask layer 430 to form a second mask opening 440 penetrating the second mask layer 430 and located above the first interconnect structure 310 .

[0114] The second mask opening 440 is used as a mask opening for patterning the first mask layer 400 . The second mask opening 440 exposes the top of the first mask layer 400 to prepare for patterning the first mask layer 400 .

[0115] Continue to refer Figure 8 , the first mask layer 400 is patterned along the second mask opening 440 to form a second opening 450 penetrating the first mask layer 400 , wherein the second opening 450 exposes the top of the first interconnect structure 310 .

[0116] The second opening 450 is used to provide a space for forming the second interconnect structure 320 . The second opening 450 exposes the top of the first interconnect structure 310 , so as to prepare for forming an electrical connection between the second interconnect structure 320 and the first interconnect structure 310 .

[0117] Combined with reference Fig. 9 and Fig.10 , a second interconnect structure 320 is formed in the second opening 450 .

[0118] Specifically, refer to Fig. 9 The step of forming the second interconnect structure 320 in the second opening 450 includes forming a second interconnect material layer 330 filling the second mask opening 440 and the second opening 450 and covering the second mask layer 430 .

[0119] The second interconnect material layer 330 is used to directly form the second interconnect structure 320 .

[0120] refer to Fig.10 , remove the second interconnect material layer 330 and the second mask layer 430 above the first mask layer 400 , and retain the second interconnect material layer 330 located in the second opening 450 as the second interconnect structure 320 .

[0121] In this embodiment, the second interconnect material layer 330 is planarized to remove the second interconnect material layer 330 and the second mask layer 430 that are higher than the top of the first mask layer 400, so that the top surface flatness of the first mask layer 400 and the second interconnect structure 320 is better, providing a better process platform for subsequent process steps.

[0122] refer to Fig.11 After forming the second interconnect structure 320 of the first mask layer 400 that penetrates the top of the first interconnect structure 310, the formation method further includes: forming an interconnect layer 600 covering the first mask layer 400 and the second interconnect structure 320, a portion of the interconnect layer 600 electrically connecting the second interconnect structure 320 with the through-hole interconnect structure 520, a portion of the interconnect layer 600 electrically connecting the second interconnect structure 320 on different devices 300, a portion of the interconnect layer 600 electrically connecting only the second interconnect structure 320, and the remaining portion of the interconnect layer 600 electrically connecting only the through-hole interconnect structure 520.

[0123] The interconnection layer 600 is used to realize the electrical connection between the second interconnection structure 320 and the outside. Specifically, part of the interconnection layer 600 is used to realize the electrical connection between the second interconnection structure 320 and the outside in the longitudinal direction, part of the interconnection layer 600 is used to realize the electrical connection between the second interconnection structure 320 and the through-hole interconnection structure 520, and then electrically connected to the outside through the through-hole interconnection structure 520, part of the interconnection layer 600 is used to realize the electrical connection between different devices 300, and the remaining part of the interconnection layer 600 is used to realize the electrical connection of the through-hole interconnection structure 520 in the longitudinal direction.

[0124] refer to Fig.12 After forming the interconnection layer 600 covering the first mask layer 400 and the second interconnection structure 320 , the forming method further includes: forming a capacitor structure on the interconnection layer 600 electrically connected to the device 300 .

[0125] The capacitor structure is used to filter signals when the two devices 300 are transmitting signals during operation of the semiconductor structure, which is beneficial to improving the stability of signal transmission.

[0126] refer to Fig.13 , a thinning process is performed along the side of the substrate 100 facing away from the dielectric layer 200 until the through hole interconnection structure 520 is exposed.

[0127] The substrate 100 is thinned along the side facing away from the dielectric layer 200 until the through hole interconnection structure 520 is exposed, so that the through hole interconnection structure 520 penetrates the substrate 100 and the dielectric layer 200 to form a silicon interposer, thereby realizing electrical connection between the substrate 100 and the dielectric layer 200 in the vertical direction.

[0128] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, including a device region and an interconnect region; A device, located on the substrate in the device area; A dielectric layer covering the substrate and the device; The through-hole interconnection structure penetrates the dielectric layer and the substrate in the interconnection area.

2. The semiconductor structure according to claim 1, wherein: Some of the devices are electrically connected to the through-hole interconnection structure, and the remaining devices are electrically isolated from the through-hole interconnection structure.

3. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes: a first interconnect structure, which penetrates the dielectric layer on the top of the device and is electrically connected to the device.

4. The semiconductor structure according to claim 3, characterized in that The semiconductor structure further includes: a mask layer covering the first interconnect structure and the dielectric layer; The through hole interconnect structure also penetrates the mask layer.

5. The semiconductor structure according to claim 3, wherein: The semiconductor structure further includes: a second interconnect structure, which penetrates the mask layer on the top of the first interconnect structure and is electrically connected to the first interconnect structure.

6. The semiconductor structure according to claim 5, characterized in that The semiconductor structure also includes: an interconnection layer, located on the mask layer, part of the interconnection layer electrically connecting the second interconnection structure with the through-hole interconnection structure, part of the interconnection layer electrically connecting the second interconnection structures on different devices, part of the interconnection layer electrically connecting only the second interconnection structure, and the remaining part of the interconnection layer electrically connecting only the through-hole interconnection structure.

7. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes an isolation layer covering the sidewalls of the through hole interconnection structure.

8. The semiconductor structure according to claim 1, wherein: The device includes a transistor structure.

9. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a device region and an interconnection region; forming a device on the substrate in the device region; forming a dielectric layer covering the device and the substrate; forming a through-hole interconnection structure penetrating the dielectric layer of the interconnection region and located in the substrate; A thinning process is performed along a side of the substrate facing away from the dielectric layer until the through-hole interconnection structure is exposed.

10. The method for forming a semiconductor structure according to claim 9, wherein: After forming a device on the substrate in the device area and before forming a through-hole interconnection structure that penetrates the dielectric layer in the interconnection area and is located in the substrate, the formation method further includes: forming a first interconnection structure that penetrates the dielectric layer on the top of the device, and the first interconnection structure is electrically connected to the device.

11. The method for forming a semiconductor structure according to claim 10, wherein: After forming the first interconnect structure and before forming the through-hole interconnect structure, the forming method further comprises: forming a first mask layer covering the dielectric layer and the first interconnect structure; In the step of forming a through-hole interconnection structure that penetrates the dielectric layer of the interconnection region and is located in the substrate, the dielectric layer and the substrate are patterned using the first mask layer as a mask.

12. The method for forming a semiconductor structure according to claim 11, wherein: The step of forming a through-hole interconnection structure penetrating the dielectric layer and the substrate in the interconnection region comprises: patterning the first mask layer to form a first mask opening located in the interconnection region, wherein the first mask opening exposes the top surface of the dielectric layer; Patterning the dielectric layer and the substrate along the first mask opening to form a first opening penetrating the dielectric layer and located in the substrate; The through-hole interconnect structure is formed in the first opening and the first mask opening.

13. The method for forming a semiconductor structure according to claim 12, wherein: The step of forming the through-hole interconnect structure in the first opening and the first mask opening includes: forming a first interconnect material layer filling the first opening and the first mask opening and covering the top of the first mask layer; The first interconnect material layer above the top of the first mask layer is removed, and the first interconnect material layer located in the first opening and the first mask opening is retained as the through-hole interconnect structure.

14. The method for forming a semiconductor structure according to claim 12, wherein: Before forming the first interconnect material layer filling the first opening and covering the top of the first mask layer, the forming method further includes: forming an isolation layer covering the top and sidewalls of the first opening and the top of the first mask layer; The step of removing the first interconnect material layer above the top of the first mask layer further includes: removing the isolation layer covering the top of the first mask layer.

15. The method for forming a semiconductor structure according to claim 11, wherein: The substrate is thinned along a side facing away from the dielectric layer until the through-hole interconnection structure is exposed. The forming method further comprises: forming a second interconnection structure of the first mask layer penetrating the top of the first interconnection structure, the second interconnection structure being electrically connected to the first interconnection structure.

16. The method for forming a semiconductor structure according to claim 15, wherein: The step of forming a second interconnect structure through the first mask layer on top of the first interconnect structure includes: forming a second mask layer covering the first mask layer; Patterning the second mask layer to form a second mask opening penetrating the second mask layer and located above the first interconnect structure; Patterning the first mask layer along the second mask opening to form a second opening penetrating the first mask layer, wherein the second opening exposes the top of the first interconnect structure; The second interconnect structure is formed in the second opening.

17. The method for forming a semiconductor structure according to claim 16, wherein: The step of forming the second interconnect structure in the second opening includes: forming a second interconnect material layer filling the second mask opening and the second opening and covering the second mask layer; The second interconnect material layer higher than the first mask layer and the second mask layer are removed, and the second interconnect material layer located in the second opening is retained as the second interconnect structure.

18. The method for forming a semiconductor structure according to claim 15, wherein: After forming the second interconnect structure of the first mask layer that penetrates the top of the first interconnect structure, the formation method further includes: forming an interconnect layer covering the first mask layer and the second interconnect structure, part of the interconnect layer electrically connecting the second interconnect structure with the through-hole interconnect structure, part of the interconnect layer electrically connecting the second interconnect structure on different devices, part of the interconnect layer electrically connecting only the second interconnect structure, and the remaining part of the interconnect layer electrically connecting only the through-hole interconnect structure.

19. The method for forming a semiconductor structure according to claim 18, wherein: After forming an interconnection layer covering the first mask layer and the second interconnection structure, the forming method further comprises: forming a capacitor structure on the interconnection layer electrically connected to the device.

20. The method for forming a semiconductor structure according to claim 9, wherein: In the step of forming a device on the substrate in the device region, the device includes a transistor structure.

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