Semiconductor module

Abstract

The invention provides a semiconductor module capable of reducing mounting difficulty while reducing parasitic inductance. This semiconductor module arrangement is provided with: a plurality of semiconductor chips arranged inside a molded resin (M); and a plurality of terminals (a first power supply terminal (51), a first second power supply terminal (52), a second power supply terminal (53), a first midpoint terminal (61), and a second midpoint terminal (62)), the respective inner lead portions of which are positioned inside the molded resin (M), and the respective outer lead portions of which are positioned outside the molded resin (M). The electric connector is characterized in that the outer lead part of the first power supply terminal 51 is provided with a front end branch structure 51B in which the front end of the terminal is divided into a plurality of branches.

Description

Technical Field

[0001] The invention relates to a semiconductor module. Background Art

[0002] In the past, bridge circuits composed of multiple semiconductor chips have been widely used. In bridge circuits, losses and ringing sometimes occur due to parasitic inductance within the circuit. In particular, when wide-bandgap semiconductors are used as semiconductor chips, parasitic inductance within the circuit becomes the main cause due to their high conversion rate and high operating frequency, and losses and ringing are prone to occur. Parasitic inductance depends on the wiring path length (also called current path length), so modularization is also considered to reduce parasitic inductance (for example, refer to Patent Document 1).

[0003] In addition, if Fig. 9 As shown, the semiconductor device 900 disclosed in Patent Document 1 includes: first to fourth semiconductor chips Q1 to Q4, a first power supply terminal 911, a second power supply terminal 912, a first midpoint terminal 921 and a second midpoint terminal 922, and constitutes a bridge circuit.

[0004]

Prior Technology Documents

[0005] [Patent Document 1] International Publication No. 2020 / 241239

[0006] However, although the parasitic inductance can be reduced by shortening and thickening the wiring, the parasitic inductance reduction effect is not sufficient because the semiconductor module having the above-mentioned current path is simply modularized, which has become a problem. In addition, if the terminal width is simply increased, the thermal capacity of the terminal will increase due to the terminal width, making it more difficult to mount the semiconductor module using a conductive bonding material (for example, solder).

[0007] Therefore, the present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a semiconductor module capable of reducing parasitic inductance and reducing the difficulty of mounting. Summary of the invention

[0008] The semiconductor module of the present invention comprises: a plurality of semiconductor chips arranged inside a molded resin; and a plurality of terminals, each inner lead portion being located on the inner side of the molded resin and each outer lead portion being located on the outer side of the molded resin, characterized in that: a width of at least one of the plurality of terminals is set to have a desired inductance, and the outer lead portion has a front end branch structure in which the front end of the terminal branches into a plurality of terminals.

[0009] Effects of the Invention

[0010] In the semiconductor module of the present invention, the width of at least one of the plurality of terminals is set to have a desired inductance, and the outer lead portion has a front end branch structure in which the front end of the terminal branches into a plurality of branches. Therefore, according to the semiconductor module of the present invention, for at least one of the plurality of terminals, even if the parasitic inductance is expanded to a terminal width (a width having a desired inductance) in which the parasitic inductance does not increase significantly from the inner lead portion to the outer lead portion, the increase in the width of the front end of the terminal can be suppressed by the front end branch structure, thereby reducing the heat capacity of the mounting portion and achieving a reduction in the difficulty of mounting. Therefore, the semiconductor module of the present invention is a semiconductor module that can reduce both parasitic inductance and mounting difficulty. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a plan view of the internal structure of the semiconductor module 1 according to the first embodiment.

[0012] Figure 2 1 is a front view and a rear view of the semiconductor module 1 according to the first embodiment. Figure 2 (a) is a front view of the semiconductor module 1 (a view when viewed from the first power terminal 51, the first second power terminal 52, and the second second power terminal 53). Figure 2 (b) is a rear view of the semiconductor module 1 (a view when viewed from the first midpoint terminal 61 and the second midpoint terminal 62). Figure 2 (a) and Figure 2 (b) The reference numerals are shown only on the terminals near the viewpoint in the drawing. This also applies to the Figure 6 and 8 .

[0013] Figure 3 This is a plan view of the internal structure of a semiconductor module 1A prepared for comparison with the semiconductor module 1 according to the first embodiment.

[0014] Figure 4 This is a graph showing the relationship between frequency and inductance in the semiconductor module 1 and the semiconductor module 1A according to the first embodiment. Figure 4 1 is a graph showing the result of an inductance simulation of a wiring path when both the first semiconductor chip Q1 and the fourth semiconductor chip Q4 are turned on.

[0015] Figure 5 It is a plan view showing the internal structure of the semiconductor module 2 according to the second embodiment.

[0016] Figure 6 2 are a front view and a rear view of a semiconductor module 2 according to Embodiment 2. Figure 6 (a) is a front view of the semiconductor module 2 (viewed from the first power terminal 51a and the second power terminal 52a side). Figure 6(b) is a rear view of the semiconductor module 2 (a view when viewed from the first midpoint terminal 61 a and the second midpoint terminal 62 a side).

[0017] Figure 7 It is a plan view of the internal structure of the semiconductor module 3 according to the third embodiment.

[0018] Figure 8 3 are the front view and the rear view of the semiconductor module 3 of the third embodiment. Figure 8 (a) is a front view of the semiconductor module 3 (viewed from the first power terminal 51b and the second power terminal 52b side). Figure 8 (b) is a rear view of the semiconductor module 3 (viewed from the midpoint terminal 61b side).

[0019] Fig. 9 This is a plan view of the internal structure of the semiconductor device in Patent Document 1. DETAILED DESCRIPTION

[0020] Hereinafter, the semiconductor module of the present invention will be described based on the various embodiments shown in the accompanying drawings. In the various embodiments described below, for structural elements having substantially the same function, even if the shapes are slightly different, the same symbols may be used across the embodiments, and the repeated descriptions may be omitted. The various embodiments described below do not limit the invention involved in the claims. In addition, not all the elements and their combinations described in the various embodiments are necessary for the solution means of the present invention.

[0021] [Implementation method 1]

[0022] Below, refer to Figure 1 and Figure 2 The internal structure of the semiconductor module 1 of the first embodiment is described. Figure 1 As shown, the semiconductor module 1 according to the first embodiment includes a plurality of semiconductor chips disposed inside a mold resin M and a plurality of terminals.

[0023] The semiconductor module 1 is sealed with a mold resin M. Figure 1 The internal structure of the semiconductor module 1 is shown in FIG. 1 , and only the outer edge is shown for the molded resin M. This also applies to the semiconductor module 1 to be described later. Figure 3 , 5 and 7.

[0024] In addition, the semiconductor module 1 includes four semiconductor chips (first to fourth semiconductor chips Q1 to Q4) as a plurality of semiconductor chips, and also includes a first power terminal 51, a second power terminal, a first midpoint terminal 61, and a second midpoint terminal 62 as a plurality of terminals. Further, the semiconductor module 1 includes a first second power terminal 52 and a second second power terminal 53 as second power terminals. The semiconductor module 1 is a semiconductor module that constitutes a bridge circuit. The first power terminal 51, the second power terminal (the first second power terminal 52 and the second second power terminal 53), the first midpoint terminal 61, and the second midpoint terminal 62 as a plurality of terminals have their respective inner lead portions located inside the molded resin M, and their respective outer lead portions located outside the molded resin M.

[0025] In addition, in addition to the above-mentioned components, the semiconductor module 1 also includes the first to fifth wiring patterns 10 to 50, a substrate 70, the first to fourth connecting members 81 to 84, the first to fourth control connecting members (not shown in the figure), the first to fourth detection connecting members (not shown in the figure), the first to fourth control wiring patterns 111 to 114, the first to fourth detection wiring patterns 121 to 124, the first to fourth control terminals T11 to T14, and the first to fourth detection terminals T21 to T24. The semiconductor module 1 may also have components other than the above-mentioned components. In the semiconductor module 1, a bridge circuit is configured in which the first semiconductor chip Q1 and the third semiconductor chip Q3 are set to the high side and the second semiconductor chip Q2 and the fourth semiconductor chip Q4 are set to the low side.

[0026] The first power supply terminal 51, the first second power supply terminal 52 and the second second power supply terminal 53 function as input power supply terminals, and the first midpoint terminal 61 and the second midpoint terminal 62 function as output power supply terminals. In such a bridge circuit, the operation of turning on the first semiconductor chip Q1 and the fourth semiconductor chip Q4 and the operation of turning on the third semiconductor chip Q3 and the second semiconductor chip Q2 are repeated alternately. The bridge circuit is formed on a substrate 70.

[0027] When the first semiconductor chip Q1 and the fourth semiconductor chip Q4 are both turned on, the third semiconductor chip Q3 and the second semiconductor chip Q2 are both turned off. In addition, when the third semiconductor chip Q3 and the second semiconductor chip Q2 are both turned on, the first semiconductor chip Q1 and the fourth semiconductor chip Q4 are both turned off. In this specification, the description of the semiconductor chip being turned off is omitted.

[0028] In the first power terminal 51, the maximum width of the inner lead portion and the maximum width of the outer lead portion are wider than the maximum width of the inner lead portion and the maximum width of the outer lead portion of the first second power terminal 52 and the second second power terminal 53. In addition, in the first power terminal 51, the width of the boundary between the inner lead portion and the outer lead portion is wider than the width of the boundary between the inner lead portion and the outer lead portion of the first second power terminal 52 and the second second power terminal 53.

[0029] In the semiconductor module 1, the width of at least one of the plurality of terminals is set to have a desired inductance, and the outer lead portion has a front end branch structure in which the terminal front end branches into a plurality of branches. In the present specification, "the width is set to have a desired inductance" means that the minimum width of the portion without the front end branch structure is more than twice the maximum width of the terminal front end after branching. To illustrate a specific example of "a width having a desired inductance", for example, when the wiring length from the front end of the front end branch structure of the first power terminal 51 (the front end two-branch structure described later) to the boundary between the inner lead portion and the outer lead portion is 6.5 mm, the terminal width (the minimum width in the portion without the front end branch structure) is 3.5 mm. Of course, the present invention is not limited to the above values.

[0030] In addition, the "terminal width" in this specification refers to the longest length of the terminal along the direction perpendicular to the direction of current flow and parallel to the surface of the terminal. In a semiconductor module such as the semiconductor module 1, the terminal width is often equivalent to the width of the surface when viewed from above. In addition, in this specification, the "branch structure of the front end of the terminal in which the front end of the terminal branches into multiple branches" includes not only a structure in which only the front end of the terminal branches into multiple branches, but also a structure in which the terminal branches into multiple branches from the base end portion to the front end terminal. In the semiconductor module 1, among the first power terminal 51, the first second power terminal 52 and the second second power terminal 53, only the outer lead portion of the first power terminal 51 has a front end branch structure 51B (refer to Figure 2 (a)).

[0031] In the first power terminal 51 and the second power terminal (the first second power terminal 52 and the second second power terminal 53), the maximum width of the inner lead portion is wider than the maximum width of the outer lead portion. In addition, at least one of the first power terminal 51 and the second power terminal (the first power terminal 51 in the first embodiment) has a front end branch structure 51B outside the molded resin M.

[0032] In this specification, “having a front end branching structure outside the molded resin” means that the branching of the terminal starts outside the molded resin (the branching point of the terminal exists outside the molded resin).

[0033] The first midpoint terminal 61 and the second midpoint terminal 62 have front end support structures 61B and 62B (see Figure 2 (b)). In the first midpoint terminal 61 and the second midpoint terminal 62, the maximum width of the inner lead portion is also wider than the maximum width of the outer lead portion. In addition, the first midpoint terminal 61 and the second midpoint terminal 62 have front end branch structures 61B and 62B outside the molding resin M, respectively.

[0034] In the semiconductor module 1, each of the front end branch structures 51B, 61B, 62B in the first power terminal 51, the first midpoint terminal 61, and the second midpoint terminal 62 is a front end branch structure in which the front end of the terminal is branched into two. The maximum width of the lead portion in each terminal is more than twice the terminal width of the branched portion in the front end two-branch structure.

[0035] In addition, in the semiconductor module 1, the first to fourth control terminals T11 to T14 and the first to fourth detection terminals T21 to T24 do not have a front end branch structure.

[0036] In the semiconductor module 1, as Figure 1 As shown, the first semiconductor chip Q1 and the third semiconductor chip Q3, and the second semiconductor chip Q2 and the fourth semiconductor chip Q4 are symmetrically arranged with respect to the center line C. In addition, the first wiring pattern 10 and the third wiring pattern 30, the second wiring pattern 20 and the fourth wiring pattern 40, the first midpoint terminal 61 and the second midpoint terminal 62, and the first second power supply terminal 52 and the second second power supply terminal 53 are also symmetrically arranged with respect to the center line C. In addition, the fifth wiring pattern 50 and the first power supply terminal 51 are formed symmetrically with respect to the center line C.

[0037] In the semiconductor module 1, the first midpoint terminal 61 and the second midpoint terminal 62 are arranged adjacent to one side of the semiconductor module 1. In addition, the first power terminal 51, the first second power terminal 52, and the second second power terminal 53 are arranged adjacent to the other side of the semiconductor module 1. The first power terminal 51 is arranged in the upper space of the fifth wiring pattern 50 in a non-contact state, and connects the first wiring pattern 10 and the third wiring pattern 30.

[0038] In addition, in the semiconductor module 1, the first to fourth semiconductor chips Q1 to Q4 are the first semiconductor chip Q1, the second semiconductor chip Q2, the third semiconductor chip Q3, and the fourth semiconductor chip Q4. In addition, the first to fifth wiring patterns 10 to 50 are the first wiring pattern 10, the second wiring pattern 20, the third wiring pattern 30, the fourth wiring pattern 40, and the fifth wiring pattern 50. In the following description, when the first to fourth semiconductor chips Q1 to Q4 are collectively described, "first" and the like are sometimes omitted and marked as "semiconductor chips Q1 to Q4". In addition, in the following description, when the first to fifth wiring patterns 10 to 50 are collectively described, "first" and the like are sometimes omitted and marked as "wiring patterns 10 to 50".

[0039] In the semiconductor module 1, it is assumed that the semiconductor chips Q1 to Q4 are MOSFETs (metal oxide semiconductor field effect transistors) whose top view shape is rectangular. In the semiconductor module 1, wiring patterns 10 to 50 are formed on a substrate 70 composed of a DCB (Direct Copper Bonding) substrate as a ceramic substrate in which a metal (copper) is directly bonded to a base composed of ceramics (alumina, aluminum nitride, silicon nitride, etc.).

[0040] In addition, the substrate used for the semiconductor module of the present invention is not limited to the DCB substrate, and other ceramic substrates such as AMB (Active Metal Brazing) substrates, metal substrate substrates with copper or aluminum bases, etc. can also be used. As the metal bonded to the ceramic substrate, metals other than copper (such as aluminum) can also be used.

[0041] The semiconductor chips Q1 to Q4 have a source electrode s, a drain electrode, and a gate electrode g, respectively. When a vertical transistor chip (a vertical transistor chip such as a MOSFET made of Si material or SiC material) is used as the semiconductor chip Q1 to Q4, the drain electrode is on the surface on the wiring pattern 10 to 40 side of the semiconductor chip Q1 to Q4 (the back side of the semiconductor chip Q1 to Q4). In addition, in the semiconductor module 1, the case where a vertical transistor chip is used as the semiconductor chip Q1 to Q4 is illustrated. Therefore, since the drain electrode is arranged on the wiring pattern 10 to 40 side and cannot be visually seen, the symbol representing the drain electrode is not shown in the figure. In addition, the gate electrode G is arranged on the surface on the source electrode S side of the semiconductor chip Q1 to Q4.

[0042] In addition, the semiconductor chips Q1 to Q4 can be appropriately changed as long as they do not change the main purpose of the present invention. For example, as the semiconductor chips Q1 to Q4, for example, a lateral transistor chip can be used. As a lateral transistor chip, for example, a GaN-HEMT composed of GaN conductive Si material, other compound semiconductor transistors composed of Ga2O3 conductive Si material, etc. can be cited. In addition, in the case of a lateral transistor chip, a plurality of gate electrodes G including a drain electrode and a source electrode S are preferably formed on the surface of the semiconductor chip. In addition, the semiconductor chips Q1 to Q4 are not limited to transistor chips, but can also be formed as modifications that are appropriately replaced with diode chips according to the circuit APP application. According to such a deformed structure, it can also be appropriately applied to a totem pole type bridgeless PFC circuit, etc.

[0043] In the semiconductor module 1 , the regions of the second wiring pattern 20 and the fourth wiring pattern 40 , which respectively connect the first midpoint terminal 61 and the second midpoint terminal 62 , are arranged adjacent to each other.

[0044] In the semiconductor module 1, the first wiring pattern 10 and the third wiring pattern 30 are arranged adjacent to each other on both sides of the fifth wiring pattern 50 (the second part described later). In addition, the first second power supply terminal 52 and the second second power supply terminal 53 are arranged on both sides of the fifth wiring pattern 50 (the first part described later). The first power supply terminal 51 has a substantially T-shape when viewed from above.

[0045] Although not shown in the figure and described, the semiconductor module 1 may also include a first decoupling capacitor disposed near the first semiconductor chip Q1 and the second semiconductor chip Q2 and connected to the first wiring pattern 10 and the fifth wiring pattern 50. The semiconductor module 1 may include a second decoupling capacitor located between the third semiconductor chip Q3 and the fourth semiconductor chip Q4 and connected to the third wiring pattern 30 and the fifth wiring pattern 50. Each decoupling capacitor has the function of preventing power supply voltage fluctuations and eliminating various noises.

[0046] In the semiconductor module 1, the fifth wiring pattern 50 is arranged at the center on the plane. The fifth wiring pattern 50 has a first portion located on the other side of the semiconductor module 1 and connecting the first second power supply terminal 52 and the second second power supply terminal 53. In addition, the fifth wiring pattern has a second portion located between the first wiring pattern 10 and the third wiring pattern 30. Moreover, the fifth wiring pattern 50 has a third portion protruding from the second portion to the semiconductor module 1 side. A tapered convex portion having a first oblique side and a second oblique side is formed in the third portion.

[0047] The angle θ between the first and second oblique sides of the convex portion is not particularly limited, but is 90 degrees in the semiconductor module 1. Therefore, the oblique side corresponding to the first oblique side of the second wiring pattern 20 and the oblique side corresponding to the second oblique side of the fourth wiring pattern 40 are both 45 degrees.

[0048] In the semiconductor module 1, the first semiconductor chip Q1 includes: a first gate electrode G1, a first source electrode S1, and a first drain electrode. The first gate electrode G1 is connected to the first control terminal T11 via a first control connection member (not shown) composed of an aluminum wire or the like and a first control wiring pattern 111. The first source electrode S1 is connected to the first detection terminal T21 via a first detection connection member (not shown) composed of an aluminum wire or the like and a first detection wiring pattern 121. In addition, the first source electrode S1 is connected to the second wiring pattern 20 via a first connection member 81 composed of an aluminum wire or the like. The first drain electrode is connected to the first wiring pattern 10.

[0049] In addition, in the semiconductor module 1, the second semiconductor chip Q2 includes a second gate electrode G2, a second source electrode S2, and a second drain electrode. The second gate electrode G2 is connected to the second control terminal T12 via a second control connection member (not shown) composed of an aluminum wire or the like and a second control wiring pattern 112. The second source electrode S2 is connected to the second detection terminal T22 via a second detection connection member (not shown) composed of an aluminum wire or the like and a second detection wiring pattern 122. In addition, the second source electrode S2 is connected to the fifth wiring pattern 50 via a second connection member 82 composed of an aluminum wire or the like. The second drain electrode is connected to the second wiring pattern 20.

[0050] In addition, in the semiconductor module 1, the third semiconductor chip Q3 includes a third gate electrode G3, a third source electrode S3, and a third drain electrode. The third gate electrode G3 is connected to the third control terminal T13 via a third control connection member (not shown) composed of an aluminum wire or the like and a third control wiring pattern 113. The third source electrode S3 is connected to the third detection terminal T23 via a third detection connection member (not shown) composed of an aluminum wire or the like and a third detection wiring pattern 123. In addition, the third source electrode S3 is connected to the fourth wiring pattern 40 via a third connection member 83 composed of an aluminum wire or the like. The third drain electrode is connected to the third wiring pattern 30.

[0051] In addition, in the semiconductor module 1, the fourth semiconductor chip Q4 includes a fourth gate electrode G4, a fourth source electrode S4, and a fourth drain electrode. The fourth gate electrode G4 is connected to the fourth control terminal T14 via a fourth control connection member (not shown in the figure) composed of an aluminum wire or the like and a fourth control wiring pattern 114. The fourth source electrode S4 is connected to the fourth detection terminal T24 via a fourth detection connection member (not shown in the figure) composed of an aluminum wire or the like and a fourth detection wiring pattern 124. In addition, the fourth source electrode S4 is connected to the fifth wiring pattern 50 via a fourth connection member 84 composed of an aluminum wire or the like. The fourth drain electrode is connected to the fourth wiring pattern 40.

[0052] In the semiconductor module 1 , the second semiconductor chip Q2 is arranged such that one of its sides is along the first oblique side of the fifth wiring pattern 50 . Also, the fourth semiconductor chip Q4 is arranged such that one of its sides is along the second oblique side of the fifth wiring pattern 50 .

[0053] In the semiconductor module 1 , the width of the inner lead of each of the first power terminal 51 , the first second power terminal 52 , the second second power terminal 53 , the first midpoint terminal 61 , and the second midpoint terminal 62 is wider than the width of the outer lead of each of them.

[0054] Next, the first power terminal 51, the first and second power terminals 52, 53, and the first and second midpoint terminals 61, 62 are described. The first power terminal 51 and the first and second second power terminals 52, 53 are terminals for supplying power to the bridge circuit. In the case of current flow, it is assumed that the first power terminal 51 is the input side of the current, and the first and second power terminals 52, 53 are the output sides of the current.

[0055] The first midpoint terminal 61 and the second midpoint terminal 62 are terminals for connecting a load not shown. The first midpoint terminal 61 is connected to the second wiring pattern 20, and the second midpoint terminal 62 is connected to the fourth wiring pattern 40. Moreover, when the first semiconductor chip Q1 and the fourth semiconductor chip Q4 are both turned on, and when the third semiconductor chip Q3 and the second semiconductor chip Q2 are both turned on, the direction of the current flowing between the first midpoint terminal 61 and the second midpoint terminal 62 is reversed.

[0056] In the semiconductor module 1, when the first semiconductor chip Q1 and the fourth semiconductor chip Q4 are both turned on, current flows from the first midpoint terminal 61 to the second midpoint terminal 62. Also, when the third semiconductor chip Q3 and the second semiconductor chip Q2 are both turned on, current flows from the second midpoint terminal 62 to the first midpoint terminal 61.

[0057] In addition, the outer lead portions of the first power terminal 51 and the second power terminal (the first second power terminal 52 and the second second power terminal 53), and the outer lead portions of the first midpoint terminal 61 and the second midpoint terminal 62 are arranged on the opposite side of the semiconductor module 1. Here, the "opposite side of the semiconductor module 1" refers to the upper side of the semiconductor module 1 as shown in the figure and the lower side of the semiconductor module 1 as shown in the figure.

[0058] In addition, the outer lead portions of the first control terminal T11 and the third control terminal T13 and the outer lead portions of the first power terminal 51, the first-second power terminal 52 and the second-second power terminal 53 are arranged on the same side of the semiconductor module 1. In addition, the outer lead portions of the second control terminal T12 and the fourth control terminal T14 and the outer lead portions of the first midpoint terminal 61 and the second midpoint terminal 62 are arranged on the same side of the semiconductor module 1.

[0059] In addition, the outer lead portions of the first detection terminal T21 and the third detection terminal T23 and the outer lead portions of the first power terminal 51, the first-second power terminal 52 and the second-second power terminal 53 are arranged on the same side of the semiconductor module 1. In addition, the outer lead portions of the second detection terminal T22 and the fourth detection terminal T24 and the outer lead portions of the first midpoint terminal 61 and the second midpoint terminal 62 are arranged on the same side of the semiconductor module 1.

[0060] Next, the effects of the semiconductor module 1 according to the first embodiment will be described.

[0061] The width of at least one of the multiple terminals of the semiconductor module 1 of the first embodiment (the first power supply terminal 51, the first midpoint terminal 61, and the second midpoint terminal 62) is set to have a desired inductance, and the terminal front end is branched into a plurality of front end branch structures 51B and 61B in the outer lead portion. Therefore, according to the semiconductor module 1 of the first embodiment, for at least one of the multiple terminals, even if the terminal width is expanded from the inner lead portion to the outer lead portion to a terminal width that does not significantly increase the parasitic inductance, the increase in the width of the terminal front end can be suppressed by the front end branch structures 51B, 61B, and 62B, and the heat capacity of the mounting portion can be reduced, thereby reducing the difficulty of mounting. Therefore, the semiconductor module 1 of the first embodiment becomes a semiconductor module that can reduce the parasitic inductance and also reduce the difficulty of mounting.

[0062] In addition, in the semiconductor module 1 of the first embodiment, at least one of the plurality of terminals (the first power terminal 51, the first midpoint terminal 61, and the second midpoint terminal 62) has a front branch structure 51B, 61B, 62B on the outside of the molded resin M. Therefore, according to the semiconductor module 1 of the first embodiment, while increasing the portion that can ensure the terminal width as much as possible, it is also possible to reduce the difficulty of mounting.

[0063] Furthermore, in the semiconductor module 1 of the first embodiment, the semiconductor module 1 has four semiconductor chips (semiconductor chips Q1 to Q4) as a plurality of semiconductor chips. Furthermore, the semiconductor module 1 has a first power terminal 51, a second power terminal (a first second power terminal 52 and a second second power terminal 53), a first midpoint terminal 61 and a second midpoint terminal 62 as a plurality of terminals. Furthermore, in the semiconductor module 1 of the first embodiment, the outer lead portions in the first midpoint terminal 61 and the second midpoint terminal 62 both have front end branch structures 61B and 62B. Therefore, according to the semiconductor module 1 of the first embodiment, by also providing the first midpoint terminal 61 and the second midpoint terminal 62 with front end branch structures 61B and 62B, the parasitic inductance can be further reduced, and the difficulty of installation can also be reduced.

[0064] In addition, in the semiconductor module 1 of the first embodiment, the semiconductor module 1 includes the first second power terminal 52 and the second second power terminal 53 as the second power terminal. In addition, in the semiconductor module 1 of the first embodiment, among the first power terminal 51, the first second power terminal 52, and the second second power terminal 53, only the outer lead portion of the first power terminal 51 has the front branch structure 51B. Therefore, in the semiconductor module 1 of the first embodiment, by making the terminal width from the inner lead portion to the outer lead portion of the first power terminal 51 wider than that of the second power terminal having two terminals and having the front branch structure 51B, it is possible to further reduce the parasitic inductance and reduce the difficulty of mounting.

[0065] In addition, in the semiconductor module 1 of the first embodiment, the maximum width of the inner lead portion is wider than the maximum width of the outer lead portion among the plurality of terminals (the first power terminal 51, the first second power terminal 52, the second second power terminal 53, the first midpoint terminal 61, and the second midpoint terminal 62). Therefore, according to the semiconductor module 1 of the first embodiment, the parasitic inductance can be further reduced.

[0066] In addition, in the semiconductor module 1 of the first embodiment, the front end branching structures 51B, 61B, and 62B are front end two-branch structures in which the front end of the terminal branches into two, and the maximum width of the inner lead portion is more than twice the width of the terminal at the branched portion in the front end two-branch structure. Therefore, according to the semiconductor module 1 of the first embodiment, the width of the inner lead portion is made wider than the separation interval of the front end two-branch structure, and the parasitic inductance can be further reduced.

[0067] In addition, in the semiconductor module 1, each component is symmetrically arranged with respect to the center line C, or is symmetrically formed with respect to the center line C. Therefore, according to the semiconductor module 1 of the first embodiment, the length of the current path flowing when the first semiconductor chip Q1 and the fourth semiconductor chip Q4 are both turned on and when the third semiconductor chip Q3 and the second semiconductor chip Q2 are both turned on can be consistent. As a result, the parasitic inductance can be matched when the first semiconductor chip Q1 and the fourth semiconductor chip Q4 are both turned on and when the third semiconductor chip Q3 and the second semiconductor chip Q2 are both turned on. Therefore, according to the semiconductor module 1, the effect of reducing the parasitic inductance can also be achieved from this point of view.

[0068] In addition, in the semiconductor module 1 of the first embodiment, when in use, currents flow in the first power terminal 51 and the first second power terminal 52 and the second second power terminal 53 in reverse directions, and currents flow in the first midpoint terminal 61 and the second midpoint terminal 62 in reverse directions. In addition, the first midpoint terminal 61 and the second midpoint terminal 62 are arranged adjacent to one side of the semiconductor module 1. In addition, the first power terminal 51, the first second power terminal 52 and the second second power terminal 53 are arranged on the other side of the semiconductor module 1, and the first power terminal 51 is arranged in a non-contact state in the upper space of the fifth wiring pattern 50. Therefore, in the semiconductor module 1 of the first embodiment, currents flow in the first power terminal 51 and the fifth wiring pattern 50 in reverse directions, and currents flow in the first midpoint terminal 61 and the second midpoint terminal 62 in reverse directions. Therefore, according to the semiconductor module 1, the magnetic field generated in the first power terminal 51 and the fifth wiring pattern 50 and the magnetic field generated in the first midpoint terminal 61 and the second midpoint terminal 62 can be offset, thereby achieving an effect of reducing parasitic inductance.

[0069] As described above, the semiconductor module 1 of the first embodiment can reduce parasitic inductance and reduce mounting difficulty, but the inventors conducted simulations to verify the effects related to parasitic inductance. The results of the simulations are described below.

[0070] In the simulation, for comparison with the semiconductor module 1 of the first embodiment, a semiconductor module 1A (see Figure 3 The semiconductor module 1A basically has the same components as the semiconductor module 1 of the first embodiment. Figure 3 In the embodiment, the components substantially the same as those in the semiconductor module 1 are denoted by the same reference numerals as those in the first embodiment.

[0071] The semiconductor module 1A includes: a first power terminal 851, a first second power terminal 852, a second second power terminal 853, a first midpoint terminal 861, and a second midpoint terminal 862 as the first power terminal, the first second power terminal, the second second power terminal, the first midpoint terminal, and the second midpoint terminal. The first power terminal 851 has a narrower inner lead and an outer lead width than the first power terminal 51. The first second power terminal 852, the second second power terminal 853, the first midpoint terminal 861, and the second midpoint terminal 862 are the same. In addition, the first power terminal 851, the first midpoint terminal 861, and the second midpoint terminal 862 do not have a front end branch structure.

[0072] The structure of the bridge circuit of the semiconductor module 1A is the same as that of the semiconductor module 1 of the first embodiment, that is, the bridge circuit with the first semiconductor chip Q1 and the third semiconductor chip Q3 as the high side and the second semiconductor chip Q2 and the fourth semiconductor chip Q4 as the low side. In the semiconductor module 1A, the first semiconductor chip Q1 and the fourth semiconductor chip Q4 are also turned on, and the third semiconductor chip Q3 and the second semiconductor chip Q2 are also turned on.

[0073] Here, the results of a simulation comparing the parasitic inductance generated in the semiconductor module 1 according to the first embodiment with the parasitic inductance generated in the semiconductor module 1A are described (see FIG. 1 ). Figure 4 Here, in the range of the frequency of the on-off operation of the bridge circuit being 1 kHz to 1 GHz or more, the parasitic inductance generated in the current path when the first semiconductor chip Q1 and the fourth semiconductor chip Q4 were turned on was measured.

[0074] In the semiconductor module 1A, when both the first semiconductor chip Q1 and the fourth semiconductor chip Q4 are turned on, the parasitic inductance generated in the current path is 22.30 nH at 1 kHz, 16.38 nH at 100 kHz, and 14.09 nH at 100 MHz.

[0075] On the other hand, in the semiconductor module 1 , when both the first semiconductor chip Q1 and the fourth semiconductor chip Q4 are turned on, the parasitic inductance generated in the current path is 20.15 nH at 1 kHz, 14.28 nH at 100 kHz, and 12.29 nH at 100 MHz.

[0076] The components of the semiconductor module 1 and the semiconductor module 1A of the first embodiment are arranged symmetrically or formed symmetrically about the center line C. Therefore, it is considered that substantially the same result can be obtained when both the third semiconductor chip Q3 and the second semiconductor chip Q2 are turned on.

[0077] From the above results, it was confirmed that the semiconductor module 1 according to the first embodiment can reduce the parasitic inductance compared to the semiconductor module 1A.

[0078] [Implementation method 2]

[0079] The semiconductor module 2 of the second embodiment has basically the same structure as the semiconductor module 1 of the first embodiment, but the structures of the first power supply terminal, the second power supply terminal, the first midpoint terminal, the second midpoint terminal and the wiring pattern are different. Figure 5 As shown, the semiconductor module 2 includes a plurality of semiconductor chips (semiconductor chips Q1 to Q4) disposed inside the mold resin M, and a first power terminal 51a, a second power terminal 52a, a first midpoint terminal 61a, and a second midpoint terminal 62a. In addition, in the semiconductor module 2, a bridge circuit is configured in which the first semiconductor chip Q1 and the third semiconductor chip Q3 are set to the high side, and the second semiconductor chip Q2 and the fourth semiconductor chip Q4 are set to the low side. The semiconductor module 2 will be described below, focusing on the differences from the semiconductor module 1 of the first embodiment.

[0080] The semiconductor module 2 has one second power supply terminal 52a. The inner lead portion of the second power supply terminal 52a is located inside the mold resin M, and the outer lead portion thereof is located outside the mold resin M.

[0081] In addition to the above-mentioned components, the semiconductor module 2 further includes: first to fourth wiring patterns 10a to 40a, a substrate 70, first to fourth connecting members 81 to 84, first to fourth control connecting members (not shown), first to fourth detection connecting members (not shown), first to fourth control wiring patterns 111 to 114, first to fourth detection wiring patterns 121 to 124, first to fourth control terminals T11 to T14, and first to fourth detection terminals T21 to T24. The semiconductor module 2 may also include components other than the above-mentioned components.

[0082] In the semiconductor module 2, the outer lead portions of the first power supply terminal 51a and the second power supply terminal 52a have a front end branch structure 51aB and 52aB in which the front end of the terminal branches into a plurality of branches (see Figure 6 (a)).

[0083] In the first power terminal 51a and the second power terminal 52a, the maximum width of the inner lead portion is wider than the maximum width of the outer lead portion. In addition, the first power terminal 51a and the second power terminal 52a have respective front end branch structures 51aB and 52aB outside the mold resin M.

[0084] The outer lead portions of the first midpoint terminal 61a and the second midpoint terminal 62a both have front end support structures 61aB and 62aB (see Figure 6 (b)). In the first midpoint terminal 61a and the second midpoint terminal 62a, the maximum width of the inner lead portion is also wider than the maximum width of the outer lead portion. In addition, the first midpoint terminal 61a and the second midpoint terminal 62a have front end branch structures 61aB and 62aB outside the mold resin M, respectively.

[0085] In the semiconductor module 2, each of the front end branch structures 51aB, 52aB, 61aB, 62aB in the first power terminal 51a, the second power terminal 52a, the first midpoint terminal 61a, and the second midpoint terminal 62a is a front end two-branch structure in which the front end of the terminal branches into two. The maximum width of the lead portion in each terminal is more than twice the terminal width of the branched portion in the front end two-branch structure.

[0086] The first power supply terminal 51a is connected to the first wiring pattern 10a. When one of the sides of the first wiring pattern 10a is used as the first side 11, a concave portion 12 is formed within a predetermined range of the first side 11. The concave portion 12 is formed within a predetermined range of the first side 11. Figure 5 In the diagram, the side located on the upper side in the figure among the sides of the first wiring pattern 10 a extending in the left-right direction in the figure is referred to as the first side 11 .

[0087] In addition, the "recess 12" is not a recessed portion that is recessed in the thickness direction of the substrate 70. Figure 5 As shown in the area surrounded by the dotted frame Z in FIG. 1 , when the first wiring pattern 10 a is viewed from above, the area is a concave portion that is recessed downward on the plane of the paper on the plane of the substrate 70 .

[0088] In addition, the first semiconductor chip Q1 and the third semiconductor chip Q3 are mounted on the first wiring pattern 10a. Here, the first semiconductor chip Q1 and the third semiconductor chip Q3 are mounted at positions sandwiching the recess 12. In addition, it is assumed that the position where the recess 12 is formed is approximately near the center of the left-right direction of the first wiring pattern 10a.

[0089] Next, the second wiring pattern 20a will be described. The second wiring pattern 20a is connected to the second power supply terminal 52a, and is surrounded on three sides by the recessed portion 12 of the first wiring pattern 10a in a plan view.

[0090] Next, the third wiring pattern 30a and the fourth wiring pattern 40a will be described. The third wiring pattern 30a and the fourth wiring pattern 40a are arranged side by side in the left-right direction along the first side 11 of the first wiring pattern 10a.

[0091] The third wiring pattern 30 a is adjacent to the first wiring pattern 10 a and the second wiring pattern 20 a , has the second semiconductor chip Q2 mounted thereon, and is connected to the first midpoint terminal 61 a .

[0092] The fourth wiring pattern 40a is adjacent to the first wiring pattern 10a and the second wiring pattern 20a, has the fourth semiconductor chip Q4 mounted thereon, and is connected to the second midpoint terminal 62a.

[0093] The term "adjacent" as used herein means, when focusing on two components of the same type, a state in which no component of the same type as the two components is arranged between them.

[0094] By arranging the wiring patterns 10 a to 40 a in this manner, the second wiring pattern 20 a is surrounded by the first wiring pattern 10 a , the third wiring pattern 30 a , and the fourth wiring pattern 40 a , and is located near the center of the substrate 70 .

[0095] Next, the semiconductor chips Q1 to Q4 will be described.

[0096] The first source electrode S1 of the first semiconductor chip Q1 is connected to the third wiring pattern 30a through a first connection member 81 composed of an aluminum wire, etc. In addition, the first drain electrode of the first semiconductor chip Q1 is connected to the first wiring pattern 10a.

[0097] The second source electrode S2 of the second semiconductor chip Q2 is connected to the second wiring pattern 20a via a second connection member 82 made of an aluminum wire, etc. In addition, the second drain electrode of the second semiconductor chip Q2 is connected to the third wiring pattern 30a.

[0098] The third source electrode S3 of the third semiconductor chip Q3 is connected to the fourth wiring pattern 40a via a third connection member 83 composed of an aluminum wire, etc. In addition, the third drain of the third semiconductor chip Q3 is connected to the first wiring pattern 10a.

[0099] The fourth source electrode S4 of the fourth semiconductor chip Q4 is connected to the second wiring pattern 20a via a fourth connection member 84 made of an aluminum wire, etc. In addition, the fourth drain electrode of the fourth semiconductor chip Q4 is connected to the fourth wiring pattern 40a.

[0100] The first to fourth control terminals T11 to T14 and the first to fourth detection terminals T21 to T24 are arranged outside the area surrounded by the first power terminal 51a and the second power terminal 52a and the area surrounded by the first midpoint terminal 61a and the second midpoint terminal 62a. The connection relationship between the first to fourth control terminals T11 to T14, the first to fourth detection terminals T21 to T24, the first to fourth control wiring patterns 111 to 114, the first to fourth detection wiring patterns 121 to 124 and the semiconductor chips Q1 to Q4 is the same as that in the first embodiment, so the description is omitted.

[0101] Next, the first and second power terminals 51a, 52a and the first and second midpoint terminals 61a, 62a in the semiconductor module 2 are described. The first power terminal 51a and the second power terminal 52a are terminals for supplying power to the bridge circuit, and from the perspective of the flow of current, it is assumed that the first power terminal 51a is the input side of the current and the second power terminal 52a is the output side of the current.

[0102] The first power terminal 51a is connected to the first wiring pattern 10a. The second power terminal 52a is connected to the second wiring pattern 20a in a non-contact manner across the first wiring pattern 10a. These first power terminals 51a and second power terminals 52a are adjacent. In addition, a decoupling capacitor 90 is arranged near the first power terminal 51a and the second power terminal 52a, and one end of the decoupling capacitor 90 is connected to the first wiring pattern 10a, and the other end is connected to the second wiring pattern 20a.

[0103] On the other hand, the first midpoint terminal 61a and the second midpoint terminal 62a are terminals to which a load not shown is connected. The first midpoint terminal 61a is connected to the third wiring pattern 30a, and the second midpoint terminal 62a is connected to the fourth wiring pattern 40a. These first midpoint terminal 61a and the second midpoint terminal 62a are adjacent. Moreover, when the first semiconductor chip Q1 and the fourth semiconductor chip Q4 are both turned on, and when the third semiconductor chip Q3 and the second semiconductor chip Q2 are both turned on, the direction of the current flowing between the first midpoint terminal 61a and the second midpoint terminal 62a is reversed.

[0104] In the semiconductor module 2, when the first semiconductor chip Q1 and the fourth semiconductor chip Q4 are both turned on, current flows from the first midpoint terminal 61a to the second midpoint terminal 62a. Also, when the third semiconductor chip Q3 and the second semiconductor chip Q2 are both turned on, current flows from the second midpoint terminal 62a to the first midpoint terminal 61a.

[0105] In addition, if Figure 5 As shown, the outer lead portions of the first power terminal 51 a and the second power terminal 52 a and the outer lead portions of the first midpoint terminal 61 a and the second midpoint terminal 62 a are arranged on opposite sides of the semiconductor module 2 .

[0106] In addition, the outer lead portion of the first control terminal T11 and the outer lead portion of the third control terminal T13, the outer lead portion of the first power terminal 51a and the outer lead portion of the second power terminal 52a are arranged on the same side of the semiconductor module 2. In addition, the outer lead portion of the second control terminal T12 and the outer lead portion of the fourth control terminal T14, the outer lead portion of the first midpoint terminal 61a and the outer lead portion of the second midpoint terminal 62a are arranged on the same side of the semiconductor module 2.

[0107] In addition, the outer lead portion of the first detection terminal T21 and the outer lead portion of the third detection terminal T23, and the outer lead portion of the first power supply terminal 51a and the outer lead portion of the second power supply terminal 52a are arranged on the same side of the semiconductor module 2. In addition, the outer lead portion of the second detection terminal T22 and the outer lead portion of the fourth detection terminal T24, and the outer lead portion of the first midpoint terminal 61a and the outer lead portion of the second midpoint terminal 62a are arranged on the same side of the semiconductor module 2.

[0108] In the semiconductor module 2, when both the first semiconductor chip Q1 and the fourth semiconductor chip Q4 are turned on, the current path is as follows: from the first power terminal 51a through the first semiconductor chip Q1 to the first midpoint terminal 61a, from the first midpoint terminal 61a through the load (not shown), and then from the second midpoint terminal 62a through the fourth semiconductor chip Q4 to the second power terminal 52a.

[0109] On the other hand, when both the third semiconductor chip Q3 and the second semiconductor chip Q2 are turned on, the current path is as follows: from the first power terminal 51a through the third semiconductor chip Q3 to the second midpoint terminal 62a, from the second midpoint terminal 62a through the load (not shown), and then from the first midpoint terminal 61a through the second semiconductor chip Q2 to the second power terminal 52a.

[0110] That is, when both the first semiconductor chip Q1 and the fourth semiconductor chip Q4 are turned on, the current path enters the first wiring pattern 10a from the first power terminal 51a, passes through the first source electrode S1 from the first drain electrode of the first semiconductor chip Q1 mounted on the first wiring pattern 10a, and then flows to the first midpoint terminal 61a through the third wiring pattern 30a via the first connection component 81 connecting the first source electrode S1 and the third wiring pattern 30a. Then, the current enters the fourth wiring pattern 40a from the second midpoint terminal 62a via the load (not shown), passes through the fourth drain electrode of the fourth semiconductor chip Q4 mounted on the fourth wiring pattern 40a, and then flows to the second power terminal 52a through the second wiring pattern 20a via the fourth connection component 84 connecting the fourth source electrode S4 and the second wiring pattern 20a.

[0111] On the other hand, when both the third semiconductor chip Q3 and the second semiconductor chip Q2 are turned on, the current path enters the first wiring pattern 10a from the first power terminal 51a, passes through the third source electrode S3 from the third drain electrode of the third semiconductor chip Q3 mounted on the first wiring pattern 10a, and then flows to the second midpoint terminal 62a through the fourth wiring pattern 40a via the third connection member 83 connecting the third source electrode S3 and the fourth wiring pattern 40a. Then, the current enters the third wiring pattern 30a from the first midpoint terminal 61a via the load (not shown), passes through the second source electrode S2 from the second drain electrode of the second semiconductor chip Q2 mounted on the third wiring pattern 30a, and then flows to the second power terminal 52a through the second connection member 82 connecting the second source electrode S2 and the second wiring pattern 20a.

[0112] As described above, when the semiconductor module 2 is used, currents flow in opposite directions through the first power supply terminal 51 a and the second power supply terminal 52 a , and currents flow in opposite directions through the first midpoint terminal 61 a and the second midpoint terminal 62 a .

[0113] In addition, the current path when the first semiconductor chip Q1 and the fourth semiconductor chip Q4 are both turned on and the current path when the third semiconductor chip Q3 and the second semiconductor chip Q2 are both turned on are formed in the second wiring pattern 20a and its periphery. This is due to the arrangement of the wiring patterns 10a to 40a, the arrangement of the semiconductor chips Q1 to Q4, the arrangement of the first and second power terminals 51a, 52a, and the arrangement of the first and second midpoint terminals 61a, 62a.

[0114] Next, the effects of the semiconductor module 2 according to the second embodiment will be described.

[0115] The semiconductor module 2 of the second embodiment is different from the semiconductor module 1 of the first embodiment in the structure of the first power terminal, the second power terminal, the first midpoint terminal, the second midpoint terminal, and the wiring pattern. However, in the semiconductor module 2 of the second embodiment, at least one of the plurality of terminals (the first power terminal 51a, the second power terminal 52a, the first midpoint terminal 61a, and the second midpoint terminal 62a) is set to have a desired inductance, and has a front end branch structure 51aB, 52aB, 61aB, 62aB that branches into a plurality of terminals at the front end of the outer lead portion. Therefore, according to the semiconductor module 2 of the second embodiment, as in the semiconductor module 1 of the first embodiment, for at least one of the plurality of terminals, even if the terminal width is expanded from the inner lead portion to the outer lead portion to a terminal width that does not significantly increase the parasitic inductance, the front end branch structures 51aB, 52aB, 61aB, 62aB can suppress the increase in the width of the terminal front end, reduce the heat capacity of the mounting portion, and thus reduce the difficulty of mounting. Therefore, the semiconductor module 2 according to the second embodiment is a semiconductor module that can reduce parasitic inductance and also reduce the difficulty of mounting.

[0116] In addition, the outer lead portions of the first power terminal 51a and the second power terminal 52a of the semiconductor module 2 of the second embodiment both have the front branch structures 51aB and 52aB. Therefore, according to the semiconductor module 2 of the second embodiment, the parasitic inductance of both the first power terminal 51a and the second power terminal 52a can be reduced, and the difficulty of mounting can also be reduced.

[0117] In the semiconductor module 2 of the second embodiment, the first power terminal 51a is adjacent to the second power terminal 52a, and the first midpoint terminal 61a is adjacent to the second midpoint terminal 62a. In addition, in the semiconductor module 2, the direction of the current flowing through the first power terminal 51a is opposite to the direction of the current flowing through the second power terminal 52a, and the direction of the current flowing through the first midpoint terminal 61a is opposite to the direction of the current flowing through the second midpoint terminal 62a. In this way, by making the terminals with different current directions adjacent to each other, the generated magnetic field can be offset, and the effect of reducing the parasitic inductance can be obtained.

[0118] Furthermore, the semiconductor module 2 according to the second embodiment also has corresponding effects among the effects possessed by the semiconductor module 1 according to the first embodiment.

[0119] [Implementation method 3]

[0120] like Figure 7As shown, the semiconductor module 3 of the third embodiment includes a plurality of semiconductor chips and a plurality of terminals arranged inside the molded resin M. Furthermore, the semiconductor module 3 includes two semiconductor chips (semiconductor chips Q1 and Q2) as a plurality of semiconductor chips. In addition, the semiconductor module 3 includes a first power supply terminal 51b, a second power supply terminal 52b, and a midpoint terminal 61b as a plurality of terminals. The semiconductor module 3 is a semiconductor module that constitutes a half-bridge circuit.

[0121] The first power terminal 51 b , the second power terminal 52 b , and the midpoint terminal 61 b ​​have their inner lead portions located inside the mold resin M and their outer lead portions located outside the mold resin M.

[0122] The outer lead portions of the first power terminal 51b and the second power terminal 52b have a terminal front end branching structure 51bB and 52bB (see Figure 8 (a)) In addition, the first power terminal 51b and the second power terminal 52b have front end branch structures 51bB and 52bB outside the mold resin M.

[0123] The outer lead portion of the midpoint terminal 61b has a front branch structure 61bB (see Figure 8 (b)) In addition, the midpoint terminal 61b has a front end branch structure 61bB outside the mold resin M.

[0124] In addition, in addition to the above-mentioned components, the semiconductor module 3 further includes first to third wiring patterns 10b to 30b, a substrate 70, first and second connecting members 81, 82, first and second control connecting members (not shown), first and second detection connecting members (not shown), first and second control wiring patterns 111, 112, first and second detection wiring patterns 121, 122, first and second control terminals T11, T12, and first and second detection terminals T21, T22. The semiconductor module 3 may also include components other than the above-mentioned components.

[0125] The first source electrode S1 of the first semiconductor chip Q1 is connected to the third wiring pattern 30b through a first connection member 81 composed of an aluminum wire, etc. In addition, the first drain of the first semiconductor chip Q1 is connected to the first wiring pattern 10b.

[0126] The second source electrode S2 of the second semiconductor chip Q2 is connected to the second wiring pattern 20b via a second connection member 82 made of an aluminum wire, etc. In addition, the second drain electrode of the second semiconductor chip Q2 is connected to the third wiring pattern 30a.

[0127] The first power terminal 51b is connected to the first wiring pattern 10b. The second power terminal 52b is connected to the second wiring pattern 20b. The first power terminal 51b and the second power terminal 52b are adjacent to each other.

[0128] On the other hand, the midpoint terminal 61b is a terminal to which a load (not shown) is connected. The midpoint terminal 61b is connected to the third wiring pattern 30b.

[0129] Next, the effects of the semiconductor module 3 according to the third embodiment will be described.

[0130] The overall structure of the semiconductor module 3 of the third embodiment is different from that of the semiconductor module 1 of the first embodiment. However, in the semiconductor module 3 of the third embodiment, the width of at least one of the plurality of terminals (the first power terminal 51b, the second power terminal 52b, and the midpoint terminal 61b) is set to have a desired inductance, and the front end branch structure 51bB, 52bB, and 61bB that branches into a plurality of terminals at the front end of the outer lead portion is provided. Therefore, according to the semiconductor module 3 of the third embodiment, as in the semiconductor module 1 of the first embodiment, for at least one of the plurality of terminals, even if the parasitic inductance increases from the inner lead portion to the outer lead portion to a terminal width that does not increase significantly, the front end branch structures 51bB, 52bB, and 61bB can suppress the increase in the width of the front end of the terminal, reduce the heat capacity of the mounting portion, and thus reduce the difficulty of mounting. Therefore, the semiconductor module 3 according to the third embodiment is a semiconductor module that can reduce the difficulty of mounting while reducing the parasitic inductance.

[0131] In addition, the semiconductor module 3 of the third embodiment has two semiconductor chips (semiconductor chips Q1, Q2) as a plurality of semiconductor chips, and has a first power terminal 51b, a second power terminal 52b, and a midpoint terminal 61b as a plurality of terminals. In addition, the outer lead portion of the midpoint terminal 61b has a front branch structure 61bB. Therefore, according to the semiconductor module 3 of the third embodiment, by making the midpoint terminal 61b also have a front branch structure 61bB, it is possible to further reduce the parasitic inductance and reduce the difficulty of mounting.

[0132] In addition, the semiconductor module 3 according to the third embodiment also has corresponding effects among the effects possessed by the semiconductor module 1 according to the first embodiment.

[0133] The present invention is not limited to the above-described embodiment, and various modifications can be implemented without departing from the gist of the present invention. For example, the following modifications are also possible.

[0134] (1) The shape, number, size, position, etc. of the components in the semiconductor module of the present invention are not limited to those shown in the drawings, and can be appropriately changed without impairing the characteristics of the present invention.

[0135] (2) The semiconductor chips Q1 to Q4 are not limited to MOSFETs, but may be other semiconductor chips such as IGBTs (insulated gate bipolar transistors).

[0136] (3) In each of the above embodiments, the semiconductor module includes four or two semiconductor chips, but the present invention is not limited thereto and is also applicable to a semiconductor module including other than four or two semiconductor chips.

[0137] (4) In the above embodiments, the front end branching structure of each terminal is described as a structure in which the front end of the terminal branches into two, but the present invention is not limited to this. The front end branching structure may be a structure in which the front end of the terminal branches into three or more.

[0138] Explanation of symbols

[0139] 1, 2, 3…semiconductor module; 51, 51a, 51b…first power terminal; 51B, 51aB, 51bB, 52aB, 52bB, 61B, 61aB, 61bB, 62B, 62aB…front end branch structure; 52…first second power terminal; 52a, 52b…second power terminal; 53…second second power terminal; 61, 61a…first midpoint terminal; 61b…midpoint terminal; 62, 61a…second midpoint terminal; M…molded resin; Q1…first semiconductor chip; Q2…second semiconductor chip; Q3…third semiconductor chip; Q4…fourth semiconductor chip.

Claims

1. A semiconductor module, comprising: A plurality of semiconductor chips disposed inside a molded resin; and a plurality of terminals each having an inner lead portion located inside the molded resin and an outer lead portion located outside the molded resin, characterized in that: The width of at least one of the plurality of terminals is set to have a desired inductance, and the outer lead portion has a front end branch structure in which the front end of the terminal branches into a plurality of terminals.

2. The semiconductor module according to claim 1, characterized in that: At least one terminal among the plurality of terminals has the front end branch structure outside the mold resin.

3. The semiconductor module according to claim 1, wherein: The semiconductor module includes four semiconductor chips as the plurality of semiconductor chips, and includes a first power supply terminal, a second power supply terminal, a first midpoint terminal, and a second midpoint terminal as the plurality of terminals, and forms a bridge circuit. The outer lead parts of the first midpoint terminal and the second midpoint terminal both have the front end branch structure.

4. The semiconductor module according to claim 3, characterized in that: The semiconductor module includes a first second power supply terminal and a second second power supply terminal as the second power supply terminal. Among the first power terminal, the first second power terminal, and the second second power terminal, only the outer lead portion of the first power terminal has the front branch structure.

5. The semiconductor module according to claim 3, characterized in that: The outer lead portions of the first power terminal and the second power terminal both have the front end branch structure.

6. The semiconductor module according to claim 1, characterized in that: The semiconductor module includes two semiconductor chips as the plurality of semiconductor chips, and includes a first power supply terminal, a second power supply terminal, and a midpoint terminal as the plurality of terminals, and forms a half-bridge circuit. The outer lead portion of the midpoint terminal has the front branch structure.

7. The semiconductor module according to claim 1, characterized in that: Among the plurality of terminals, a maximum width of the inner lead portion is wider than a maximum width of the outer lead portion.

8. The semiconductor module according to claim 1, characterized in that: The front end branch structure is a front end two-branch structure in which the front end of the terminal branches into two. The maximum width of the inner lead portion is more than twice the terminal width of the branched portion of the front two-branch structure.

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