Bump arrangements for flip-chip bonded integrated circuits

Abstract

An integrated circuit includes a semiconductor chip, a first bump row, and a second bump row. The semiconductor chip has a first side oriented in a first planar direction. The first bump row includes a plurality of first bumps aligned in a first planar direction along the first side, and the second bump row includes a plurality of second bumps aligned in the first planar direction. The second bump row is positioned farther from the first side of the semiconductor chip than the first bump row. A first width of the first bump in the first plane direction is narrower than a second width of the second bump in the first plane direction.

Description

Technical Field

[0001] The present disclosure generally relates to bump arrangements for integrated circuits for flip chip bonding. Background Art

[0002] Flip chip bonding is a widely used technology for bonding an integrated circuit (IC) chip to a device substrate. An IC chip suitable for flip chip bonding may include an array of bumps, and the bumps may be bonded to bonding pads formed on the device substrate to provide mechanical and electrical connections between the IC chip and the device substrate. The bonding pads may be coupled to circuit elements disposed on the device substrate via wiring traces or interconnects. The use of flip chip bonding effectively promotes the miniaturization of electronic devices incorporating IC chips. An example of flip chip bonding is chip on glass (COG) technology, in which the IC chip is bonded to a glass substrate in a flip chip manner. COG technology is widely used to bond display driver ICs to the glass substrate of a display panel.

[0003] In order to interface with a large number of signals, some IC chips suitable for flip chip bonding may include a large number of bumps. For example, a display driver IC chip configured to drive a display panel (e.g., an organic light emitting diode (OLED) display panel, a micro light emitting diode (LED) display panel, and a liquid crystal display (LCD) panel) may include hundreds to thousands of bumps for outputting data signals to the display panel via the bumps. An increase in the number of bumps (which will be accompanied by an increase in the number of bonding pads on the device substrate) may cause difficulties in the placement and routing of the bumps, bonding pads, and wiring traces coupled to the bonding pads. Summary of the invention

[0004] This summary is provided to introduce a selection of concepts that are further described below in a simplified form. This summary is not intended to necessarily identify key features or essential features of the present disclosure. The present disclosure may include the following various aspects and embodiments.

[0005] In an exemplary embodiment, the present disclosure provides an integrated circuit comprising a semiconductor chip, a first bump row and a second bump row. The semiconductor chip has a first side oriented in a first planar direction. The first bump row comprises a plurality of first bumps aligned in the first planar direction along the first side, and the second bump row comprises a plurality of second bumps aligned in the first planar direction. The second bump row is positioned farther from the first side of the semiconductor chip than the first bump row. The first width of the first bump in the first planar direction is narrower than the second width of the second bump in the first planar direction.

[0006] In another exemplary embodiment, the present disclosure provides a display device, which includes a display panel and a display driver integrated circuit (IC). The display driver IC is bonded to the display panel. The display driver IC includes a semiconductor chip, a first bump row, and a second bump row. The semiconductor chip includes a first side oriented in a first planar direction. The first bump row includes a plurality of first bumps aligned in the first planar direction along the first side. The second bump row includes a plurality of second bumps aligned in the first planar direction. The second bump row is positioned farther from the first side of the semiconductor chip than the first bump row. The first width of the first bump in the first planar direction is narrower than the second width of the second bump in the first planar direction.

[0007] In another exemplary embodiment, the present disclosure provides a method. The method includes generating a data voltage by a display driver IC. The display driver IC includes a semiconductor chip, a first bump, and a second bump. The semiconductor chip has a first side oriented in a first planar direction. The first bump row includes a plurality of first bumps aligned in the first planar direction along the first side, and the second bump row includes a plurality of second bumps aligned in the first planar direction. The second bump row is positioned farther from the first side of the semiconductor chip than the first bump row. The first width of the first bump in the first planar direction is narrower than the second width of the second bump in the first planar direction. The method also includes providing a data voltage to a display panel via the plurality of first bumps and the plurality of second bumps.

[0008] Additional features and aspects are described in additional detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 An example configuration of a display device is shown.

[0010] Figure 2 Show Figure 1 An example side view configuration of a display device shown in .

[0011] Figure 3 is a partially enlarged side view of a display device illustrating an example bonding structure for bonding a display driver IC to a display panel.

[0012] Figure 4 An example arrangement of a bump array on a major surface of a semiconductor chip is shown.

[0013] Figure 5A is a partial enlarged view of an example bump array.

[0014] Figure 5B is a partially enlarged view showing an example arrangement of conductors on a substrate of a display panel.

[0015] Fig. 6A Show Figure 5A The bumps shown in Figure 5B The positional relationship between the wiring traces shown in .

[0016] Figure 6B An example of the effect of increasing the number of bump rows is shown.

[0017] Figure 7 An example scheme for facilitating placement of routing traces coupled to bond pads is shown in accordance with one or more embodiments.

[0018] Figure 8 An example configuration of a display driver IC configured to drive a display panel according to one or more embodiments is shown.

[0019] Fig.9A According to one or more embodiments Figure 8 A partial enlarged view of the output bump array shown in FIG.

[0020] Fig. 9B is a diagram showing a method according to one or more embodiments Figure 8 0 is a partially enlarged view of an example configuration of a display panel driven by a display driver IC shown in .

[0021] To facilitate understanding, the same reference numerals have been used, where possible, to designate elements common to the drawings. It is contemplated that elements disclosed in one embodiment may be utilized in other embodiments without specific description. Suffixes may be appended to reference numerals to distinguish elements from one another. Unless specifically noted, the drawings referred to herein should not be understood to be drawn to scale. Moreover, for clarity of presentation and explanation, the drawings are generally simplified, and details or components are omitted. The drawings and discussion are used to explain the principles discussed below. DETAILED DESCRIPTION

[0022] The following specific embodiments are exemplary in nature and are not intended to limit the present disclosure or the application and use of the present disclosure. In addition, there is no intention to be bound by any express or implied theory presented in the above background technology, invention content and accompanying drawings or the following specific embodiments.

[0023] In the following detailed description, many specific details are set forth in order to provide a more thorough understanding of the disclosed technology. However, it will be apparent to one of ordinary skill in the art that the disclosed technology can be practiced without these specific details. In other instances, well-known features have not been described in detail to avoid unnecessarily complicating the description.

[0024] As used herein, the term "coupled" means directly connected to one or more intermediate components or circuits or connected by one or more intermediate components or circuits. In addition, throughout this application, ordinal numbers (e.g., first, second, third, etc.) can be used as adjectives of elements (i.e., any noun in this application). Unless explicitly disclosed, such as by using the terms "before", "after", "single" and other such terms, the use of ordinal numbers is not intended to imply or create any specific ordering of elements, nor is it intended to limit any element to only a single element. On the contrary, the use of ordinal numbers is intended to distinguish between elements. For example, the first element is different from the second element, and the first element may include more than one element and be after (or before) the second element in the ordering of the elements.

[0025] As discussed above, some IC chips suitable for flip chip bonding may include a large number of bumps to dock with an increased number of signals. For example, with the recent increase in display resolution, a display driver IC configured to drive a display panel (e.g., an OLED display panel, a micro-LED display panel, and an LCD panel) may include an increased number of bumps to provide an increased number of signals (e.g., data voltages for updating pixels) to the display panel. The display driver IC chip may include hundreds to thousands of bumps to output data signals to the display panel via the bumps. As the number of bumps increases, the number of bonding pads bonded to the bumps and the number of wiring traces coupled to the bonding pads may also increase.

[0026] To facilitate placement of bonding pads and routing traces, the bumps may be arranged in a "staggered" arrangement. In a staggered bump arrangement, the bumps may be arranged in multiple rows, wherein corresponding bumps of adjacent rows are offset from each other, and the bonding pads may be arranged in positions determined according to the staggered bump arrangement. The staggered bump arrangement may allow an increased number of routing traces to be placed in the bonding pad array while reducing the area required to arrange the bumps on the IC chip.

[0027] In an implementation in which a large number of bumps are arranged within a limited width of a bump array, an increased number of bump rows can be arranged in a bump array. The present disclosure recognizes that an increase in the number of bump rows may cause difficulties in the placement of wiring traces coupled to bonding pads bonded to the bumps, because the number of wiring traces passing between adjacent bumps (or between adjacent bonding pads) may also increase. The present disclosure provides an implementation in which an increased number of bump rows are arranged in a bump array to facilitate the placement of wiring traces coupled to bonding pads. It should be noted that although the following mainly describes an implementation based on a display driver IC, the technology can be applied to other types of ICs.

[0028] Figure 1An example configuration of a display device 1000 is shown. In the example shown, the display device 1000 includes a display panel 100, a display driver IC 200, and a flexible printed circuit board (FPC) 500. The display panel 100 includes a pixel array arranged in an active area 105. In one implementation, the display panel 100 is an OLED display panel. In an alternative implementation, the display panel 100 may be a micro-LED display panel, an LCD panel, or another type of display panel. The display driver IC 200 is configured to drive or update pixels of the display panel 100 based on image data (the image data is generated by an image source (such as an application processor (AP), a central processing unit (CPU), or other processors configured to generate the image data)). The FPC 500 includes wiring traces or interconnections to provide image data and other control data and / or control signals to the display driver IC 200. The FPC 500 may also include other components (e.g., one or more ICs, capacitors, and / or other passive components) for signal processing and / or conversion.

[0029] Figure 2 Show Figure 1 1000 is an example side view configuration of the display device 1000 shown in FIG. In one or more embodiments, the display driver IC 200 is mounted on the display panel 100 using a flip chip bonding technique. The FPC 500 is bonded to the display panel 100 to provide signals to the display driver IC 200 via conductors formed on the display panel 100.

[0030] Figure 31 is a partially enlarged side view of the display device 1000, which shows an example bonding structure for bonding the display driver IC 200 to the display panel 100. In the example shown, the display driver IC 200 includes a semiconductor chip 210 having a main surface, and the bump arrays 220 and 230 are formed on the main surface to realize flip chip bonding. The main surface mentioned herein is the surface facing the display panel 100. The bump array 220 includes a bump set used by the display driver IC 200 to output a signal (e.g., a data voltage for updating a pixel on the display panel 100) to a component on the display panel 100. Therefore, the bump array 220 may also be referred to as the output bump array 220 hereinafter. The bump array 230 includes a bump set for inputting data and / or signals (e.g., display data, control data, control signals, and other data / signals) to the display driver IC 200. Therefore, the bump array 230 may also be referred to as the input bump array 230 hereinafter. The display panel 100 includes a substrate 110 and conductors 120 and 130 formed on the substrate 110. In one implementation, the conductors 120 and 130 may be formed of indium tin oxide (ITO). The bumps of the output bump array 220 are bonded to the conductor 120, and the bumps of the input bump array 230 are bonded to the conductor 130. An anisotropic conductive film (ACF) layer may be used to bond the bump arrays 220 and 230 to the conductors 120 and 130. The conductor 120 is used to provide a signal from the display driver IC 200 to the relevant components (e.g., pixels) of the display panel 100, and the conductor 130 is used to provide a signal and / or data (e.g., image data, control data, and / or control signal) to the display driver IC 200.

[0031] Figure 4 An example arrangement of bump arrays 220 and 230 on the main surface of semiconductor chip 210 is shown. Figure 4 (and subsequent figures), the plane direction in the main surface of the semiconductor chip 210 can be defined by the X-axis and Y-axis defined perpendicular to each other. In the embodiment shown, the main surface of the semiconductor chip 210 has a rectangular shape, and the rectangular shape has long sides 210a, 210b and short sides 210c and 210d. Long sides 210a and 210b are oriented in a first planar direction parallel to the X-axis (this direction may also be referred to as a horizontal plane direction), while short sides 210c and 210d are oriented in a second planar direction parallel to the Y-axis (this direction may also be referred to as a vertical plane direction). The semiconductor chip 210 is arranged so that the long side 210a faces the active area 105 of the display panel 100.

[0032] The output bump array 220 has a "staggered" bump arrangement in which bumps are arranged in multiple rows, wherein the corresponding bumps of adjacent rows deviate from each other. In the example shown, the output bump array 220 includes a plurality of bump rows 240, each of which includes a plurality of bumps 250 aligned in the horizontal plane direction (i.e., the X-axis direction), wherein the corresponding bumps 250 in the adjacent bump rows 240 are positioned to deviate from each other in the horizontal plane direction. In the example shown, the output bump array 220 includes six bump rows 240-1, 240-2, 240-3, 240-4, 240-5, and 240-6. The bump row 240-1 is closest to the long side 210a, the bump row 240-2 is the second closest to the long side 210a, the bump row 240-3 is the third closest to the long side 210a, and so on. The bump 250-2 of the bump row 240-2 is positioned to be offset from the corresponding bump 250-1 of the bump row 240-1 in the horizontal plane direction, the bump 250-3 of the bump row 240-3 is positioned to be offset from the corresponding bump 250-2 of the bump row 240-2 in the horizontal plane direction, and so on. Figure 4 Six bump rows 240 are shown in FIG. 2 , but the output bump array 220 may include fewer or more than six bump rows.

[0033] Figure 5A yes Figure 4 FIG. 2 is a partial enlarged view of the output bump array 220. As described above, the output bump array 220 includes six bump rows 240-1, 240-2, 240-3, 240-4, 240-5, and 240-6. When the bump rows 240-1 to 240-6 are not distinguished from each other, the bump rows 240-1 to 240-6 may be collectively referred to as bump rows 240. Each of the bump rows 240-1, 240-2, 240-3, 240-4, 240-5, and 240-6 includes an array of bumps 250 aligned in a horizontal plane direction (or an X-axis direction).

[0034] Figure 5B 1 is a partially enlarged view showing an example arrangement of the conductors 120 provided on the substrate 110 of the display panel 100. Figure 5B Shown in Figure 5A 1 and 14. The conductor 120 is coupled to a portion of the output bump array 220 shown in FIG. The conductor 120 forms a bonding pad array 125 including a plurality of bonding pad rows 140-1, 140-2, 140-3, 140-4, 140-5, and 140-6. Each of the bonding pad rows 140-1 to 140-6 includes an array of bonding pads 150 aligned in a horizontal plane direction. When the bonding pad rows 140-1 to 140-6 are not distinguished from each other, the bonding pad rows 140-1 to 140-6 may be collectively referred to as bonding pad rows 140.

[0035] The bonding pads 150 of each bonding pad row 140 are respectively bonded to the corresponding bumps 250 of the corresponding bump row 240. More specifically, the bonding pads 150 of the bonding pad row 140-1 are bonded to the corresponding bumps 250 of the bump row 240-1, the bonding pads 150 of the bonding pad row 140-2 are bonded to the corresponding bumps 250 of the bump row 240-2, the bonding pads 150 of the bonding pad row 140-3 are bonded to the corresponding bumps 250 of the bump row 240-3, etc. In other words, the bonding pads 150 of the bonding pad row 140-i are bonded to the corresponding bumps 250 of the bump row 240-i, where i is any integer between one and six (inclusive). The planar shape of the bonding pad 150 (eg, the width in the horizontal plane (or X-axis) direction and the height in the vertical plane (or Y-axis) direction) is substantially the same as those of the corresponding bump 250 .

[0036] The conductor 120 also includes wiring traces 160 coupled to the bonding pads 150, respectively. The wiring traces 160 provide electrical connections between the bonding pads 150 and circuit elements provided in the active area 105 of the display panel 100, such as source lines, pixels, and multiplexers configured to select source lines coupled to the bonding pads 150 (if such multiplexers are provided in the active area 105). Signals and / or voltages output from the bumps 250 of the display driver IC 200 (e.g., data voltages for driving pixels of the display panel 100) are provided to the active area 105 via the corresponding bonding pads 150 and the wiring traces 160. Figure 5B As shown in FIG. 1 (wherein a dashed line 170a indicates a projection of a long side 210a of the display driver IC 200 onto the display panel 100), the wiring trace 160 passes under the long side 210a of the display driver IC 200. In addition, a series of five wiring traces 160 respectively coupled to the bonding pads 150 of the bonding pad rows 140-2 to 140-6 pass between every two of the bonding pads 150 of the bonding pad row 140-1.

[0037] Fig. 6A Show Figure 5A The bump 250 of the display driver IC 200 shown in FIG. Figure 5B 1 shows the positional relationship between the wiring traces 160 of the display panel 100 shown in FIG. Note that the wiring traces 160 are indicated by dotted lines because the wiring traces 160 are actually positioned below the display driver IC 200. Fig. 6A In the example shown in , all bumps 250 have the same horizontal width of "a". Fig. 6AIn the embodiment of the present invention, "A" indicates the spacing between two horizontally adjacent bumps 250 in each bump row 240. In addition, "X" indicates the horizontal spacing between two adjacent bumps 250 in each bump row 240. As mentioned herein, the horizontal spacing between two adjacent bumps 250 is the distance between the vertical center lines of two horizontally adjacent bumps 250 in the horizontal plane direction. Fig. 6A In the example shown in , the pitch “ p1 ” between two horizontally adjacent routing traces 160 is X / 6.

[0038] With the recent increase in display resolution, the display driver IC may be configured to provide an increased number of signals (e.g., data voltages for driving or updating pixels) to the display panel. The increase in the number of signals provided to the display panel may be accompanied by an increase in the number of bumps and bonding pads. In such cases, the increased number of bump rows may be arranged in a bump array.

[0039] Figure 6B 2 shows an example effect of increasing the number of bump rows, where eight bump rows 240-1 to 240-8 are arranged in the bump array 220. Figure 6B In the example shown in FIG. 1 , the horizontal spacing “X” between two adjacent bumps 250 in each bump row 240 is equal to Fig. 6A The example shown in FIG. 2 is unchanged from that in FIG. 2 , because increasing the horizontal spacing “X” between two adjacent bumps 250 will undesirably increase the horizontal width of the bump row 240 and thereby increase the chip size of the display driver IC 200. Figure 6B In the example shown in FIG. 1 , the spacing “p2” between two horizontally adjacent routing traces 160 is X / 8, which is less than Fig. 6A In the example shown in FIG. 8 , a spacing “ p1 ” is provided between two horizontally adjacent routing traces 160 .

[0040] The present disclosure recognizes that increasing the number of bump rows 240 undesirably increases the number of routing traces 160 passing between two horizontally adjacent bumps 250, thereby reducing the spacing between two horizontally adjacent routing traces 160. Since routing trace design rules define the minimum line width of routing traces, the minimum spacing between adjacent routing traces, and other constraints on routing trace placement, reducing the spacing between two horizontally adjacent routing traces 160 may make it difficult to design routing traces 160 within the design rules. An example embodiment for facilitating the placement of routing traces coupled to bonding pads in a case where an increased number of bump rows are arranged in a bump array is presented below. It should be noted that although the following mainly describes embodiments based on display driver ICs, the technology disclosed herein may be applied to other types of ICs.

[0041] Figure 7 Shows an example arrangement for facilitating the placement of wiring traces coupled to bond pads, according to one or more embodiments. Figure 7 The right portion of [reference] shows an example arrangement of a bump array 420 for facilitating wiring placement, according to one or more embodiments, while Figure 7 the left portion of [reference] shows, as a comparative example, Figure 6B the bump arrangement shown in [reference]. In Figure 7 the right portion of [reference], reference numeral 410a refers to the long side of the display driver IC, which corresponds to the long side 210a of the display driver IC 200.

[0042] As Figure 7 shown in the right portion of [reference], the bump array 420 includes eight bump rows 440-1, 440-2, 440-3, 440-4, 440-5, 440-6, 440-7, and 440-8. The bump row 440-1 is closest to the long side 410a, the bump row 440-2 is the second closest to the long side 410a, the bump row 440-3 is the third closest to the long side 410a, and so on. Each of the bump rows 440-1 to 440-8 includes bumps 450 (two are shown for each bump row) aligned in the horizontal plane direction. The bumps 450 of the bump rows 440-1, 440-2, 440-3, 440-4, 440-5, 440-6, 440-7, and 440-8 may be referred to as bumps 450-1, 450-2, 450-3, 450-4, 450-5, 450-6, 450-7, and 450-8, respectively.

[0043] In the illustrated embodiment, the horizontal widths of the bumps 450-1, 450-2, 450-3, 450-4, 450-5, 450-6, 450-7, and 450-8 are narrower as the respective distances from the long side 410a of the display driver IC decrease. The "horizontal width" of a bump as referred to herein is the height of the bump in the horizontal plane (or X-axis) direction. More specifically, the bumps 450-1, 450-2, 450-3, 450-4, 450-5, 450-6, 450-7, and 450-8 have horizontal widths of "b", "c", "a", "d", "e", "f", "g", and "h", respectively, where b < c < a < d < e < f < g < h. In this bump arrangement, the horizontal spacing between adjacent bumps 450 is wider as the distance from the long side 410a decreases. Such a bump arrangement effectively facilitates the placement of an increased number of wiring traces passing between two horizontally adjacent bumps 450 by relaxing the constraints on the width and / or spacing of the wiring traces 360 passing between two adjacent bumps 450.

[0044] More specifically, the bump 450-1 of the bump row 440-1 (the bump is closest to the long side 410a of the semiconductor chip 410) has the narrowest horizontal width "b". When the maximum number (seven in the illustrated embodiment) of wiring traces 360 pass between two adjacent bumps 450-1, the use of the narrowest horizontal width "b" of the bump 450-1 allows the spacing "D" between the two adjacent bumps 450-1 to increase, thereby effectively relaxing the constraints on the width of the wiring trace 360 ​​and the spacing or spacing between the two adjacent wiring traces 360. In some embodiments, the horizontal width "b" of the bump 450-1 of the bump row 440-1 can be the minimum horizontal width allowed for the bump defined by the design rules. In addition, the bump 450-2 of the bump row 440-2 (the bump is second closest to the long side 410a of the semiconductor chip 410) has the second narrowest horizontal width "c". When a second largest number (six in the illustrated embodiment) of routing traces 360 pass between two adjacent bumps 450-2, the use of a second narrow horizontal width "c" of the bump 450-2 allows the spacing between two adjacent bumps 450-2 to increase, thereby also effectively relaxing the constraints on the width of the routing trace 360 ​​and the spacing or spacing between two adjacent routing traces 360.

[0045] At the same time, the bump 450-8 of the bump row 440-8 (the bump is farthest from the long side 410a of the semiconductor chip 410) has the widest horizontal width "h". The use of the widest horizontal width "h" of the bump 450-8 does not affect the routing of the wiring trace 360 ​​in any way, because no wiring trace 360 ​​passes between two adjacent bumps 450-8. Similarly, the use of the second widest horizontal width "g" of the bump 450-7 of the bump row 440-7 (the bump is the second farthest from the long side 410a of the semiconductor chip 410) does not affect the routing of the wiring trace 360 ​​in any way, because only one wiring trace 360 ​​passes between two adjacent bumps 450-7.

[0046] In one or more embodiments, the vertical heights (or heights in the vertical plane direction) of the bumps 450-1, 450-2, 450-3, 450-4, 450-5, 450-6, 450-7, and 450-8 are adjusted to decrease as the distance from the long side 410a of the semiconductor chip 410 increases. The "vertical height" of the bumps mentioned herein is the height of the bumps in the vertical plane (or Y-axis) direction. More specifically, bump 450-1 of bump row 440-1 (the bump is closest to long side 410a of semiconductor chip 410) has the largest vertical height, bump 450-2 of bump row 440-2 (the bump is second closest to long side 410a of semiconductor chip 410) has the second largest vertical height, bump 450-3 of bump row 440-3 (the bump is third closest to long side 410a of semiconductor chip 410) has the third largest vertical height, and so on. The vertical heights of bumps 450-1, 450-2, 450-3, 450-4, 450-5, 450-6, 450-7, and 450-8 that decrease with distance from long side 410a allow the total vertical height "Yg" of bump array 420 to be reduced. Figure 7 In the implementation shown in , the total vertical height “Yg” of the bump array 420 is less than the total vertical height “Ya” of the bump array 220 , wherein the vertical height of the bump 250 is constant.

[0047] In one or more embodiments, the horizontal plane width and vertical plane height of the corresponding bumps 450-1 to 450-8 can be adjusted so that the area (or plane area) of the bumps 450-1 to 450-8 is substantially the same. The term "substantially the same" as used herein may mean that the difference is within the range of manufacturing variation. The arrangement in which the areas of the bumps 450-1 to 450-8 are substantially the same allows the contact resistance between the bumps 450-1 to 450-8 and the bonding pads bonded to the bumps 450-1 to 450-8 to be the same, which can improve the performance of the circuit electrically connected to the bumps 450-1 to 450-8. For example, in an embodiment in which a display driver IC is configured to provide data voltages to pixels of a display panel via bumps 450-1 to 450-8 to drive the pixels, a bump arrangement in which the contact resistance between bumps 450-1 to 450-8 and bonding pads bonded to bumps 450-1 to 450-8 is the same can suppress mura or brightness instability that may be caused by variations in contact resistance.

[0048] Figure 8An example configuration of a display driver IC 400 configured to drive a display panel (such as an OLED display panel, a micro LED display panel, and an LCD panel) according to one or more embodiments is shown. In the illustrated embodiment, the display driver IC 400 includes a semiconductor chip 410, an output bump array 420, and an input bump array 430. The display driver IC 400 is configured to generate a data voltage and provide the data voltage to the display panel via the bumps of the output bump array 420 to drive or update the pixels of the display panel with the data voltage. In the illustrated embodiment, the main surface of the semiconductor chip 410 has a rectangular shape having long sides 410a, 410b and short sides 410c and 410d. Long sides 410a and 410b are oriented in a horizontal plane direction parallel to the X axis, while short sides 410c and 410d are oriented in a vertical direction parallel to the Y axis. Note that both the X axis and the Y axis are oriented in the plane direction of the main surface of the semiconductor chip 410. The output bump array 420 is positioned adjacent to the long side 410 a , while the input bump array 430 is positioned adjacent to the long side 410 b .

[0049] Fig.9A According to one or more embodiments Figure 8 The output bump array 420 is a partially enlarged view of the output bump array 420. Figure 7 4. The output bump array 420 is configured as shown in the right part of . In the embodiment shown, the output bump array 420 has a "staggered" bump arrangement in which bumps are arranged in multiple rows (wherein the corresponding bumps of adjacent rows deviate from each other). The output bump array 420 includes a plurality of bump rows 440, each of which includes a plurality of bumps 450 aligned in the horizontal plane direction (i.e., the X-axis direction), wherein the corresponding bumps 450 in the adjacent bump rows 440 are positioned to deviate from each other in the horizontal plane direction. In the example shown, the output bump array 420 includes eight bump rows 440-1, 440-2, 440-3, 440-4, 440-5, 440-6, 440-7 and 440-8. The bump row 440-1 is closest to the long side 410a, the bump row 440-2 is the second closest to the long side 410a, the bump row 440-3 is the third closest to the long side 210a, and so on. The bump 450-2 of the bump row 440-2 is positioned to be offset from the corresponding bump 450-1 of the bump row 440-1 in the horizontal plane direction, the bump 450-3 of the bump row 440-3 is positioned to be offset from the corresponding bump 450-2 of the bump row 440-2 in the horizontal plane direction, and so on. Fig.9AEight bump rows 440 are shown, but the output bump array 420 may include fewer or more than eight bump rows. In other embodiments, the output bump array 420 may be arranged in a bump layout in which corresponding bumps 450 in bump rows 440-1 to 440-8 are aligned in the vertical plane direction. In such embodiments, bump 450-2 of bump row 440-2 may be aligned with corresponding bump 450-1 of bump row 440-1 in the vertical plane direction, bump 450-3 of bump row 440-3 may be aligned with corresponding bump 450-2 of bump row 440-2 in the vertical plane direction, and so on.

[0050] As discussed above for Figure 7 the horizontal widths of bumps 450-1, 450-2, 450-3, 450-4, 450-5, 450-6, 450-7, and 450-8 become narrower as the distance from the long side 410a of the semiconductor chip 410 decreases. More specifically, bumps 450-1, 450-2, 450-3, 450-4, 450-5, 450-6, 450-7, and 450-8 have horizontal widths of "b", "c", "a", "d", "e", "f", "g", and "h", respectively, where b < c < a < d < e < f < g < h. In addition, the vertical heights of bumps 450-1, 450-2, 450-3, 450-4, 450-5, 450-6, 450-7, and 450-8 decrease as the distance from the long side 410a of the semiconductor chip 410 increases. More specifically, bump 450-1 of bump row 440-1 (the bump closest to the long side 410a of the semiconductor chip 410) has the largest vertical height, and bump 450-2 of bump row 440-2 (the bump second closest to the long side 410a of the semiconductor chip 410) has the second largest vertical height, bump 450-3 of bump row 440-3 (the bump third closest to the long side 410a of the semiconductor chip 410) has the third largest vertical height, and so on. In one or more embodiments, the horizontal widths and vertical heights of the respective bumps 450-1 to 450-8 may be adjusted such that the areas (or planar areas) of bumps 450-1 to 450-8 are substantially the same, as discussed for Figure 7

[0051] Fig. 9B is a partial enlarged view showing an example configuration of a display panel 300 driven by a Figure 8 display driver IC 400 according to one or more embodiments. In Fig. 9B is shown coupled to Fig.9A ​4. The display panel 300 includes a portion of the output bump array 420 shown in FIG. The display panel 300 includes an active area 305 and a bonding pad array 325. The active area 305 may include a pixel array, a source line, a gate line, and other circuit elements arranged according to the type of the display panel 300 (e.g., a multiplexer configured to select a source line). The bonding pad array 325 includes a plurality of bonding pad rows 340-1, 340-2, 340-3, 340-4, 340-5, 340-6, 340-7, and 340-8, each of which includes an array of bonding pads 350 aligned in a horizontal plane direction. The bonding pads 350 of the bonding pad rows 340-1 to 340-8 may also be referred to as bonding pads 350-1 to 350-8, respectively. When the bonding pad rows 340 - 1 to 340 - 8 are not distinguished from each other, the bonding pad rows 340 - 1 to 340 - 8 may be collectively referred to as a bonding pad row 340 .

[0052] The bonding pads 350 of each bonding pad row 340 are respectively bonded to corresponding bumps 450 of corresponding bump rows 440. The bonding pads 350-1 of the bonding pad row 340-1 are bonded to corresponding bumps 450-1 of the bump row 440-1, and the bonding pads 350-2 of the bonding pad row 340-2 are bonded to corresponding bumps 450-2 of the bump row 440-2, etc. More specifically, the bonding pads 350-j of the bonding pad row 340-j are bonded to corresponding bumps 450-j of the bump row 440-j, where j is any integer from one to eight.

[0053] The planar shape (e.g., the width in the horizontal plane (or X-axis) direction and the height in the vertical plane (or Y-axis) direction) of the bonding pad 350 is substantially the same as those of the corresponding bump 450. Since the horizontal widths of the bumps 450-1, 450-2, 450-3, 450-4, 450-5, 450-6, 450-7, and 450-8 become narrower as the distance from the long side 410a of the semiconductor chip 410 decreases, the horizontal widths of the bonding pads 350-1, 350-2, 350-3, 350-4, 350-5, 350-6, 350-7, and 350-8 become narrower as the distance from the long side 410a of the semiconductor chip 410 decreases. More specifically, since the bumps 450-1, 450-2, 450-3, 450-4, 450-5, 450-6, 450-7, and 450-8 have horizontal widths of “b,” “c,” “a,” “d,” “e,” “f,” “g,” and “h,” respectively, as described above, the bonding pads 350-1, 350-2, 350-3, 350-4, 350-5, 350-6, 350-7, and 350-8 have horizontal widths of “b,” “c,” “a,” “d,” “e,” “f,” “g,” and “h,” respectively, where b is the horizontal width of the bumps 450-1, 450-2, 450-3, 450-4, 450-5, 450-6, 450-7, and 450-8. <c<a<d<e<f<g<h。

[0054] Furthermore, in one or more embodiments, the vertical heights of the bonding pads 350-1, 350-2, 350-3, 350-4, 350-5, 350-6, 350-7, and 350-8 are adjusted to decrease as the distance from the long side 410a of the semiconductor chip 410 increases. More specifically, the bonding pad 350-1 of the bonding pad row 340-1 (the bonding pad is closest to the long side 410a of the semiconductor chip 410) has the largest vertical height, the bonding pad 350-2 of the bonding pad row 340-2 (the bonding pad is second closest to the long side 410a of the semiconductor chip 410) has the second largest vertical height, the bonding pad 350-3 of the bonding pad row 340-3 (the bonding pad is third closest to the long side 410a of the semiconductor chip 410) has the third largest vertical height, and so on. Furthermore, according to one or more embodiments, similar to the bumps 450-1 to 450-8 of the bump array 420, the horizontal widths and vertical heights of the corresponding bonding pads 350-1 to 350-8 may be adjusted such that the areas (or planar areas) of the bonding pads 350-1 to 350-8 are the same.

[0055] The bonding pads 350-1 to 350-8 are coupled to wiring traces 360, respectively. The wiring traces 360 provide electrical connections between the bonding pads 350 and circuit elements provided in the active area 305 of the display panel 300, such as source lines, pixels, and multiplexers configured to select source lines coupled to the bonding pads 350 (if such multiplexers are provided in the active area 305). Signals and / or voltages output from the bumps 450 of the display driver IC 400 (e.g., data voltages for driving pixels of the display panel 300) are provided to the active area 305 via the corresponding bonding pads 350 and the wiring traces 360. Fig. 9B As shown in FIG. 3 , (wherein a dashed line 370 a indicates a projection of a long side 410 a of the display driver IC 400 onto the display panel 300 ), the routing trace 360 ​​passes under the long side 410 a of the display driver IC 400 .

[0056] Unless otherwise indicated herein or clearly contradicted by context, the use of the terms "a", "an", "the", "at least one", and similar referents in the context of describing the present invention (especially in the context of the following claims) is to be interpreted as covering both the singular and the plural. Unless otherwise indicated herein or clearly contradicted by context, the use of the term "at least one" followed by a listing of one or more items (e.g., "at least one of A and B") is to be interpreted as meaning one item (A or B) selected from the listed items or any combination of two or more items in the listed items (A and B). Unless otherwise indicated, the terms "comprising, including", "having", and "containing" are to be interpreted as open-ended terms (i.e., meaning "including but not limited to"). Unless otherwise indicated herein, the recitation of ranges of values ​​herein is intended merely to serve as a shorthand method of individually referring to each individual value falling within the range, and each individual value is incorporated into the specification as if it were individually recited herein. Unless otherwise indicated herein or otherwise clearly contradicted with the context, all methods described herein can be performed in any suitable order. Unless otherwise claimed, the use of any and all examples or exemplary language (e.g., "such as") provided herein is only intended to better illustrate the present invention and does not limit the scope of the present invention. The language in this specification should not be interpreted as indicating any unclaimed elements that are necessary for practicing the present invention.

[0057] Exemplary embodiments are described herein. When reading the foregoing description, variations of those exemplary embodiments may become apparent to those of ordinary skill in the art. The inventor expects that the skilled person will adopt such variations when appropriate, and the inventor intends to practice the present invention in other ways except as specifically described herein. Therefore, the present invention includes all modifications and equivalents of the subject matter recorded in the claims attached to the present invention as permitted by applicable law. In addition, unless otherwise indicated herein or otherwise clearly contradictory to the context, the present invention includes any combination of the above-described elements in all possible variations thereof.

Claims

1. An integrated circuit, comprising: A semiconductor chip comprising a first side oriented in a first planar direction; a first bump row including a plurality of first bumps aligned along the first side in the first planar direction; as well as a second bump row including a plurality of second bumps aligned in the first planar direction, the second bump row being positioned farther from the first side of the semiconductor chip than the first bump row, Wherein, a first width of the first bump in the first plane direction is narrower than a second width of the second bump in the first plane direction.

2. The integrated circuit of claim 1, wherein: A first height of the first bump in a second planar direction perpendicular to the first planar direction is greater than a second height of the second bump in the second planar direction.

3. The integrated circuit of claim 2, wherein: A first area of ​​one of the plurality of first bumps is substantially equal to a second area of ​​one of the plurality of second bumps.

4. The integrated circuit of claim 1, wherein: Each of the second bumps is positioned to be offset from a corresponding one of the first bumps in the first planar direction.

5. The integrated circuit of claim 1 , further comprising a third bump row, the third bump row comprising a plurality of third bumps aligned in the first planar direction, in, The third bump row is positioned farther from the first side of the semiconductor chip than the second bump row, and, The second width of the second bump in the first plane direction is narrower than the third width of the third bump in the first plane direction.

6. The integrated circuit of claim 5, wherein: A first height of the first bump in a second planar direction perpendicular to the first planar direction is greater than a second height of the second bump in the second planar direction, The second height of the second bump is greater than the third height of the third bump in the second plane direction, and, Wherein, one of the plurality of first bumps, one of the plurality of second bumps, and one of the plurality of third bumps respectively have substantially equal areas.

7. The integrated circuit of claim 1, wherein: The integrated circuit is a display driver integrated circuit (IC) configured to drive a display panel.

8. The integrated circuit of claim 7, wherein: The display driver IC is configured as: generating data voltages, pixels of the display panel being driven using the data voltages; and The data voltage is provided to the display panel via the first bump and the second bump.

9. The integrated circuit of claim 7, wherein: The semiconductor chip further includes a second side oriented in a second planar direction perpendicular to the first planar direction, and Wherein, the second side is shorter than the first side.

10. A display device, comprising: Display panel; as well as A display driver integrated circuit (IC) bonded to the display panel, the display driver IC comprising: A semiconductor chip comprising a first side oriented in a first planar direction; A first bump row includes a plurality of a first bump; and a second bump row including a plurality of second bumps aligned in the first planar direction, the second bump row being positioned farther from the first side of the semiconductor chip than the first bump row, Wherein, a first width of the first bump in the first plane direction is narrower than a second width of the second bump in the first plane direction.

11. The display device according to claim 10, wherein: A first height of the first bump in a second planar direction perpendicular to the first planar direction is greater than a second height of the second bump in the second planar direction.

12. The display device according to claim 11, wherein: A first area of ​​one of the plurality of first bumps is substantially equal to a second area of ​​one of the plurality of second bumps.

13. The display device according to claim 10, wherein: Each of the second bumps is positioned to be offset from a corresponding one of the first bumps in the first planar direction.

14. The display device according to claim 10, wherein: The display panel comprises: an active area, which includes pixels; a plurality of first bonding pads, the plurality of first bonding pads being respectively bonded to the plurality of first bumps of the first bump row; a plurality of second bonding pads, the plurality of second bonding pads being respectively bonded to the plurality of second bumps of the second bump row; a plurality of first routing traces electrically coupling the first bonding pad to the active area; and A plurality of second routing traces electrically couple the first bonding pad to the active region.

15. The display device according to claim 14, wherein: The plurality of first and second wiring traces include wiring trace portions extending in a second planar direction perpendicular to the first planar direction to pass under the first side of the display driver IC.

16. The display device according to claim 10, wherein the display driver IC further comprises a third bump row, the third bump row comprising a plurality of third bumps aligned in the first planar direction, in, the third bump row being positioned farther from the first side of the semiconductor chip than the second bump row, wherein each of the third bumps is positioned to be offset from a corresponding one of the second bumps in the first plane direction, and, The second width of the second bump in the first plane direction is narrower than the third width of the third bump in the first plane direction.

17. The display device according to claim 16, wherein: A first height of the first bump in a second planar direction perpendicular to the first planar direction is greater than a second height of the second bump in the second planar direction, The second height of the second bump is greater than the third height of the third bump in the second plane direction, and, Wherein, one of the plurality of first bumps, one of the plurality of second bumps, and one of the plurality of third bumps respectively have substantially equal areas.

18. A method comprising: The data voltage is generated by a display driver IC, the display driver IC comprising: A semiconductor chip comprising a first side oriented in a first planar direction; A first bump row includes a plurality of a first bump; and a second bump row including a plurality of second bumps aligned in the first planar direction, the second bump row being positioned farther from the first side of the semiconductor chip than the first bump row, wherein a first width of the first bump in the first plane direction is narrower than a second width of the second bump in the first plane direction; and The data voltage is provided to the display panel via the plurality of first bumps and the plurality of second bumps.

19. The method of claim 18, wherein: A first height of the first bump in a second planar direction perpendicular to the first planar direction is greater than a second height of the second bump in the second planar direction.

20. The method of claim 19, wherein: A first area of ​​one of the plurality of first bumps is substantially equal to a second area of ​​one of the plurality of second bumps.

Images