Semiconductor structure and preparation method thereof, storage system and electronic equipment

Abstract

The invention provides a semiconductor structure and a preparation method thereof, a storage system and electronic equipment, relates to the technical field of semiconductor chips, and aims to solve the problem of burnout of a metal interconnection layer. The semiconductor structure includes a device structure, a pad and a first contact structure disposed on the device structure, a first conductive structure, and a first connection portion connecting the pad and the first contact structure. The device structure comprises a semiconductor layer and a metal interconnection layer arranged on the semiconductor layer. And the bonding pad is connected with the metal interconnection layer. The first conductive structure is disposed on the semiconductor layer. The bonding pad is arranged on one side of the metal interconnection layer away from the semiconductor layer, and the first contact structure is arranged on one side of the metal interconnection layer away from the semiconductor layer. The first contact structure is connected to the semiconductor layer through the metal interconnection layer and the first conductive structure. The semiconductor structure is applied to the three-dimensional memory so as to realize data reading and writing operation.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor structure and a preparation method thereof, a storage system, and an electronic device. Background Art

[0002] As the feature size of the memory cell approaches the process limit, the planar process and manufacturing technology become challenging and costly, which causes the storage density of 2D or planar NAND flash memory to approach the upper limit. To overcome the limitations of 2D or planar NAND flash memory, the industry has developed a memory with a three-dimensional structure (3D NAND), which increases the storage density by arranging the memory cells three-dimensionally on the substrate.

[0003] In a three-dimensional memory, pads are used to implement signal transmission and connection of multiple partition structures in the three-dimensional memory.

[0004] However, in actual use, some pads may cause metal wiring in the three-dimensional memory to burn out due to leakage, resulting in failure of the three-dimensional memory. Summary of the invention

[0005] The embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, a storage system, and an electronic device, aiming to solve the problem of burning of a metal interconnection layer.

[0006] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0007] On the one hand, a semiconductor structure is provided. The semiconductor structure includes a device structure, a pad and a first contact structure arranged on the device structure, a first conductive structure, and a first connection portion connecting the pad and the first contact structure. The device structure includes a semiconductor layer and a metal interconnect layer arranged on the semiconductor layer. The pad is connected to the metal interconnect layer. The first conductive structure is arranged on the semiconductor layer. The pad is arranged on a side of the metal interconnect layer away from the semiconductor layer, and the first contact structure is arranged on a side of the metal interconnect layer away from the semiconductor layer. The first contact structure is connected to the semiconductor layer through the metal interconnect layer and the first conductive structure.

[0008] In the semiconductor structure provided by the above-mentioned embodiment of the present disclosure, the first contact structure is connected to the semiconductor layer through the metal interconnection layer and the first conductive structure to achieve electrostatic protection, and the pad is connected to the first contact structure through the first connection portion, so that the charge generated on the pad is connected to the semiconductor layer through the first connection portion, the first contact structure and the first conductive structure, so as to play the role of electrostatic protection for the pad. Therefore, it is possible to avoid the charge generated during the packaging process from accumulating on the pad, thereby avoiding voltage overload of the metal interconnection layer connected to the pad, and avoiding burning of the metal interconnection layer.

[0009] In some embodiments, the metal interconnect layer includes a metal contact structure connected to the first conductive structure; the first conductive structure and the metal contact structure are connected to form a first sealing ring.

[0010] In some embodiments, the first conductive structure includes an electrostatic protection circuit; and the first contact structure is connected to the semiconductor layer through the metal interconnect layer and the electrostatic protection circuit.

[0011] In some embodiments, the semiconductor structure also includes a second contact structure and a second conductive structure; the second contact structure is arranged on the side of the metal interconnection layer away from the semiconductor layer; the second conductive structure is arranged on the semiconductor layer; the second contact structure is connected to the semiconductor layer through the metal interconnection layer and the second conductive structure; the semiconductor structure also includes a second connecting portion; the second connecting portion connects the second contact structure and the pad.

[0012] In some embodiments, the semiconductor structure further includes a third connection portion; the third connection portion connects the first contact structure and the second contact structure.

[0013] In some embodiments, the second conductive structure includes an electrostatic protection circuit; the metal interconnect layer includes a metal contact structure connected to the first conductive structure; and the first conductive structure and the metal contact structure are connected to form a second sealing ring.

[0014] In some embodiments, the pad, the first contact structure, and the first connecting portion are disposed in the same layer.

[0015] In some embodiments, the device structure includes a first sub-device structure and a second sub-device structure; the semiconductor layer is located on the side of the second sub-metal interconnect layer away from the first sub-device structure; the first sub-device structure and the second sub-device structure are coupled through the metal interconnect layer; the semiconductor structure also includes a third conductive structure and a fourth conductive structure; the third conductive structure runs through the first sub-device structure, and the fourth conductive structure runs through the first sub-device structure; the pad is connected to the metal interconnect layer through the third conductive structure; the first contact structure is connected to the semiconductor layer through the fourth conductive structure, the metal interconnect layer and the first conductive structure.

[0016] In some embodiments, the first sub-device structure also includes a stacked substrate and a first dielectric layer; the third conductive structure includes a first through contact and a first interconnect contact, the first through contact penetrates the substrate, and the first interconnect contact penetrates the first dielectric layer; the fourth conductive structure includes a second through contact and a second interconnect contact, the second through contact penetrates the substrate, and the second interconnect contact penetrates the first dielectric layer.

[0017] In some embodiments, the metal interconnect layer includes a metal contact structure connected to a first conductive structure; the first conductive structure and the metal contact structure are connected to form a first sealing ring; the second through contact is connected to a second interconnect contact to form a third sealing ring; the first sealing ring and the third sealing ring are connected.

[0018] In some embodiments, the first through-contact and the second through-contact are disposed on the same layer; the first interconnection contact and the second interconnection contact are disposed on the same layer.

[0019] In some embodiments, one of the first sub-device structure and the second sub-device structure is an array device structure, and the other is a peripheral device structure.

[0020] In some embodiments, the first sub-device structure includes an array device structure and the second sub-device structure includes a peripheral device structure.

[0021] On the other hand, a method for preparing a semiconductor structure is provided, comprising: providing a device structure; the device structure comprising a semiconductor layer and a metal interconnection layer arranged on the semiconductor layer; a first conductive structure is arranged on the semiconductor layer and connected to the metal interconnection layer; forming a solder pad; the solder pad is formed on a side of the metal interconnection layer away from the semiconductor layer; the solder pad is connected to the metal interconnection layer; forming a first contact structure; the first contact structure is formed on a side of the metal interconnection layer away from the semiconductor layer; the first contact structure is connected to the semiconductor layer through the metal interconnection layer and the first conductive structure; forming a first connecting portion, the first connecting portion connecting the solder pad and the first contact structure.

[0022] In the method for preparing the semiconductor structure provided by the above-mentioned embodiment of the present disclosure, the first contact structure is connected to the semiconductor layer through the metal interconnection layer and the first conductive structure to achieve electrostatic protection, and a first connection portion is formed, and the pad is connected to the first contact structure through the first connection portion, so that the charge generated on the pad is connected to the semiconductor layer through the first connection portion, the first contact structure and the first conductive structure, so as to play an electrostatic protection role for the pad. Therefore, it is possible to avoid the charge generated during the packaging process from accumulating on the pad, thereby avoiding voltage overload of the metal interconnection layer connected to the pad, and avoiding burning of the metal interconnection layer.

[0023] In addition, in the solution provided by the embodiment of the present application, during the preparation process, only a slight change is required to the mask for forming the pad and the first contact structure, so that the pad, the first contact structure and the first connecting portion can be formed in the same process step. Therefore, the solution provided by the embodiment of the present application has a simple process, does not require additional processes, and is easy to operate.

[0024] In some embodiments, the preparation method also includes: forming a second contact structure; the second contact structure is formed on the side of the metal interconnect layer away from the semiconductor layer; the second contact structure is connected to the semiconductor layer through the metal interconnect layer and the second conductive structure; the second conductive structure is disposed on the semiconductor layer; forming a second connecting portion; the second connecting portion connects the second contact structure and the pad.

[0025] In some embodiments, the preparation method further includes: forming a third connecting portion; the third connecting portion connects the first contact structure and the second contact structure.

[0026] In yet another aspect, a storage system is provided, comprising: the semiconductor structure as described above, and a controller coupled to the semiconductor structure to control the semiconductor structure to store data.

[0027] On the other hand, an electronic device is provided, comprising the storage system as described above.

[0028] It can be understood that the beneficial effects that can be achieved by the storage system and electronic device provided by the above embodiments of the present disclosure can refer to the beneficial effects of the semiconductor structure described above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0030] Figure 1A A block diagram of a storage system provided in an embodiment of the present application;

[0031] Figure 1B A structural block diagram of a memory card provided in an embodiment of the present application;

[0032] Figure 1C A structural block diagram of another memory card provided in an embodiment of the present application;

[0033] Figure 2A A schematic diagram of the three-dimensional structure of a three-dimensional memory provided in an embodiment of the present application;

[0034] Figure 2B A partial cross-sectional view of a three-dimensional memory provided in an embodiment of the present application;

[0035] Figure 3 A schematic diagram of a semiconductor structure provided in an embodiment of the present application;

[0036] Figure 4 A schematic diagram of another semiconductor structure provided in an embodiment of the present application;

[0037] Figure 5 A schematic diagram of a process for preparing a semiconductor structure provided in an embodiment of the present application;

[0038] Figure 6A-6G A schematic diagram of a process of preparing a semiconductor structure provided in an embodiment of the present application;

[0039] Figure 7A-7D A schematic diagram of another method for preparing a semiconductor structure provided in an embodiment of the present application;

[0040] Figure 8A-8C A schematic diagram of a process of another method for preparing a semiconductor structure provided in an embodiment of the present application;

[0041] Figure 9A-9B A schematic diagram of a process of another method for preparing a semiconductor structure provided in an embodiment of the present application;

[0042] Fig.10 A schematic diagram of a process of another method for preparing a semiconductor structure provided in an embodiment of the present application;

[0043] Figure 11A-11B A schematic diagram of a process of another method for preparing a semiconductor structure provided in an embodiment of the present application;

[0044] Figure 12A-12B A schematic diagram of a process of another method for preparing a semiconductor structure provided in an embodiment of the present application;

[0045] Fig.13 A schematic diagram of another semiconductor structure provided in an embodiment of the present application;

[0046] Fig.14A A schematic diagram of another semiconductor structure provided in an embodiment of the present application;

[0047] Fig. 14B A schematic diagram of another semiconductor structure provided in an embodiment of the present application;

[0048] Fig.15A A schematic diagram of another semiconductor structure provided in an embodiment of the present application;

[0049] Fig. 15B A schematic diagram of another semiconductor structure provided in an embodiment of the present application;

[0050] Fig. 15C A schematic diagram of another semiconductor structure provided in an embodiment of the present application;

[0051] Fig.16A A schematic diagram of another semiconductor structure provided in an embodiment of the present application;

[0052] Fig. 16B A schematic diagram of another semiconductor structure provided in an embodiment of the present application;

[0053] Fig.17 A schematic diagram of another semiconductor structure provided in an embodiment of the present application;

[0054] Fig.18 A schematic diagram of another semiconductor structure provided in an embodiment of the present application;

[0055] Fig.19 A schematic structural diagram of another semiconductor structure provided in an embodiment of the present application.

[0056] Reference numerals

[0057] 10-semiconductor structure; 100-device structure; 130-first sub-device structure; 140 second sub-device structure; 110-semiconductor layer; 120-metal interconnect layer; 121-metal contact structure; 122-first metal interconnect layer; 123-second metal interconnect layer; 200-pad; 310-first contact structure; 320-second contact structure; 410-first conductive structure; 411-electrostatic protection circuit; 420-second conductive structure; 430-third conductive structure; 440-fourth Conductive structure; 450-fifth conductive structure; 510-first connecting part; 520-second connecting part; 530-third connecting part; 610-first sealing ring; 620-second sealing ring; 630-third sealing ring; 131-substrate; 132-first dielectric layer; 133-second dielectric layer; 133'-second dielectric film; 134-mask layer; 135-photoresist; 431-first through contact; 432-first interconnection contact; 441-second through contact; 442-second interconnection contact. DETAILED DESCRIPTION

[0058] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0059] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0060] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0061] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0062] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0063] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0064] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0065] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0066] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0067] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0068] In the context of the present disclosure, the meanings of “on,” “over,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “over” or “above” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something without intervening features or layers therebetween (i.e., directly on something).

[0069] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0070] As used herein, the term "substrate" refers to a material on which subsequent material layers may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0071] The term "three-dimensional memory" refers to a semiconductor device formed by a memory cell transistor string (referred to herein as a "memory cell string", such as a NAND memory cell string) arranged in an array on a main surface of a substrate or source layer and extending in a direction perpendicular to the substrate or source layer. As used herein, the term "vertical / vertically" means nominally perpendicular to the main surface (i.e., lateral surface) of the substrate or source layer.

[0072] The embodiment of the present application provides an electronic device, which may be a mobile phone, a mobile phone, a desktop computer, a tablet computer, a laptop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device (such as a smart watch, a smart bracelet, smart glasses, etc.), a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, a server, or any other suitable electronic device having a storage device. The embodiment of the present application does not specifically limit the specific form of the above-mentioned electronic device, and it may be any electronic device having a storage device. In some embodiments, the electronic device may include a printed circuit board in addition to a storage device. The printed circuit board is coupled to the storage device and integrated into the electronic device.

[0073] The storage device may be a universal flash storage (UFS) package or an embedded Multi Media Card (eMMC) package, wherein the storage system may be integrated into various types of storage devices.

[0074] An example of a storage system structure is as follows: Figure 1A As shown, the storage system 1 mainly includes one or more memory devices 2 and a memory controller 3, and the memory controller 3 is coupled to the memory device 2 to control the storage data of the memory device 2. Among them, the storage system 1 can be integrated into a variety of memory cards such as a personal computer memory card international association (PCMCIA or PC), a compact flash (CF) card, a smart media (SM) card, a memory stick, a multimedia card (MMC), a secure digital memory card (SD), a universal flash storage (UFS) and a solid state drive (SSD). The embodiment of the present application does not limit the number of memory devices 2 included in the storage system 1, and it can be reasonably set according to actual conditions.

[0075] The memory controller 3 is configured to operate in a low duty cycle environment, which may include, for example, an SD card, a CF card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0076] Alternatively, the memory controller 3 is configured to operate in a high duty cycle environment SSD or eMMC used for data storage of mobile devices such as smartphones, tablet computers, laptop computers, and enterprise storage arrays.

[0077] Alternatively, the memory controller 3 is configured to manage data stored in the memory device 2 and communicate with an external device (e.g., a host) according to a specific communication protocol. The communication protocol includes at least one of a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI-E protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer system interface (SCSI) protocol, an enhanced small drive interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, and a FireWire protocol.

[0078] The memory controller 3 may also be configured to control the operation of the memory device 2, such as read, erase, and program operations. In some embodiments, the memory controller 3 may also be configured to manage various functions regarding data stored or to be stored in the memory device 2, including at least one of bad block management, garbage collection, logical to physical address conversion, and wear leveling. In some embodiments, the memory controller 3 may also be configured to process error correction codes regarding data read from the memory device 2 or written to the memory device 2. The memory controller 3 may also perform any other suitable functions, such as formatting the memory device 2.

[0079] In some embodiments, Figure 1A As shown, the storage system 1 includes a host 4. For example, the host 4 is coupled to a memory controller 3.

[0080] Exemplarily, the storage system 1 may be integrated into the above-mentioned electronic device. The host 4 may be a processor of the electronic device, such as a central processing unit (CPU), or may be a system-on-chip (SoC), such as an application processor (AP). The host 4 may be configured to send or receive data to and from the memory device 2.

[0081] The memory controller 3 is coupled to the memory device 2 and the host 4, and is configured to control the memory device 2. The memory controller 3 can manage data stored in the memory device 2 and communicate with the host 4. In some embodiments, the memory controller 3 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact Flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 3 is designed to operate in a high duty cycle environment, such as an SSD or an embedded multi-media card 28 (embedded multi-media-card, eMMC) used as a data storage device for mobile devices, and an enterprise storage array, and the mobile device is a smart phone, a tablet computer, a laptop computer, etc. The memory controller 3 can be configured to control the operation of the memory device 2, such as read, erase, and program operations. In some embodiments, the memory controller 3 is configured to control an array of memory cells through a first peripheral circuit and a second peripheral circuit. The memory controller 3 may also be configured to manage various functions related to data stored in or to be stored in the memory device 2, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 3 is further configured to process error correction codes (ECC) related to data read from or written to the memory device 2. Any other appropriate functions may also be performed by the memory controller 3, such as formatting the memory device 2. The memory controller 3 may communicate with an external device (e.g., a host 4) according to a specific communication protocol.For example, the memory controller 3 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, peripheral component interconnection (PCI) protocol, high-speed PCI (PCI-express, PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer small interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, Firewire protocol, etc.

[0082] The memory controller 3 and one or more memory devices 2 can be integrated into various types of memory devices, for example, included in the same package (such as a universal Flash storage (UFS) package or an eMMC package). That is, the memory system 1 can be implemented and packaged into different types of final electronic devices.

[0083] In some embodiments, Figure 1B As shown, the memory controller 3 and the single memory device 2 may be integrated into the memory card 11. The memory card 11 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 11 may further include a processor that connects the memory card 11 to a host (e.g., Figure 1A A memory card connector 5 coupled to a host 4).

[0084] In some embodiments, Figure 1C As shown, the memory controller 3 and the plurality of memory devices 2 may be integrated into the SSD 12. The SSD 12 may further include a method for connecting the SSD 12 to a host (eg, Figure 1A In some embodiments, the storage capacity and / or operating speed of the SSD 12 is higher than the storage capacity and / or operating speed of the memory card 11.

[0085] As an example, a memory device 2 is also shown. Figure 2A and Figure 2B As shown, taking three-dimensional memory as an example, Figure 2A A schematic diagram of the three-dimensional structure of a three-dimensional memory provided in an embodiment of the present application, Figure 2B A partial cross-sectional view of a three-dimensional memory.

[0086] It should be noted that in Figure 2A and Figure 2B In the embodiment, the three-dimensional memory extends in the XY plane, and the first direction X and the second direction Y are, for example, two orthogonal directions in the plane where the source layer SL is located: the first direction X is, for example, the extension direction of the word line WL, and the second direction Y is, for example, the extension direction of the bit line BL. The third direction Z is perpendicular to the plane where the source layer SL is located, that is, perpendicular to the XY plane.

[0087] As used in the present disclosure, whether a component (e.g., layer, structure, or device) is "on," "over," or "under" another component (e.g., layer, structure, or device) of a semiconductor device (e.g., a three-dimensional memory) is determined relative to a substrate or source layer of the semiconductor device in a third direction Z when the substrate or source layer is located in the lowest plane of the semiconductor device in the third direction Z. The same concept is applied throughout the present disclosure to describe spatial relationships.

[0088] In order to more clearly illustrate the structure of the device, Figure 2B , a view of the array area CA is shown, that is, the view of the array area CA shows the cross-sectional structure along the Y direction.

[0089] See also Figure 2A and Figure 2B Some embodiments of the present disclosure provide a memory device 2. The memory device 2 may include an array device 30. The memory device 2 may also include a source layer SL coupled to the array device 30, and a peripheral device 20 coupled to the array device 30. The peripheral device 20 may be disposed on a side of the array device 30 away from the source layer SL.

[0090] The source layer SL may include a semiconductor material, such as single crystal silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials. The source layer SL may be partially or fully doped. Exemplarily, the source layer SL may include a doped region, and the doped region is doped with a p-type dopant. The source layer SL may also include a non-doped region.

[0091] The array device 30 may include array-arranged memory cell transistor strings (referred to herein as “memory cell strings”, such as NAND memory cell strings) 31. The source layer SL may be coupled to source terminals of the plurality of memory cell strings 31.

[0092] Continue to see Figure 2A and Figure 2B In some embodiments, the array device 30 may further include an array interconnect layer 40. The array interconnect layer 40 may be coupled to the memory cell string 31. The array interconnect layer 40 may include a drain terminal (i.e., a bit line BL) of the memory cell string 31, and the drain terminal may be coupled to a semiconductor channel of each transistor T in at least one memory cell string 31.

[0093] The array interconnect layer 40 may include one or more first interlayer insulating layers 42, and may also include a plurality of contacts insulated from each other by these first interlayer insulating layers 42, the contacts may include, for example, a bit line contact BL-CNT coupled to the bit line BL, and a drain select gate contact SGD-CNT coupled to the drain select gate SGD (also referred to as a top select gate). The array interconnect layer 40 may also include one or more first interconnect conductor layers 41. The first interconnect conductor layer 41 may include a plurality of connection lines, for example, a bit line BL, and a word line connection line WL-CL coupled to the word line WL. The material of the first interconnect conductor layer 41 and the contacts may be a conductive material, such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, or other suitable materials. The material of the first interlayer insulating layer 42 is an insulating material, such as a combination of one or more of silicon oxide, silicon nitride, and a high dielectric constant insulating material, or other suitable materials.

[0094] The peripheral device 20 may include peripheral circuits. The peripheral circuits are configured to control and sense the array device. The peripheral circuits may be any suitable digital, analog, and / or mixed signal control and sensing circuits for supporting the operation (or work) of the array device, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuits may also include any other circuits compatible with advanced logic processes, including logic circuits (e.g., processors and programmable logic devices (PLDs) or storage circuits (e.g., static random access memories (SRAMs)).

[0095] Specifically, in some embodiments, the peripheral device 20 may include a substrate 21, a transistor 22 disposed on the substrate 21, and a peripheral interconnect layer 23 disposed on the substrate 21. The peripheral circuit may include the transistor 22.

[0096] The material of the substrate 21 may be single crystal silicon, or other suitable materials, such as silicon germanium, germanium, or silicon-on-insulator thin film.

[0097] The peripheral interconnection layer 23 is coupled to the transistor 22 to transmit electrical signals between the transistor 22 and the peripheral interconnection layer 23. The peripheral interconnection layer 23 may include one or more second interlayer insulating layers 231, and may also include one or more second interconnect conductor layers 232. Different second interconnect conductor layers 232 may be coupled through contacts. The material of the second interconnect conductor layer 232 and the contact may be a conductive material, such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, or other suitable materials. The material of the second interlayer insulating layer 231 is an insulating material, such as a combination of one or more of silicon oxide, silicon nitride, and high dielectric constant insulating materials, or other suitable materials.

[0098] The peripheral interconnect layer 23 can be coupled to the array interconnect layer 40, so that the array device 30 and the peripheral device 20 can be coupled. Specifically, since the peripheral interconnect layer 23 is coupled to the array interconnect layer 40, the peripheral circuit in the peripheral device 20 can be coupled to the storage cell string in the array device 30 to achieve the transmission of electrical signals between the peripheral circuit and the storage cell string. In some possible implementations, a bonding interface 500 can be provided between the peripheral interconnect layer 23 and the array interconnect layer 40, and the peripheral interconnect layer 23 and the array interconnect layer 40 can be bonded and coupled to each other through the bonding interface 500.

[0099] The present application also provides a semiconductor structure. It is explained here that the semiconductor structure can be the above-mentioned three-dimensional memory. Alternatively, the semiconductor structure can also be a part of the above-mentioned three-dimensional memory, for example, it can include the array device 30 in the above-mentioned embodiment. The present application does not limit this, and it can be reasonably set according to actual conditions.

[0100] like Figure 3 As shown, the semiconductor structure 10 includes a device structure 100 and a pad 200 disposed on the device structure 100. The device structure 100 includes a semiconductor layer 110 and a metal interconnection layer 120 disposed on the semiconductor layer 110. Exemplarily, the pad (PAD) 200 is connected to the metal interconnection layer 120.

[0101] In some embodiments, the semiconductor structure 10 is integrated on a chip and packaged to form a chip packaging structure. When the chip packaging structure is packaged and tested, it is found that the chip packaging structure fails. After slicing and analyzing the chip packaging structure and conducting electrical tests, it is found that the chip packaging structure fails due to the burning of the metal interconnect layer 120 in the chip packaging structure and the leakage of some pads 200. The burning of the metal interconnect layer 120 is due to the lack of an electrostatic protection circuit in the metal interconnect layer 120 connected to some pads 200, and the small spacing between the metal wirings in the metal interconnect layer 120, which causes the charge generated during the packaging process to accumulate on the pads 200, causing the voltage of the metal interconnect layer 120 connected to the pads 200 to overload and burn the metal interconnect layer 120.

[0102] Based on this, in order to solve the problem of burning of the metal interconnect layer 120, the embodiment of the present application also provides a semiconductor structure. Figure 4 As shown, the semiconductor structure 10 includes a device structure 100, a pad 200 and a first contact structure 310 disposed on the device structure 100, a first conductive structure 410, and a first connecting portion 510 connecting the pad 200 and the first contact structure 310. The device structure 100 includes a semiconductor layer 110 and a metal interconnect layer 120 disposed on the semiconductor layer 110. The pad 200 is connected to the metal interconnect layer 120. The first conductive structure 410 is disposed on the semiconductor layer 110. The pad 200 is disposed on a side of the metal interconnect layer 120 away from the semiconductor layer 110, and the first contact structure 310 is disposed on a side of the metal interconnect layer 120 away from the semiconductor layer 110. The first contact structure 310 is connected to the semiconductor layer 110 through the metal interconnect layer 120 and the first conductive structure 410. Figure 5 As shown, the embodiment of the present application also provides a method for preparing a semiconductor structure, comprising:

[0103] S1, such as Fig. 6A As shown, a device structure 100 is provided.

[0104] In some embodiments, Fig. 6A As shown, the device structure 100 includes a semiconductor layer 110 and a metal interconnection layer 120 disposed on the semiconductor layer 110 .

[0105] The material of the semiconductor layer 110 may include, for example, silicon (single crystal silicon, polycrystalline silicon or amorphous silicon), germanium (single crystal germanium), silicon germanium, silicon carbide, glass, gallium nitride, gallium arsenide, glass, SOI (silicon on insulator), GOI (germanium on insulator) or other suitable III-V compound substrates, and the semiconductor layer 110 may also be P-type doped or N-type doped.

[0106] like Fig. 6AAs shown, the device structure 100 further includes a first conductive structure 410 . The first conductive structure 410 is disposed on the semiconductor layer 110 . The first conductive structure 410 is also connected to the metal interconnection layer 120 .

[0107] In some embodiments, Fig. 6A As shown, a first conductive structure 410 is disposed on the semiconductor layer 110 .

[0108] Exemplarily, the first conductive structure 410 includes an electrostatic protection circuit.

[0109] Or, for example, Figure 6B As shown, the metal interconnect layer 120 includes a metal contact structure 121 .

[0110] like Figure 6B As shown, the metal contact structure 121 is connected to the first conductive structure 410 .

[0111] At this time, if Figure 6B As shown, the first conductive structure 410 is connected to the metal contact structure 121 to form a first sealing ring 610. The first sealing ring 610 is disposed at the periphery of the chip to prevent moisture, ions, etc. from entering the chip and prevent cracks from propagating into the chip.

[0112] It is explained here that the device structure 100 in the embodiment of the present application can be the above Figure 2B The peripheral device 20 structure in the embodiment. Alternatively, it can also be the above Figure 2B The array device 30 structure in the present application embodiment is not limited to this, and it can be reasonably set according to actual conditions.

[0113] Exemplarily, the device structure 100 may be Figure 2B In the peripheral device 20 , the metal interconnection layer 120 may be a peripheral interconnection layer 23 .

[0114] Alternatively, the device structure 100 may be, for example, Figure 2B In the array device 30 , the metal interconnection layer 120 may be the array interconnection layer 40 .

[0115] Alternatively, the device structure 100 may be, for example, Figure 2B In the peripheral device 20 and the array device 30 , the metal interconnection layer 120 may be a peripheral interconnection layer 23 and an array interconnection layer 40 .

[0116] In other embodiments, Figure 6C As shown, a plurality of conductive structures (a first conductive structure 410 and a second conductive structure 420 ) are disposed on the semiconductor layer 110 .

[0117] The semiconductor layer 110 is provided with two conductive structures for illustration. For the convenience of illustration, the two conductive structures are referred to as the first conductive structure 410 and the second conductive structure 420 . That is, the first conductive structure 410 and the second conductive structure 420 are both provided on the semiconductor layer 110 .

[0118] For example, the first conductive structure 410 and the second conductive structure may be Figure 2B Alternatively, the first conductive structure 410 and the second conductive structure may be disposed at the same layer as the interconnect conductor layer 232 of the peripheral interconnect layer 23. Figure 2B The memory cell string 31 is arranged in the same layer close to the source layer SL.

[0119] The first conductive structure 410 and the second conductive structure 420 may be the same or different.

[0120] Exemplarily, the first conductive structure 410 includes an electrostatic protection circuit. The second conductive structure 420 includes an electrostatic protection circuit.

[0121] Or, for example, Figure 6C As shown, the first conductive structure 410 is connected to the metal contact structure 121 to form a second sealing ring 620. The second conductive structure 420 includes an electrostatic protection circuit.

[0122] Or, for example, Fig.6D As shown, the first conductive structure 410 is connected to the metal contact structure 121 to form a first sealing ring 610 . The second conductive structure 420 is also connected to the metal contact structure on the metal interconnect layer 120 to form a second sealing ring 620 .

[0123] The embodiments of the present application do not limit this, and can be reasonably set according to actual conditions.

[0124] For example, the device structure 100 may also be a structure where the metal interconnect layer 120 and the first conductive structure 410 and other conductive structures are first formed on the substrate. During the preparation process, the substrate may be removed according to actual conditions to re-form the semiconductor layer.

[0125] Alternatively, illustratively, the substrate may not be removed and in this case, the substrate serves as the semiconductor layer 110 .

[0126] In other embodiments, Fig. 6E As shown, the device structure 100 includes a first sub-device structure 130 and a second sub-device structure 140 .

[0127] The first sub-device structure 130 and the second sub-device structure 140 are coupled via the metal interconnection layer 120 .

[0128] For example, Fig. 6EAs shown, the metal interconnection layer 120 includes a first metal interconnection layer 122 and a second metal interconnection layer 123 .

[0129] At this time, the first sub-device structure 130 and the second sub-device structure 140 may be coupled via the first metal interconnection layer 122 and the second metal interconnection layer 123 .

[0130] For example, the first metal interconnection layer 122 may include a metal wiring layer formed by a front-end process, and the second metal interconnection layer 123 may include a metal wiring layer formed by a back-end process.

[0131] It is understood that the first sub-device structure 130 may include a first metal interconnection layer 122 , and the second sub-device structure 140 may include a second metal interconnection layer 123 .

[0132] Or, for example, Fig. 6E As shown, a bonding interface 500 may be provided between the first metal interconnection layer 122 and the second metal interconnection layer 123 , and the first metal interconnection layer 122 and the second metal interconnection layer 123 may be bonded and coupled to each other through the bonding interface 500 .

[0133] The embodiment of the present application does not limit the specific device structures of the first sub-device structure 130 and the second sub-device structure 140 , and they can be reasonably configured according to actual conditions.

[0134] In some embodiments, one of the first sub-device structure 130 and the second sub-device structure 140 is an array device structure, and the other is a peripheral device structure.

[0135] Exemplarily, the first sub-device structure 130 includes Figure 2B The array device 30 structure in the second sub-device structure 140 includes Figure 2B Correspondingly, the first metal interconnection layer 122 includes Figure 2B The array interconnection layer 40 in the second metal interconnection layer 123 includes Figure 2B The peripheral interconnect layer 23 in.

[0136] Alternatively, illustratively, the first sub-device structure 130 includes Figure 2B The peripheral device 20 structure in the second sub-device structure 140 includes Figure 2B Correspondingly, the first metal interconnection layer 122 includes Figure 2B The peripheral interconnection layer 23 in the second metal interconnection layer 123 includes Figure 2B The array interconnect layer 40 in.

[0137] The present application embodiment does not limit this, and can be reasonably set according to actual conditions. For the sake of convenience, the following takes the device structure 100 as an example, which includes two sub-device structures (a first sub-device structure 130 and a second sub-device structure 140), and the first sub-device structure 130 includes a peripheral device structure (for example, see Figure 2B The peripheral device 20 in the second sub-device structure 140 includes an array device structure (for example, see Figure 2B Array device 30).

[0138] Continue to refer Fig. 6E The semiconductor layer 110 is located on a side of the second sub-device structure 140 away from the first sub-device structure 130 .

[0139] For example, the semiconductor layer 110 may be Figure 2B The substrate 21 in the embodiment of the present invention.

[0140] It is understandable that the second sub-device structure 140 may include the semiconductor layer 110. Alternatively, the second sub-device structure 140 may also not include the semiconductor layer 110. This application does not limit this.

[0141] At this time, the first conductive structure 410 is disposed on the semiconductor layer 110. The second sub-device structure 140 may include the first conductive structure 410. Alternatively, the second sub-device structure 140 may not include the first conductive structure 410. This application does not limit this.

[0142] like Fig. 6E As shown, the first sub-device structure 130 further includes a substrate 131 and a first dielectric layer 132. The substrate 131 and the first dielectric layer 132 are stacked.

[0143] That is, the semiconductor layer 110 , the second metal interconnection layer 123 , the bonding interface 500 , the first metal interconnection layer 122 , the first dielectric layer 132 and the substrate 131 are stacked in sequence.

[0144] The material of the substrate 131 may include, for example, a semiconductor material, such as silicon (single crystal silicon, polycrystalline silicon or amorphous silicon), germanium (single crystal germanium), silicon germanium, silicon carbide, glass, gallium nitride, gallium arsenide, glass, SOI (silicon on insulator), GOI (germanium on insulator) or other suitable III-V compound substrates, etc. The substrate 131 may also be P-type doped or N-type doped.

[0145] The materials of the substrate 131 and the semiconductor layer 110 may be the same or different, which is not limited in the present embodiment.

[0146] Exemplarily, the material of the first dielectric layer 132 may include, for example, silicon oxide carbon (SiOCH), silicon oxynitride (SiON), silicon carbide (SiC), or silicon nitride (SiN).

[0147] like Fig. 6E As shown, the first sub-device structure 130 further includes a third conductive structure 430 and a fourth conductive structure 440 .

[0148] The third conductive structure 430 penetrates the first sub-device structure 130 , and the fourth conductive structure 440 penetrates the first sub-device structure 130 .

[0149] That is, the third conductive structure 430 penetrates the substrate 131 and the first dielectric layer 132 , and the fourth conductive structure 440 penetrates the substrate 131 and the first dielectric layer 132 .

[0150] Exemplarily, the third conductive structure 430 is connected to the metal interconnect layer 120 . The fourth conductive structure 440 is connected to the semiconductor layer 110 through the metal interconnect layer 120 and the first conductive structure 410 .

[0151] For example, the third conductive structure 430 and the fourth conductive structure 440 may be Figure 2B The storage unit strings 31 in the same layer are arranged.

[0152] like Fig. 6E As shown, the third conductive structure 430 may include a first through-contact 431 and a first interconnection contact 432. The fourth conductive structure 440 may include a second through-contact 441 and a second interconnection contact 442.

[0153] The first through contact 431 penetrates the substrate 131 , and the first interconnection contact 432 penetrates the first dielectric layer 132 . The second through contact 441 penetrates the substrate 131 , and the second interconnection contact 442 penetrates the first dielectric layer 132 .

[0154] That is to say, Fig. 6E As shown, the first through-contact 431 and the first interconnection contact 432 are connected to the metal interconnection layer 120 , and the second through-contact 441 and the second interconnection contact 442 are connected to the semiconductor layer 110 through the metal interconnection layer 120 and the first conductive structure 410 .

[0155] Exemplarily, the first through-contact 431 and the second through-contact 441 are disposed on the same layer, and the first interconnection contact 432 and the second interconnection contact 442 are disposed on the same layer.

[0156] In some embodiments, Fig. 6EAs shown, a first interlayer dielectric layer 433 is further disposed between the first through-contact 431 and the substrate 131 . A second interlayer dielectric layer 443 is further disposed between the second through-contact 441 and the substrate 131 .

[0157] In some embodiments, Fig. 6F As shown, the metal interconnection layer 120 includes a metal contact structure 121 connected to the first conductive structure 410 .

[0158] At this time, if Fig. 6F As shown, the first conductive structure 410 is connected to the metal contact structure 121 to form a first sealing ring 610. The second through contact 441 is connected to the second interconnection contact 442 to form a third sealing ring 630. The first sealing ring 610 and the third sealing ring 630 are connected.

[0159] That is, the first sealing ring 610 and the third sealing ring 630 are connected to the semiconductor layer 110 .

[0160] In other embodiments, Figure 6G As shown, a second conductive structure 420 may also be disposed on the semiconductor layer 110. That is, a first conductive structure 410 and a second conductive structure 420 are disposed on the semiconductor layer 110.

[0161] For example, Figure 6G As shown, the fifth conductive structure 450 is connected to the semiconductor layer 110 through the metal interconnect layer 120 and the second conductive structure 420. The fifth conductive structure 450 is disposed in the first sub-device structure 130 and penetrates the first sub-device structure 130.

[0162] The fifth conductive structure 450 may have the same structure as the third conductive structure 430 and the fourth conductive structure 440 . For details, reference may be made to the above description of the third conductive structure 430 and the fourth conductive structure 440 , which will not be repeated here.

[0163] The description about the first conductive structure 410 and the second conductive structure 420 is the same as above, and the details can be referred to the above introduction.

[0164] It is explained here that any one of the first sub-device structure 130 or the second sub-device structure 140 can be used alone as the device structure 100 .

[0165] That is, the device structure 100 may include a third conductive structure 430 and a fourth conductive structure 440 .

[0166] In the embodiment of the present application, the number of conductive structures (eg, the third conductive structure 430 and the fourth conductive structure 440 ) penetrating the device structure 100 (eg, the first sub-device structure 130 ) is not limited and can be reasonably set according to actual conditions.

[0167] S2, such as Fig. 7A As shown, a pad 200 is formed.

[0168] In some embodiments, the pad 200 is formed on a side of the metal interconnection layer 120 away from the semiconductor layer 110 , wherein the pad 200 is connected to the metal interconnection layer 120 .

[0169] Exemplarily, the device structure 100 may be Figure 2B The peripheral device 20 in the embodiment of the present invention, the metal interconnection layer 120 may be a peripheral interconnection layer 23, and the pad 200 is formed on Figure 2B The middle substrate 21 is on a surface away from the peripheral interconnection layer 23 .

[0170] Alternatively, the device structure 100 may be, for example, Figure 2B The array device 30 in the embodiment of the present invention, the metal interconnection layer 120 may be the array interconnection layer 40, and the pad 200 is formed on Figure 2B The source layer SL is located away from the surface of the array interconnection layer 40 .

[0171] Alternatively, the device structure 100 may be, for example, Figure 2B The peripheral device 20 and the array device 30, the metal interconnection layer 120 can be the peripheral interconnection layer 23 and the array interconnection layer 40, and the pad 200 can be formed on Figure 2B On the surface of the middle substrate 21 away from the peripheral interconnection layer 23, or on Figure 2B The source layer SL is located away from the surface of the array interconnection layer 40 .

[0172] In some other embodiments, the pad 200 is formed on a side of the first sub-device structure 130 away from the second sub-device structure 140 .

[0173] Exemplarily, the first sub-device structure 130 may be Figure 2B The array device 30 structure in the embodiment of the present invention, the second sub-device structure 140 may be Figure 2B The first metal interconnect layer 122 may be Figure 2B The array interconnect layer 40 in the second metal interconnect layer 123 may be Figure 2B The peripheral interconnect layer 23 in the bonding pad 200 can be formed on Figure 2B The source layer SL is located away from the surface of the array interconnection layer 40 .

[0174] Alternatively, the first sub-device structure 130 may be, for example, Figure 2BThe peripheral device 20 structure in the second sub-device structure 140 may be Figure 2B The first metal interconnect layer 122 may be Figure 2B The peripheral interconnection layer 23 in the second metal interconnection layer 123 may be Figure 2B The pad 200 may be formed on the array interconnect layer 40. Figure 2B The middle substrate 21 is on a surface away from the peripheral interconnection layer 23 .

[0175] like Fig. 7A As shown, the pad 200 is connected to the metal interconnect layer 120 through the third conductive structure 430 .

[0176] That is, the pad 200 is connected to the metal interconnection layer 120 through the first through contact 431 and the first interconnection contact 432. The pad 200 is electrically connected to the metal interconnection layer 120.

[0177] It is explained here that if Fig. 7A As shown, the pad 200 is not connected to the semiconductor layer 110 through the metal interconnection layer 120. In other words, there is no connection between the portion of the metal interconnection layer 120 connected to the pad 200 and the semiconductor layer 110. That is, the pad 200 is not grounded or connected to the electrostatic protection circuit.

[0178] In other embodiments, a conductive structure may be formed on the semiconductor layer 110, and the conductive structure is connected to the pad 200 through the metal interconnect layer 120 and the third conductive structure 430. This embodiment of the present application does not limit this, and it can be reasonably set according to actual conditions.

[0179] Regarding the method of forming the pad 200 , for example, it can be prepared by a damascene process, that is, a process of first etching out the area where the pad 200 is to be formed on the dielectric layer, and then filling the area with metal material to form the pad 200 .

[0180] In some embodiments, step S2 includes:

[0181] S21, such as Figure 7B As shown, a second dielectric film 133 ′ is formed on the substrate 131 .

[0182] That is to say, Figure 7C As shown, a second dielectric film 133 ′ is formed on a side of the substrate 131 away from the first dielectric layer 132 .

[0183] In other words, the second dielectric film 133 ′ is formed on a side of the substrate 131 away from the first dielectric layer 132 . For example, the second dielectric film 133 ′ is formed on a surface of the substrate 131 away from the first dielectric layer 132 .

[0184] For example, the material of the second dielectric film 133' may include silicon oxide containing carbon (SiOCH), silicon oxynitride (SiON), silicon carbide (SiC) or silicon nitride (SiN). It is explained here that the material of the second dielectric film 133' may be the same as the material of the first dielectric layer 132, or may be different. This embodiment of the application does not limit this.

[0185] S22, opening a first via hole in the second dielectric film 133'.

[0186] For example, the first via hole may be opened on the second dielectric film 133 ′ by a photoforming process and an etching process.

[0187] like Figure 7C As shown, the first via hole 101 penetrates the second dielectric film 133'. The first via hole 101 is used to fill metal material to form the pad 200. The second dielectric film 133' with the via hole (eg, the first via hole 101) is referred to as the second dielectric layer 133.

[0188] It is explained here that the first via hole 101 exposes the third conductive structure 430 , so that the subsequently formed pad 200 can be electrically connected to the third conductive structure 430 .

[0189] That is, the first via hole 101 exposes the first through-contact 431 of the third conductive structure 430 , so that the subsequently formed pad 200 is electrically connected to the first through-contact 431 .

[0190] Regarding the method of forming the first via hole 101, for example, a mask material and a photoresist may be sequentially formed on the second dielectric film 133', and then the photoresist is patterned to expose the area where the first via hole 101 is to be formed, and the mask material and the second dielectric film 133' are sequentially etched.

[0191] For example, Figure 7C As shown, step S22 includes:

[0192] S221 , forming a mask 134 ′ on the second dielectric film 133 ′.

[0193] That is to say, Figure 7C As shown, a mask layer 134 is formed on a side of the second dielectric film 133 ′ away from the substrate 131 .

[0194] In other words, the mask 134 ′ is formed on the side of the second dielectric film 133 ′ away from the substrate 131 . For example, the mask 134 ′ is formed on the surface of the second dielectric film 133 ′ away from the substrate 131 .

[0195] The mask 134 ′ may be a hard mask. The material of the mask 134 ′ may include silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ) or polysilicon (poly).

[0196] S222, such as Figure 7C As shown, a photoresist is formed on the surface of the mask 134', and the photoresist is patterned to expose the area where the first via hole 101 is to be opened.

[0197] That is, photoresist (PR) is spin-coated on the surface of the mask 134' away from the second dielectric film 133'.

[0198] For example, a light shielding plate (mask) can be used to shield the photoresist, and the light shielding plate can set the area where the first via hole 101 is to be opened as a light-proof area, and the remaining area is set as a light-transmitting area. Then, after the coated photoresist is cured, the light shielding plate is irradiated with light to activate the photoresist in the light-transmitting area, and the photoresist in the light-transmitting area is removed, thereby exposing the area where the first via hole 101 is opened.

[0199] It should be noted that the photoresists mentioned in the specific implementation of the embodiments of the present application are all positive photoresists, that is, the photoresists can be activated after illumination, and then the activated photoresists can be removed. Of course, in actual operation, negative photoresists can also be used. It should be noted that negative photoresists will not be dissolved by developer after illumination, and those without illumination will be dissolved by developer. The choice of developer is related to the developed photoresist. Therefore, when using negative photoresists, the light-transmitting area and the light-impermeable area of ​​the above-mentioned shading plate need to be exchanged, that is, the original light-transmitting area becomes the light-impermeable area, and the original light-impermeable area becomes the light-transmitting area, and other steps are not changed. Whether using positive photoresists or negative photoresists, they all belong to the protection scope of the embodiments of the present application.

[0200] S223, such as Figure 7C As shown, the mask 134 ′ is etched to form a mask layer 134 .

[0201] The mask layer 134 exposes the area where the first via hole 101 is opened.

[0202] Exemplarily, the mask 134' can be etched by inductively coupled plasma (ICP) dry etching to transfer the area of ​​the photoresist exposed by the photoresist where the first via hole 101 is to be opened to the mask layer 134, so that the mask layer 134 exposes the area where the first via hole 101 is to be opened.

[0203] S224, such as Figure 7C As shown, a first via hole 101 is opened.

[0204] Exemplarily, the mask layer 134 is used as a mask to etch the second dielectric film 133 ′, and the area of ​​the mask layer 134 where the first via hole 101 is exposed is transferred to the second dielectric film 133 ′, so that the first via hole 101 is opened in the second dielectric film 133 ′ to form the second dielectric layer 133 .

[0205] S23, such as Fig.7D As shown, a pad 200 is formed in the first via hole 101 .

[0206] That is to say, Fig.7D As shown, a pad 200 is formed in the second dielectric layer 133 , and the pad 200 penetrates the second dielectric layer 133 .

[0207] It is noted here that in some implementations, the photoresist and the mask layer 134 are removed after the pad 200 is formed.

[0208] The pad 200 may be exposed, or may be covered by an insulating layer, which is not limited in the present embodiment.

[0209] S3, such as Fig. 8A As shown, a first contact structure 310 is formed.

[0210] For example, Fig. 8A As shown, the first contact structure 310 is formed on a side of the metal interconnection layer 120 away from the semiconductor layer 110 .

[0211] That is, the first contact structure 310 is formed on a side of the first sub-device structure 130 away from the second sub-device structure 140 .

[0212] It is explained here that the first contact structure 310 and the pad 200 are formed on the same side of the device structure 100 .

[0213] The method for forming the first contact structure 310 is similar to the method for forming the pad 200 . The specific method may refer to the method for forming the pad 200 in step S2 , and will not be repeated here.

[0214] The first contact structure 310 may be exposed, or may be covered by an insulating layer, which is not limited in the present embodiment.

[0215] It is explained here that the process of forming the first contact structure 310 and the process of forming the pad 200 can be implemented in the same process step.

[0216] In this way, the process is simple and no additional process is required. It can be achieved by simply changing a layer of mask.

[0217] For example, Figure 8BAs shown, in the same process step, a first via hole 101 and a second via hole 102 are opened on the second dielectric film 133 ′. Then, a pad 200 is formed in the first via hole 101 , and a first contact structure 310 is formed in the second via hole 102 .

[0218] like Figure 8B As shown, the first contact structure 310 is connected to the semiconductor layer 110 through the metal interconnection layer 120 and the first conductive structure 410 .

[0219] That is, the first contact structure 310 is connected to the semiconductor layer 110 through the fourth conductive structure 440 , the metal interconnection layer 120 , and the first conductive structure 410 .

[0220] In other words, the first contact structure 310 is connected to the semiconductor layer 110 through the second through-contact 441 , the second interconnection contact 442 , the metal interconnection layer 120 , and the first conductive structure 410 .

[0221] Exemplarily, the first conductive structure 410 includes an electrostatic protection circuit. In this case, the first contact structure 310 can be used as another pad of the semiconductor structure 10 .

[0222] In this way, the first contact structure 310 is a pad with an electrostatic protection circuit, which can prevent the charges generated during the packaging process from accumulating on the first contact structure 310, thereby preventing the metal interconnection layer 120 connected to the first contact structure 310 from voltage overload and preventing the metal interconnection layer 120 from burning.

[0223] Or, for example, Figure 8C As shown, the metal interconnection layer 120 includes a metal contact structure 121 connected to the first conductive structure 410 .

[0224] At this time, if Figure 8C As shown, the first conductive structure 410 is connected to the metal contact structure 121 to form a first sealing ring 610. The second through contact 441 is connected to the second interconnection contact 442 to form a third sealing ring 630. The first sealing ring 610 and the third sealing ring 630 are connected.

[0225] That is, the first contact structure 310 is connected to the semiconductor layer 110 through the first sealing ring 610 and the third sealing ring 630 .

[0226] In this way, the first contact structure 310 is connected to the semiconductor layer 110 for grounding, so that the first contact structure 310 can prevent the charges generated during the packaging process from accumulating on the first contact structure 310, thereby preventing the metal interconnection layer 120 connected to the first contact structure 310 from voltage overload and preventing the metal interconnection layer 120 from burning.

[0227] S4, such as Fig. 9A As shown, a first connecting portion 510 is formed.

[0228] The first connection portion 510 connects the pad 200 and the first contact structure 310 .

[0229] For example, Fig. 9A As shown, the first connection portion 510 is formed on a side of the metal interconnection layer 120 away from the semiconductor layer 110 .

[0230] That is, the first connection portion 510 is formed on a side of the first sub-device structure 130 away from the second sub-device structure 140 .

[0231] It is explained here that the first connection portion 510 , the pad 200 and the first contact structure 310 are formed on the same side of the device structure 100 .

[0232] The method of forming the first connection portion 510 is similar to the method of forming the pad 200 . The specific method may refer to the method of forming the pad 200 in step S2 , and will not be repeated here.

[0233] The first connection portion 510 may be exposed, or may be covered by an insulating layer, which is not limited in the present embodiment.

[0234] It is explained here that the process of forming the first connection portion 510 , the process of forming the first contact structure 310 , and the process of forming the pad 200 may be implemented in the same process step.

[0235] In this way, the process is simple and no additional process is required. It can be achieved by simply changing a layer of mask.

[0236] That is to say, illustratively, the pad 200 , the first contact structure 310 , and the first connection portion 510 are disposed in the same layer.

[0237] For example, Fig. 9B As shown, in the same process step, the first via hole 101, the second via hole 102 and the third via hole 103 are opened on the second dielectric film 133 ′. Then, the pad 200 is formed in the first via hole 101, the first contact structure 310 is formed in the second via hole 102, and the first connecting portion 510 is formed in the third via hole 103.

[0238] In this way, the pad 200 is connected to the first contact structure 310 through the first connection portion 510, thereby grounding the pad 200 to provide electrostatic protection for the pad 200. Therefore, it is possible to prevent the charges generated during the packaging process from accumulating on the pad 200, thereby preventing the metal interconnect layer 120 connected to the pad 200 from overloading and burning.

[0239] It is explained here that if Fig. 9B As shown, a portion of the material of the second dielectric layer 133 may be retained between the first connecting portion 510 and the substrate 131. Fig. 9A As shown, the first connection portion 510 may also be formed on a surface of the substrate 131 away from the semiconductor layer 110. This embodiment of the present application does not limit this.

[0240] After forming the first connection portion 510 , a layer of insulating material may be formed to cover the surface of the first connection portion 510 away from the substrate 131 , so that the surface of the first connection portion 510 away from the substrate 131 is flush with the surface of the pad 200 or the surface of the first contact structure 310 away from the substrate 131 .

[0241] In some embodiments, the device structure 100 provided in step S1 is as follows: Figure 6G As shown, a first conductive structure 410 and a second conductive structure are formed on the semiconductor layer 110 of the device structure 100, and the method for preparing the semiconductor structure further includes:

[0242] S5, such as Fig.10 As shown, a second contact structure 320 is formed.

[0243] For example, Fig.10 As shown, the second contact structure 320 is formed on a side of the metal interconnection layer 120 away from the semiconductor layer 110 .

[0244] That is, the second contact structure 320 is formed on a side of the first sub-device structure 130 away from the second sub-device structure 140 .

[0245] It is explained here that the second contact structure 320 , the pad 200 and the first contact structure 310 are formed on the same side of the device structure 100 .

[0246] The method for forming the second contact structure 320 is similar to the method for forming the pad 200 . The specific method may refer to the method for forming the pad 200 in step S2 , and will not be repeated here.

[0247] The second contact structure 320 may be exposed, or may be covered by an insulating layer, which is not limited in the present embodiment.

[0248] It is explained here that the pad 200 , the first contact structure 310 , the first connection portion 510 and the second contact structure 320 may be formed in the same process step.

[0249] In this way, the process is simple and no additional process is required. It can be achieved by simply changing a layer of mask.

[0250] like Fig.10As shown, the second contact structure 320 is connected to the semiconductor layer 110 through the metal interconnect layer 120 and the second conductive structure 420 .

[0251] That is, the second contact structure 320 is connected to the semiconductor layer 110 through the fifth conductive structure 450 , the metal interconnection layer 120 , and the second conductive structure 420 .

[0252] The fifth conductive structure 450 may be the same as or different from the third conductive structure 430 and the fourth conductive structure 440 .

[0253] S6, such as Fig.11A As shown, a second connection portion 520 is formed.

[0254] The second connection portion 520 connects the pad 200 and the second contact structure 320 .

[0255] For example, Fig. 11B As shown, Fig. 11B for Fig.11A A cross-sectional view along the A1A2 direction. The second connection portion 520 is formed on a side of the metal interconnection layer 120 away from the semiconductor layer 110 .

[0256] That is, the second connection portion 520 is formed on a side of the first sub-device structure 130 away from the second sub-device structure 140 .

[0257] It is explained here that the second connection portion 520 , the pad 200 and the first contact structure 310 are formed on the same side of the device structure 100 .

[0258] like Fig.11A and 11B As shown, a first connection portion 510 and a second connection portion 520 are formed so that the pad 200 is connected to the first contact structure 310 through the first connection portion 510 , and the pad 200 is connected to the second contact structure 320 through the second connection portion 520 .

[0259] The second connection portion 520 may be exposed, or may be covered by an insulating layer, which is not limited in the present embodiment.

[0260] The method for forming the second connection portion 520 is similar to the method for forming the first connection portion 510 . The specific method may refer to the method for forming the first connection portion 510 in step S4 , and will not be repeated here.

[0261] It is explained here that the pad 200 , the first contact structure 310 , the first connection portion 510 , the second contact structure 320 , and the second connection portion 520 may be formed in the same process step.

[0262] In this way, the process is simple and no additional process is required. It can be achieved by simply changing a layer of mask.

[0263] S7, such as Fig. 12A As shown, a third connection portion 530 is formed.

[0264] The third connection portion 530 connects the first contact structure 310 and the second contact structure 320 .

[0265] For example, Fig. 12B As shown, Fig. 12B for Fig. 12A A cross-sectional view along the B1B2 direction. The third connection portion 530 is formed on a side of the metal interconnection layer 120 away from the semiconductor layer 110 .

[0266] That is, the third connection portion 530 is formed on a side of the first sub-device structure 130 away from the second sub-device structure 140 .

[0267] It is explained here that the third connection portion 530 , the pad 200 and the first contact structure 310 are formed on the same side of the device structure 100 .

[0268] like Fig. 12A and Fig. 12B As shown, a third connection portion 530 is further formed, so that the first contact structure 310 is connected to the second contact structure 320 through the third connection portion 530 .

[0269] The method for forming the third connection portion 530 is similar to the method for forming the first connection portion 510 . The specific method may refer to the method for forming the first connection portion 510 in step S4 , and will not be repeated here.

[0270] The third connection portion 530 may be exposed, or may be covered by an insulating layer, which is not limited in the present embodiment.

[0271] It is explained here that the pad 200 , the first contact structure 310 , the first connection portion 510 , the second contact structure 320 , the second connection portion 520 , and the third connection portion 530 may be formed in the same process step.

[0272] In this way, the process is simple and no additional process is required. It can be achieved by simply changing a layer of mask.

[0273] The above preparation method provided in the embodiments of the present application is not limited to any step sequence and can be reasonably adjusted as needed.

[0274] In addition, the above steps S1-S7 may remove some of the steps as needed, and are not limited to including every step. Some steps may also be added as needed, and are not limited to only including the above steps.

[0275] In the method for preparing the semiconductor structure 10 provided by the present application, the first contact structure 310 is connected to the semiconductor layer 110 through the metal interconnection layer 120 and the first conductive structure 410 to achieve electrostatic protection, and the first connecting portion 510 is formed. The pad 200 is connected to the first contact structure 310 through the first connecting portion 510, so that the charge generated on the pad 200 is connected to the semiconductor layer 110 through the first connecting portion 510, the first contact structure 310 and the first conductive structure 410, so as to play an electrostatic protection role for the pad 200. Therefore, it is possible to prevent the charge generated during the packaging process from accumulating on the pad 200, thereby preventing the metal interconnection layer 120 connected to the pad 200 from voltage overload, and preventing the metal interconnection layer 120 from burning.

[0276] In addition, in the solution provided in the embodiment of the present application, during the preparation process, only a slight change is required to be made to the mask layer 134 for forming the pad 200 and the first contact structure 310, so that the pad 200, the first contact structure 310 and the first connecting portion 510 can be formed in the same process step. Therefore, the solution provided in the embodiment of the present application has a simple process, does not require additional processes, and is easy to operate.

[0277] The semiconductor structure provided in the embodiment of the present application is described below. The semiconductor structure can be obtained by using the above-mentioned method for preparing the semiconductor structure.

[0278] Based on this, Fig.13 As shown, the semiconductor structure 10 includes a device structure 100 , a pad 200 and a first contact structure 310 disposed on the device structure 100 , a first conductive structure 410 , and a first connection portion 510 connecting the pad 200 and the first contact structure 310 .

[0279] The device structure 100 includes a semiconductor layer 110 and a metal interconnection layer 120 disposed on the semiconductor layer 110 .

[0280] In some embodiments, the device structure 100 may include at least one of a peripheral device or an array device. This embodiment of the present application does not limit this, and it can be reasonably configured according to actual conditions.

[0281] Exemplarily, the device structure 100 may be Figure 2B Alternatively, the device structure 100 may also be Figure 2B Alternatively, the device structure 100 may also be Figure 2B The peripheral device 20 and the array device 30 are included.

[0282] Exemplarily, the semiconductor layer 110 may be a substrate. The material of the substrate may include, for example, silicon (single crystal silicon, polycrystalline silicon or amorphous silicon), germanium (single crystal germanium), silicon germanium, silicon carbide, glass, gallium nitride, gallium arsenide, glass, SOI (silicon on insulator), GOI (germanium on insulator) or other suitable III-V compound substrates, and the semiconductor layer 110 may also be P-type doped or N-type doped. For example, the semiconductor layer 110 may be the above Figure 2B The substrate 21 in the embodiment of the present invention.

[0283] like Fig.13 As shown, the pad 200 is disposed on a side of the metal interconnect layer 120 away from the semiconductor layer 110. In other words, the pad 200 is disposed opposite to the semiconductor layer 110.

[0284] Exemplarily, the device structure 100 may be Figure 2B The peripheral device 20 in the embodiment of the present invention, the metal interconnection layer 120 may be a peripheral interconnection layer 23, and the pad 200 is formed on Figure 2B The middle substrate 21 is on a surface away from the peripheral interconnection layer 23 .

[0285] Alternatively, the device structure 100 may be, for example, Figure 2B The array device 30 in the embodiment of the present invention, the metal interconnection layer 120 may be the array interconnection layer 40, and the pad 200 is formed on Figure 2B The source layer SL is located away from the surface of the array interconnection layer 40 .

[0286] Alternatively, the device structure 100 may be, for example, Figure 2B The peripheral device 20 and the array device 30, the metal interconnection layer 120 can be the peripheral interconnection layer 23 and the array interconnection layer 40, and the pad 200 can be formed on Figure 2B On the surface of the middle substrate 21 away from the peripheral interconnection layer 23, or on Figure 2B The source layer SL is located away from the surface of the array interconnection layer 40 .

[0287] The pad 200 is connected to the metal interconnection layer 120 .

[0288] For example, Fig.13 As shown, the pad 200 is not connected to the semiconductor layer 110 through the metal interconnection layer 120. In other words, there is no connection relationship between the portion of the metal interconnection layer 120 connected to the pad 200 and the semiconductor layer 110.

[0289] At this time, the pad 200 can be used as a dummy pad and subsequently used to connect chips to chips.

[0290] For example, the pad 200 may be exposed, or may be covered by an insulating layer, which is not limited in the present embodiment.

[0291] Alternatively, for example, a conductive structure may be provided on the semiconductor layer 110, and the conductive structure is connected to the pad 200 via the metal interconnect layer 120. This embodiment of the present application does not limit this, and it can be reasonably set according to actual conditions.

[0292] like Fig.13 As shown, the first conductive structure 410 is disposed on the semiconductor layer 110 .

[0293] For example, the first conductive structure 410 may be Figure 2B Alternatively, the first conductive structure 410 may be disposed at the same layer as the interconnect conductor layer 232 of the peripheral interconnect layer 23. Figure 2B The memory cell string 31 is arranged in the same layer close to the source layer SL.

[0294] For example, Fig.14A As shown, the metal interconnection layer 120 includes a metal contact structure 121 . The metal contact structure 121 is connected to the first conductive structure 410 .

[0295] At this time, the first conductive structure 410 is connected to the metal contact structure 121 to form a first sealing ring 610 .

[0296] Alternatively, illustratively, the first conductive structure 410 includes an electrostatic protection circuit.

[0297] At this time, the first contact structure 310 is connected to the semiconductor layer 110 through the metal interconnection layer 120 and the electrostatic protection circuit.

[0298] In this way, the first contact structure 310 may be a pad having an electrostatic protection circuit.

[0299] like Fig.14A As shown, the first contact structure 310 is disposed on a side of the metal interconnection layer 120 away from the semiconductor layer 110 .

[0300] That is, the first contact structure 310 is disposed opposite to the semiconductor layer 110 , and the first contact structure 310 and the pad 200 are disposed on the same side.

[0301] The first contact structure 310 is connected to the semiconductor layer 110 through the metal interconnection layer 120 and the first conductive structure 410 .

[0302] The first contact structure 310 may be exposed, or may be covered by an insulating layer, which is not limited in the present embodiment.

[0303] Continue to refer Fig.14A , the first connection portion 510 is disposed on a side of the metal interconnection layer 120 away from the semiconductor layer 110 .

[0304] That is, the pad 200 , the first contact structure 310 and the first connection portion 510 are disposed on the same side. That is, the first connection portion 510 , the pad 200 and the first contact structure 310 are formed on the same side of the device structure 100 .

[0305] Exemplarily, the pad 200 , the first contact structure 310 , and the first connection portion 510 are disposed in the same layer.

[0306] The first connection portion 510 may be exposed, or may be covered by an insulating layer, which is not limited in the present embodiment.

[0307] In some embodiments, Fig.14A As shown, the first connection portion 510 may also be disposed on the surface of the substrate 131 away from the semiconductor layer 110. Alternatively, as shown in FIG. Fig. 14B As shown, a second dielectric layer 133 may be further disposed between the first connecting portion 510 and the substrate 131. This embodiment of the present application does not limit this.

[0308] For example, Fig. 14B As shown, the surface of the first connection portion 510 away from the substrate 131 may be flush with the pad 200 or the surface of the first contact structure 310 away from the substrate 131 .

[0309] Alternatively, illustratively, the surface of the pad 200 or the first contact structure 310 away from the substrate 131 exceeds the surface of the first connection portion 510 away from the substrate 131 .

[0310] Regarding the thickness of the first connection portion 510, that is, the size of the first connection portion 510 along the thickness direction of the semiconductor layer 110, exemplarily, the thickness of the first connection portion 510 is less than the thickness of the pad 200 or the first contact structure 310. Alternatively, exemplarily, the thickness of the first connection portion 510 is equal to the thickness of the pad 200 or the first contact structure 310. Alternatively, exemplarily, the thickness of the first connection portion 510 is greater than the thickness of the pad 200 or the first contact structure 310. The present application embodiment does not limit this, and it can be reasonably set according to actual conditions.

[0311] like Fig.14A As shown, the first connection portion 510 connects the pad 200 and the first contact structure 310 .

[0312] In this way, the pad 200 is connected to the semiconductor layer 110 through the first connection portion 510, the first contact structure 310 and the first conductive structure 410, thereby achieving grounding of the pad 200, so as to provide electrostatic protection for the pad 200. Therefore, it is possible to prevent the charges generated during the packaging process from accumulating on the pad 200, thereby preventing the metal interconnection layer 120 connected to the pad 200 from voltage overload and preventing the metal interconnection layer 120 from burning.

[0313] In some embodiments, Fig.15A As shown, the semiconductor structure 10 further includes a second contact structure 320 and a second conductive structure 420 disposed on the semiconductor layer 110 .

[0314] like Fig.15A As shown, the second contact structure 320 is disposed on the side of the metal interconnect layer 120 away from the semiconductor layer 110. That is, the first contact structure 310 and the second contact structure 320 are disposed on the same side. That is, the second contact structure 320 and the pad 200 and the first contact structure 310 are disposed on the same side of the device structure 100.

[0315] The second contact structure 320 may be exposed, or may be covered by an insulating layer, which is not limited in the present embodiment.

[0316] The second contact structure 320 is connected to the semiconductor layer 110 through the metal interconnect layer 120 and the second conductive structure 420 .

[0317] Exemplarily, the second conductive structure may be Figure 2B Alternatively, the second conductive structure may be disposed at the same layer as the interconnect conductor layer 232 of the peripheral interconnect layer 23. Figure 2B The memory cell string 31 is arranged in the same layer close to the source layer SL.

[0318] It is explained here that, for example, Fig.15A As shown, the pad 200 can be disposed between the first contact structure 310 and the second contact structure 320. Alternatively, illustratively, the pad 200 can also be disposed on the side of the first contact structure 310 away from the second contact structure 320. Alternatively, illustratively, the pad 200 can also be disposed on the side of the second contact structure 320 away from the first contact structure 310. The embodiment of the present application does not limit this, and it can be reasonably set according to actual conditions.

[0319] The first conductive structure 410 and the second conductive structure 420 may be the same or different, which is not limited in the present embodiment and can be reasonably configured according to actual conditions.

[0320] Exemplarily, the first conductive structure 410 includes an electrostatic protection circuit. The second conductive structure 420 includes an electrostatic protection circuit.

[0321] In this way, both the first contact structure 310 and the second contact structure 320 can be used as pads with electrostatic protection circuits.

[0322] Or, for example, Fig. 15B As shown, the first conductive structure 410 is connected to the metal contact structure 121 to form a second sealing ring 620. The second conductive structure 420 includes an electrostatic protection circuit.

[0323] In this way, the second contact structure 320 can be used as a pad with an electrostatic protection circuit.

[0324] Or, for example, Fig. 15C As shown, the first conductive structure 410 is connected to the metal contact structure 121 to form a first sealing ring 610 . The second conductive structure 420 is also connected to the metal contact structure on the metal interconnect layer 120 to form a second sealing ring 620 .

[0325] For example, Fig. 15C As shown, the semiconductor structure 10 further includes a second connection portion 520 . The second connection portion 520 connects the second contact structure 320 and the pad 200 .

[0326] The second connection portion 520 is disposed on a side of the metal interconnection layer 120 away from the semiconductor layer 110 .

[0327] That is, the pad 200 , the second contact structure 320 and the second connection portion 520 are disposed on the same side. That is, the second connection portion 520 , the pad 200 and the first contact structure 310 are disposed on the same side of the device structure 100 .

[0328] Exemplarily, the pad 200 , the second contact structure 320 , and the second connection portion 520 are disposed in the same layer.

[0329] The second connection portion 520 may be exposed, or may be covered by an insulating layer, which is not limited in the present embodiment.

[0330] In this way, the pad 200 is connected to the semiconductor layer 110 through the second connection portion 520, the second contact structure 320 and the second conductive structure 420, thereby achieving grounding of the pad 200, so as to provide electrostatic protection for the pad 200. Therefore, it is possible to prevent the charges generated during the packaging process from accumulating on the pad 200, thereby preventing the metal interconnection layer 120 connected to the pad 200 from voltage overload and preventing the metal interconnection layer 120 from burning.

[0331] For example, Fig.16A and Fig. 16B As shown, Fig. 16B for Fig.16A A cross-sectional view along the C1C2 direction. The semiconductor structure 10 further includes a third connection portion 530 . The third connection portion 530 connects the first contact structure 310 and the second contact structure 320 .

[0332] The third connection portion 530 is disposed on a side of the metal interconnection layer 120 away from the semiconductor layer 110 .

[0333] That is, the first contact structure 310 , the second contact structure 320 and the third connection portion 530 are disposed on the same side. That is, the third connection portion 530 , the pad 200 and the first contact structure 310 are disposed on the same side of the device structure 100 .

[0334] Exemplarily, the first contact structure 310 , the second contact structure 320 , and the third connection portion 530 are disposed in the same layer.

[0335] The third connection portion 530 may be exposed, or may be covered by an insulating layer, which is not limited in the present embodiment.

[0336] It is explained here that the pad 200 can be connected to the first contact structure 310 only through the first connection portion 510. Alternatively, the pad 200 can also be connected to the second contact structure 320 only through the second connection portion 520. Alternatively, the pad can also be connected to the first contact structure 310 through the first connection portion 510 and to the second contact structure 320 through the second connection portion 520. The embodiment of the present application does not limit this, and it is only necessary that the pad 200 is connected to the semiconductor layer 110 through any contact structure (the first contact structure 310 or the second contact structure 320).

[0337] In this way, the pad 200 is connected to the semiconductor layer 110, thereby grounding the pad 200, so as to provide electrostatic protection for the pad 200. Therefore, it is possible to prevent the charge generated during the packaging process from accumulating on the pad 200, thereby preventing the metal interconnection layer 120 connected to the pad 200 from voltage overload and burning.

[0338] In other embodiments, Fig.17 As shown, the device structure 100 includes a first sub-device structure 130 and a second sub-device structure 140 .

[0339] The first sub-device structure 130 and the second sub-device structure 140 are coupled via the metal interconnection layer 120 .

[0340] For example, Fig.17 As shown, the metal interconnection layer 120 includes a first metal interconnection layer 122 and a second metal interconnection layer 123 .

[0341] At this time, the first sub-device structure 130 and the second sub-device structure 140 may be coupled via the first metal interconnection layer 122 and the second metal interconnection layer 123 .

[0342] For example, the first metal interconnection layer 122 may include a metal wiring layer formed by a front-end process, and the second metal interconnection layer 123 may include a metal wiring layer formed by a back-end process.

[0343] It is understood that the first sub-device structure 130 may include a first metal interconnection layer 122 , and the second sub-device structure 140 may include a second metal interconnection layer 123 .

[0344] Or, for example, Fig.17 As shown, a bonding interface 500 may be provided between the first metal interconnection layer 122 and the second metal interconnection layer 123 , and the first metal interconnection layer 122 and the second metal interconnection layer 123 may be bonded and coupled to each other through the bonding interface 500 .

[0345] The embodiment of the present application does not limit the specific device structures of the first sub-device structure 130 and the second sub-device structure 140 , and they can be reasonably configured according to actual conditions.

[0346] In some embodiments, one of the first sub-device structure 130 and the second sub-device structure 140 is an array device structure, and the other is a peripheral device structure.

[0347] Exemplarily, the first sub-device structure 130 includes an array device structure, and the second sub-device structure 140 includes a peripheral device structure. Correspondingly, the first metal interconnection layer 122 includes an array interconnection layer, and the second metal interconnection layer 123 includes a peripheral interconnection layer.

[0348] Alternatively, illustratively, the first sub-device structure 130 includes a peripheral device structure, and the second sub-device structure 140 includes an array device structure. Correspondingly, the first metal interconnection layer 122 includes a peripheral interconnection layer, and the second metal interconnection layer 123 includes an array interconnection layer.

[0349] Exemplarily, the first sub-device structure 130 may be Figure 2B The array device 30 structure in the embodiment of the present invention, the second sub-device structure 140 may be Figure 2B The first metal interconnect layer 122 may be Figure 2B The array interconnect layer 40 in the second metal interconnect layer 123 may be Figure 2B The peripheral interconnect layer 23 in the bonding pad 200 can be formed on Figure 2B The source layer SL is located away from the surface of the array interconnection layer 40 .

[0350] Alternatively, the first sub-device structure 130 may be, for example, Figure 2B The peripheral device 20 structure in the second sub-device structure 140 may be Figure 2B The first metal interconnect layer 122 may be Figure 2B The peripheral interconnection layer 23 in the second metal interconnection layer 123 may be Figure 2B The pad 200 may be formed on the array interconnect layer 40. Figure 2BThe middle substrate 21 is on a surface away from the peripheral interconnection layer 23 .

[0351] The present application embodiment does not limit this, and can be reasonably set according to actual conditions. For the convenience of illustration, the device structure 100 includes two sub-device structures (a first sub-device structure 130 and a second sub-device structure 140) as an example, the first sub-device structure 130 includes a peripheral device structure, and the second sub-device structure 140 includes an array device structure.

[0352] Continue to refer Fig.17 The semiconductor layer 110 is located on a side of the second sub-device structure 140 away from the first sub-device structure 130 .

[0353] It is understandable that the second sub-device structure 140 may include the semiconductor layer 110. Alternatively, the second sub-device structure 140 may also not include the semiconductor layer 110. This application does not limit this.

[0354] At this time, the first conductive structure 410 is disposed on the semiconductor layer 110. The second sub-device structure 140 may include the first conductive structure 410. Alternatively, the second sub-device structure 140 may not include the first conductive structure 410. This application does not limit this.

[0355] It is explained here that a second conductive structure 420 may be further disposed on the semiconductor layer 110 .

[0356] like Fig.17 As shown, the first sub-device structure 130 further includes a substrate 131 and a first dielectric layer 132. The substrate 131 and the first dielectric layer 132 are stacked.

[0357] That is, the semiconductor layer 110 , the second metal interconnection layer 123 , the bonding interface 500 , the first metal interconnection layer 122 , the first dielectric layer 132 and the substrate 131 are stacked in sequence.

[0358] The material of the substrate 131 may include, for example, a semiconductor material, such as silicon (single crystal silicon, polycrystalline silicon or amorphous silicon), germanium (single crystal germanium), silicon germanium, silicon carbide, glass, gallium nitride, gallium arsenide, glass, SOI (silicon on insulator), GOI (germanium on insulator) or other suitable III-V compound substrates, etc. The substrate 131 may also be P-type doped or N-type doped.

[0359] The materials of the substrate 131 and the semiconductor layer 110 may be the same or different, which is not limited in the present embodiment.

[0360] Exemplarily, the material of the first dielectric layer 132 may include, for example, silicon oxide carbon (SiOCH), silicon oxynitride (SiON), silicon carbide (SiC), or silicon nitride (SiN).

[0361] At this time, for example, Fig.17 As shown, the pad 200 , the first contact structure 310 , and the first connection portion 510 are all disposed on a side of the first sub-device structure 130 away from the second sub-device structure 140 .

[0362] like Fig.17 As shown, the first sub-device structure 130 further includes a third conductive structure 430 and a fourth conductive structure 440 .

[0363] For example, the third conductive structure 430 and the fourth conductive structure 440 may be Figure 2B The storage unit strings 31 in the same layer are arranged.

[0364] The third conductive structure 430 penetrates the first sub-device structure 130 , and the fourth conductive structure 440 penetrates the first sub-device structure 130 .

[0365] Exemplarily, the third conductive structure 430 penetrates the substrate 131 and the first dielectric layer 132 , and the fourth conductive structure 440 penetrates the substrate 131 and the first dielectric layer 132 .

[0366] like Fig.17 As shown, the third conductive structure 430 may include a first through-contact 431 and a first interconnection contact 432. The fourth conductive structure 440 may include a second through-contact 441 and a second interconnection contact 442.

[0367] The first through contact 431 penetrates the substrate 131 , and the first interconnection contact 432 penetrates the first dielectric layer 132 . The second through contact 441 penetrates the substrate 131 , and the second interconnection contact 442 penetrates the first dielectric layer 132 .

[0368] Exemplarily, the first through-contact 431 and the second through-contact 441 are disposed on the same layer, and the first interconnection contact 432 and the second interconnection contact 442 are disposed on the same layer.

[0369] like Fig.17 As shown, the pad 200 is connected to the metal interconnect layer 120 through the third conductive structure 430 .

[0370] That is, the pad 200 is connected to the metal interconnection layer 120 through the first through contact 431 and the first interconnection contact 432. The pad 200 is electrically connected to the metal interconnection layer 120.

[0371] The first contact structure 310 is connected to the semiconductor layer 110 through the fourth conductive structure 440 , the metal interconnection layer 120 , and the first conductive structure 410 .

[0372] In other words, the first contact structure 310 is connected to the semiconductor layer 110 through the second through-contact 441 , the second interconnection contact 442 , the metal interconnection layer 120 , and the first conductive structure 410 .

[0373] For example, Fig.18 As shown, the first conductive structure 410 is connected to the metal contact structure 121 to form a first sealing ring 610. The second through contact 441 is connected to the second interconnection contact 442 to form a third sealing ring 630. The first sealing ring 610 and the third sealing ring 630 are connected.

[0374] That is, the first sealing ring 610 and the third sealing ring 630 are connected to the semiconductor layer 110 .

[0375] It is explained here that any one of the first sub-device structure 130 or the second sub-device structure 140 can be used alone as the device structure 100 .

[0376] That is, the device structure 100 may include a third conductive structure 430 and a fourth conductive structure 440 .

[0377] In some embodiments, Fig.19 As shown, the semiconductor structure 10 further includes a second contact structure 320 and a second conductive structure 420 .

[0378] For example, Fig.19 As shown, the semiconductor structure 10 further includes a second connection portion 520 connecting the pad 200 and the second contact structure 320 , and a third connection portion 530 connecting the first contact structure 310 and the second contact structure 320 .

[0379] The second contact structure 320 , the second connection portion 520 , and the third connection portion 530 are all disposed on a side of the first sub-device structure 130 away from the second sub-device structure 140 .

[0380] At this time, the second contact structure 320 is connected to the semiconductor layer 110 through the fifth conductive structure 450 , the metal interconnection layer 120 , and the second conductive structure 420 .

[0381] In the semiconductor structure 10 provided in the embodiment of the present application, the first contact structure 310 is connected to the semiconductor layer 110 through the metal interconnection layer 120 and the first conductive structure 410 to achieve electrostatic protection, and the pad 200 is connected to the first contact structure 310 through the first connection portion 510, so that the charge generated on the pad 200 is connected to the semiconductor layer 110 through the first connection portion 510, the first contact structure 310 and the first conductive structure 410, so as to play an electrostatic protection role for the pad 200. Therefore, it is possible to prevent the charge generated during the packaging process from accumulating on the pad 200, thereby preventing the metal interconnection layer 120 connected to the pad 200 from voltage overload, and preventing the metal interconnection layer 120 from burning.

[0382] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that: include: A device structure comprising a semiconductor layer and a metal interconnection layer disposed on the semiconductor layer; A pad is disposed on a side of the metal interconnect layer away from the semiconductor layer; the pad is connected to the metal interconnect layer; a first contact structure and a first conductive structure, wherein the first contact structure is disposed on a side of the metal interconnect layer away from the semiconductor layer; the first conductive structure is disposed on the semiconductor layer; and the first contact structure is connected to the semiconductor layer through the metal interconnect layer and the first conductive structure; The first connecting portion connects the pad and the first contact structure.

2. The semiconductor structure according to claim 1, characterized in that: The metal interconnection layer includes a metal contact structure connected to the first conductive structure; the first conductive structure and the metal contact structure are connected to form a first sealing ring.

3. The semiconductor structure according to claim 1, characterized in that: The first conductive structure includes an electrostatic protection circuit; the first contact structure is connected to the semiconductor layer through the metal interconnect layer and the electrostatic protection circuit.

4. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure further includes a second contact structure and a second conductive structure; the second contact structure is disposed on a side of the metal interconnect layer away from the semiconductor layer; the second conductive structure is disposed on the semiconductor layer; the second contact structure is connected to the semiconductor layer through the metal interconnect layer and the second conductive structure; The semiconductor structure further includes a second connection portion; the second connection portion connects the second contact structure and the pad.

5. The semiconductor structure according to claim 4, characterized in that: The semiconductor structure further includes a third connection portion; the third connection portion connects the first contact structure and the second contact structure.

6. The semiconductor structure according to claim 4 or 5, characterized in that: The second conductive structure includes an electrostatic protection circuit; the metal interconnection layer includes a metal contact structure connected to the first conductive structure; and the first conductive structure and the metal contact structure are connected to form a second sealing ring.

7. The semiconductor structure according to claim 1, characterized in that: The pad, the first contact structure and the first connecting portion are arranged in the same layer.

8. The semiconductor structure according to claim 1, characterized in that: The device structure includes a first sub-device structure and a second sub-device structure; the semiconductor layer is located on a side of the second sub-device structure away from the first sub-device structure; the first sub-device structure and the second sub-device structure are coupled via the metal interconnection layer; The semiconductor structure further includes a third conductive structure and a fourth conductive structure; the third conductive structure runs through the first sub-device structure, and the fourth conductive structure runs through the first sub-device structure; The pad is connected to the metal interconnect layer through the third conductive structure; the first contact structure is connected to the semiconductor layer through the fourth conductive structure, the metal interconnect layer and the first conductive structure.

9. The semiconductor structure according to claim 8, characterized in that: The first sub-device structure further includes a substrate and a first dielectric layer which are stacked; the third conductive structure includes a first through contact and a first interconnection contact, the first through contact penetrates the substrate, and the first interconnection contact penetrates the first dielectric layer; The fourth conductive structure includes a second through-contact and a second interconnection contact, wherein the second through-contact penetrates the substrate, and the second interconnection contact penetrates the first dielectric layer.

10. The semiconductor structure according to claim 9, characterized in that: The metal interconnect layer includes a metal contact structure connected to the first conductive structure; The first conductive structure is connected to the metal contact structure to form a first sealing ring; The second through contact is connected to the second interconnection contact to form a third sealing ring; and the first sealing ring is connected to the third sealing ring.

11. The semiconductor structure according to claim 9, characterized in that: The first through contact and the second through contact are arranged on the same layer; the first interconnection contact and the second interconnection contact are arranged on the same layer.

12. The semiconductor structure according to claim 8, characterized in that One of the first sub-device structure and the second sub-device structure is an array device structure, and the other is a peripheral device structure.

13. The semiconductor structure according to claim 8, characterized in that The first sub-device structure includes the array device structure, and the second sub-device structure includes the peripheral device structure.

14. A method for preparing a semiconductor structure, characterized in that: include: Providing a device structure; the device structure comprises a semiconductor layer and a metal interconnection layer disposed on the semiconductor layer; A first conductive structure is disposed on the semiconductor layer and connected to the metal interconnection layer; forming a pad; the pad is formed on a side of the metal interconnect layer away from the semiconductor layer; the pad is connected to the metal interconnect layer; forming a first contact structure; the first contact structure is formed on a side of the metal interconnect layer away from the semiconductor layer; the first contact structure is connected to the semiconductor layer through the metal interconnect layer and the first conductive structure; A first connection portion is formed, the first connection portion connecting the pad and the first contact structure.

15. The method for preparing a semiconductor structure according to claim 14, characterized in that: The preparation method further comprises: forming a second contact structure; the second contact structure is formed on a side of the metal interconnect layer away from the semiconductor layer; the second contact structure is connected to the semiconductor layer through the metal interconnect layer and the second conductive structure; the second conductive structure is disposed on the semiconductor layer; A second connection portion is formed; the second connection portion connects the second contact structure and the pad.

16. The method for preparing a semiconductor structure according to claim 15, characterized in that: The preparation method further comprises: A third connecting portion is formed; the third connecting portion connects the first contact structure and the second contact structure.

17. A storage system, characterized in that: include: A semiconductor structure, wherein the semiconductor structure is the semiconductor structure according to any one of claims 1 to 13; The controller is coupled to the semiconductor structure to control the semiconductor structure to store data.

18. An electronic device, characterized in that: Comprising the storage system as claimed in claim 17.

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