Semiconductor packaging structure and preparation method thereof

Abstract

The invention provides a semiconductor structure and a preparation method. The semiconductor structure includes a first substrate having a first side and a second side opposite to the first side, where the first side includes a recess recessed from the first side; a first semiconductor die disposed in the recess and bonded to the first side of the first substrate; a second semiconductor die bonded to the second side of the first substrate; a second substrate electrically bonded to the first side of the first substrate; a plurality of conductive vias disposed along and extending through the second substrate; and a plurality of conductive lines disposed on the second substrate.

Description

Technical Field

[0001] This application claims priority to U.S. patent application No. 18 / 385,499 (i.e., the priority date is "October 31, 2023"), the contents of which are incorporated herein by reference in their entirety.

[0002] The present disclosure relates to a semiconductor structure and a method for preparing the semiconductor structure, and more particularly to a bonding structure, including a semiconductor packaging structure and a method for preparing the semiconductor interconnect packaging structure. Background Art

[0003] As the semiconductor industry moves into higher technology nodes in pursuit of higher component density and performance, photolithography precision has reached advanced levels. Further reductions in component size require proportional reductions in component size and distance between components. However, the reduction in component size and distance between components poses challenges to the precise control of these parameters.

[0004] The bonding structure of the component is essential to maintain the ability to electrically connect to external components. To facilitate this, an interface is established between the semiconductor component and other components in the package, which consists of bonding bumps or connectors that form a bonding structure with sufficient connection. Due to the reduction in the occupied area of ​​the component and the increase in the number of input / output terminals, the bonding pad or connector area is limited, so sufficient bonding structure must be created. Therefore, it is necessary to establish an enhanced bonding structure to provide a reliable connection interface within the bonding package of the semiconductor component.

[0005] The above description of “prior art” only provides background technology, does not admit that the above description of “prior art” discloses the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of this case. Summary of the invention

[0006] An embodiment of the present disclosure provides a semiconductor structure, including a first substrate having a first side and a second side opposite to the first side, wherein the first side includes a groove recessed from the first side; a first semiconductor grain disposed in the groove and bonded to the first side of the first substrate; a second semiconductor grain bonded to the second side of the first substrate; a second substrate electrically bonded to the first side of the first substrate; a plurality of conductive through holes disposed along the second substrate and extending through the second substrate; and a plurality of conductive wires disposed on the second substrate.

[0007] According to some embodiments of the present disclosure, the conductive via includes: a filling layer, arranged along the second substrate and extending through the second substrate; and two isolation layers, arranged on both sides of the filling layer, wherein the two isolation layers include silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane, or parylene, epoxy resin, poly(p-xylene) (poly(p-xylene)).

[0008] According to some embodiments of the present disclosure, the conductive via includes a seed layer located between the second isolation layer and the filling layer and between the filling layer and a corresponding conductive line on the second substrate.

[0009] According to some embodiments of the present disclosure, the conductive via includes an adhesion layer located between the seed layer and the two isolation layers and between the seed layer and corresponding conductive lines on the second substrate, wherein the adhesion layer includes titanium, tantalum, titanium tungsten or manganese nitride.

[0010] According to some embodiments of the present disclosure, the conductive via includes a barrier layer located between the adhesive layer and the two isolation layers and between the adhesive layer and the corresponding conductive lines on the second substrate, wherein the barrier layer includes tantalum, tantalum nitride, titanium, titanium nitride, rhenium, nickel boride or a tantalum nitride / tantalum double layer.

[0011] According to some embodiments of the present disclosure, the second isolation layer has a thickness ranging from about 50 nm to about 200 nm.

[0012] According to some embodiments of the present disclosure, the second isolation layer has a thickness ranging from about 1 μm to about 5 μm.

[0013] According to some embodiments of the present disclosure, the seed layer includes copper or ruthenium.

[0014] According to some embodiments of the present disclosure, the filling layer is copper.

[0015] According to some embodiments of the present disclosure, the semiconductor structure further includes a molding material encapsulating the first substrate, the second substrate, the first semiconductor die, and the second semiconductor die.

[0016] According to some embodiments of the present disclosure, the molding material includes epoxy resin, PI, BCB, PBO, and PEEK.

[0017] According to some embodiments of the present disclosure, the semiconductor structure further includes a plurality of connectors, wherein each connector is located on a corresponding conductive line.

[0018] According to some embodiments of the present disclosure, the plurality of connectors include Sn, Pb, Ni, Au, Ag, Cu, Bi or a combination thereof.

[0019] Another embodiment of the present disclosure provides a semiconductor structure, including a first substrate, including a horizontal portion and a protruding portion extending on a peripheral area of ​​the horizontal portion; a first semiconductor grain, bonded to a first side of the horizontal portion; a second semiconductor grain, bonded to a second side of the horizontal portion and laterally surrounded by the protruding portion; a second substrate, electrically bonded to the protruding portion of the first substrate; a passivation layer, located on the second substrate; and a barrier layer, located on the second substrate and in the passivation layer.

[0020] According to some embodiments of the present disclosure, the passivation layer defines a plurality of openings disposed along the passivation layer to expose a portion of the second substrate.

[0021] According to some embodiments of the present disclosure, the barrier layer is located in the plurality of openings.

[0022] According to some embodiments of the present disclosure, a thickness of the passivation layer is greater than a thickness of the barrier layer.

[0023] According to some embodiments of the present disclosure, the semiconductor structure further includes a plurality of connectors located on the barrier layer.

[0024] According to some embodiments of the present disclosure, a first portion of the connector extends to the passivation layer, completely fills the plurality of openings, and is disposed on the barrier layer.

[0025] According to some embodiments of the present disclosure, a second portion of the connector protrudes from a plane coplanar with an upper surface of the passivation layer and is disposed on the first portion of the connector.

[0026] According to some embodiments of the present disclosure, the passivation layer includes polybenzoxazole, polyimide, benzocyclobutene, a solder mask, the like, or a combination thereof.

[0027] According to some embodiments of the present disclosure, the passivation layer includes silicon nitride, silicon oxide, silicon oxynitride, silicon oxynitride, phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, or a combination thereof.

[0028] According to some embodiments of the present disclosure, the barrier layer includes aluminum fluoride and zinc oxide.

[0029] According to some embodiments of the present disclosure, the sidewall of the opening is substantially vertical or tapered.

[0030] According to some embodiments of the present disclosure, the connector is a solder joint.

[0031] According to some embodiments of the present disclosure, the solder joint includes tin, silver or copper.

[0032] According to some embodiments of the present disclosure, the semiconductor structure further includes a molding material encapsulating the first substrate, the second substrate, the first semiconductor die, and the second semiconductor die.

[0033] According to some embodiments of the present disclosure, the molding material includes epoxy resin, PI, BCB, PBO, and PEEK.

[0034] Another embodiment of the present disclosure provides a semiconductor structure, including a first substrate having a first side and a second side opposite to the first side, wherein the first side includes a groove recessed from the first side; a first semiconductor grain disposed in the groove and bonded to the first side of the first substrate; a second semiconductor grain bonded to the second side of the first substrate; a second substrate electrically bonded to the first side of the first substrate; a plurality of conductive vias disposed along and extending through the second substrate; a passivation layer located on the second substrate; and a barrier layer located on the second substrate and in the passivation layer.

[0035] According to some embodiments of the present disclosure, the conductive via includes: two isolation layers, conformally formed on two side walls of the via opening; a via barrier layer, conformally formed on the isolation layer and on the lower surface of the via opening, wherein the via barrier layer has a U-shaped cross-sectional profile and includes tantalum, tantalum nitride, titanium, titanium nitride, rhenium, nickel boride or a tantalum nitride / tantalum double layer; an adhesion layer, conformally formed on the barrier layer, wherein the adhesion layer has a U-shaped cross-sectional profile and includes titanium, tantalum, titanium tungsten or manganese nitride; a seed layer, conformally formed on the adhesion layer, wherein the seed layer has a U-shaped cross-sectional profile and includes copper or ruthenium; and a filling layer, formed on the seed layer and completely fills the via opening, wherein the filling layer is copper.

[0036] According to some embodiments of the present disclosure, the second isolation layer includes silicon oxide, silicon nitride, silicon oxynitride or tetra-ethyl ortho-silicate.

[0037] According to some embodiments of the present disclosure, the second isolation layer has a thickness between about 50 nm and about 200 nm.

[0038] According to some embodiments of the present disclosure, the second isolation layer includes parylene, epoxy resin, or poly(p-xylene).

[0039] According to some embodiments of the present disclosure, the second isolation layer has a thickness ranging from about 1 μm to about 5 μm.

[0040] According to some embodiments of the present disclosure, the adhesive layer has a thickness between about 5 nm and about 50 nm.

[0041] According to some embodiments of the present disclosure, the seed layer has a thickness between about 10 nm and about 40 nm.

[0042] According to some embodiments of the present disclosure, the passivation layer defines a plurality of openings disposed along the passivation layer to expose a portion of the second substrate.

[0043] According to some embodiments of the present disclosure, the barrier layer is located in the plurality of openings.

[0044] According to some embodiments of the present disclosure, a thickness of the passivation layer is greater than a thickness of the barrier layer.

[0045] According to some embodiments of the present disclosure, the semiconductor structure further includes a connector located on the barrier layer.

[0046] According to some embodiments of the present disclosure, a first portion of the connector extends to the passivation layer, completely fills the opening, and is disposed on the barrier layer.

[0047] According to some embodiments of the present disclosure, a second portion of the connector protrudes from a plane coplanar with the upper surface of the passivation layer and is disposed on the first portion of the connector.

[0048] According to some embodiments of the present disclosure, the passivation layer includes polybenzoxazole, polyimide, benzocyclobutene, a solder mask, the like, or a combination thereof.

[0049] According to some embodiments of the present disclosure, the passivation layer includes silicon nitride, silicon oxide, silicon oxynitride, silicon oxynitride, phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, or a combination thereof.

[0050] According to some embodiments of the present disclosure, the barrier layer includes aluminum fluoride and zinc oxide.

[0051] According to some embodiments of the present disclosure, the sidewall of the opening is substantially vertical or tapered.

[0052] According to some embodiments of the present disclosure, the connector is a solder joint.

[0053] According to some embodiments of the present disclosure, the solder joint includes tin, silver or copper.

[0054] According to some embodiments of the present disclosure, the semiconductor structure further includes a molding material encapsulating the first substrate, the second substrate, the first semiconductor die, and the second semiconductor die.

[0055] According to some embodiments of the present disclosure, the molding material includes epoxy resin, PI, BCB, PBO, and PEEK.

[0056] Through the joint structure disclosed in the present invention, the connector can be arranged in a larger area in the packaging structure, and the position or size of the connector can be selected more flexibly. The connector layout can also be determined to meet the design specifications, thereby improving the joint efficiency.

[0057] The above has been a fairly broad overview of the technical features and advantages of the present disclosure so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the patent application scope of the present disclosure will be described below. Those with ordinary knowledge in the technical field to which the present disclosure belongs should understand that the concepts and specific embodiments disclosed below can be used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the attached patent application scope. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] A more complete understanding of the present disclosure may be obtained by reference to the detailed description and the scope of the claims. The present disclosure should also be understood to be associated with the element numbers of the drawings, which represent similar elements throughout the description. It should be understood that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for the sake of clarity of discussion, the sizes of various features may be increased or decreased at will.

[0059] Figure 1A and Figure 1B 2 are cross-sectional and bottom-up schematic diagrams, respectively illustrating semiconductor package structures according to some embodiments of the present disclosure.

[0060] Figure 2A and Figure 2B 2 is a cross-sectional schematic diagram illustrating a semiconductor package structure according to different embodiments of the present disclosure.

[0061] Figures 3A to 3G Schematic cross-sectional views illustrating various intermediate stages of a method for preparing a substrate according to some embodiments of the present disclosure.

[0062] FIG. 4A to FIG. 4C Schematic cross-sectional views illustrating various intermediate stages of a method for preparing a substrate according to some embodiments of the present disclosure.

[0063] FIG. 5A to FIG. 5E Schematic cross-sectional views illustrating various intermediate stages of a method for preparing a substrate according to some embodiments of the present disclosure.

[0064] FIG. 6A to FIG. 6DIt is a cross-sectional schematic diagram illustrating various intermediate stages of the method for preparing semiconductor grains according to some embodiments of the present disclosure.

[0065] FIG. 7A to FIG. 7H Schematic cross-sectional views illustrating various intermediate stages of a method for preparing a semiconductor package structure according to some embodiments of the present disclosure.

[0066] FIG. 8A to FIG. 8C Schematic cross-sectional views illustrating various intermediate stages of a method for preparing a semiconductor package structure according to some embodiments of the present disclosure.

[0067] FIG. 9A to FIG. 9E Schematic cross-sectional views illustrating various intermediate stages of a method for preparing a semiconductor package structure according to some embodiments of the present disclosure.

[0068] Fig.10 1 is a flow chart illustrating a method for preparing a semiconductor packaging structure according to some embodiments of the present disclosure.

[0069] Fig.11A 2 is a cross-sectional schematic diagram illustrating a semiconductor package structure according to different embodiments of the present disclosure.

[0070] Fig. 11B is a close-up cross-sectional schematic diagram illustrating some embodiments of the present disclosure. Fig. 11B The dashed area A is shown.

[0071] Fig.12 2 is a cross-sectional schematic diagram illustrating a semiconductor package structure according to different embodiments of the present disclosure.

[0072] Fig.13 2 is a cross-sectional schematic diagram illustrating a semiconductor package structure according to different embodiments of the present disclosure.

[0073] The accompanying drawings are described as follows:

[0074] 100:Semiconductor packaging structure

[0075] 101:Semiconductor packaging structure

[0076] 102:Semiconductor packaging structure

[0077] 103:Semiconductor packaging structure

[0078] 104:Semiconductor packaging structure

[0079] 108: Electrical insulation material

[0080] 109: first passivation layer

[0081] 110: First base

[0082] 110A: First side

[0083] 110B: Second side

[0084] 110E: Surrounding area

[0085] 110H: horizontal part

[0086] 110M:Depth or Height

[0087] 110P: protruding part

[0088] 110R: Groove

[0089] 110S: Sidewall

[0090] 110T: Bottom (upper) surface

[0091] 111A: Bottom surface

[0092] 112: Wire

[0093] 113: Conductive via

[0094] 114: Wire

[0095] 115: Conductive via

[0096] 116: Wire

[0097] 117: Conductive via

[0098] 118: Electrical insulation material

[0099] 120: Second base

[0100] 120A: First side

[0101] 120B: Second side

[0102] 121A: Upper surface

[0103] 122: Wire

[0104] 124: Wire

[0105] 125: Conductive via

[0106] 130: first semiconductor grain

[0107] 130B: Back

[0108] 130F:Front

[0109] 130T:Thickness

[0110] 132: Connector (conductive pad)

[0111] 140: second semiconductor grain

[0112] 140B: Back

[0113] 140F:Front

[0114] 142: Connector (conductive pad)

[0115] 150: Molding material

[0116] 150S: Space

[0117] 150T: Space

[0118] 150V: Space

[0119] 152:Joint assembly

[0120] 160: Connector

[0121] 201: cushion

[0122] 203: first barrier layer

[0123] 205: First connector

[0124] 216: Wire

[0125] 242: Conductive pad

[0126] 250: Wire

[0127] 300: Preparation method

[0128] 302: Base

[0129] 304: Base

[0130] 306: Base

[0131] 312: first dielectric layer

[0132] 314: Second dielectric layer

[0133] 316: third dielectric layer

[0134] 318: Fourth dielectric layer

[0135] 320: fifth dielectric layer

[0136] 400: Preparation method

[0137] 401: Base

[0138] 402: Base

[0139] 404: Base

[0140] 410: Copper foil layer

[0141] 420: Copper foil layer

[0142] 500: Preparation method

[0143] 501: Composite core layer

[0144] 600: Preparation method

[0145] 602: Base

[0146] 604: Base

[0147] 610: Base

[0148] 620:Semiconductor components

[0149] 630: Interconnection layer

[0150] 640: Conductive pad

[0151] 650: Cutting tools

[0152] 700: Preparation method

[0153] 900: Preparation method

[0154] 1000: Preparation method

[0155] AL: Adhesive layer

[0156] BL: Barrier layer

[0157] FL: Filling layer

[0158] IL: Isolation Layer

[0159] OP1: First opening

[0160] R1: Region

[0161] S1000: Steps

[0162] S1000: Preparation method

[0163] S1002: Steps

[0164] S1004: Steps

[0165] S1006: Steps

[0166] S1008: Steps

[0167] S1012: Steps

[0168] S1014: Steps

[0169] SL: Seed layer

[0170] T1: Thickness

[0171] T2: Thickness

[0172] VO: Through hole opening. DETAILED DESCRIPTION

[0173] Specific examples of components and configurations are described below to simplify the embodiments of the present disclosure. Of course, these embodiments are for illustration only and are not intended to limit the scope of the present disclosure. For example, in the description, the first component is formed on the second component, which may include an embodiment in which the first and second components are in direct contact, and may also include an embodiment in which additional components are formed between the first and second components so that the first and second components are not in direct contact. In addition, the embodiments of the present disclosure may repeat reference numbers and / or letters in many examples. The purpose of these repetitions is to simplify and clarify, and unless otherwise specified in the text, they do not themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0174] It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. On the contrary, these terms are only used to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the progressive conception of the present disclosure, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0175] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms "comprises" and / or "comprising" are used in this specification, the multiple terms specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the above.

[0176] For ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature shown in the figures to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0177] Although the numerical ranges and parameters describing the broad scope of the present disclosure are approximate, the numerical values ​​described in the specific embodiments are reported as accurately as possible. However, any numerical value inherently contains certain errors, which are necessarily caused by the deviations usually found in the corresponding test measurements. Moreover, as used herein, the terms "approximately", "roughly" or "substantially" generally mean within 10%, 5%, 1% or 0.5% of a given value or range. Alternatively, the terms "approximately", "roughly" or "substantially" refer to within the acceptable standard error of the mean value when considered by a person of ordinary knowledge in the art. Except for the operating / working examples, or unless otherwise expressly stated, all numerical ranges, quantities, values ​​and percentages disclosed herein, such as the quantity of materials, the duration of time, temperature, operating conditions, the ratio of quantities, etc., should be understood to be modified by the terms "approximately", "roughly" or "substantially" in all cases. Therefore, unless otherwise indicated, the numerical parameters described in the present disclosure and the attached patent scope are approximate values ​​that can be changed as needed. At least, each numerical parameter should at least be interpreted according to the number of reported significant figures and by applying ordinary rounding techniques. Ranges may be expressed herein as from one endpoint to the other endpoint or between two endpoints. Unless otherwise stated, all ranges disclosed herein include the endpoints.

[0178] As used throughout this disclosure, the terms "coupled" or "connected" refer to a physical or electrical connection between two or more objects. These objects may also be said to be "coupled" or "connected" through the exchange of data or information. These "coupled" or "connected" objects may in some cases be in direct contact, or indirectly contacted through other intermediary objects.

[0179] Embodiments of the present disclosure discuss a semiconductor package structure formed by a plurality of memory cells and a method for preparing the semiconductor package structure. According to some embodiments of the present disclosure, at least two semiconductor grains are bonded together by a first substrate used as a first interconnect structure. According to some embodiments of the present disclosure, at least two semiconductor grains include memory grains or other suitable semiconductor grains. At least two semiconductor grains are bonded to the first substrate in a vertical manner on both sides of the first substrate, so that the package footprint can be minimized. In addition, in order to minimize the thickness of the components of the semiconductor package, the first substrate is recessed to form a groove, in which one of the semiconductor grains can be accommodated in the groove and bonded to the substrate. According to some embodiments of the present disclosure, the semiconductor package structure includes a plurality of connectors, which may include a plurality of solder bumps, configured to be electrically coupled to an external component or circuit. Due to the presence of the groove, the available bonding area of ​​the surface on which the solder bump is formed may be reduced. As a result, the available bonding area may be less than the minimum requirement for the bonding area. The configuration of the solder bump, such as position, pitch, and size, is limited and may not meet the design specifications.

[0180] In order to solve the above problems, a second substrate used as a second interconnect structure is proposed to help join multiple semiconductor grains, wherein the first substrate and at least one semiconductor grain are joined to the first side of the second substrate. The solder bump is joined to the second side of the second substrate and is electrically coupled to multiple semiconductor grains through the first substrate and the second substrate. As a result, the bonding area of ​​the solder bump is increased. Therefore, the degree of freedom of distributing the solder bump can be greatly increased. Therefore, the solder bump can be configured in a desired manner that meets the design specifications without compromising the performance of the component.

[0181] Figure 1A 1 is a cross-sectional schematic diagram illustrating a semiconductor package structure 100 of some embodiments of the present disclosure. According to some embodiments of the present disclosure, the semiconductor package structure 100 is a memory package. However, other types of semiconductor packages are also within the scope of the present disclosure, such as application specific integrated circuit (ASIC) packaging, field programmable gate array (FPGA) packaging, processor packaging, network integrated circuit (NIC) packaging, micro-electromechanical system (MEMS) packaging, three-dimensional semiconductor IC packaging, hybrid packaging or other appropriate types of packaging. According to some embodiments of the present disclosure, the semiconductor package structure 100 includes a first substrate 110, a second substrate 120, a first semiconductor die 130, a second semiconductor die 140, a molding material 150 and a plurality of connectors 160.

[0182] According to some embodiments of the present disclosure, the first substrate 110 includes an interconnect structure electrically insulated by an electrically insulating material 108. According to some embodiments of the present disclosure, the interconnect structure of the first substrate 110 is composed of a plurality of wire layers and a plurality of conductive via layers. The wire layers and the conductive via layers are collectively referred to herein as metallization layers.

[0183] Each conductor layer includes one or more conductors, such as conductors 112, 114, 116, arranged parallel to each other in the same conductor layer, and each conductive via layer includes one or more conductive vias, such as conductive vias 113, 115, and 117, which are arranged in the same conductive via layer and are configured to electrically couple a conductor in the underlying conductor layer to another conductor in the overlying conductor layer. According to some embodiments of the present disclosure, the elements of the interconnect structure, namely the conductors 112, 114, 116 and the conductive vias 113, 115, 117, include metal materials, such as aluminum, copper, tungsten, titanium, titanium nitride, tantalum, tantalum nitride, alloys thereof, or other suitable conductive materials. According to some embodiments of the present disclosure, the conductors 112, 114, 116 and the conductive vias 113, 115, 117 include a single-layer structure or a multi-layer structure, wherein the multi-layer structure includes at least one of a diffusion barrier layer, a seed layer, and a filling layer.

[0184] According to some embodiments of the present disclosure, the conductive elements of the wire layer and the conductive via layer are electrically insulated by an electrically insulating material 108. The electrically insulating material 108 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, a high-k dielectric material, or a polymeric material, such as a polymer, epoxy, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), or the like. According to some embodiments of the present disclosure, the electrically insulating material 108 includes a multilayer structure.

[0185] According to some other embodiments of the present disclosure, the first substrate 110 is a printed circuit board (PCB) substrate. The illustrative PCB substrate may include a composite epoxy copper-clad laminate, an epoxy glass fiber fabric copper-clad laminate (FR-4), a paper phenolic copper-clad laminate (XPC / FR-1), or the like. For example, the first substrate 110 may include a copper-clad laminate structure (not shown separately), which includes a core layer, two prepreg layers (prepreg layer) located on both sides of the core layer, and one or more circuit layers on the outside of each prepreg layer to form a copper laminate. According to some embodiments of the present disclosure, the core layer includes an electrical insulating material, for example, the fabric uses glass fiber cloth, and the core material uses bleached kraft paper. According to some embodiments of the present disclosure, an epoxy resin material is deposited on the fabric and the core material to form a prepreg layer. One or more copper foil layers are deposited on the prepreg layer, and one or more insulating layers including an electrical insulating material or a dielectric material such as epoxy resin and copper foil layers are alternately arranged on the outside of the prepreg layer. By patterning each copper foil layer, the circuit layer is formed into a conductor layer. According to some embodiments of the present disclosure, a conductive via layer is formed by performing a through-hole drilling and electroplating operation on the drilled through hole to penetrate the insulating layer. The conductive via is formed to electrically connect the circuits in the upper copper foil layer and the lower copper foil layer.

[0186] According to some embodiments of the present disclosure, the second substrate 120 includes an interconnect structure electrically insulated by an electrically insulating material 118. According to some embodiments of the present disclosure, the interconnect structure of the second substrate 120 is composed of one or more metallization layers (e.g., a wire layer and a conductive via layer). Each wire layer includes one or more wires arranged parallel to each other in the same wire layer, such as wires 122 and 124, and each conductive via layer includes one or more conductive vias in the same conductive via layer, such as conductive via 125, and is configured to electrically couple a wire 122 in the underlying wire layer to another wire 124 in the overlying wire layer.

[0187] According to some embodiments of the present disclosure, the elements of the interconnect structure, such as the conductive lines 122, 124 and the conductive vias 125, include metal materials, such as aluminum, copper, tungsten, titanium, titanium nitride, tantalum, tantalum nitride, alloys thereof, or other suitable conductive materials. According to some embodiments of the present disclosure, the conductive lines 122, 124 and the conductive vias 125 include a single-layer structure or a multi-layer structure. According to some embodiments of the present disclosure, the conductive vias extend through the thickness of the second substrate 120, and are therefore also referred to herein as through-substrate vias (TSVs).

[0188] According to some embodiments of the present disclosure, the conductive components of the conductive line layer and the conductive via layer are electrically insulated by the electrically insulating material 118. The electrically insulating material 118 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, a high-k dielectric material, or a polymer material, such as a polymer, epoxy, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), polyetheretherketone (PEEK) or the like. According to some embodiments of the present disclosure, the electrically insulating material 108 includes a multilayer structure.

[0189] According to some embodiments of the present disclosure, at least one of the first substrate 110 and the second substrate 120 is a printed circuit board (PCB). Exemplary PCB substrates may include composite epoxy copper clad laminates, epoxy glass fiber fabric copper clad laminates (FR-4), paper phenolic copper clad laminates (XPC / FR-1), or the like. The second substrate 120 may include a copper clad laminate structure similar to the copper clad laminate structure of the first substrate 110 described above.

[0190] According to some embodiments of the present disclosure, each of the first semiconductor die 130 and the second semiconductor die 140 includes a memory die, a processor die, a network interface die, a MEMS die, or other suitable semiconductor die. In the depicted example, at least one of the first semiconductor die 130 and the second semiconductor die 140 is a memory die that includes one or more memory arrays and control circuits configured to control read / write access to the memory arrays.

[0191] According to some embodiments of the present disclosure, the first semiconductor die 130 includes a front side 130F facing a first side 110A of the first substrate 110 and a back side 130B facing the second side 120B of the second substrate 120. Similarly, according to some embodiments of the present disclosure, the second semiconductor die 140 includes a front side 140F facing the second side 110B of the first substrate 110 or the second substrate 120, and a back side 140B facing away from the first substrate 110 or the second substrate 120.

[0192] According to some embodiments of the present disclosure, the first substrate 110 includes a groove 110R formed on the first side 110A of the first substrate 110. The groove 110R may be disposed in the center of the first side 110A. As a result, the first side 110A includes a concave surface 121A, which is referred to herein as an upper surface 121A of the first side 110A. According to some embodiments of the present disclosure, the groove 110R includes a rectangular shape from a bottom view (see Figure 1B). According to some embodiments of the present disclosure, the surface 121A of the groove 110R includes a straight sidewall 110S and a substantially flat bottom (upper) surface 110T connected to the sidewall 110S. The height of the sidewall 110S or the depth of the groove 110R may be in a range between about 50 μm and about 400 μm. According to some embodiments of the present disclosure, the area ratio between the groove 110R and the entire first side 110A is in a range between about 20% and about 80%.

[0193] According to some embodiments of the present disclosure, the back side 130B of the first semiconductor grain 130 is higher than the bottom surface or lower surface 111A of the first side 110A of the first substrate 110. However, in some other embodiments, the back side 130B of the first semiconductor grain 130 is lower than (i.e., extends beyond) or substantially flush with the bottom surface 111A or lower surface 111A of the first side 110A of the first substrate 110. According to some embodiments of the present disclosure, the thickness 130T of the first semiconductor grain 130 is greater than, substantially equal to, or less than the depth or height 110M of the groove 110R. By disposing the first semiconductor grain 130 in the groove 110R of the first substrate 110, the thickness of the bonding structure of the first substrate 110 and the first semiconductor grain 130 is significantly reduced, and the transmission distance between the first substrate 110 and the first semiconductor grain 130 is reduced due to the groove 110R. The electrical performance of the semiconductor package structure 100 is thus improved.

[0194] According to some embodiments of the present disclosure, the first semiconductor die 130 includes one or more connectors 132 formed on the upper surface 121A of the first side 110A and electrically coupling the first semiconductor die 130 to the first side 110A of the first substrate 110, for example, the wire 216 of the first substrate 110. Similarly, according to some embodiments of the present disclosure, the second semiconductor die 140 includes one or more connectors 142 formed on the front side 140F and electrically coupling the second semiconductor die 140 to the second side 110B of the first substrate 110, for example, the wire 116 of the first substrate 110. The connector 132 or 142 may be a conductive pad used as a bonding pad and include a conductive material, such as copper, aluminum, tungsten, silver, gold, titanium, titanium nitride, tantalum, tantalum nitride, alloys thereof, and the like.

[0195] According to some embodiments of the present disclosure, the molding material 150 encapsulates the first substrate 110, the second substrate 120, the first semiconductor die 130, and the second semiconductor die 140. According to some embodiments of the present disclosure, the molding material 150 fills a space 150T between the first substrate 110 and the first semiconductor die 130. According to some embodiments of the present disclosure, the molding material 150 fills a space 150V between the first substrate 110 and the second semiconductor die 140. According to some embodiments of the present disclosure, the molding material 150 includes a dielectric material, that is, a polymer material, such as epoxy resin, PI, BCB, PBO, PEEK or the like.

[0196] According to some embodiments of the present disclosure, the connector 160 is formed on the first side 120A of the second substrate 120 . Figure 1B FIG. 1 is a bottom view schematically illustrating a semiconductor package structure 100 according to some embodiments of the present disclosure. Figure 1A and Figure 1B As shown, the connector 160 is formed to overlap with the lower surface 111A and the upper surface 121A of the first substrate 110, that is, from a bottom view or a top view, the connector 160 at least overlaps with the groove 110R. According to some embodiments of the present disclosure, the connector 160 forms an array, and the area occupied by it is larger than the area of ​​the groove 110R projected on the first substrate 110. By arranging the connector 160 on the first side 120A of the second substrate 120, the available bonding area of ​​the connector 160 is correspondingly increased, and the design specifications of the position configuration of the specific input / output terminals of the semiconductor package structure 100 can be easily achieved through the connector 160.

[0197] According to some embodiments of the present disclosure, the connector 160 is a solder material including a lead-based material, such as Sn, Pb, Ni, Au, Ag, Cu, Bi, a combination thereof, or a mixture of other conductive materials. According to some other embodiments, the connector 160 includes a lead-free material. According to some embodiments of the present disclosure, the connector 160 includes a spherical shape. However, the connector 160 may also be other shapes. According to some embodiments of the present disclosure, the connector 160 is configured to contact a plurality of bumps, such as a controlled collapse chip connection (C4) bump, a ball grid array bump, or a micro bump.

[0198] According to some embodiments of the present disclosure, the semiconductor package structure 100 further includes a bonding component 152 located between the first substrate 110 and the second substrate 120 and configured to bond the first substrate 110 to the second substrate 120. According to some embodiments of the present disclosure, the bonding component 152 bonds the wires 112 of the first substrate 110 to the corresponding wires 122 of the second substrate 120.

[0199] According to some embodiments of the present disclosure, the bonding component 152 includes a metal material, such as copper, tungsten or other suitable metals. According to some embodiments of the present disclosure, the bonding component 152 is a solder material including a lead-based material, such as Sn, Pb, Ni, Au, Ag, Cu, Bi, a combination thereof or a mixture of other conductive materials. According to some other embodiments, the bonding component 152 includes a lead-free material. According to some embodiments of the present disclosure, the bonding component 152 is configured to be a conductive bump, a conductive post, a conductive pillar or the like.

[0200] According to some embodiments of the present disclosure, the first semiconductor die 130 is bonded to the first substrate 110 by flip-chip bonding, wherein the front side 130F faces the first side 110A (or the upper surface 121A) of the first substrate 110. Such bonding can reduce the transmission length between the first substrate 110 and the first semiconductor die 130. However, since the entire back side 130B of the first semiconductor die 130 is covered by the molding material 150, the first semiconductor die 130 does not include any bonding pads on the back side 130B. As a result, the recessed area of ​​the first side 110A caused by the groove 110R cannot be used to form a connector between the first substrate 110 and the external circuit. The remaining available bonding area may be insufficient for the specifications of a specific input / output terminal configuration. However, the introduction of the second substrate 120 provides an additional bonding area on the first side 120A compared to the first side 110A of the first substrate 110. As such, the connector 160 formed on the first side 120A of the second substrate 120 can adapt to a specific input / output terminal configuration and can meet the bonding requirements of the semiconductor package structure 100 without affecting the performance of the semiconductor package structure 100 .

[0201] Figure 2A 1 is a cross-sectional schematic diagram illustrating a semiconductor package structure 101 of different embodiments of the present disclosure. The semiconductor package structure 101 is similar to the semiconductor package structure 100 in many aspects, so these similar features will not be repeated here. The difference between the semiconductor package structure 101 and the semiconductor package structure 100 is mainly that the first substrate 110 of the semiconductor package structure 101 is directly bonded to the second substrate 120 without the need for a bonding component 152. In other words, according to some embodiments, the wire 112 of the first substrate 110 is in physical contact with the wire 122 of the second substrate 120 by forming a metal bond between the wire 112 and the wire 122. According to some embodiments of the present disclosure, the wire 112 and the wire 122 include the same metal (e.g., copper) to facilitate the formation of the metal bond.

[0202] Figure 2B 1 is a cross-sectional schematic diagram illustrating a semiconductor package structure 102 according to different embodiments of the present disclosure. The semiconductor package structure 102 is similar to the semiconductor package structure 101 in many aspects, and therefore these similar features will not be repeated here. The difference between the semiconductor package structure 102 and the semiconductor package structure 101 is mainly that the second semiconductor die 140 of the semiconductor package structure 101 is bonded to the first substrate 110 via a wire (or conductive trace) 250 through wire bonding and a conductive pad 242 formed on the front side 140F of the second semiconductor die 140. In addition, the front side 140F of the second semiconductor die 140 faces away from the first substrate 110. According to some embodiments of the present disclosure, the wire 250 includes a conductive material, such as copper, aluminum, silver, gold, tungsten, an alloy thereof, or the like. According to some embodiments of the present disclosure, the wire 250 is bonded to the wire 116 of the first substrate 110. The wire 250 is also encapsulated by the molding material 150 together with the first substrate 110. Therefore, the integrity and robustness of the bonding performance of the wire bonding through the wire 250 can be maintained.

[0203] Figures 3A to 3G 1 is a cross-sectional schematic diagram illustrating various intermediate stages of a method 300 for preparing an interconnection structure of a first substrate 110 according to some embodiments of the present disclosure. Figures 3A to 3G Additional steps are provided before, during, and after the steps shown, and some of the steps described below may be replaced or eliminated in additional embodiments of the manufacturing method 300. The order of the steps may be interchanged.

[0204] Please refer to Figure 3A , forming, providing or receiving a substrate 302. According to some embodiments of the present disclosure, the substrate 302 is a carrier substrate. The substrate 302 may include a semiconductor material, such as bulk silicon or other suitable semiconductor materials. According to some other embodiments, the substrate 302 includes glass, ceramic or other substrate materials.

[0205] According to some embodiments of the present disclosure, a first dielectric layer 312 is deposited over the substrate 302. Figure 1A and Figure 3A, the first dielectric layer 312 may be the topmost sublayer of the first substrate 110. The first dielectric layer 312 may include silicon nitride, silicon oxide, silicon oxynitride, silicon carbide or other dielectric materials. The first dielectric layer 312 may be deposited on the substrate 302 by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating or other deposition methods. According to some embodiments of the present disclosure, a patterning operation is performed on the first dielectric layer 312. The patterning operation may include photolithography and etching operations. As an example, in the photolithography operation, a photoresist film is deposited over the first dielectric layer 312. An exposure operation is performed to transfer a circuit pattern to the photoresist film via a patterned mask or photomask. The exposed photoresist film is developed to remove unwanted portions of the photoresist film, thereby leaving the circuit pattern on the photoresist film. An etching operation is then performed, using the photoresist film as an etching mask to etch the first dielectric layer 312. According to some embodiments of the present disclosure, the etching operation may include dry etching, wet etching, a combination thereof, such as reactive ion etching (RIE), or the like. Through the etching operation, a plurality of openings are formed through the first dielectric layer 312 .

[0206] A deposition operation may be formed to fill a conductive material in the plurality of openings. The conductive material may include copper, aluminum, tungsten, silver, gold, titanium, titanium nitride, tantalum, tantalum nitride, alloys thereof, or the like. The deposition operation may include CVD, PVD, ALD, electroplating, or other suitable deposition methods. According to some embodiments of the present disclosure, a planarization operation is performed to remove excess material of the conductive material above the surface of the first dielectric layer 312. The planarization operation may include chemical mechanical polishing (CMP), mechanical polishing, or other suitable polishing operations. Thus, the wire 116 is formed in the first dielectric layer 312. Please refer to Figure 1A and Figure 3A The first dielectric layer 312 and the conductive lines 116 in the first dielectric layer 312 may be collectively referred to as a first metallization layer of the first substrate 110 .

[0207] According to some embodiments, a region R1 in a center of the first dielectric layer 312 is retained and is not used for depositing the conductive line 116. The region R1 does not have any conductive components of the interconnect structure, and the retained region R1 is removed to form Figure 1A , Figure 1B , Figure 2A and Figure 2B The groove 110R shown in FIG.

[0208] Please refer to Figure 3BA second dielectric layer 314 is formed over the first dielectric layer 312 and the conductive line 116. The second dielectric layer 314 is patterned, wherein a conductive via 113 is formed to pass through the second dielectric layer 314 and electrically couple to the conductive line 116. The material, structure, and formation method of the second dielectric layer 314 and the conductive via 113 are similar to the material, structure, and formation method of the first dielectric layer 312 and the conductive line 116. Please refer to Figure 1A and Figure 3B The second dielectric layer 314 and the conductive vias 113 in the second dielectric layer 314 may be collectively referred to as a second metallization layer of the first substrate 110 .

[0209] According to some embodiments, the space of region R1 in first dielectric layer 312 extends through second dielectric layer 314 and is not used for conductive via 113. Region R1 is not as Figure 1A , Figure 1B , Figure 2A and Figure 2B Any conductive components of the interconnect structure of the first substrate 110 are shown.

[0210] Please refer to Figure 3C A third dielectric layer 316 is formed over the second dielectric layer 314 and the conductive via 113. The third dielectric layer 316 is patterned, wherein the conductive line 114 is formed in the third dielectric layer 316 and electrically coupled to the conductive via 113. The materials, configurations, and formation methods of the third dielectric layer 316 and the conductive line 116 are similar to those of the first dielectric layer 312 and the conductive line 116. Please refer to Figure 1A and Figure 3C The third dielectric layer 316 and the conductive lines 114 in the third dielectric layer 316 may be collectively referred to as a third metallization layer of the first substrate 110 .

[0211] Please refer to Figure 3D A fourth dielectric layer 318 is formed over the third dielectric layer 316 and the conductive line 116. The fourth dielectric layer 318 is patterned, wherein a conductive via 117 is formed to pass through the fourth dielectric layer 318 and electrically couple to the conductive line 116.

[0212] According to some embodiments of the present disclosure, a plurality of vias are formed through the dielectric layers 318, 316, 314 to expose the conductive wires 116 in the first dielectric layer 312. One or more conductive materials are deposited in the plurality of vias to form a plurality of conductive vias 115. The conductive vias 115 may be formed to be exposed through the fourth dielectric layer 318 and configured to electrically couple the conductive wires 116 to the conductive components in the cover layer. The materials, configurations, and formation methods of the fourth dielectric layer 318 and the conductive vias 117, 115 are similar to the materials, configurations, and formation methods of the first dielectric layer 312 and the conductive wires 116. Please refer to Figure 1A and Figure 3DThe fourth dielectric layer 318 and the conductive vias 117 and 115 in the fourth dielectric layer 318 may be collectively referred to as a fourth metallization layer of the first substrate 110 .

[0213] Please refer to Figure 3E A fifth dielectric layer 320 is formed over the fourth dielectric layer 318 and the conductive via 117. The fifth dielectric layer 320 is patterned, wherein the conductive line 112 is formed in the fifth dielectric layer 320 and electrically coupled to the conductive vias 117 and 115. The materials, configurations, and formation methods of the fifth dielectric layer 320 and the conductive line 112 are similar to those of the first dielectric layer 312 and the conductive line 116. Please refer to Figure 1A and Figure 3E The fifth dielectric layer 320 and the conductive line 112 in the fifth dielectric layer 320 may be collectively referred to as a fifth metallization layer of the first substrate 110 .

[0214] According to some embodiments of the present disclosure, the dielectric layers 312, 314, 316, 318, and 329 constitute the main body of the first substrate 110, and the conductive lines 112, 114, 116 and the conductive vias 113, 117 are electrically interconnected to form an interconnection structure in the first substrate 110. The interconnection structure is configured to electrically couple the first semiconductor die 130 and the second semiconductor die 140 to the second substrate 120. Figure 1A , Figure 2A , Figure 2B as well as FIG. 3A to FIG. 3E Five metallization layers of the first substrate 110 are shown, but are shown for illustration purposes only. Other numbers of metallization layers of the first substrate 110 and other configurations of conductive lines and conductive vias are also within the contemplated scope of the present disclosure.

[0215] Subsequently, the first substrate 110 is turned over and placed on another substrate 304, as shown in FIG. Figure 3F According to some embodiments of the present disclosure, substrate 304 is a carrier substrate. Substrate 304 may include a semiconductor material, such as bulk silicon or other suitable semiconductor materials. According to some other embodiments, substrate 304 includes glass, ceramic or other substrate materials. According to some embodiments of the present disclosure, substrate 304 includes a material similar to the material of substrate 302.

[0216] The substrate 302 is removed from the first substrate 110. According to some embodiments, the substrate 302 is removed by an etching operation. According to some embodiments, a release film (not shown separately) is bonded between the substrate 302 and the first dielectric layer 312 of the first substrate 110. When the substrate 302 is removed from the first substrate 110, the release film is peeled off from the surface of the first dielectric layer 312 by heat or ultraviolet light, thereby removing the release film from the first substrate 110 together with the substrate 302.

[0217] According to some embodiments, an etching operation, such as dry etching, wet etching, RIE or the like, is performed to make the space of the groove 110R recessed from the first side 110A. The etching operation may be terminated at the conductive line 114, so that the conductive line 114 is exposed by the etching operation. Through the etching operation, the first side 110A of the first substrate 110 includes a stepped shape, and when inverted ( Figure 1A When viewed from a direction of the first side 110A, the first side 110A includes an upper surface 121A and a lower surface 111A. According to some embodiments, the sidewall 110S of the groove 110R may be vertical, inclined, or include a curved shape.

[0218] According to some embodiments of the present disclosure, the first substrate 110 including the groove 110R includes a horizontal portion 110H and a protruding portion 110P, wherein the protruding portion 110P protrudes from the surrounding area 110E of the horizontal portion 110H and defines the recess 110R. According to some embodiments of the present disclosure, the third dielectric layer 316, the fourth dielectric layer 318, and the fifth dielectric layer 320 together with the conductive lines 112, 114 and the conductive via 117 (which may also include a portion of the conductive via 115) form the horizontal portion 110H, while the first dielectric layer 312, the second dielectric layer 314 together with the conductive line 116 and the conductive via 113 (which may also include a portion of the conductive via 115) form the protruding portion 110P. According to some embodiments of the present embodiment, the depth of the groove 110R is substantially equal to the height of the protruding portion 110P.

[0219] Please refer to Figure 3G , the first substrate 110 is flipped again and placed on another substrate 306. According to some embodiments of the present disclosure, the substrate 306 is a carrier substrate. The substrate 306 may include a semiconductor material, such as bulk silicon or other suitable semiconductor materials. According to some other embodiments, the substrate 306 includes glass, ceramic or other substrate materials. According to some embodiments of the present disclosure, the substrate 306 includes a material that is similar to the material of the substrate 302 or 304.

[0220] According to some embodiments of the present disclosure, a plurality of conductive pads 142 are formed on the second side 110B of the first substrate 110. The conductive pads 142 are used as bonding pads for bonding the first substrate 110 to other semiconductor elements (e.g., the second semiconductor die 140). The conductive pads 142 may be bonded to the wires 112. The fabrication techniques of the conductive pads 142 may include CVD, PVD, ALD, electroplating, or other suitable deposition operations.

[0221] FIG. 4A to FIG. 4C 1 is a cross-sectional schematic diagram illustrating various intermediate stages of the method 400 for preparing the second substrate 120 in some embodiments of the present disclosure. It should be understood that FIG. 4A to FIG. 4CAdditional steps are provided before, during, and after the steps shown, and some of the steps described below may be replaced or eliminated in additional embodiments of the preparation method 400. The order of the steps may be interchanged.

[0222] Please refer to Figure 4A , providing or receiving a substrate 402. According to some embodiments of the present disclosure, the substrate 402 is a carrier substrate. The substrate 402 may include a semiconductor material, such as bulk silicon or other suitable semiconductor materials. According to some other embodiments, the substrate 402 includes glass, ceramic or other substrate materials.

[0223] According to some embodiments of the present disclosure, a substrate 401 is provided or received. According to some embodiments, the substrate 401 includes a semiconductor material, such as bulk silicon or other suitable semiconductor materials. According to some embodiments, the substrate 401 is a semiconductor wafer and has a circular or rectangular shape.

[0224] According to some embodiments of the present disclosure, a patterning operation is performed on substrate 401. The patterning operation may include photolithography and etching operations. As an example, in the photolithography operation, a photoresist film is deposited above substrate 401. An exposure operation is performed to transfer a circuit pattern to the photoresist film via a patterned mask or photomask. The exposed photoresist film is developed to remove unwanted portions of the photoresist film, thereby leaving the circuit pattern on the photoresist film. An etching operation is then performed, using the photoresist film as an etching mask to etch substrate 401.

[0225] According to some embodiments of the present disclosure, the etching operation may include dry etching, wet etching, a combination thereof, such as reactive ion etching (RIE) or similar operations. Via the etching operation, a plurality of through holes are formed through the substrate 401. A deposition operation may be formed to fill the plurality of through holes with a conductive material. The conductive material may include copper, aluminum, tungsten, silver, gold, titanium, titanium nitride, tantalum, tantalum nitride, an alloy thereof, or the like. The deposition operation may include CVD, PVD, ALD, electroplating or other suitable deposition methods. According to some embodiments of the present disclosure, a planarization operation is performed to remove excess material of the conductive material above the surface of the substrate 401. The planarization operation may include CMP, mechanical polishing or other suitable grinding operations. Therefore, the conductive via 125 is formed as TSVs through the substrate 401.

[0226] A plurality of conductive lines 124 are formed on the first side 120A of the second substrate 120 and electrically coupled to the conductive vias 125. An exemplary process for forming the conductive lines 124 may include deposition of a blanket conductive material on the first side 120A of the second substrate 120, followed by performing a patterning operation on the blanket conductive material. The patterning operation of the conductive lines 124 may be similar to the patterning operation of the first dielectric layer 312 discussed previously.

[0227] Subsequently, the second substrate 120 is turned over and placed on another substrate 404, as shown in FIG. Figure 4B According to some embodiments of the present disclosure, substrate 404 is a carrier substrate. Substrate 404 may include a semiconductor material, such as bulk silicon or other suitable semiconductor materials. According to some other embodiments, substrate 404 includes glass, ceramic or other substrate materials. According to some embodiments of the present disclosure, substrate 404 includes a material similar to the material of substrate 402.

[0228] The substrate 402 is removed from the second substrate 120. According to some embodiments, the substrate 402 is removed by an etching operation. According to some embodiments, a release film (not shown separately) is bonded between the substrate 402 and the second substrate 120. When the substrate 402 is removed from the first substrate 110, the release film is peeled off from the surface of the second substrate 120 by heat or ultraviolet light, thereby removing the release film from the second substrate 120 together with the substrate 402.

[0229] A plurality of conductive lines 122 are formed on the second side 120B of the second substrate 120 and are electrically coupled to the conductive vias 125. The material, construction, and forming method of the conductive lines 122 are similar to the material, construction, and forming method of the conductive lines 124. The conductive lines 122, 124, and the conductive vias 125 are electrically interconnected to form an interconnection structure of the second substrate 120. Figure 1A , Figure 2A , Figure 2B as well as FIG. 4A to FIG. 4C Only two conductive line layers of the second substrate 120 are shown, but they are shown for illustration purposes only. One or more dielectric layers, such as the dielectric layers 312, 314, 316, 318, 320 of the first substrate 110, and other configurations of conductive lines and conductive vias are also within the contemplated scope of the present disclosure, for example, conductive lines 112, 114, 116 and conductive vias 113, 117 can be incorporated into the second substrate 120 to create a multi-layer structure with multiple metallization layers in the second substrate 120.

[0230] Please refer to Figure 4C, a plurality of bonding components 152 are formed on the surface of the wire 122. The bonding components 152 can be deposited on the wire 122 by CVD, PVD, ALD, electroplating or other appropriate deposition methods. The manufacturing technology of the bonding components 152 can selectively include ball dropping, solder pasting, stencil printing or any other appropriate operation. According to some embodiments of the present disclosure, from a top view, the bonding components 152 do not overlap with the groove 110R.

[0231] FIG. 5A to FIG. 5E 1 is a cross-sectional schematic diagram illustrating various intermediate stages of the method 500 for preparing the second substrate 120 in some embodiments of the present disclosure. It should be understood that FIG. 5A to FIG. 5E Additional steps are provided before, during, and after the steps shown, and some of the steps described below may be replaced or eliminated in additional embodiments of the method 500. The order of the steps may be interchanged.

[0232] Please refer to Figure 5A , a laminate structure of the second substrate 120 is provided or accommodated on the substrate 402. According to some embodiments of the present disclosure, the laminate structure includes a copper-clad laminate structure and has a composite core layer 501 and two copper foil layers 410, 420 located on both sides of the composite core layer 501. According to some embodiments of the present disclosure, the composite core layer 501 includes a core layer and two prepreg layers (prepreg layer) located on both sides of the core layer. Copper foil layers 410, 420 are formed on the outside of each prepreg layer to form a copper laminate. According to some embodiments of the present disclosure, the core layer includes an electrically insulating material, for example, the fabric is glass fiber cloth, and the core material is bleached kraft paper. An epoxy resin material is deposited on the fabric and the core material to form a prepreg layer. According to some embodiments of the present disclosure, the copper foil layers 410, 420 are replaced by other metals, such as aluminum, tungsten or the like.

[0233] Please refer to Figure 5B , a patterning operation is performed on the copper foil layer 410 to form a plurality of conductive lines 124. The patterning operation may include photolithography and etching operations. According to some embodiments of the present disclosure, the etching operation includes dry etching, wet etching, RIE or the like.

[0234] Please refer to Figure 5C, flip the second substrate 120 and place it on the substrate 404. According to some embodiments of the present disclosure, the substrate 404 is a carrier substrate. Remove the substrate 402 from the second substrate 120. According to some embodiments of the present disclosure, a patterning operation is performed on the copper foil layer 420 to form a plurality of conductive lines 122. The patterning operation may include photolithography and etching operations. According to some embodiments of the present disclosure, the etching operation includes dry etching, wet etching, RIE or the like.

[0235] Figure 5D The formation of a conductive via 125 through the composite core layer 501 is depicted. According to some embodiments of the present disclosure, a drilling operation is performed to form a plurality of through holes through the composite core layer 501 and the copper foil layers 410, 420. A deposition operation may be performed to deposit a conductive material on each sidewall of the plurality of through holes. The conductive material may include copper, aluminum, tungsten, silver, gold, titanium, titanium nitride, tantalum, tantalum nitride, alloys thereof, or the like. The deposition operation may include CVD, PVD, ALD, electroplating, or other suitable deposition methods. Thus, a conductive via 125 is formed to pass through the composite core layer 501 and serve as a TSV to electrically couple the wire 122 to the corresponding wire 124.

[0236] Please refer to Figure 5E , a plurality of bonding components 152 are formed on the surface of the wire 122. The bonding components 152 may be deposited on the wire 122 by CVD, PVD, ALD, electroplating, ball drop, solder on, template printing or other appropriate deposition methods. According to some embodiments of the present disclosure, from a top view, the bonding components 152 do not overlap with the groove 110R.

[0237] FIG. 6A to FIG. 6D 1 is a cross-sectional schematic diagram illustrating various intermediate stages of a method 600 for preparing a first semiconductor crystal grain 130 or a second semiconductor crystal grain 140 in some embodiments of the present disclosure. FIG. 6A to FIG. 6D Additional steps are provided before, during, and after the steps shown, and some of the steps described below may be replaced or eliminated in additional embodiments of the method 600. The order of the steps may be interchanged.

[0238] Please refer to Fig. 6A , a substrate 610 is provided or formed on a substrate 602. According to some embodiments of the present disclosure, the substrate 602 is a carrier substrate. The substrate 602 may include a semiconductor material, such as bulk silicon or other suitable semiconductor materials. In some other embodiments, the substrate 602 includes glass, ceramic or other substrate materials.

[0239] According to some embodiments of the present disclosure, the substrate 610 includes a semiconductor material, such as bulk silicon. In some embodiments, the substrate 610 includes other semiconductor materials, such as silicon germanium, silicon carbide, gallium arsenide, or the like. According to some embodiments of the present disclosure, the substrate 610 is a P-type semiconductor substrate (acceptor type). According to some other embodiments of the present disclosure, an N-type semiconductor substrate (donor type) 610 may be used. Alternatively, the substrate 610 includes other elemental semiconductors, such as germanium; a compound semiconductor including gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, or GaInAsP; or a combination thereof. According to some embodiments of the present disclosure, the substrate 610 includes a semiconductor-on-insulator (SOI) substrate. According to some embodiments of the present disclosure, the substrate 610 includes a doped epitaxial layer, a gradient semiconductor layer, and / or a semiconductor layer covering another semiconductor layer of a different type, such as a silicon layer on a silicon germanium layer.

[0240] One or more semiconductor elements 620 are formed on an upper surface of the substrate 610. For example, one or more active elements, such as transistors, are formed on the upper surface of the substrate 610. According to some embodiments of the present disclosure, the transistor includes a field effect transistor (FET), which is divided into a planar FET, a fin FET (FinFET), a gate-all-around (GAA) FET, a nanosheet FET, a nanowire FET, or the like. The semiconductor element 620 may also include passive elements, such as diodes, resistors, capacitors, inductors, fuses, and the like. According to some embodiments, each semiconductor element 620 includes one or more input and output terminals for receiving and providing power or signals. According to some embodiments of the present disclosure, each semiconductor element 620 includes a memory cell array. Each semiconductor element 620 may also include a memory control circuit.

[0241] Please refer to Figure 6B According to some embodiments of the present disclosure, an interconnection layer 630 is formed above the substrate 610. The interconnection layer 630 may include a plurality of metallization layers, each of which includes a wire layer or a conductive via layer. Each wire layer includes a plurality of parallel wires, and each conductive via layer includes a plurality of conductive vias. The wire layer may be alternately arranged with the conductive via layer. The conductive vias in each conductive via layer are configured to electrically connect one wire in the overlying conductive layer to another wire in the underlying conductive layer. As a result, an interconnection structure is formed in the interconnection layer 630 to interconnect the input / output terminals of the semiconductor element 620 in the substrate 610 or to interconnect the semiconductor element 620 to an overlying circuit or element.

[0242] According to some embodiments of the present disclosure, the interconnect layer 630 includes one or more conductive pads 640 located at the topmost sublayer of the interconnect layer 630. The conductive pads 640 can be formed as conductive lines in a manner similar to forming conductive lines in a metallization layer. The conductive pads 640 can be exposed through the front side 130F, 140F of the substrate 610 and used as bonding pads for the first or second semiconductor dies 130, 140 formed subsequently.

[0243] According to some embodiments of the present disclosure, the manufacturing technology of the semiconductor element 620 or the interconnection layer 630 includes a series of semiconductor processes, which may include, for example, at least one of a photolithography operation, an exposure operation, an etching operation, an ion implantation, an annealing operation, an alignment operation, a cleaning operation, a deposition operation, a bonding operation, a segmentation operation, a testing operation, and the like. Through a series of semiconductor processes, the semiconductor element 620 may include one or more conductive layers, dielectric layers, and semiconductor layers to provide a specific designed function.

[0244] Please refer to Figure 6C , flip the substrate 610 and place it on the substrate 604. According to some embodiments of the present disclosure, the substrate 604 is a carrier substrate. The substrate 604 may include a semiconductor material, such as bulk silicon or other suitable semiconductor materials. According to some other embodiments, the substrate 604 includes glass, ceramic or other substrate materials.

[0245] The substrate 602 is removed from the substrate 610. According to some embodiments, the substrate 602 is removed by an etching operation or by peeling off a release film (not separately shown) disposed between the substrate 602 and the substrate 610.

[0246] According to some embodiments of the present disclosure, the substrate 610 is thinned from the back side 130B / 140B of the substrate 610. The thinning operation may be performed by CMP, mechanical polishing, laser etching, or other thinning operations.

[0247] Please refer to Fig.6D , a singulation operation is performed to separate the semiconductor elements 620 on the substrate 610 into individual semiconductor dies 130, 140. The singulation operation may be performed by a cutting tool 650 such as a diamond blade, a laser blade, or the like. The singulation operation may be performed to cut through the scribe lines between the plurality of semiconductor elements 620.

[0248] FIG. 7A to FIG. 7H 1 is a cross-sectional view illustrating various intermediate stages of a method 700 for preparing a semiconductor package structure 100 according to some embodiments of the present disclosure. 7A to 7H Additional steps are provided before, during, and after the steps shown, and some of the steps described below may be replaced or eliminated in additional embodiments of the method 700. The order of the steps may be interchanged.

[0249] Please refer to Fig. 7A , the manufactured second semiconductor die 140 and the first substrate 110 are transferred to a bonding tool (not shown separately). According to some embodiments of the present disclosure, the second semiconductor die 140 is moved to a position above the first substrate 110. An alignment operation is performed to align the second semiconductor die 140 with the first substrate 110.

[0250] Please refer to Figure 7B , the second semiconductor die 140 moves toward the first substrate 110 (e.g., in a downward direction) and is bonded to the first substrate 110. The bonding pad (not shown separately) of the second semiconductor die 140 is aligned with the conductive pad 142 of the first substrate 110. The second semiconductor die 140 is bonded to the bonding pad 142 of the first substrate 110. According to some embodiments of the present disclosure, the conductive pad 142 is not initially formed on the first substrate, but is formed on the front side 140F of the second semiconductor die 140 and bonded to the first substrate 110. According to some embodiments of the present disclosure, please refer to Figure 3F and Figure 7B The second semiconductor die 140 is bonded to the second side 110B of the horizontal portion 110H. According to some embodiments of the present disclosure, the bonding operation may include flip-chip bonding, thermal bonding, thermocompression bonding, ultrasonic bonding, hybrid bonding, or the like.

[0251] Please refer to Figure 7C , the bonded semiconductor package structure 100 and the manufactured first semiconductor die 130 are transferred to a bonding tool (not shown separately). The bonded semiconductor package structure 100 is turned over. According to some embodiments of the present disclosure, the first semiconductor die 130 is aligned with the groove 110R of the first substrate 110. Then, the first semiconductor die 130 is bonded to the first substrate 110 via the conductive pad 132 in the groove 110R. According to some embodiments of the present disclosure, please refer to Figure 3F and Figure 7C , the first semiconductor grain 130 is bonded to the first side 110A of the horizontal portion 110H. The first semiconductor grain 130 may be laterally surrounded by the protruding portion 110P. According to some embodiments of the present disclosure, the thickness 130T of the first semiconductor grain 130 is greater than, substantially equal to, or less than the height 110M of the protruding portion 110P.

[0252] FIG. 7D to FIG. 7E FIG. 1 shows the bonding between the second substrate 120 and the semiconductor package structure 100 . Fig.7D, the semiconductor package structure 100 and the second substrate 120 are transferred to a bonding tool (not shown separately). According to some embodiments of the present disclosure, the semiconductor package structure 100 is moved to a position above the second substrate 120. An alignment operation is performed to align the semiconductor package structure 100 with the second substrate 120. The wires 112 of the first substrate 110 are aligned with the bonding components 152 of the second substrate 120.

[0253] Please refer to Fig. 7E , the semiconductor package structure 100 moves toward the second substrate 120 (eg, in a downward direction) and is bonded to the second substrate 120. The wire 112 is bonded to the bonding component 152 of the second substrate 120. According to some embodiments of the present disclosure, please refer to Figure 3F and Fig. 7E , the second substrate 120 is bonded to the protruding portion 110P of the first substrate 110. The first semiconductor grain 130 is surrounded by the first substrate 110 and the second substrate 120. According to some embodiments of the present disclosure, the bonding operation may include flip chip bonding, thermal bonding, thermocompression bonding, ultrasonic bonding, hybrid bonding, or the like.

[0254] Please refer to Figure 7F The molding material 150 is used to encapsulate the first substrate 110, the second substrate 120, the first semiconductor die 130, the second semiconductor die 140, the conductive pads 132, 142 and the bonding component 152. The molding material may include epoxy resin, PI, BCB, PBO, PEEK or the like. The molding material 150 may fill the space 150T of the groove 110R between the first substrate 110 and the first semiconductor die 130 and the space 150V between the first substrate 110 and the second substrate 120. According to some embodiments of the present disclosure, the molding material 150 encapsulates or laterally surrounds the bonding component 152 and the conductive pads 132, 142. The packaging operation may include injection molding or other suitable molding processes.

[0255] Please refer to Figure 7G , removing or thinning excess portions of the molding material 150. The thinning operation may reduce the thickness of the molding material 150. The thinning operation may keep the back side 140B of the second semiconductor grain 140 covered by the molding material 150. The thinning operation may include CMP, mechanical polishing, laser etching, or the like.

[0256] Please refer to Figure 7H, the connector 160 is formed on the first side 120A of the second substrate 120. According to some embodiments of the present disclosure, the connector 160 is formed on the corresponding wire 124. The connector 160 may include a solder material. According to some embodiments of the present disclosure, the solder material includes Sn, Pb, Ni, Au, Ag, Cu, Bi, a combination thereof, or a mixture of other conductive materials. According to some other embodiments, the solder material includes a lead-based material, such as SnAg, SnPb, SnAgCu or the like. According to some other embodiments of the present disclosure, the solder material is a lead-free material. According to some embodiments of the present disclosure, the manufacturing technology of the connector 160 includes ball drop, soldering, template printing or any other appropriate operation. In some embodiments, the connector 160 is reflowed after deposition. As previously discussed, the connector 160 can form an array that occupies an area overlapping the groove 110R from a bottom view or a top view. Therefore, the bonding area of ​​the connector 160 is increased compared to the existing bonding structure without the second substrate 120. The bonding performance of the semiconductor package structure 100 is also improved accordingly.

[0257] FIG. 8A to FIG. 8C 1 is a cross-sectional view illustrating various intermediate stages of a method 800 for preparing a semiconductor package structure 101 according to some embodiments of the present disclosure. FIG. 8A to FIG. 8C Additional steps are provided before, during, and after the steps shown, and some of the steps described below may be replaced or eliminated in additional embodiments of the manufacturing method 800. The order of the steps may be interchanged. The structure and method of forming the semiconductor package structure 101 are similar to the structure and method of forming the semiconductor package structure 100, and therefore, similar features are not described again in detail.

[0258] Please refer to Fig. 8A , the first substrate 110 bonded with the first semiconductor die 130 and the second semiconductor die 140 is transferred to a bonding tool (not shown separately). In addition, the second substrate 120 is transferred to the bonding tool. Fig.7D and Fig. 8A , Fig. 8A The second substrate 120 is shown without the bonding assembly 152 .

[0259] Please refer to Figure 8B , without the bonding component 152, the bonded first substrate 110 is directly bonded to the second substrate 120. According to some embodiments of the present disclosure, the wire 112 of the first substrate 110 is bonded to the wire 122 of the second substrate 120, wherein the metal atoms of the wire 112 and 122 form a metal bond, thereby bonding the first substrate 110 to the second substrate 120. According to some embodiments of the present disclosure, Figure 8B The bonding operation shown includes thermocompression bonding.

[0260] Please refer to Figure 8C , using molding material 150 similar to Figure 7F The first substrate 110, the second substrate 120, the first semiconductor die 130 and the second semiconductor die 140 are packaged in the manner shown in FIG. In addition, the thinning molding material 150 is formed, and the connector 160 is formed in a manner similar to Figure 7G and Figure 7H The process shown is formed on the second substrate 120 .

[0261] FIG. 9A to FIG. 9E 1 is a cross-sectional view illustrating various intermediate stages of a method 900 for preparing a semiconductor package structure 102 according to some embodiments of the present disclosure. 9A to 9E Additional steps are provided before, during, and after the steps shown, and some of the steps described below may be replaced or eliminated in additional embodiments of the manufacturing method 900. The order of the steps may be interchanged. The structure and method of forming the semiconductor package structure 102 are similar to the structure and method of forming the semiconductor package structure 101, and therefore, similar features are not described again herein.

[0262] Please refer to Fig.9A , the first substrate 110 bonded with the first semiconductor die 130 and the second semiconductor die 140 is transferred to a bonding tool. In addition, the second substrate 120 is transferred to the bonding tool. Fig. 8A and Fig.9A , set as Fig.9A The second semiconductor die 140 is shown with its back side 140B facing the first substrate 110 and its front side 140F facing away from the first substrate 110. According to some embodiments of the present disclosure, the second semiconductor die 140 includes a conductive pad 242 formed on the front side 140F and used as a bonding pad. According to some embodiments of the present disclosure, the second semiconductor die 140 does not include any bonding pads on the back side 140B of the second semiconductor die 140. The entire back side 140B of the second semiconductor die 140 may include bulk silicon.

[0263] Please refer to Fig. 9B , the second semiconductor die 140 moves toward the first substrate 110 (eg, in a downward direction) and is bonded to the first substrate 110. The bonding pad 242 of the second semiconductor die 140 remains facing away from the first substrate 110. The back side 140B of the second semiconductor die 140 is electrically insulated from the first substrate 110.

[0264] Please refer to Fig. 9C, the semiconductor package structure 102 and the manufactured first semiconductor die 130 are transferred to a bonding tool (not shown separately). The semiconductor package structure 102 is flipped over. According to some embodiments of the present disclosure, an alignment operation is performed to align the first semiconductor die 130 with the groove 110R of the first substrate 110. Then, the first semiconductor die 130 is bonded to the first substrate 110 via the conductive pad 132 in the groove 110R.

[0265] Fig.9D The bonding of the second substrate 120 to the semiconductor package structure 102 is depicted. The semiconductor package structure 102 and the second substrate 120 are transferred to a bonding tool (not shown separately). According to some embodiments of the present disclosure, the semiconductor package structure 102 is moved to a position above the second substrate 120. An alignment operation is performed to align the semiconductor package structure 102 with the second substrate 120. Subsequently, the semiconductor package structure 102 is moved toward (e.g., in a downward direction) the second substrate 120 and bonded to the second substrate 120. The wire 112 of the first substrate 110 is aligned with the wire 122 of the second substrate 120 (or with the bonding component 152 if there is a bonding component 152). The wire 112 is bonded to the wire 122 of the second substrate 120 (or the bonding component 152 if there is a bonding component 152). According to some embodiments of the present disclosure, the bonding operation may include flip chip bonding, thermal bonding, thermocompression bonding, ultrasonic bonding, hybrid bonding, or the like.

[0266] Wire bonding is performed to electrically couple the second semiconductor die 140 to the first substrate 110 via the wires 116, 250, and the conductive pads 242. Both ends of each wire 250 are bonded to the wires 116 and the conductive pads 242 via a ball bonding operation, a wedge bonding operation, or the like.

[0267] Please refer to Fig.9E , the molding material 150 is used to encapsulate the first substrate 110, the second substrate 120, the first semiconductor die 130 and the second semiconductor die 140. The molding material 150 may include epoxy resin, PI, BCB, PBO, PEEK or the like. The molding material 150 may fill the space 150T of the groove 110R between the first substrate 110 and the first semiconductor die 130 and the space 150S between the first substrate 110 and the second substrate 120. According to some embodiments of the present disclosure, the molding material 150 encapsulates or laterally surrounds the bonding component 152 and the conductive pads 132, 242. The packaging operation may include injection molding or other suitable molding processes.

[0268] According to some embodiments of the present disclosure, excess portions of the molding material 150 are removed or thinned. The thinning operation may reduce the thickness of the molding material 150. The thinning operation may include CMP, mechanical polishing, laser etching, or the like.

[0269] According to some embodiments of the present disclosure, the connector 160 is formed on the first side 120A of the second substrate 120. According to some embodiments of the present disclosure, the connector 160 is similar to the reference Figure 7H The described method is formed on the corresponding conductive line 124.

[0270] Fig.10 FIG. 1 is a flow chart illustrating a method 1000 for preparing a semiconductor package structure according to some embodiments of the present disclosure. It should be understood that Fig.10 Additional steps are provided before, during, and after the steps shown, and some of the steps described below may be replaced or eliminated in additional embodiments of the preparation method S1000. The order of the steps may be interchanged. The semiconductor package structure may be similar to the semiconductor package structures 100, 101, or 102.

[0271] In step S1002 , a first substrate (eg, substrate 110 ) is provided, which includes a first side (eg, first side 110A) and a second side (eg, second side 110B) opposite to the first side.

[0272] In step S1004 , a groove (eg, groove 110R) is etched on the first side of the first substrate.

[0273] In step S1006 , a first semiconductor die (eg, first semiconductor die 130 ) is disposed in the groove, and the first semiconductor die is bonded to the first side of the first substrate.

[0274] In step S1008, a second semiconductor die (eg, second semiconductor die 140) is bonded to the second side of the first substrate. The order of steps S1006 and S1008 can be interchanged.

[0275] In step S1010, a second substrate (e.g., second substrate 120) is bonded to the first side of the first substrate. According to some embodiments, the second substrate includes a first side (e.g., first side 120B) and a second side (e.g., second side 120A) opposite to the first side of the second substrate. The first side of the second substrate is bonded to the first side of the first substrate.

[0276] In step S1012 , the first substrate, the second substrate, the first semiconductor die, and the second semiconductor die are encapsulated by a molding material (eg, molding material 150 ).

[0277] In step S1014 , a plurality of connectors are formed on the second side of the second substrate opposite to the first side.

[0278] Fig.11A 1 is a schematic cross-sectional view illustrating a semiconductor package structure 103 according to different embodiments of the present disclosure. Fig. 11B is a close-up cross-sectional schematic diagram illustrating some embodiments of the present disclosure. Fig. 11B The dashed area A is shown. The semiconductor package structure 103 is similar to the semiconductor package structure 100 in many aspects, so these similar features will not be repeated here. The main differences are described as follows.

[0279] Please refer to Fig.11A and Fig. 11B , the conductive via 125 may include a filling layer FL, a seed layer SL, an adhesive layer AL, a barrier layer BL and two isolation layers IL.

[0280] Please refer to Fig. 11B , the two isolation layers IL may be conformally formed on the two side walls of the through hole opening VO. According to some embodiments of the present disclosure, for example, the two isolation layers IL may include silicon oxide, silicon nitride, silicon oxynitride or tetra-ethyl ortho-silicate. The two isolation layers IL may have a thickness between about 50 nm and about 200 nm. Alternatively, in some embodiments, for example, the two isolation layers IL may include parylene, epoxy resin, poly(p-xylene). The two isolation layers IL may have a thickness between about 1 μm and about 5 μm. The two isolation layers IL may ensure that the filling layer FL is electrically isolated in the second substrate 120.

[0281] According to some embodiments of the present disclosure, the barrier layer BL may be conformally formed on the isolation layer IL and on the lower surface of the through hole opening VO. The barrier layer BL may have a U-shaped cross-sectional profile. For example, the barrier layer BL may include tantalum, tantalum nitride, titanium, titanium nitride, rhenium, nickel boride, or a tantalum nitride / tantalum double layer. The barrier layer BL may inhibit the conductive material of the filling layer FL from diffusing into the isolation layer IL. The manufacturing technology of the barrier layer BL may include a deposition process, such as physical vapor deposition, atomic layer deposition, chemical vapor deposition, or sputtering.

[0282] According to some embodiments of the present disclosure, the adhesion layer AL may be conformally formed on the barrier layer BL and may have a U-shaped cross-sectional profile. For example, the adhesion layer AL may include titanium, tantalum, titanium tungsten, or manganese nitride. The adhesion layer AL may improve the adhesion between the seed layer SL and the barrier layer BL. The adhesion layer AL may have a thickness between about 5 nm and about 50 nm. The manufacturing technology of the adhesion layer AL may include a deposition process, such as physical vapor deposition, atomic layer deposition, chemical vapor deposition, or sputtering.

[0283] According to some embodiments of the present disclosure, the seed layer SL may be conformally formed on the adhesion layer AL and may have a U-shaped cross-sectional profile. The seed layer SL may have a thickness between about 10 nm and about 40 nm. For example, the seed layer SL may include copper or ruthenium. The manufacturing technology of the seed layer SL may include a deposition process such as physical vapor deposition, atomic layer deposition, chemical vapor deposition or sputtering. The seed layer SL may reduce the resistivity of the through-hole opening VO during the formation of the filling layer FL by an electroplating process.

[0284] According to some embodiments of the present disclosure, a filling layer FL may be formed on the seed layer SL and completely fill the via opening VO. The filling layer FL may be, for example, copper. The manufacturing technology of the filling layer FL may include an electroplating process.

[0285] Fig.12 1 is a cross-sectional view illustrating a semiconductor package structure 104 according to various embodiments of the present disclosure. The semiconductor package structure 104 is similar to the semiconductor package structure 100 in many aspects, and thus these similar features will not be repeated here. The main differences are described as follows.

[0286] Please refer to Fig.12 , the first passivation layer 109 may be disposed on the second substrate 120. According to some embodiments of the present disclosure, the first passivation layer 109 may be a single-layer structure or a multi-layer structure. In some embodiments, the first passivation layer 109 may include polybenzoxazole, polyimide, benzocyclobutene, solder mask, the like, or a combination thereof. In some other embodiments, the first passivation layer 109 may be a dielectric layer. The dielectric layer may include a nitride such as silicon nitride, an oxide such as silicon oxide, such as silicon oxynitride, silicon oxynitride, phosphosilicate glass, borosilicate glass, an oxide of boron-doped phosphosilicate glass, or a combination thereof.

[0287] Please refer to Fig.12, a first opening OP1 may be set along the first passivation layer 109 to expose a portion of the pad layer 201. According to some embodiments of the present disclosure, the sidewalls of the first opening OP1 may be substantially vertical. According to some embodiments of the present disclosure, the sidewalls of the first opening OP1 may be tapered. It should be understood that in the description of the present disclosure, if there is a vertical plane and the root mean square roughness of the surface deviates from the surface by no more than three times the root mean square roughness of the surface, then the surface is "substantially vertical".

[0288] Please refer to Fig.12 , the first barrier layer 203 may be disposed on the second substrate 120 and in the first opening OP1 of the first passivation layer 109. According to some embodiments of the present disclosure, the first barrier layer 203 may have a thickness T1 that is less than a thickness T2 of the first passivation layer 109. The first barrier layer 203 may include aluminum fluoride. Due to the saturated bonding characteristics of aluminum fluoride, it is stable and can prevent the conductive via 125 from being corroded by various semiconductor processes, especially processes containing fluoride ions. In some embodiments, the first barrier layer 203 may also include zinc oxide, which may increase the electronic properties of the first barrier layer 203. In some embodiments, the content of zinc oxide may be greater than the content of aluminum fluoride.

[0289] Please refer to Fig.12 , the first connector 205 may be disposed on the first barrier layer 203. According to some embodiments of the present disclosure, the upper portion of the first connector 205 may extend to the first passivation layer 109, completely fill the first opening OP1, and be disposed on the first barrier layer 203. The lower portion of the first connector 205 may protrude from a plane coplanar with the upper surface of the first passivation layer 109, and be disposed on the upper portion of the first connector 205. According to some embodiments of the present disclosure, the first connector 205 may include a conductive material having a low resistivity, such as tin, lead, silver, copper, nickel, bismuth, or an alloy thereof.

[0290] According to some embodiments of the present disclosure, the first connector 205 may be a solder joint. The solder joint may include a material such as tin, or other suitable materials such as silver or copper. In an embodiment where the solder joint is a tin solder joint, a tin layer having a thickness of about 10 μm to about 100 μm may be formed by evaporation, electroplating, printing, solder transfer, or ball planting. Once the tin layer has been formed and filled on the first opening OP1 and the first passivation layer 109, a reflow process may be performed to shape the solder joint into a desired shape.

[0291] Fig.13 1 is a cross-sectional view illustrating a semiconductor package structure 105 according to various embodiments of the present disclosure. The semiconductor package structure 105 is similar to the semiconductor package structure 100 in many aspects, and thus these similar features will not be repeated here. The main differences are described as follows.

[0292] Please refer to Fig.13 The semiconductor package structure 105 includes a plurality of conductive vias 125 (eg Fig.11A ), a first barrier layer 203, a first connector 205, and a first passivation layer 109 (as shown in Fig.12 Therefore, the semiconductor package structure 105 may have the above-mentioned related characteristics and advantages.

[0293] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements can be made without departing from the spirit and scope of the present disclosure defined by the scope of the claims. For example, many of the above processes can be implemented in different ways, and other processes or combinations thereof can be used to replace many of the above processes.

[0294] Furthermore, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, material compositions, means, methods, and steps described in the specification. A person skilled in the art can understand from the disclosure of the present disclosure that existing or future developed processes, machines, manufactures, material compositions, means, methods, or steps that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. Accordingly, such processes, machines, manufactures, material compositions, means, methods, or steps are included in the scope of the patent application of the present application.

Claims

1. A semiconductor structure comprising: A first substrate having a first side and a second side opposite to the first side, wherein the first side includes a groove recessed from the first side; a first semiconductor die disposed in the groove and bonded to the first side of the first substrate; a second semiconductor die bonded to the second side of the first substrate; a second substrate electrically bonded to the first side of the first substrate; a plurality of conductive vias disposed along and extending through the second substrate; as well as A plurality of conductive lines are arranged on the second substrate.

2. The semiconductor structure of claim 1, wherein the conductive via comprises: a filling layer disposed along the second substrate and extending through the second substrate; as well as Two isolation layers are arranged on both sides of the filling layer, wherein the two isolation layers include silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane, or parylene, epoxy resin, and polyparaxylene. 3 . The semiconductor structure of claim 2 , wherein the conductive via comprises a seed layer located between the second isolation layers and the filling layer and between the filling layer and a corresponding conductive line on the second substrate.

4. The semiconductor structure of claim 3 , wherein the conductive via comprises an adhesion layer between the seed layer and the two isolation layers and between the seed layer and the corresponding conductive line on the second substrate, wherein the adhesion layer comprises titanium, tantalum, titanium tungsten or manganese nitride.

5. The semiconductor structure of claim 4 , wherein the conductive via comprises a barrier layer between the adhesion layer and the two isolation layers and between the adhesion layer and the corresponding conductive line on the second substrate, wherein the barrier layer comprises tantalum, tantalum nitride, titanium, titanium nitride, rhenium, nickel boride or a tantalum nitride / tantalum bilayer. 6 . The semiconductor structure as claimed in claim 5 , wherein the two isolation layers have a thickness ranging from 50 nm to 200 nm. 7 . The semiconductor structure as claimed in claim 5 , wherein the two isolation layers have a thickness ranging from 1 μm to 5 μm. The semiconductor structure of claim 7 , wherein the seed layer comprises copper or ruthenium.

9. The semiconductor structure as claimed in claim 8, wherein the filling layer is copper. 10 . The semiconductor structure as claimed in claim 1 , further comprising a molding material encapsulating the first substrate, the second substrate, the first semiconductor die and the second semiconductor die. 11 . The semiconductor structure as claimed in claim 10 , wherein the molding material comprises epoxy resin, polyimide, benzocyclobutene, polybenzoxazole or polyetheretherketone.

12. The semiconductor structure of claim 11, further comprising a plurality of connectors, wherein each connector is located on a corresponding conductive line.

13. The semiconductor structure of claim 12, wherein the plurality of connectors comprises Sn, Pb, Ni, Au, Ag, Cu, Bi or a combination thereof.

14. A semiconductor structure comprising: a first substrate including a horizontal portion and a protruding portion extending on a peripheral area of ​​the horizontal portion; a first semiconductor die bonded to a first side of the horizontal portion; a second semiconductor die bonded to a second side of the horizontal portion and laterally surrounded by the protruding portion; a second substrate electrically bonded to the protruding portion of the first substrate; a passivation layer, located on the second substrate; as well as A barrier layer is located on the second substrate and in the passivation layer. 15 . The semiconductor structure of claim 14 , wherein the passivation layer defines a plurality of openings disposed along the passivation layer to expose a portion of the second substrate. The semiconductor structure of claim 15 , wherein the barrier layer is located in the plurality of openings. The semiconductor structure as claimed in claim 16 , wherein a thickness of the passivation layer is greater than a thickness of the barrier layer.

18. The semiconductor structure of claim 17, further comprising a plurality of connectors disposed on the barrier layer. 19 . The semiconductor structure of claim 18 , wherein a first portion of the connector extends to the passivation layer, completely fills the plurality of openings, and is disposed on the barrier layer. 20 . The semiconductor structure of claim 18 , wherein a second portion of the connector protrudes from a plane coplanar with an upper surface of the passivation layer and is disposed on the first portion of the connector.

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