Semiconductor element with polymer liner and manufacturing method thereof

Abstract

The invention provides a semiconductor element and a preparation method thereof. The semiconductor device includes a first substrate including a front surface and a back surface; a first passivation layer over the front surface; the second passivation layer is positioned above the back surface and is provided with an upper surface; a conductive feature in the first passivation layer; a through substrate via (TSV) penetrating the second passivation layer and the first substrate and electrically coupled to the through substrate via of the conductive feature; and a polymer pad between the TSV and the first substrate, where an upper surface of the polymer pad is lower than the upper surface of the second passivation layer; a barrier layer between the second passivation layer and the TSV, between the polymer pad and the TSV, and between the interconnect structure and the TSV; and an adhesive layer between the barrier layer and the TSV.

Description

Technical Field

[0001] This application claims priority to U.S. patent application No. 18 / 385,504 (i.e., the priority date is "October 31, 2023"), the contents of which are incorporated herein by reference in their entirety.

[0002] The present disclosure relates to a semiconductor element and a method for preparing the semiconductor element, and more particularly to a semiconductor element having a polymer liner and a method for preparing the semiconductor element having the polymer liner. Background Art

[0003] Semiconductor components are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. As the semiconductor industry advances to advanced technology process nodes, pursuing greater device density, higher performance, and lower costs, challenges have emerged in facilitating the integration of components of different sizes and complex features, especially for multi-stacked structured components.

[0004] The above “prior art” description only provides background technology, does not admit that the above “prior art” description reveals the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of this case. Summary of the invention

[0005] An embodiment of the present disclosure provides a semiconductor element, including a first substrate, including a front side and a back side parallel to the front side; a first passivation layer, located above the front side of the first substrate; a second passivation layer, located above the back side of the first substrate, wherein the second passivation layer has an upper surface facing away from the first substrate; a conductive feature, located in the first passivation layer, wherein the conductive feature includes a conductive pad and an interconnection structure electrically connected to the conductive pad; a through substrate via (TSV), penetrating the second passivation layer and the first substrate, wherein the through substrate via is electrically coupled to the conductive feature; a polymer liner, located between the through substrate via and the first substrate, wherein an upper surface of the polymer liner is lower than the upper surface of the second passivation layer; a barrier layer, located between the second passivation layer and the through substrate via, between the polymer liner and the through substrate via, and between the interconnection structure and the through substrate via; and an adhesive layer, located between the barrier layer and the through substrate via.

[0006] Another embodiment of the present disclosure provides a semiconductor element, including a first semiconductor wafer, including a first substrate, the first substrate having a front side and a back side parallel to the front side; a first passivation layer located above the front side of the first substrate and a second passivation layer located above the back side of the first substrate, wherein the second passivation layer has an upper surface facing away from the first substrate; a conductive feature located in the first passivation layer and a through-substrate via exposed through the second passivation layer and electrically coupled to the conductive feature; a polymer liner located between the through-substrate via and the first substrate; a barrier layer located between the second passivation layer and the through-substrate via, between the polymer liner and the through-substrate via, and between the conductive feature and the through-substrate via; an adhesive layer located between the barrier layer and the through-substrate via; and a second semiconductor wafer coupled to the first semiconductor wafer at a bonding interface and including a second substrate coupled to the first substrate. The polymer liner of the first semiconductor wafer is separated from the bonding interface.

[0007] Another embodiment of the present disclosure provides a method for preparing a semiconductor element, including forming a conductive feature in a first passivation layer above a front surface of a first substrate; forming a second passivation layer above a back surface of the first substrate; forming a first recess in an upper surface of the second passivation layer to expose the conductive feature; conformally forming an isolation liner on a side wall of the first recess; performing a pulse etching operation to conformally form a polymer liner on the side wall of the isolation liner, wherein an upper surface of the polymer liner is lower than the upper surface of the second passivation layer; conformally forming a barrier layer on the polymer liner and the isolation liner; conformally forming an adhesion layer on the barrier layer; and forming a conductive material in the first recess to form a through substrate via (TSV).

[0008] In pursuit of greater device density, the distance between adjacent pairs of conductive vias (e.g., two through-substrate vias) is becoming smaller and smaller. As a result, electrical interference may occur, thereby reducing device performance. In addition, through-substrate vias with smaller dimensions may face reliability issues. For example, a stress concentration problem may cause a defect in a device. In addition, it is also important to improve the yield of hybrid bonding.

[0009] The design of the semiconductor element and the manufacturing method thereof discussed in the present disclosure are intended to solve the above problems. Specifically, the present disclosure provides a semiconductor element having a polymer liner and a method for preparing the semiconductor element having the polymer liner.

[0010] The above has outlined the technical features and advantages of the present disclosure in a fairly broad manner, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the claims of the present disclosure will be described below. It should be understood by those with ordinary knowledge in the technical field to which the present disclosure belongs that the concepts and specific embodiments disclosed below can be used to modify or design other structures or processes to achieve the same purpose as the present disclosure. It should also be understood by those with ordinary knowledge in the technical field to which the present disclosure belongs that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] A more complete understanding of the present disclosure may be obtained by referring to the detailed description and claims.The present disclosure should also be understood to be associated with the element numbers of the drawings, which represent similar elements throughout the description.

[0012] Figure 1 It is a schematic flow chart illustrating a method for preparing a semiconductor element according to some embodiments of the present disclosure.

[0013] Figures 2A to 2D is a schematic cross-sectional view illustrating an intermediate stage of formation of a semiconductor device according to some embodiments of the present disclosure.

[0014] Figure 2D' is an enlarged schematic diagram illustrating the semiconductor elements of some embodiments of the present disclosure. Figure 2D The dotted area A1 is shown.

[0015] Figure 2E and Figure 2F is a schematic cross-sectional view illustrating an intermediate stage of formation of a semiconductor device according to some embodiments of the present disclosure.

[0016] Figure 2F' is an enlarged schematic diagram illustrating the semiconductor elements of some embodiments of the present disclosure. Figure 2F The dotted area A2 is shown.

[0017] Figure 2G is a schematic cross-sectional view illustrating an intermediate stage of formation of a semiconductor device according to some embodiments of the present disclosure.

[0018] Figure 2G' is a bias power-time graph illustrating a pulsed etching operation of some embodiments of the present disclosure.

[0019] Figure 2G” is a bias power-time graph illustrating a pulsed etching operation of some embodiments of the present disclosure.

[0020] Figure 2H to Figure 2L is a schematic cross-sectional view illustrating an intermediate stage of formation of a semiconductor device according to some embodiments of the present disclosure.

[0021] Figure 2M , Figure 2N , Fig.2O and Figure 3 is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure.

[0022] Figure 4 It is a schematic flow chart illustrating a method for preparing a semiconductor element according to some embodiments of the present disclosure.

[0023] FIG. 5A to FIG. 5C is a schematic cross-sectional view illustrating an intermediate stage of formation of a semiconductor device according to some embodiments of the present disclosure.

[0024] Figure 5D is a schematic cross-sectional view illustrating an intermediate stage of formation of a semiconductor device according to some embodiments of the present disclosure.

[0025] Figure 5E is a schematic cross-sectional view illustrating an intermediate stage of formation of a semiconductor device according to some embodiments of the present disclosure.

[0026] Figure 6 is a schematic cross-sectional view illustrating an intermediate stage of formation of a semiconductor device according to some embodiments of the present disclosure.

[0027] The reference numerals are described as follows:

[0028] 1A: First semiconductor wafer

[0029] 1A': Second semiconductor wafer

[0030] 1B: Semiconductor components

[0031] 1C: Semiconductor components

[0032] 100: First base

[0033] 100': Second base

[0034] 100B: Back

[0035] 100F: Front

[0036] 100SW: Sidewall

[0037] 100U: recessed part

[0038] 101: First passivation layer

[0039] 101B: Back

[0040] 101SW: Sidewall

[0041] 102: Second passivation layer

[0042] 102SW: Sidewall

[0043] 102T: Top surface

[0044] 2A: First semiconductor wafer

[0045] 201: Interconnection Structure

[0046] 202: Conductive pad

[0047] 202E: Exposed Surface

[0048] 203: Through-substrate via

[0049] 203A: Part I

[0050] 203B: Part 2

[0051] 203M: Conductive material

[0052] 203SD: Seed layer

[0053] 203SDT: Upper surface

[0054] 203SW: Sidewall

[0055] 203T: Upper surface

[0056] 204: Barrier layer

[0057] 204T: Upper surface

[0058] 205: Polymer liner

[0059] 205FP: Part I

[0060] 205H: Upper part

[0061] 205L: lower part

[0062] 205M: polymer material layer

[0063] 205SP: Part 2

[0064] 205SW: Sidewall

[0065] 205T: Upper surface

[0066] 206: Isolation pad

[0067] 206B: Bottom

[0068] 206M: Isolation liner material layer

[0069] 206P: protrusion

[0070] 206S: Side wall

[0071] 206SW: Sidewall

[0072] 206T: Top

[0073] 206TS: Upper surface

[0074] 210: Conductive characteristics

[0075] 301: Upper passivation layer

[0076] 303: Upper barrier layer

[0077] 305: Upper connector

[0078] AL: Adhesive layer

[0079] ALT: Upper surface

[0080] BND1: ​​First bonding surface

[0081] BND2: Second bonding surface

[0082] BT: Bottom

[0083] D1: Depth

[0084] INT: Bonding interface

[0085] OP1: Opening

[0086] R1: First depression

[0087] R2: Second depression

[0088] REF: Imaginary Surface

[0089] S1: Preparation method

[0090] S1': Preparation method

[0091] S11~S20: Steps

[0092] S16': Steps

[0093] T1: First thickness

[0094] T2: Second thickness

[0095] T3: Thickness

[0096] T4: Thickness

[0097] TK1: Thickness

[0098] W1: Width

[0099] W2: Width

[0100] W3: Width

[0101] Z: Direction DETAILED DESCRIPTION

[0102] Specific examples of components and configurations are described below to simplify the embodiments of the present disclosure. Of course, these embodiments are for illustration only and are not intended to limit the scope of the present disclosure. For example, in the description, the first component is formed on the second component, which may include an embodiment in which the first and second components are in direct contact, and may also include an embodiment in which additional components are formed between the first and second components so that the first and second components are not in direct contact. In addition, the embodiments of the present disclosure may repeat reference numbers and / or letters in many examples. The purpose of these repetitions is to simplify and clarify, and unless otherwise specified in the text, they do not themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0103] It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. On the contrary, these terms are only used to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the progressive conception of the present disclosure, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0104] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms "comprises" and / or "comprising" are used in this specification, these terms specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the above.

[0105] In pursuit of greater device density, the distance between adjacent pairs of conductive vias (e.g., two through-substrate vias, TSVs) is becoming smaller and smaller. As a result, electrical interference may occur, thereby reducing device performance. In addition, smaller through-substrate vias may face reliability issues. For example, a stress concentration problem may cause a defect in a device. In addition, it is also important to improve the yield of hybrid bonding.

[0106] Specifically, the present disclosure provides a semiconductor device with a polymer liner and a method for preparing a semiconductor device with a polymer liner. The performance of the device formed according to the method and the product yield of the device are improved. For example, electrical interference can be reduced, the reliability of through-substrate vias can be improved, and the yield of hybrid bonding can be improved.

[0107] Figure 1 : is a flow chart illustrating a method S1 for preparing a semiconductor element of some embodiments of the present disclosure. The method S1 includes a plurality of steps (S11, S12, S13, S14, S15, S16, S17, S18, S19 and S20), and the description and drawings should not be considered as limiting the order of the steps. In step S11, a conductive feature is formed in a first passivation layer above a front surface of a first substrate. In step S12, the first substrate is thinned on a back surface of the first substrate. In step S13, a second passivation layer is formed above the back surface of the first substrate. In step S14, a first recess is formed in an upper surface of the second passivation layer to expose the conductive feature, and a recessed portion is formed in a side wall of the first substrate. In step S15, an isolation liner is formed in the first recess. In step S16, a pulse etching operation is performed to form a polymer liner in the first recess, wherein an upper surface of the polymer liner is lower than the upper surface of the second passivation layer. In step S17, a barrier layer and an adhesive layer are formed in the first recess. In step S18, a conductive material is formed in the first recess to form a through substrate via (TSV). In step S19, a second substrate is bonded to the first substrate by performing a hybrid bonding operation. In step S20, an upper connector is formed over the conductive feature.

[0108] Figures 2A to 2L Schematic cross-sectional view illustrating various manufacturing stages constructed by the preparation method S1 of some embodiments of the present disclosure. Figure 2M , Figure 2N , Fig.2O and Figure 3 is a schematic cross-sectional view illustrating various components manufactured by executing the steps of the preparation method S1.

[0109] Figure 2A 1 is a cross-sectional schematic diagram illustrating an intermediate stage of the formation of a semiconductor element of some embodiments of the present disclosure. Prior to step S11, a first substrate 100 having a first thickness T1 is provided, received or formed. The first substrate 100 has a front surface 100F and a back surface 100B opposite to the front surface 100F. The front surface 100F and the back surface 100B are parallel to each other. The front surface 100F faces upward and the back surface 100B faces downward.

[0110] A first passivation layer 101 is formed over the front surface 100F of the first substrate 100. In step S11, a conductive feature 210 is formed in the first passivation layer 101 over the front surface 100F of the first substrate 100. In some embodiments, the conductive feature 210 includes a conductive pad 202 exposed through the back surface 101B of the first passivation layer 101, and an interconnection structure 201 electrically connected to the conductive pad 202. The conductive pad 202 and the interconnection structure 201 may include conductive materials, such as copper, aluminum copper, other types of metals, or other suitable materials. In some embodiments, a planarization operation, such as a chemical mechanical planarization (CMP) operation, may be performed on the first passivation layer 101 in step S11, so that an exposed surface 202E of the conductive pad 202 is coplanar with the back surface 101B of the first passivation layer 101.

[0111] The first substrate 100 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. The first substrate 100 may include an elemental semiconductor including silicon or germanium in a single crystal form, a polycrystalline form, or an amorphous form; a compound semiconductor material including at least one of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor material including at least one of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable material; or a combination thereof. In some embodiments, the alloy semiconductor substrate may be a SiGe alloy having a gradient SiGe feature, wherein the Si and Ge composition changes from one ratio at one location of the gradient SiGe feature to another ratio at another location. In other embodiments, the SiGe alloy is formed over a silicon substrate. In some embodiments, the SiGe alloy may be mechanically strained by another material in contact with the SiGe alloy.

[0112] In some embodiments, the first substrate 100 may have a multi-layer structure, or the first substrate 100 may include a multi-layer compound semiconductor structure. In some embodiments, the first substrate 100 includes a semiconductor element, an electronic component, an electronic element, or a combination thereof. In some embodiments, the first substrate 100 includes a transistor or a functional unit of a transistor.

[0113] In some embodiments, the first passivation layer 101 includes an insulating material, such as SiON, SiO 2 , SiCN, a silicon-based material, a nitride-based material, an oxide-based material, a carbide-based material, a combination thereof, or other suitable materials.

[0114] Figure 2B1 is a cross-sectional view illustrating an intermediate stage of forming a semiconductor device according to some embodiments of the present disclosure. In step S12, a thinning operation is performed on the back surface 100B of the first substrate 100. For example, a thickness of the first substrate 100 is reduced from a first thickness T1 (e.g., Figure 2A The thinning operation of step S12 includes grinding the back side 100B of the first substrate 100 .

[0115] Figure 2C 1 is a cross-sectional schematic diagram illustrating an intermediate stage of the formation of a semiconductor device in some embodiments of the present disclosure. In step S13, a second passivation layer 102 is formed on the back side 100B of the first substrate 100. The second passivation layer 102 has an upper surface 102T facing away from the first substrate 100. In some embodiments, the second passivation layer 102 includes an insulating material, such as SiON, SiO2, SiCN, a silicon-based material, a nitride-based material, an oxide-based material, a carbide-based material, a combination thereof, or other suitable materials. In some embodiments, the first substrate 100 is flipped before step S13.

[0116] Figure 2C is a cross-sectional schematic diagram illustrating an intermediate stage of formation of a semiconductor device according to some embodiments of the present disclosure, and Figure 2D' is an enlarged schematic diagram illustrating the semiconductor elements of some embodiments of the present disclosure. Figure 2D In step S14, the first recess R1 is formed by recessing the upper surface 102T of the second passivation layer 102. The formation of the first recess R1 may include a lithography operation and / or an etching operation. In some embodiments, the etching operation includes repeating the following cycle: (1) applying a CF x The present invention relates to a method for forming a silicon-based substrate 200 by using a silicon-based plasma to deposit a thin film (not shown), (2) removing a lower portion of the thin film by an anisotropic etching operation, and (3) performing a silicon etching operation with fluorine radicals in SF6 plasma. The above etching operation is more suitable for forming deep trenches than some other types of etching operations. After performing the etching operation, a side wall 102SW of the second passivation layer 102, a side wall 100SW of the first substrate 100, and a side wall 101SW of the first passivation layer 101 are exposed in the first recess R1. As a result, the exposed side wall 102SW of the second passivation layer 102, the exposed side wall 100SW of the first substrate 100, and the exposed side wall 101SW of the first passivation layer 101 can be referred to as the side wall of the first recess R1. A portion of the conductive feature 210 is located below a projected area of ​​the first recess R1. In addition, a bottom BT of the first recess R1 can terminate at the conductive feature 210. For example, a portion of the interconnect structure 201 is exposed at the bottom BT of the first recess R1.

[0117] In addition, if Figure 2D' As shown, a recessed portion 100U may also be formed in step S14. Specifically, when the above-mentioned etching operation is performed, a portion of the first substrate 100 close to the back side 100B of the first substrate 100 may be partially removed in the lateral direction. In an embodiment where the first substrate 100 includes silicon, the formation of the recessed portion 100U close to the back side 100B of the first substrate 100 may be referred to as "silicon undercut". The recessed portion 100U is located at a surrounding area of ​​the first recess R1 in the sidewall 100SW of the first substrate 100. A plurality of second recesses R2 are formed in the recessed portion 100U in the sidewall 100SW of the first substrate 100 at a position close to the second passivation layer 102. A depth D1 of a second recess R2 (i.e., a distance measured from the tip of the second recess R2 to an imaginary surface REF, wherein the imaginary surface REF is aligned with the sidewall 102SW of the second passivation layer 102) may be between about 100nm and about 500nm. If the depth D1 is greater than about 500 nm, the first substrate 100 may suffer from excessive material loss, which may cause reliability issues.

[0118] Figure 2E and Figure 2F 2 is a cross-sectional view illustrating an intermediate stage of forming a semiconductor device according to some embodiments of the present disclosure. In step S15, an isolation liner 206 is formed in the first recess R1 (eg, Figure 2F Step S15 includes a multi-step operation, including forming an isolation liner material layer 206M in the first recess R1 and above the upper surface 102T of the second passivation layer 102 (as shown in FIG. Figure 2E As shown) and partially removing the isolation liner material layer 206M to form the isolation liner 206 (as shown Figure 2F ). In some embodiments, a blanket deposition is performed to form an isolation liner material layer 206M in the first recess R1 and on the upper surface 102T of the second passivation layer 102. The isolation liner material layer 206M includes (1) a top portion 206T located above the upper surface 102T of the second passivation layer 102, (2) a sidewall portion 206S lining the sidewall of the first recess R1 (i.e., lining the sidewall 100SW of the first substrate 100, the sidewall 101SW of the first passivation layer 101, and the sidewall 102SW of the second passivation layer 102), and (3) a bottom portion 206B located at the bottom BT of the first recess R1 and located above the interconnect structure 201.

[0119] In some embodiments, a material of the isolation liner material layer 206M includes an oxide-based material, a nitride-based material, or other suitable materials, and can be selected from materials with a low dielectric constant.

[0120] Still referring to step S15, an etching operation is performed to remove the top 206T and the bottom 206B of the isolation liner material layer 206M, wherein the remaining portion of the isolation liner material layer 206M, i.e., the sidewall portion 206S, constitutes the isolation liner 206. Thereby, the isolation liner 206 is formed on the sidewall 100SW of the first substrate 100, on the sidewall 101SW of the first passivation layer 101, and on the sidewall 102SW of the second passivation layer 102. In some embodiments, an upper portion of the sidewall portion 206S of the isolation liner material layer 206M may also be partially removed, but the present disclosure is not limited thereto.

[0121] Figure 2F' is an enlarged schematic diagram illustrating the semiconductor elements of some embodiments of the present disclosure. Figure 2F The dotted area A2 is shown in FIG. Figure 2E and Figure 2F Following the discussion of FIG. 1 , an isolation liner 206 is also formed in the second recess R2 in the recessed portion 100U. The isolation liner 206 includes a plurality of protrusions 206P located in the second recess R2, wherein the protrusions 206P protrude toward the first substrate 100. The protrusions 206P are in physical contact with the first substrate 100. A height D2 of a protrusion 206P may correspond to Figure 2D' The depth D1 shown in FIG. 1 is between about 100 nm and about 500 nm. The depth D2 may be greater than 100 nm so that the adhesion between the isolation liner 206 and the first substrate 100 can be enhanced, thereby improving the reliability of the semiconductor device.

[0122] In step S16, a polymer liner 205 is formed in the first recess R1. Figures 2G to 2H The formation of polymer liner 205 is discussed.

[0123] Figure 2Gis a cross-sectional schematic diagram illustrating an intermediate stage of the formation of a semiconductor element in some embodiments of the present disclosure. A polymer material layer 205M is formed in the first recess R1 and above a side wall 206SW of the isolation liner 206. The formation of the polymer material layer 205M includes supplying a carbon-based chemical above the first recess R1. In some embodiments, the carbon-based chemical may be a carbon-rich gas, such as C4F8 or C4F6. In some alternative embodiments, the carbon-based chemical may be carbon monoxide (CO). A material of the polymer material layer 205M may be a fluorine-based polymer, which also contains carbon. A dielectric constant of the polymer material layer 205M may be less than 3.5. The polymer material layer 205M is formed above the isolation liner 206. In some embodiments, the manufacturing technique of the polymer material layer 205M includes a pulse etching operation, which includes multiple repeated cycles of: (1) partially removing a polymer material in a first state, and (2) depositing a polymer material in a second state. By appropriately controlling a removal rate in the first state and a deposition rate in the second state, the polymer material layer 205M can be shaped in a desired manner. The pulse etching operation may include repeatedly changing a bias power over time, as shown in FIG. Figure 2G' or Figure 2G” As discussed above, various factors or conditions (e.g., temperature, etching time, etc.) of the pulse etching operation are controlled simultaneously. In addition, the polymer material layer 205M can be formed in different ways at different locations. In some embodiments, the removal rate of the polymer material layer 205M near an opening of the first recess R1 can be greater than a removal rate at a lower position of the first recess R1.

[0124] Figure 2G' is a bias power-time graph illustrating pulsed etching operations of some embodiments of the present disclosure. The first type of pulsed etching operation is as follows Figure 2G' In the first type of pulsed etching operation, the step (1) of partially removing the polymer material in the first state is first performed, and then the step (2) of depositing the polymer material in the second state is performed. In the first state, a higher bias power is applied, wherein the reactants are dissociated. In the second state, the bias power is reduced, thereby making the reactants in an atomic state and capable of being deposited on a surface in solid form. The switching interval of the bias power in the first type of pulsed etching operation can be about 10 -4 That is, the first state and the second state are switched alternately and repeatedly, and the switching interval is about 10-4s to about 10s.

[0125] Figure 2G” is a bias power-time graph illustrating a pulsed etching operation of some embodiments of the present disclosure. Figure 2G A second type of pulsed etching operation is depicted. The second type of pulsed etching operation is similar to reference Figure 2G' The first type of pulse etching operation discussed herein is different in that step (2) of depositing the polymer material in the second state is performed before step (1) of partially removing the polymer material in the first state. The switching interval of the bias power in the second type of pulse etching operation may be about 10 -4 That is, the first state and the second state are switched alternately and repeatedly, and the switching interval is about 10 -4 s to about 10s.

[0126] Please refer back Figure 2G , by executing the reference Figure 2G' The first type of pulsed etching operation discussed or referred to Figure 2G” The second type of pulse etching operation discussed can control a shape of the polymer material layer 205M. Therefore, the initially deposited polymer material layer 205M includes a lower portion 205L and an upper portion 205H above the lower portion 205L, wherein the upper portion 205H is close to the upper surface 102T of the second passivation layer 102. During the pulse etching operation (first type or second type pulse etching operation), a removal rate of the upper portion 205H is greater than a deposition rate of the upper portion 205H, and a deposition rate of the lower portion 205L is greater than a removal rate of the lower portion 205L. In addition, a removal rate of the polymer material at the bottom BT of the first recess R1 is greater than the deposition rate of the polymer material, so that the interconnect structure 201 can remain exposed to the first recess R1 after the pulse etching operation. The result of shaping the polymer material layer 205M into a polymer liner 205 is as follows. Figure 2H shown.

[0127] Figure 2H 2 is a cross-sectional view illustrating an intermediate stage of forming a semiconductor device according to some embodiments of the present disclosure. A polymer liner 205 formed of a polymer material layer 205M is deposited in the first recess R1. As a result, the polymer liner 205 has an upper surface 205T that is lower than the upper surface 102T of the second passivation layer 102. A portion of the isolation liner 206 may be exposed above the polymer liner 205. In some embodiments, as shown in FIG. Figure 2HAs shown, the upper surface 205T of the polymer liner 205 is located above the back side 100B of the first substrate 100. In some embodiments, the polymer liner 205 includes a first portion 205FP laterally surrounded by the second passivation layer 102, and a second portion 205SP laterally surrounded by the first substrate 100 and a portion of the first passivation layer 101. The first portion 205FP is located above the second portion 205SP. The first portion 205FP is located above the back side 100B of the first substrate 100. In some embodiments, the polymer liner 205 has a thickness TK1 between about 50nm and about 500nm. The second portion 205SP of the polymer liner 205 is in direct contact with the interconnect structure 201 of the conductive feature 210. A material of the polymer liner 205 may include a fluorine-based polymer, which also includes carbon. A dielectric constant of the polymer liner 205 may be less than 3.5.

[0128] Fig.2I 2 is a cross-sectional schematic diagram illustrating an intermediate stage of the formation of a semiconductor element in some embodiments of the present disclosure. In step S17, a barrier layer 204 is formed in the first recess R1. In some embodiments, the barrier layer 204 is formed by a blanket deposition technique. The barrier layer 204 is formed over the upper surface 102T of the second passivation layer 102, over the sidewall 205SW of the polymer liner 205, over the upper surface 205T of the polymer liner 205, over the sidewall 206SW of the isolation liner 206, and over the interconnect structure 201 exposed at the bottom BT of the first recess R1. In some embodiments, the barrier layer 204 may include cobalt, titanium, titanium nitride, ruthenium, tantalum, tantalum nitride, indium oxide, tungsten nitride, titanium nitride, nickel boride, tantalum nitride / tantalum double layer, or other suitable materials.

[0129] In step S17, an adhesion layer AL is formed in the first recess R1. In some embodiments, the manufacturing technique of the adhesion layer AL includes blanket deposition. In some embodiments, the manufacturing technique of the adhesion layer AL includes a deposition process, such as physical vapor deposition, atomic layer deposition, chemical vapor deposition, sputtering or other appropriate deposition processes. The adhesion layer AL is conformally formed over the barrier layer 204. In some embodiments, for example, the adhesion layer AL may include titanium, tantalum, titanium tungsten or manganese nitride. The adhesion layer AL may improve the adhesion between the barrier layer 204 and the seed layer 203SD, which will be described below. In some embodiments, the adhesion layer AL has a thickness between about 5 nm and about 50 nm.

[0130] After performing step S17, a seed layer 203SD may be formed over the adhesion layer AL. In some embodiments, the seed layer 203SD has a thickness between about 10 nm and about 40 nm. In some embodiments, for example, the seed layer 203SD includes copper or ruthenium. In some embodiments, the manufacturing technique of the seed layer 203SD includes a deposition process, such as physical vapor deposition, atomic layer deposition, chemical vapor deposition, sputtering, or other appropriate deposition processes. In some embodiments, the seed layer 203SD may reduce the resistivity of the first recess R1 during the formation of the conductive material 203M, which will be described below.

[0131] In step S18, a conductive material 203M is formed in the first recess R1 to form a through substrate via (TSV) 203. Figure 2J and Figure 2K Give a description.

[0132] Figure 2J 1 is a cross-sectional schematic diagram illustrating an intermediate stage of the formation of a semiconductor element in some embodiments of the present disclosure. In step S18, a conductive material 203M (e.g., copper or other types of metals, alloys, etc.) is formed in the first recess R1 and above the upper surface 102T of the second passivation layer 102. In some embodiments, the manufacturing technology of the conductive material 203M may include electroplating, chemical plating, sputtering, or other types of deposition operations.

[0133] Figure 2Kis a cross-sectional schematic diagram illustrating an intermediate stage of the formation of a semiconductor device of some embodiments of the present disclosure. Step S18 also includes a planarization operation, such as a chemical mechanical planarization (CMP) operation. By using the planarization operation, the excess portion of the conductive material 203M can be removed to form a through-substrate via 203, thereby forming a first semiconductor wafer 1A. After performing the planarization operation, an upper surface 203T of the through-substrate via 203 is coplanar with an upper surface 102T of the second passivation layer 102, an upper surface 204T of the barrier layer 204, an upper surface 203SDT of the seed layer 203SD, an upper surface ALT of the adhesion AL layer, and an upper surface 206TS of the isolation liner 206. Therefore, the upper surface 203T of the through substrate via 203, the upper surface 102T of the second passivation layer 102, the upper surface 204T of the barrier layer 204, the upper surface 203SDT of the seed layer 203SD, the upper surface ALT of the adhesive layer AL, and the upper surface 206TS of the isolation liner 206 are collectively referred to as a first bonding surface BND1. In some embodiments, the upper surface 205T of the polymer liner 205 is separated from the first bonding surface BND1. Therefore, the polymer liner 205 is not exposed through the first bonding surface BND1. In addition, the barrier layer 204 is consistent with the sidewall 203SW of the through substrate via 203. The barrier layer 204 extends between the polymer liner 205 and the through substrate via 203. The adhesive layer AL is consistent with the barrier layer 204. The adhesive layer AL is disposed between the barrier layer 204 and the through substrate via 203. The seed layer 203SD is consistent with the adhesive layer AL. The seed layer 203SD is disposed between the adhesion layer AL and the through substrate via 203. In some embodiments, the seed layer 203SD includes the same material as the through substrate via 203 and is referred to as a portion of the through substrate via 203.

[0134] The through substrate via 203 is electrically coupled to the interconnect structure 201 of the conductive feature 210. The through substrate via 203 penetrates the second passivation layer 102 and the first substrate 100. The through substrate via 203 may have a first portion 203A and a second portion 203B, wherein a width W1 of the first portion 203A is greater than a width W2 of the second portion 203B. The first portion 203A is located above the second portion 203B, and the second portion 203B penetrates the first substrate 100. In some embodiments, a width W1 of the first portion 203A is less than a width W3 of the conductive pad 202. In some embodiments, a width W1 of the first portion 203A is equal to or greater than a width W3 of the conductive pad 202.

[0135] The first semiconductor wafer 1A can be used in various types of semiconductor components, such as dynamic random access memory (DRAM), three-dimensional integrated circuit (3DIC), memory stacking, logic stacking, memory components, and the like. In some embodiments, the first semiconductor wafer 1A can be stacked with other semiconductor wafers or semiconductor structures to form a semiconductor component. Figures 2L to 2M , Figure 2N , Fig.2O and Figure 3 Some embodiments are discussed.

[0136] In step S19, the first semiconductor wafer 1A is coupled to the second semiconductor wafer 1A'. In some embodiments, the first semiconductor wafer 1A is bonded to the second semiconductor wafer 1A' by performing a hybrid bonding operation. In some embodiments, the configuration of the second semiconductor wafer 1A' may be similar to the configuration of the first semiconductor wafer 1A. The second semiconductor wafer 1A' includes a second substrate 100' similar to the first substrate 100. The first substrate 100 of the first semiconductor wafer 1A is coupled to the second substrate 100' of the second semiconductor wafer 1A' via a hybrid bonding operation. Figure 2L to Figure 2M , Figure 2N , Fig.2O and Figure 3 In the example shown, the second semiconductor wafer 1A' is substantially identical to the first semiconductor wafer 1A, and the second substrate 100' is substantially identical to the first substrate 100. However, it should be understood that the design of the second semiconductor wafer 1A' and the design of the second substrate 100' may also vary.

[0137] Figure 2K 1 is a cross-sectional schematic diagram illustrating an intermediate stage of the formation of a semiconductor element of some embodiments of the present disclosure. Step S19 includes aligning the first semiconductor wafer 1A and the second semiconductor wafer 1A', wherein the first bonding surface BND1 of the first semiconductor wafer 1A faces a second bonding surface BND2 of the second semiconductor wafer 1A'. As in the first semiconductor wafer 1A, in the second semiconductor wafer 1A', the conductive pad 202 can be exposed through the back side 101B of the first passivation layer 101 of the second semiconductor wafer 1A' and exposed through the second bonding surface BND2.

[0138] Figure 2Mis a cross-sectional schematic diagram illustrating semiconductor elements of some embodiments of the present disclosure. Step S19 includes coupling the first semiconductor wafer 1A to the second semiconductor wafer 1A'. First, the first bonding surface BND1 of the first semiconductor wafer 1A is bonded to the second bonding surface BND2 of the second semiconductor wafer 1A' at a bonding interface INT at a first temperature (which may be around room temperature, for example, approximately 25°C). Secondly, the first semiconductor wafer 1A and the second semiconductor wafer 1A' are annealed at a second temperature higher than the first temperature, so that the first semiconductor wafer 1A can be bonded to the second semiconductor wafer 1A' by a hybrid bonding operation. In some embodiments, the second temperature is between approximately 200°C and 350°C. The through-substrate via 203 of the first semiconductor wafer 1A is in direct contact with the first passivation layer 101 of the second semiconductor wafer 1A'.

[0139] Figure 2N 2 is a cross-sectional view illustrating a semiconductor device of some embodiments of the present disclosure. Step S20 includes forming an upper connector 305 above the interconnect structure 201 of the first semiconductor wafer 1A. Before step S20, the semiconductor device 1A is flipped over. Figure 2M The intermediate semiconductor element shown. Subsequently, the back side 101B of the first passivation layer 101 of the first semiconductor wafer 1A faces upward. An upper passivation layer 301 is formed over the back side 101B of the first passivation layer 101 of the first semiconductor wafer 1A. An opening OP1 is formed through the upper passivation layer 301 to expose the conductive pad 202 of the first semiconductor wafer 1A. An upper barrier layer 303 is formed over the conductive pad 202 of the first semiconductor wafer 1A and within the opening OP1. An upper connector 305 is formed over the upper barrier layer 303 and completely fills the opening OP1. After the upper connector 305 is formed, the semiconductor element 1B is obtained.

[0140] In some embodiments, the upper passivation layer 301 is a single-layer structure or a multi-layer structure. In some embodiments, the upper passivation layer 301 includes polybenzoxazole, polyimide, benzocyclobutene, solder mask, the like, or a combination thereof. Polymer materials (e.g., polyimide) can have many attractive properties, such as the ability to fill openings with high aspect ratios, relatively low dielectric constants (approximately 3.2), simple deposition processes, reduction of sharp features or steps in the bottom layer, and high temperature resistance after curing. In addition, some photosensitive polymer materials (e.g., photosensitive polyimide) can have all of the above properties, can be patterned like a photoresist mask, and can be retained on a surface on which the photosensitive polymer material has been deposited after patterning and etching to serve as part of a passivation layer. In some other embodiments, the upper passivation layer 301 can be a dielectric layer. The dielectric layer may include a nitride such as silicon nitride, an oxide such as silicon oxide, an oxynitride such as silicon oxynitride, silicon oxynitride, phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, the like, or a combination thereof.

[0141] In some embodiments, an opening OP1 is formed to penetrate the upper passivation layer 301 to expose the conductive pad 202 and a portion of the back side 101B of the first passivation layer 101 of the first semiconductor wafer 1A. In some embodiments, the sidewalls of the opening OP1 are substantially vertical. In some embodiments, the sidewalls of the opening OP1 are tapered. It should be understood that in the description of the present disclosure, if there is a vertical plane, the root mean square roughness of the surface deviating from the surface does not exceed three times the root mean square roughness of the surface, then the surface is "substantially vertical".

[0142] In some embodiments, the upper barrier layer 303 is formed above the conductive pad 202 and within the opening OP1. The upper barrier layer 303 may have a thickness T3 that is less than a thickness T4 of the upper passivation layer 301. For example, the upper barrier layer 303 includes aluminum fluoride. Due to its saturated bonding properties, aluminum fluoride is stable and can protect the underlying conductive pad 202 from corrosion caused by various semiconductor processes, especially those containing fluoride ions. In some embodiments, the upper barrier layer 303 may also include zinc oxide, which can improve the electrical performance of the upper barrier layer 303. In some embodiments, a concentration of zinc oxide in the upper barrier layer 303 may be greater than a concentration of aluminum fluoride in the upper barrier layer 303.

[0143] In some embodiments, the upper connector 305 is formed over the upper barrier layer 303 and the upper passivation layer 301 and completely fills the opening OP1. A lower portion of the upper connector 305 extends into the upper passivation layer 301, completely fills the opening OP1, and is disposed over the upper barrier layer 303. An upper portion of the upper connector 305 protrudes from a plane coplanar with an upper surface of the upper passivation layer 301, covers the lower portion of the upper connector 305, and covers a portion of the upper surface of the upper passivation layer 301 near the opening OP1. In some embodiments, for example, the upper connector 305 includes a conductive material with low resistivity, such as tin, lead, silver, copper, nickel, bismuth, or an alloy thereof.

[0144] In some embodiments, the upper connector 305 is a solder joint. The solder joint includes a material such as tin, or other suitable materials such as silver or copper. In one embodiment where the solder joint is a tin solder joint, the solder joint manufacturing technique includes first forming a tin layer with a thickness of about 10 μm to about 100 μm by evaporation, electroplating, printing, solder transfer or ball planting. Once the tin layer has been formed, fills the opening OP1 and protrudes above the upper passivation layer 301, a reflow process can be performed to shape the solder joint into a desired shape.

[0145] In some embodiments, the polymer liner 205 is separated from the bonding interface INT, thereby improving the reliability of the adhesion between the first semiconductor wafer 1A and the second semiconductor wafer 1A′ during the hybrid bonding operation and mitigating or limiting the negative impact on the electrical performance of the semiconductor device 1B.

[0146] Conventional bonding operations face problems caused by the expansion of conductive materials at the operating temperature of hybrid bonding. The deformation of the conductive material may cause the bonding surface to have an uneven profile, which in turn leads to poor adhesion between the two wafers.

[0147] In order to solve the above problems, the present disclosure provides a semiconductor element having a polymer liner 205. Specifically, due to its good flexibility, the polymer liner 205 can reduce the deformation of the through-substrate via 203 or buffer the negative impact caused by the deformation of the through-substrate via 203. Therefore, the degree of deformation of the through-substrate via 203 (especially in the vertical direction) can be reduced, and the stress concentration in the through-substrate via 203 can be alleviated. As a result, the yield of the hybrid bonding operation can be improved.

[0148] Fig.2O is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure. Fig.2O The semiconductor element 1C shown is similar to Figure 2MThe difference is that the semiconductor device 1C includes a stack of more than two semiconductor chips. For example, a first semiconductor chip 1A is coupled to more than one second semiconductor chip 1A' (see Figures 2K to 2N ). The hybrid bonding operation may be repeated. It should be understood that as the number of semiconductor wafers in the stack increases, the deformation of the through-substrate via 203 may compound, exacerbating a tolerance problem associated with hybrid bonding. Therefore, the present disclosure provides a solution to such problems for multi-wafer stacking configurations.

[0149] Figure 3 is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure. Figure 3 The semiconductor device 1D shown is similar to Figure 2M The difference is that each of the first semiconductor wafer 1A and the second semiconductor wafer 1A′ may have two or more through-substrate vias 203 .

[0150] In pursuit of greater device density, the distance between adjacent pairs of through substrate vias 203 becomes smaller and smaller. Therefore, the inclusion of polymer liner 205 can help mitigate electrical interference, thereby improving device performance.

[0151] Figure 4 is a flow chart illustrating a method for preparing a semiconductor element of some embodiments of the present disclosure. Preparation method S1' includes a plurality of steps (S11, S12, S13, S14, S15, S16', S17, S18, S19 and S20), and the description and drawings should not be regarded as limiting the order of the steps. In step S11, a conductive feature is formed in a first passivation layer above a front surface of a first substrate. In step S12, the first substrate is thinned from a back surface of the first substrate. In step S13, a second passivation layer is formed above the back surface of the first substrate. In step S14, a first recess is formed in an upper surface of the second passivation layer to expose the conductive feature, and a recessed portion is formed in a side wall of the first substrate. In step S15, an isolation liner is formed in the first recess. In step S16', a pulse etching operation is performed to form a polymer liner in the first recess, wherein an upper surface of the polymer liner is lower than the back surface of the first substrate. In step S17, a barrier layer and an adhesive layer are formed in the first recess. In step S18, a conductive material is formed in the first recess to form a through substrate via (TSV). In step S19, a second substrate is bonded to the first substrate by performing a hybrid bonding operation. In step S20, an upper connector is formed over the conductive feature.

[0152] FIG. 5A to FIG. 5DSchematic cross-sectional views illustrating different manufacturing stages of the preparation method S1 ′ according to some embodiments of the present disclosure. Figure 5D , Figure 5E and Figure 6 is a schematic diagram showing different components that can be manufactured by performing the steps of the manufacturing method S1'. In addition, the manufacturing method S1' is similar to Figure 1 The preparation method S1 shown in FIG. 1 is different in that step S16' in the preparation method S1' is different from step S16 in the preparation method S1, as described below. Specifically, in the preparation method S1', when performing steps S11, S12, S13, S14 and S15 (which correspond to FIG. 2A to FIG. 2F′ Step S16', S17, S18, S19 and S20 executed after step S15 are FIG. 5A to FIG. 5D Have a discussion.

[0153] Figure 5A 2 is a cross-sectional view illustrating an intermediate stage of forming a semiconductor device according to some embodiments of the present disclosure. A polymer material layer 205M is formed in the first recess R1 and on a side wall 206SW of an isolation liner 206. The formation of the polymer material layer 205M includes performing a reference Figure 2G And reference Figure 2G' or Figure 2G” The pulse etching operation discussed. A material of the polymer material layer 205M may include a fluorine-based polymer, and the fluorine-based polymer also includes carbon. A dielectric constant of the polymer material layer 205M may be less than 3.5. The polymer material layer 205M is formed over the isolation liner 206.

[0154] A shape of the polymer material layer 205M can be controlled. Therefore, the polymer material layer 205M includes a lower portion 205L and an upper portion 205H above the lower portion 205L when initially deposited, wherein the upper portion 205H is close to an upper surface 102T of a second passivation layer 102. During a pulse etching operation (i.e., a first type or second type pulse etching operation), a removal rate of the upper portion 205H is greater than a deposition rate of the upper portion 205H, and a deposition rate of the lower portion 205L is greater than a removal rate of the lower portion 205L. Furthermore, a removal rate of the polymer material at the bottom BT of the first recess R1 is greater than a deposition rate of the polymer material at the bottom BT; therefore, after performing the pulse etching operation, the interconnect structure 201 can remain exposed to the first recess R1.

[0155] With reference Figure 2G The discussed embodiments are compared to the reference Figure 5A The upper portion 205H in the embodiment discussed instead extends to a position below a back surface 100B of a first substrate 100 . Figure 5BA result of forming the polymer material layer 205M into the polymer liner 205 is shown.

[0156] Figure 5B 2 is a cross-sectional view illustrating an intermediate stage of forming a semiconductor device according to some embodiments of the present disclosure. A polymer liner 205 formed of a polymer material layer 205M is deposited in the first recess R1. As a result, the polymer liner 205 has an upper surface 205T that is lower than the upper surface 102T of the second passivation layer 102. A portion of the isolation liner 206 may be exposed above the polymer liner 205. In some embodiments, as shown in FIG. Figure 5B As shown, the upper surface 205T of the polymer liner 205 is located below the back surface 100B of the first substrate 100. In some embodiments, the polymer liner 205 has a thickness TK1 between about 50nm and about 500nm. The polymer liner 205 is in direct contact with the interconnect structure 201 of a conductive feature 210. A material of the polymer liner 205 may include a fluorine-based polymer. A dielectric constant of the polymer liner 205 may be less than 3.5.

[0157] Figure 5C is a cross-sectional schematic diagram illustrating an intermediate stage of forming a semiconductor element according to some embodiments of the present disclosure. Figures 2I to 2K The steps depicted, steps S17 and S18 are performed. In step S17, a barrier layer 204 is formed in the first recess R1. In some embodiments, the barrier layer 204 is formed on the sidewall 205SW of the polymer liner 205, on the upper surface 205T of the polymer liner 205, on the sidewall 206SW of the isolation liner 206, and on the interconnect structure 201 exposed at the bottom BT of the first recess R1. The adhesion layer AL is conformally formed on the barrier layer 204. After performing step S17, the seed layer 203SD can be conformally formed on the adhesion layer AL. In step S18, a through substrate via 203 manufacturing technique includes depositing a conductive material in the first recess R1 and then performing a planarization operation, such as a chemical mechanical planarization (CMP) operation. Thus, the first semiconductor wafer 2A is formed.

[0158] Figure 5C The first semiconductor wafer 2A shown is similar to Figure 2KThe first semiconductor wafer 1A shown in FIG. 1 is different in that, in the first semiconductor wafer 2A, the upper surface 205T of the polymer liner 205 is located below the back surface 100B of the first substrate 100. The first semiconductor wafer 2A can be used in various types of semiconductor components, such as dynamic random access memory (DRAM), three-dimensional integrated circuits (3DIC), memory stacking, logic stacking, memory components, and the like. In some embodiments, in order to form the aforementioned semiconductor components, the first semiconductor wafer 2A can be stacked with other semiconductor wafers or semiconductor structures. Figure 5D , Figure 5E and Figure 6 Some embodiments are discussed.

[0159] Figure 5D is a cross-sectional schematic diagram illustrating an intermediate stage of the formation of a semiconductor element of some embodiments of the present disclosure. In steps S19 and S20, the first semiconductor wafer 2A is coupled to the second semiconductor wafer 2A', and an upper connector 305 is formed above the conductive pad 202 of the first semiconductor wafer 2A. In some embodiments, the first semiconductor wafer 2A is bonded to the second semiconductor wafer 2A' by performing a hybrid bonding operation. Next, an upper passivation layer 301, an upper barrier layer 303, and an upper connector 305 are formed above the back side 101B of the first passivation layer 101 of the first semiconductor wafer 2A, thereby obtaining the semiconductor element 1B. In some embodiments, the configuration of the second semiconductor wafer 2A' may be similar to Figure 5C The first semiconductor wafer 2A or Figure 2K The second semiconductor wafer 2A' comprises a first semiconductor wafer 1A having a configuration similar to that of FIG. Figure 2K The first substrate 100 of the first semiconductor wafer 2A is coupled to the second substrate 100' of the second semiconductor wafer 2A' via a hybrid bonding operation. Figures 2L to 2M The details of the hybrid joining operation are discussed above with reference to Figure 2N Details of the formation of the upper passivation layer 301 , the upper barrier layer 303 , and the upper connector 305 are discussed.

[0160] Figure 5E is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure. Figure 5E The semiconductor element 2C shown is similar to Figure 5D The semiconductor element 2B shown is different in that Figure 5E The depicted semiconductor component 2C includes more than two stacked semiconductor wafers in a stack. For example, one first semiconductor wafer 2A is coupled to more than one second semiconductor wafer 2A'. In such an embodiment, the hybrid bonding operation can be repeated.

[0161] Figure 6 is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure. Figure 6 The semiconductor element 2D shown is similar to Figure 5D The semiconductor element 2B is shown in FIG. 2D. The difference is that in the semiconductor element 2D, each of the first semiconductor wafer 2A and the second semiconductor wafer 2A′ may have two or more through-substrate vias 203 .

[0162] An embodiment of the present disclosure provides a semiconductor element, including a first substrate, including a front side and a back side parallel to the front side; a first passivation layer, located above the front side of the first substrate; a second passivation layer, located above the back side of the first substrate, wherein the second passivation layer has an upper surface facing away from the first substrate; a conductive feature, located in the first passivation layer, wherein the conductive feature includes a conductive pad and an interconnection structure electrically connected to the conductive pad; a through substrate via (TSV), penetrating the second passivation layer and the first substrate, wherein the through substrate via is electrically coupled to the conductive feature; a polymer liner, located between the through substrate via and the first substrate, wherein an upper surface of the polymer liner is lower than the upper surface of the second passivation layer; a barrier layer, located between the second passivation layer and the through substrate via, between the polymer liner and the through substrate via, and between the interconnection structure and the through substrate via; and an adhesive layer, located between the barrier layer and the through substrate via.

[0163] Another embodiment of the present disclosure provides a semiconductor element, including a first semiconductor wafer, including a first substrate, the first substrate having a front side and a back side parallel to the front side; a first passivation layer located above the front side of the first substrate and a second passivation layer located above the back side of the first substrate, wherein the second passivation layer has an upper surface facing away from the first substrate; a conductive feature located in the first passivation layer and a through-substrate via exposed through the second passivation layer and electrically coupled to the conductive feature; a polymer liner located between the through-substrate via and the first substrate; a barrier layer located between the second passivation layer and the through-substrate via, between the polymer liner and the through-substrate via, and between the conductive feature and the through-substrate via; an adhesive layer located between the barrier layer and the through-substrate via; and a second semiconductor wafer coupled to the first semiconductor wafer at a bonding interface and including a second substrate coupled to the first substrate. The polymer liner of the first semiconductor wafer is separated from the bonding interface.

[0164] Another embodiment of the present disclosure provides a method for preparing a semiconductor element, including forming a conductive feature in a first passivation layer above a front surface of a first substrate; forming a second passivation layer above a back surface of the first substrate; forming a first recess in an upper surface of the second passivation layer to expose the conductive feature; conformally forming an isolation liner on a side wall of the first recess; performing a pulse etching operation to conformally form a polymer liner on the side wall of the isolation liner, wherein an upper surface of the polymer liner is lower than the upper surface of the second passivation layer; conformally forming a barrier layer on the polymer liner and the isolation liner; conformally forming an adhesion layer on the barrier layer; and forming a conductive material in the first recess to form a through substrate via (TSV).

[0165] In summary, the present disclosure provides a semiconductor device having a polymer liner and a method for preparing the semiconductor device having a polymer liner.

[0166] In order to solve the problem of poor yield caused by expansion and deformation of conductive materials at high temperatures in hybrid bonding operations, the present disclosure provides a semiconductor element with a polymer liner. Specifically, since the polymer liner has good flexibility, the polymer liner can reduce the deformation of the through-substrate via or buffer the negative impact caused by the deformation of the through-substrate via. Therefore, the degree of deformation of the through-substrate via (especially in the vertical direction) can be reduced, and the stress concentration in the through-substrate via can be alleviated.

[0167] A shape of the polymer pad can be obtained by referring to Figure 2G The pulse etching operation conditions discussed are controlled, for example Figure 2G' The first type of pulsed etching operation as depicted in Figure 2G” The second type of pulse etching operation is depicted in FIG. As a result, the following can be obtained: Figure 2K The first semiconductor wafer 1A with the polymer liner 205 shown in FIG. Figure 5C A first semiconductor wafer 2A is shown having a polymer liner 205 .

[0168] The first semiconductor wafer 1A and the first semiconductor wafer 2A can be used in a stacked structure to form various types of devices, such as Figure 2M , Figure 2N , Fig.2O , Figure 3 , Figure 5D , Figure 5E or Figure 6 The above-mentioned semiconductor device or semiconductor structure manufacturing technology may include bonding a plurality of substrates or wafers together using a hybrid bonding operation.

[0169] Furthermore, in pursuit of greater component density, the distance between adjacent pairs of through-substrate vias becomes increasingly smaller. Thus, the construction of the polymer liner can help reduce the number of semiconductor components with greater component density (e.g., Figure 3 The semiconductor device 1D or Figure 6 The electrical interference in the semiconductor device 2D) shown in the figure is used to improve the device performance.

[0170] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements may be made without departing from the spirit and scope of the present disclosure as defined in the claims. For example, many of the above processes may be implemented in different ways, and other processes or combinations thereof may be used to replace many of the above processes.

[0171] Furthermore, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. A person skilled in the art can understand from the disclosure of the present disclosure that existing or future developed processes, machines, manufactures, compositions of matter, means, methods, or steps that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. Accordingly, such processes, machines, manufactures, compositions of matter, means, methods, or steps are included in the claims of the present application.

Claims

1. A semiconductor element, comprising: A first substrate including a front surface and a back surface parallel to the front surface; a first passivation layer located above the front surface of the first substrate; a second passivation layer located above the back surface of the first substrate, wherein the second passivation layer has an upper surface facing away from the first substrate; a conductive feature in the first passivation layer, wherein the conductive feature comprises a conductive pad and an interconnect structure electrically connected to the conductive pad; a through substrate via (TSV) penetrating the second passivation layer and the first substrate, wherein the through substrate via is electrically coupled to the conductive feature; a polymer liner located between the through substrate via and the first substrate, wherein an upper surface of the polymer liner is lower than the upper surface of the second passivation layer; a barrier layer between the second passivation layer and the through substrate via, between the polymer liner and the through substrate via, and between the interconnect structure and the through substrate via; and An adhesive layer is located between the barrier layer and the through substrate via. 2 . The semiconductor device as claimed in claim 1 , further comprising a seed layer located between the adhesive layer and the through substrate via. 3 . The semiconductor device as claimed in claim 2 , further comprising an isolation liner located between the barrier layer and the second passivation layer and between the polymer liner and the first substrate. The semiconductor device as claimed in claim 1 , wherein the through substrate via extends to the first passivation layer. 5 . The semiconductor device of claim 1 , wherein the through substrate via comprises a first portion and a second portion, the second portion is located above the interconnect structure, and the first portion is located above the second portion and above the upper surface of the polymer liner. The semiconductor device as claimed in claim 5 , wherein a width of the first portion is greater than a width of the second portion. 7 . The semiconductor device of claim 1 , wherein a thickness of the polymer liner is between about 50 nm and about 500 nm. 8 . The semiconductor device as claimed in claim 3 , wherein the adhesion layer comprises titanium, tantalum, titanium tungsten or manganese nitride. 9 . The semiconductor device as claimed in claim 3 , wherein the seed layer comprises copper or ruthenium.

10. The semiconductor device of claim 3, wherein the barrier layer comprises cobalt, titanium, titanium nitride, ruthenium, tantalum, tantalum nitride, indium oxide, tungsten nitride, nickel boride, or a tantalum nitride / tantalum double layer.

11. The semiconductor device as claimed in claim 3, wherein the polymer liner comprises a fluorine-based polymer. 12 . The semiconductor device as claimed in claim 6 , wherein a width of the conducting pad is different from a width of the first portion.

13. A semiconductor element, comprising: A first semiconductor wafer comprises a first substrate having a front surface and a back surface parallel to the front surface; A first passivation layer located above the front surface of the first substrate and a second passivation layer located above the back surface of the first substrate, wherein the second passivation layer has an upper surface facing away from the first substrate; a conductive feature in the first passivation layer and a through substrate via exposed through the second passivation layer and electrically coupled to the conductive feature; a polymer liner located between the through substrate via and the first substrate; a barrier layer between the second passivation layer and the through substrate via, between the polymer liner and the through substrate via, and between the conductive feature and the through substrate via; an adhesive layer disposed between the barrier layer and the through substrate via; as well as a second semiconductor wafer coupled to the first semiconductor wafer at a bonding interface and comprising a second substrate coupled to the first substrate, The polymer liner of the first semiconductor wafer is separated from the bonding interface. 14 . The semiconductor device of claim 13 , wherein the first passivation layer comprises a back surface parallel to the front surface of the first substrate, and the conductive feature is exposed through the back surface of the first passivation layer.

15. The semiconductor device of claim 14, further comprising an upper connector located above the conductive feature.

16. The semiconductor device of claim 15, further comprising an upper barrier layer between the upper connector and the conductive feature. 17 . The semiconductor device as claimed in claim 16 , further comprising an upper passivation layer located above the back surface of the first passivation layer, wherein the upper barrier layer is located in the upper passivation layer. 18 . The semiconductor device as claimed in claim 17 , wherein the upper passivation layer comprises polybenzoxazole, polyimide, benzocyclobutene, a solder mask, or a combination thereof.

19. The semiconductor device as claimed in claim 17, wherein the upper barrier layer comprises aluminum fluoride and zinc oxide. 20 . The semiconductor device as claimed in claim 19 , wherein a concentration of zinc oxide in the upper barrier layer is greater than a concentration of aluminum fluoride in the upper barrier layer.

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