ESD structure and semiconductor device

Abstract

The invention provides an ESD structure, which comprises a substrate, and an isolation well region, at least one first well region and at least one second well region which are located in the substrate, the first well region and the second well region are alternately arranged along a predetermined direction, the isolation well region is located outside the first well region and the second well region, and the first well region and the second well region are alternately arranged along the predetermined direction. The first well region is internally provided with a first contact region, the second well region is internally provided with two second contact regions which are arranged at intervals along the preset direction, and the isolation well region is internally provided with an isolation contact region; one of the first well region, the isolation well region, the isolation contact region and the second well region has a first doping type, and the other one of the second well region, the first contact region and the second well region has a second doping type. The ESD structure is small in area, and the area of the device can be greatly saved. In addition, the invention also provides a semiconductor device comprising the ESD structure.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to an ESD structure and a semiconductor device. Background Art

[0002] Electrostatic discharge (ESD) is ubiquitous in the manufacturing, packaging, testing and use of devices. The accumulated static charge is released in nanoseconds to microseconds with a current of several amperes or tens of amperes. The instantaneous power is as high as hundreds of kilowatts, and the discharge energy can reach millijoules, which has a great destructive intensity on the device. Therefore, the design of the ESD structure in the device design is directly related to the functional stability of the device and is extremely important.

[0003] With the development of technology, the feature size of devices has gradually become smaller, and the design difficulty of ESD structures has further increased. At present, ESD structures occupy a large device area, thereby limiting the further miniaturization of devices. Summary of the invention

[0004] The purpose of the present application is to provide an ESD structure and a semiconductor device to solve the problem that the existing ESD structure has a large area.

[0005] In order to achieve the above-mentioned object, the present application provides an ESD structure, including a substrate and an isolation well region, at least one first well region and at least one second well region located in the substrate, wherein the first well region and the second well region are alternately arranged along a predetermined direction, the isolation well region is located outside the first well region and the second well region, the first well region has a first contact region, the second well region has two second contact regions arranged at intervals along the predetermined direction, and the isolation well region has an isolation contact region;

[0006] One of the first well region, the isolation well region, the isolation contact region and the second well region has a first doping type, and another of the second well region, the first contact region and the second well region has a second doping type.

[0007] Optionally, the second contact region is used to connect to a high potential, and the isolation contact region and the first contact region are used to connect to a low potential.

[0008] Optionally, the isolation well region is ring-shaped and is arranged around the first well region and the second well region.

[0009] Optionally, one of the first doping type and the second doping type is N-type, and the other is P-type.

[0010] Optionally, in the same second well region, the second contact region having the first doping type and the second contact region having the second doping type are arranged sequentially along the predetermined direction; or, in the same second well region, the second contact region having the second doping type and the second contact region having the first doping type are arranged sequentially along the predetermined direction.

[0011] Optionally, the first well region and the isolation well region are an integrated structure.

[0012] Optionally, the first well region and the isolation well region are independent of each other.

[0013] Optionally, the substrate further has an isolation structure, and the isolation structure is located between adjacent first contact regions and second contact regions, between two adjacent second contact regions, and between the isolation contact region and the first contact region and the second contact region.

[0014] Optionally, all the first well regions are an integrated structure; or, each of the first well regions is independent of each other.

[0015] The present invention also provides a semiconductor device, comprising the ESD structure.

[0016] In the ESD structure provided in the present application, it includes a substrate and an isolation well region located in the substrate, at least one first well region and at least one second well region, the first well region and the second well region are alternately arranged along a predetermined direction, the isolation well region is located outside the first well region and the second well region, the first well region has a first contact region, the second well region has two second contact regions arranged at intervals along the predetermined direction, and the isolation well region has an isolation contact region; one of the second contact regions in the first well region, the isolation well region, the isolation contact region and the second well region has a first doping type, and the other of the second contact regions in the second well region, the first contact region and the second well region has a second doping type. The ESD structure in the present application has a large antistatic ability, basically does not change the performance of the device, and has a small area, which can greatly save the area of ​​the device. Correspondingly, the present application also provides a semiconductor device including the above-mentioned ESD structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a planar schematic diagram of an ESD structure;

[0018] Figure 2 for Figure 1 Schematic diagram of the cross section of the ESD structure along the AA direction;

[0019] Figure 3 for Figure 2Equivalent circuit diagram of the ESD structure in;

[0020] Figure 4 A schematic plan view of the ESD structure provided in Example 1 of the present application;

[0021] Figure 5 for Figure 4 Schematic diagram of the cross section of the ESD structure along the AA direction;

[0022] Figure 6 A schematic diagram of an ESD structure provided in Example 2 of the present application;

[0023] Wherein, the accompanying drawings are marked as follows:

[0024] 100, 200 - substrate; 101, 201 - first well region; 111, 211 - first contact region; 102, 202 - second well region; 112, 212 - second contact region; 103 - isolation well region; 113 - isolation contact region; 104, 204 - isolation structure. DETAILED DESCRIPTION

[0025] Figure 1 It is a planar schematic diagram of an ESD structure. Figure 2 for Figure 1 The cross-sectional diagram of the ESD structure along the AA direction. Figure 1 and Figure 2 As shown, there is an ESD structure including a substrate 200 and at least one first well region 201 and at least one second well region 202 located in the substrate 200, wherein the first well region 201 and the second well region 202 are alternately arranged along a predetermined direction, and all the first well regions 201 may be an integral structure or may be independent of each other. Figure 1 2 shows that all the first well regions 201 are an integrated structure. The first well region 201 has two first contact regions 211 arranged at intervals along the predetermined direction, and the second well region 202 has two second contact regions 212 arranged at intervals along the predetermined direction. An isolation structure 204 is provided between adjacent first contact regions 211 and second contact regions 212, between two adjacent first contact regions 211, and between two adjacent second contact regions 212.

[0026] The substrate 200, one of the first contact regions 211 in the first well region 201 has a first doping type, and another of the first contact regions 211 has a second doping type; one of the second contact regions 212 in the second well region 202 has the first doping type, and another of the second contact regions 212 has the second doping type, and the contact regions with the first doping type (the first contact region 211 or the second contact region 212) and the contact regions with the second doping type (the first contact region 211 or the second contact region 212) are arranged alternately. The first contact region 211 is used to connect to a low potential, which can usually be grounded to VSS, and the second contact region 212 is used to connect to a high potential, which can usually be connected to a power supply VDD.

[0027] Taking the first doping type as P type and the second doping type as N type as an example, Figure 2 The doping types of the four contact regions in the embodiment are P-type, N-type, P-type, and N-type from left to right, and the doping types of the first well region 201 and the second well region 202 are P-type and N-type, respectively. At this time, the N-type first contact area 211, the P-type substrate 200 and the N-type second well area 202 constitute an NPN transistor, and the N-type first contact area 211, the P-type substrate 200 and the N-type second well area 202 are respectively the emitter, base and collector of the NPN transistor; the P-type second contact area 212, the N-type second well area 202 and the P-type substrate 200 constitute a PNP transistor, and the P-type second contact area 212, the N-type second well area 202 and the P-type substrate 200 are respectively the emitter, base and collector of the PNP transistor; the resistance of the substrate 200 at the bottom of the first well area 201 can be equivalent to the resistance Rp, and the internal resistance of the second well area 202 can be equivalent to the resistance Rn, and finally it can be obtained as follows Figure 3 The equivalent circuit diagram is shown.

[0028] like Figure 3As shown, the emitter of the PNP transistor is connected to one end of the resistor Rn and the power supply VDD, the base of the PNP transistor is connected to the other end of the resistor Rn and the collector of the NPN transistor, the collector of the PNP transistor is connected to the base of the NPN transistor and one end of the resistor Rp, and the other end of the resistor Rp is connected to the emitter of the NPN transistor and then connected to the ground VSS. When static electricity is generated, the static electricity reaches the ESD structure through VDD. At this time, the PNP transistor is turned on first (there is a resistor Rn on the other path, so the static electricity will first go through the path with the PNP transistor). After the PNP transistor is turned on, the voltage on its collector increases, so that the NPN transistor is turned on, and the static electricity can be introduced into the ground VSS to achieve ESD protection. However, the first well region 201 and the second well region 202 of this ESD structure both have two doping regions, which are large in area and will occupy a large device area, thereby limiting the further miniaturization of the device.

[0029] Based on this, the present application provides an ESD structure, including a substrate and an isolation well region located in the substrate, at least one first well region and at least one second well region, the first well region and the second well region are alternately arranged along a predetermined direction, the isolation well region is located outside the first well region and the second well region, the first well region has a first contact region, the second well region has two second contact regions arranged at intervals along the predetermined direction, and the isolation well region has an isolation contact region; one of the second contact regions in the first well region, the isolation well region, the isolation contact region and the second well region has a first doping type, and the other of the second contact regions in the second well region, the first contact region and the second well region has a second doping type. The ESD structure in the present application has a large antistatic ability, basically does not change the performance of the device, and has a small area, which can greatly save the area of ​​the device. Correspondingly, the present application also provides a semiconductor device including the above-mentioned ESD structure.

[0030] The specific implementation of the present application will be described in more detail below in conjunction with the schematic diagram. Based on the following description, the advantages and features of the present application will become clearer. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present application.

[0031] Embodiment 1

[0032] Figure 4 A schematic plan view of the ESD structure provided in an embodiment of the present application, Figure 5 for Figure 4 The cross-sectional diagram of the ESD structure along the AA direction. Figure 4 and Figure 5As shown, the ESD structure includes a substrate 100 and an isolation well region 103, at least one first well region 101, and at least one second well region 102 located in the substrate 100, wherein the isolation well region 103, the first well region 101, and the second well region 102 all extend from the surface of the substrate 100 to the inside of the substrate 100. In this embodiment, the isolation well region 103, the first well region 101, and the second well region 102 have the same depth, but this should not be limiting.

[0033] Specifically, the first well region 101 and the second well region 102 may be arranged alternately along a predetermined direction. In this embodiment, the predetermined direction is Figure 4 , but should not be limited thereto. The first well region 101 has a first contact region 111, which extends from the surface of the first well region 101 to the inside of the first well region 101; the second well region 102 has two second contact regions 112 arranged at intervals along the predetermined direction, which extend from the surface of the second well region 102 to the inside of the second well region 102. The isolation well region 103 is located outside the first well region 101 and the second well region 102, and has an isolation contact region 113 in the isolation well region 103, which extends from the surface of the isolation well region 103 to the inside of the isolation well region 103. The first contact region 111, the second contact region 112 and the isolation contact region 113 are all doped regions. The substrate 100, the first well region 101, the isolation well region 103, the isolation contact region 113, and one of the second well regions 102, the second contact region 112 have a first doping type, and the second well region 102, the first contact region 111, and another of the second well regions 102, the second contact region 112 have a second doping type. One of the first doping type and the second doping type is N-type, and the other is P-type.

[0034] In this embodiment, in the same second well region 102, the second contact region 112 having the first doping type and the second contact region 112 having the second doping type are arranged in sequence along the predetermined direction. In some embodiments, in the same second well region 102, the second contact region 112 having the second doping type and the second contact region 112 having the first doping type are arranged in sequence along the predetermined direction. That is, the arrangement of the two second contact regions 112 of the doping type in the second well region 102 is not limited.

[0035] In this embodiment, the isolation well region 103 is annular and surrounds the first well region 101 and the second well region 102, which can reduce the resistance of the substrate 100. In some embodiments, the isolation well region 103 can also be in other shapes, such as a straight shape, a C shape, or an L shape, that is, the isolation well region 103 does not necessarily need to surround the first well region 101 and the second well region 102. For example, it can be set on one side of the first well region 101 and the second well region 102, and this application does not limit it.

[0036] Since the first well region 101 and the isolation well region 103 have the same doping type, in this embodiment, the first well region 101 and the isolation well region 103 are an integrated structure. At this time, the isolation well region 103 and the first well region 101 are connected as one piece, which can reduce the difficulty of preparation and save preparation costs. In this case, all the first well regions 101 can be an integrated structure, so that all the first well regions 101 are connected as one piece with the isolation well region 103; of course, each of the first well regions 101 can also be independent of each other, so that all the first well regions 101 can be connected as one piece through the isolation well region 103.

[0037] Furthermore, the substrate 100 further has an isolation structure 104, which extends from the surface of the substrate 100 into the substrate 100, and the isolation structure 104 may be a trench isolation structure 104. The isolation structure 104 is located between adjacent first contact regions 111 and second contact regions 112, between two adjacent second contact regions 112, and between the isolation contact region 113 and the first contact region 111 and the second contact region 112, so as to achieve isolation.

[0038] In this embodiment, the second contact area 112 is used to connect to a high potential, usually connected to the power supply VDD; the isolation contact area 113 and the first contact area 111 are used to connect to a low potential, usually connected to the ground VSS. Taking the first doping type as P type and the second doping type as N type as an example, Figure 5The doping types of the four contact regions (the isolation contact region 113, the first contact region 111 and the two second contact regions 112) are P-type, N-type, P-type and N-type from left to right, respectively; the doping types of the first well region 101 and the isolation well region 103 are P-type, and the doping type of the second well region 102 is N-type. At this time, the N-type first contact region 111, the P-type substrate 100 and the N-type second well region 102 constitute an NPN transistor, and the N-type first contact region 111, the P-type substrate 100 and the N-type second well region 102 are respectively the emitter, base and collector of the NPN transistor; the P-type second contact region 112, the N-type second well region 102 and the P-type substrate 100 constitute a PNP transistor, and the P-type second contact region 112, the N-type second well region 102 and the P-type substrate 100 are respectively the emitter, base and collector of the PNP transistor; the resistance of the substrate 100 at the bottom of the first well region 101 (the isolation well region 103) can be equivalent to a resistance Rp, and the internal resistance of the second well region 102 can be equivalent to a resistance Rn, and finally the following can be obtained: Figure 3 The equivalent circuit diagram shown in FIG. Similarly, the emitter of the PNP transistor in this embodiment is connected to the power supply VDD with one end of the resistor Rn, the base of the PNP transistor is connected to the other end of the resistor Rn and the collector of the NPN transistor, the collector of the PNP transistor is connected to the base of the NPN transistor and one end of the resistor Rp, and the other end of the resistor Rp is connected to the emitter of the NPN transistor and then to the ground VSS. When static electricity is generated, the static electricity reaches the ESD structure through VDD. At this time, the PNP transistor is turned on first. After the PNP transistor is turned on, the voltage on its collector increases, causing the NPN transistor to be turned on. Static electricity can be introduced into the ground VSS to achieve ESD protection. It can be seen that compared to Figure 1 and Figure 2 The ESD structure in this embodiment also has the same anti-static ability and basically does not change the performance of the device. Moreover, since the first well region 101 only includes one first contact region 111, the size of the ESD structure can be reduced, which greatly saves the area of ​​the device.

[0039] It should be noted that when the doping types of two different second contact regions in the second well region 102 are exchanged, the type of the formed transistor may also change, but this does not affect the implementation of the present application.

[0040] Furthermore, this embodiment also provides a semiconductor device, including the above-mentioned ESD structure.

[0041] Embodiment 2

[0042] Figure 6Schematic diagram of the ESD structure provided in this embodiment. Figure 6 As shown, the difference from the first embodiment is that in this embodiment, the first well region 101 and the isolation well region 103 are independent of each other. At this time, all the first well regions 101 can be an integrated structure, and each of the first well regions 101 can also be independent of each other.

[0043] In summary, the ESD structure provided in the embodiment of the present application includes a substrate 100 and an isolation well region 103, at least one first well region 101 and at least one second well region 102 located in the substrate 100, the first well region 101 and the second well region 102 are arranged alternately along a predetermined direction, the isolation well region 103 is located outside the first well region 101 and the second well region 102, the first well region 101 has a first contact region 111, the second well region 102 has two second contact regions 112 arranged at intervals along the predetermined direction, and the isolation well region 103 has an isolation contact region 113; the first well region 101, the isolation well region 103, the isolation contact region 113 and one of the second well region 102 have a first doping type, and the second well region 102, the first contact region 111 and the other of the second well region 102 have a second doping type. The ESD structure in the present application has a large antistatic capability, does not substantially change the performance of the device, and has a small area, which can greatly save the area of ​​the device. Accordingly, the present application also provides a semiconductor device including the above-mentioned ESD structure.

[0044] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referred to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0045] It should also be noted that, although the present application has been disclosed as above with preferred embodiments, the above embodiments are not intended to limit the present application. For any technician familiar with the art, without departing from the scope of the technical solution of the present application, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present application, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still falls within the scope of protection of the technical solution of the present application.

[0046] It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are merely used to distinguish between the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0047] It should also be recognized that the terms described herein are only used to describe specific embodiments and are not used to limit the scope of the present application. It should be noted that the singular forms "one" and "a kind" used herein and in the appended claims include plural references unless the context clearly indicates the opposite meaning. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps and secondary devices. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have a definition of logical "or", rather than a definition of logical "exclusive or", unless the context clearly indicates the opposite meaning. In addition, the implementation of the method and / or device in the embodiment of the present application may include performing the selected task manually, automatically, or in combination.

Claims

1. An ESD structure, characterized in that: The method comprises a substrate and an isolation well region, at least one first well region and at least one second well region in the substrate, wherein the first well region and the second well region are alternately arranged along a predetermined direction, the isolation well region is located outside the first well region and the second well region, the first well region has a first contact region, the second well region has two second contact regions arranged at intervals along the predetermined direction, and the isolation well region has an isolation contact region; One of the first well region, the isolation well region, the isolation contact region and the second well region has a first doping type, and another of the second well region, the first contact region and the second well region has a second doping type.

2. The ESD structure according to claim 1, wherein: The second contact region is used for connecting to a high potential, and the isolation contact region and the first contact region are used for connecting to a low potential.

3. The ESD structure according to claim 1, wherein: The isolation well region is ring-shaped and is arranged around the first well region and the second well region.

4. The ESD structure according to claim 1, wherein: One of the first doping type and the second doping type is N-type, and the other is P-type.

5. The ESD structure according to any one of claims 1 to 4, wherein: In the same second well region, the second contact region having the first doping type and the second contact region having the second doping type are arranged sequentially along the predetermined direction; or, in the same second well region, the second contact region having the second doping type and the second contact region having the first doping type are arranged sequentially along the predetermined direction.

6. The ESD structure according to claim 1, wherein: The first well region and the isolation well region are an integrated structure.

7. The ESD structure according to claim 1, wherein: The first well region and the isolation well region are independent of each other.

8. The ESD structure according to claim 6 or 7, characterized in that: The substrate also has an isolation structure therein, and the isolation structure is located between adjacent first contact regions and second contact regions, between two adjacent second contact regions, and between the isolation contact region and the first contact region and the second contact region.

9. The ESD structure according to claim 6 or 7, characterized in that: All the first well regions are an integrated structure; or, each of the first well regions is independent of each other.

10. A semiconductor device, characterized in that: The invention comprises the ESD structure according to any one of claims 1 to 9.

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