Semiconductor device and method of forming fan-out package structure with embedded

Abstract

A semiconductor device has an electrical component and a first interconnect structure disposed adjacent to the electrical component. The electrical component may be a direct metal-bonded semiconductor die or a flip-chip semiconductor die. The first interconnect structure may be an interposer cell or a conductive pillar. A split antenna is disposed over the electrical component and the first interconnect structure. The split antenna has a first antenna section and a second antenna section with an adhesive material disposed between the first antenna section and the second antenna section. A second interconnect structure is formed over the electrical component and the first interconnect structure. The second interconnect structure has one or more conductive layers and an insulating layer. The first interconnect structure and the second interconnect structure provide a conductive path between the electrical component and the split antenna. An encapsulant is deposited around the electrical component and the first interconnect structure.

Description

Technical Field

[0001] The present invention relates generally to semiconductor devices, and more particularly to semiconductor devices and methods of forming a fan-out package structure with an embedded overhang backside antenna. Background Art

[0002] Semiconductor devices are commonly found in modern electronic products. Semiconductor devices perform a wide range of functions such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, optoelectronics, and creating visual images for television displays. Semiconductor devices are found in the fields of communications, power conversion, networking, computers, entertainment, and consumer products. Semiconductor devices are also found in military applications, aviation, automobiles, industrial controllers, and office equipment.

[0003] Semiconductor devices, especially in high frequency applications such as radio frequency (RF) wireless communications, typically contain one or more integrated passive devices (IPDs) to perform necessary electrical functions. Multiple semiconductor dies and IPDs can be integrated into a system-in-package (SiP) module for higher density and expanded electrical functionality in a small space. Within the SiP module, the semiconductor die and IPD are disposed on a first surface of a substrate for structural support and electrical interconnection. An encapsulant is deposited over the semiconductor die, IPD, and substrate.

[0004] The antenna can be arranged on the second surface of the substrate to provide wireless communication for the SiP module. With the addition of the antenna, the SiP constitutes an antenna-in-package (AiP). AiPs become large due to performance and functionality. AiPs can be manufactured at the wafer level or panel level. However, the current wafer and panel level AiP approaches lack flexibility in material options, in addition to long manufacturing cycle times due to sequential processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1a-1e illustrates a semiconductor wafer having a plurality of semiconductor dies separated by saw streets;

[0006] Figure 2a-2f illustrates a process of forming a split antenna segment for an AiP module;

[0007] Figure 3a-3f A process of forming an interposer unit is illustrated;

[0008] Figure 4a-4b illustrates mounting an interposer unit to a split antenna section;

[0009] Figure 5a-5k illustrates disposing an interposer unit and a split antenna segment over and around an electrical component having an interconnect structure;

[0010] Figure 6a-6b The diagram shows the settings in the Figure 5a-5k additional details of the interposer unit and split antenna sections on and around the electrical components;

[0011] Figure 7a-7b Conductive posts and split antenna segments disposed over and around electrical components are illustrated;

[0012] Figure 8a-8g Another embodiment of disposing an interposer unit and a split antenna segment over and around an electrical component having an interconnect structure is illustrated;

[0013] Fig. 9 The diagram shows the settings in the Figure 8a-8g Additional details of the electrical components on and around the interposer unit and split antenna sections; and

[0014] Fig.10 A printed circuit board (PCB) is illustrated, with different types of packages arranged on a surface of the PCB. DETAILED DESCRIPTION

[0015] In the following description with reference to the figures, the present invention is described in one or more embodiments, wherein like numbers represent the same or similar elements. Although the present invention is described in terms of the best mode for achieving the purposes of the invention, it will be appreciated by those skilled in the art that the present invention is intended to cover substitutions, modifications and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents, as supported by the following disclosure and the accompanying drawings. The term "semiconductor die" as used herein refers to both the singular and plural forms of the word, and thus may refer to both a single semiconductor device and a plurality of semiconductor devices.

[0016] Semiconductor devices are typically manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves forming multiple die on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components such as transistors and diodes have the ability to control the flow of current. Passive electrical components such as capacitors, inductors, and resistors create a relationship between voltage and current that is necessary to perform the circuit function.

[0017] Back-end manufacturing refers to cutting or singulating the completed wafer into individual semiconductor die, and packaging the semiconductor die for structural support, electrical interconnection and environmental isolation. In order to singulate the semiconductor die, the wafer is scribed and broken along the non-functional area of ​​the wafer (called saw road or scribing line). The wafer is singulated using a laser cutting tool or a saw blade. After singulation, the individual semiconductor die is arranged on a package substrate, which includes pins or contact pads for interconnection with other system components. Then, the contact pads formed on the semiconductor die are connected to the contact pads in the package. Electrical connection can be made with a conductive layer, a bump, a columnar bump, a conductive paste or a bonding wire. Encapsulant or other molding materials are deposited on the package to provide physical support and electrical isolation. The completed package is then inserted into the electrical system, and the functionality of the semiconductor device is made available to other system components.

[0018] Figure 1a A semiconductor wafer 100 is shown having a base substrate material 102 such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk material for structural support. A plurality of semiconductor die or components 104 are formed on the wafer 100, which is separated by non-active, inter-die wafer regions or saw streets 106. The saw streets 106 provide a cutting area to singulate the semiconductor wafer 100 into individual semiconductor die 104. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100-450 millimeters (mm). The semiconductor die 104 can process RF signals transmitted and received by an antenna.

[0019] Figure 1b A cross-sectional view of a portion of a semiconductor wafer 100 is shown. Each semiconductor die 104 has a back or inactive surface 108 and an active surface 110 that contains analog or digital circuitry implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuitry may include one or more transistors, diodes, and other circuit elements formed within the active surface 110 to implement analog or digital circuitry, such as a digital signal processor (DSP), an application specific integrated circuit (ASIC), memory, or other signal processing circuitry. The semiconductor die 104 may also include IPDs for RF signal processing, such as inductors, capacitors, and resistors.

[0020] Conductive layer 112 is formed over active surface 110 using PVD, CVD, electrolytic plating, chemical plating process or other suitable metal deposition process. Conductive layer 112 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag) or other suitable conductive materials. Conductive layer 112 serves as a contact pad or conductive post or pillar electrically connected to the circuit on active surface 110.

[0021] The insulating layer 114 is formed on the active surface 110 and the conductive layer 112. The insulating layer 114 can be formed using PVD, CVD, printing, lamination, spin coating, spray coating, sintering or thermal oxidation. The insulating layer 114 contains one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), solder resist, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO) and other materials with similar insulating and structural properties. A portion of the insulating layer 114 is removed using an etching process or laser direct ablation (LDA) to expose the conductive layer 112.

[0022] exist Figure 1c 1 , a saw blade or laser cutting tool 116 is used to singulate the semiconductor wafer 100 through the saw streets 106 into individual semiconductor dies 104. In one embodiment, the semiconductor dies 104 are direct metal bonded semiconductor dies. The individual semiconductor dies 104 can be inspected and electrically tested to identify known good dies or units (KGD / KGU) after singulation.

[0023] In another embodiment, from Figure 1a Next, a conductive layer 120 is formed over the active surface 110 using PVD, CVD, electrolytic plating, chemical plating or other suitable metal deposition process, such as Figure 1d Conductive layer 120 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials. Conductive layer 120 serves as a contact pad electrically connected to the circuit on active surface 110.

[0024] An insulating layer 122 is formed over the active surface 110 and the conductive layer 120. The insulating layer 122 may be formed using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, or thermal oxidation. The insulating layer 122 may include one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO, and other materials having similar insulating and structural properties. A portion of the insulating layer 122 may be removed using an etching process or LDA to expose the conductive layer 120.

[0025] Conductive bump material is deposited on the conductive layer 120 using evaporation, electrolytic plating, chemical plating, ball drop or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder and combinations thereof, with optional flux solution. For example, the bump material can be eutectic Sn / Pb, high lead solder or lead-free solder. The bump material is bonded to the conductive layer 120 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a ball or bump 124. In one embodiment, the bump 124 is formed on an under-bump metallization (UBM) having a wetting layer, a barrier layer and an adhesive layer. The bump 124 can also be compression bonded or thermocompressed to the conductive layer 120. The bump 124 represents a type of interconnect structure that can be formed on the conductive layer 120. The interconnect structure can also use bonding wires, conductive pastes, columnar bumps, micro bumps or other electrical interconnects.

[0026] exist Figure 1e 1 , the semiconductor wafer 100 is singulated into individual semiconductor dies 126 through the saw streets 106 using a saw blade or laser cutting tool 116. In one embodiment, the semiconductor dies 126 are flip-chip semiconductor dies. The individual semiconductor dies 126 can be inspected and electrically tested to identify known good dies or units (KGD / KGU) after singulation.

[0027] Figure 2a-2f The process of forming separate or split antenna sections is illustrated. Figure 2a A cross-sectional view of an interconnect and antenna substrate 130 is shown, which includes a core material 132, such as Ajinomoto built-up film (ABF), pre-impregnated polytetrafluoroethylene (PTFE) (prepreg or PPG), a multi-layer flexible laminate, or other dielectric material. In one embodiment, the core material 132 is a low-loss dielectric PPG with fillers, fibers, and resins or polymers. In another embodiment, the core material 132 is stacked with fillers and resins or polymers. Alternatively, the core material 132 can be an epoxy molding compound (EMC), a polymer matrix composite material, a resin or polymer with fillers and fibers, a polyimide dielectric, and one or more conductive layers. The core material 132 can be a combination of woven glass, matte glass, FR-4, FR-1, CEM-1 or CEM-3, and phenolic cotton paper, epoxy resin, polyester and other reinforcing fibers or fabrics. The core material 132 can be a multi-layer ceramic, a copper clad laminate (CCL), glass, or an epoxy molding compound with fillers. The substrate 130 has a major surface 134 and a major surface 136 opposite to the surface 134 .

[0028] exist Figure 2bIn the embodiment, a plurality of through holes 140 extending through the substrate 130 between the surface 134 and the surface 136 are formed through the core material 132 by an etching process or LDA using a laser 142. Figure 2c In the embodiment, the via 140 is filled with a conductive material to form a conductive via 144. The conductive via 144 may be Al, Cu, Sn, Ni, Au, Ag, a multi-layer combination, or other suitable conductive materials.

[0029] exist Figure 2d In the embodiment, a conductive layer 146 is formed on the surface 134 using PVD, CVD, electrolytic plating, chemical plating process or other suitable metal deposition process. The conductive layer 146 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials.

[0030] An insulating layer 148 is formed over the surface 134 and the conductive layer 146. The insulating layer 148 may be formed using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, or thermal oxidation. The insulating layer 148 may include one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO, and other materials having similar insulating and structural properties. An etching process or LDA is used to remove a portion of the insulating layer 148 to form an opening 150 exposing the conductive layer 146.

[0031] Conductive layer 152 is formed over surface 136 using PVD, CVD, electrolytic plating, chemical plating process or other suitable metal deposition process. Conductive layer 152 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials. Conductive layer 152 is electrically connected to conductive pillar 144 and serves as an antenna for transmitting and receiving RF signals of later formed electrical components 196. Conductive layer 146 is electrically connected to conductive pillar 144 to provide electrical communication through substrate 130 to conductive layer 152 through conductive via 144.

[0032] Insulating layer 154 is formed over surface 136 and conductive layer 152. Insulating layer 154 may be formed using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, or thermal oxidation. Insulating layer 154 may include one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO, and other materials having similar insulating and structural properties.

[0033] exist Figure 2e15, an etching process or LDA using a laser 156 is used to partially singulate substrate 130 to form antenna segments 157a, 157b, 157c, and 157d. Antenna segment 157b and antenna segment 157c will be separated during final singulation. Antenna substrate 158 with split antenna segments 157a-157d can use a laminate substrate or wafer / panel level process.

[0034] Figure 3a A cross-sectional view of an interconnect substrate or interposer 160 including a core material 161 is shown, such as ABF, PTFE prepreg or PPG, a multi-layer flexible laminate, or other dielectric material. In one embodiment, the core material 161 is a low-loss dielectric PPG with fillers, fibers, and resins or polymers. In another embodiment, the core material 161 is stacked with fillers and resins or polymers. Alternatively, the core material 161 can be a multi-layer flexible laminate or other dielectric material. Alternatively, the core material 161 can be an EMC, a polymer matrix composite, a resin or polymer with fillers and fibers, a polyimide dielectric, and one or more conductive layers. The core material 161 can be a combination of woven glass, matte glass, FR-4, FR-1, CEM-1 or CEM-3, and phenolic cotton paper, epoxy resin, polyester, and other reinforcing fibers or fabrics. The core material 161 can be a multi-layer ceramic, CCL, glass, or epoxy resin molding compound with fillers. The substrate 160 has a major surface 162 and a major surface 164 opposite to the surface 162 .

[0035] Similar to Figure 2b A plurality of through holes extending through the substrate 160 between the surface 162 and the surface 164 are formed through the core material 161 by an etching process or LDA. Figure 3b In the embodiment, the vias are filled with a conductive material to form conductive vias 168. Conductive vias 168 may be Al, Cu, Sn, Ni, Au, Ag, a multi-layer combination, or other suitable conductive materials.

[0036] exist Figure 3c In the embodiment of the present invention, a conductive layer 170 is formed on the surface 162 using PVD, CVD, electrolytic plating, chemical plating process or other suitable metal deposition process. The conductive layer 170 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials. The conductive layer 170 is electrically connected to the conductive pillar 168.

[0037] Insulating layer 172 is formed over surface 162 and conductive layer 170. Insulating layer 172 may be formed using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, or thermal oxidation. Insulating layer 172 may include one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO, and other materials having similar insulating and structural properties.

[0038] Conductive layer 174 is formed over surface 164 using PVD, CVD, electrolytic plating, chemical plating process or other suitable metal deposition process. Conductive layer 174 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials. Conductive layer 174 is electrically connected to conductive pillars 168 to provide electrical communication between conductive layers 170 and 174 through interconnect substrate 160.

[0039] Insulating layer 176 is formed over surface 164 and conductive layer 174. Insulating layer 176 may be formed using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, or thermal oxidation. Insulating layer 176 may include one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO, and other materials having similar insulating and structural properties.

[0040] exist Figure 3d In the example embodiment, an etching process or LDA using a laser 180 is used to singulate the interconnect substrate or interposer 160 to form individual interposer units 178 .

[0041] Figure 3eA first type of interposer unit 186 is shown, in which a portion of the insulating layer 172 is removed using an etching process or LDA to form an opening exposing the conductive layer 170. Similarly, a portion of the insulating layer 176 is removed using an etching process or LDA to form an opening exposing the conductive layer 174. A conductive bump material is deposited over the conductive layer 174 using an evaporation, electrolytic plating, chemical plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn / Pb, high lead solder, or lead-free solder. The bump material is bonded to the conductive layer 174 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a ball or bump 184. In one embodiment, the bump 184 is formed over a UBM having a wetting layer, a barrier layer, and an adhesive layer. Bump 184 may also be compression bonded or thermocompression bonded to conductive layer 174. Bump 184 represents a type of interconnect structure that may be formed over conductive layer 174. The interconnect structure may also use bonding wires, conductive paste, stud bumps, micro bumps, or other electrical interconnects. A conductive path is provided through interposer unit 186, including conductive layer 170, conductive via 168, conductive layer 174, and bump 184.

[0042] Figure 3f Shows something like Figure 3e A second type of interposer unit 190 is shown in which a portion of the insulating layer 172 is removed using an etching process or LDA to form an opening exposing the conductive layer 170. Figure 3e , a bump 188 is formed over the exposed conductive layer 170. A complete conductive path is provided through the substrate 160 of the interposer unit 190, including the bump 188, the conductive layer 170, the conductive via 168, the conductive layer 174, and the bump 184. The interposer units 186 and 190 represent prefabricated embedded trace substrates (ETS) made with laminate substrates or wafer / panel level processes.

[0043] exist Figure 4a In, from Figure 3e A plurality of interposer elements 186a, 186b, 186c, and 186d are disposed over the surface 134 of the interconnect and antenna substrate 158 to electrically and mechanically connect to the conductive layer 146. Using a pick and place operation, the interposer elements 186a-186d are each positioned over the antenna segments 157a-157d, respectively. The interposer elements 186a-186d are brought into contact with the conductive layer 146. The bumps 184 are reflowed to mechanically and electrically connect the interposer elements 186a-186d to the conductive layer 146. Figure 4bInterposer elements 186 a - 186 d are shown mechanically and electrically connected to conductive layer 146 of interconnect and antenna substrate 158 as semiconductor assembly 192 .

[0044] Figure 5a A temporary substrate or carrier 191 is shown containing a sacrificial base material 193, such as silicon, polymer, beryllium oxide, glass, metal, or other suitable low-cost rigid material for structural support. The substrate 191 has a major surface 195 and a major surface 197 opposite to the surface 195. In one embodiment, the carrier 191 is a support structure having a temporary bonding layer 199 formed on the surface 195 of the carrier. The temporary bonding layer 199 can be a double-sided tape. The temporary bonding layer can also be a penetrable material, such as a polymer, epoxy resin, acrylic B-stage material, or other similar materials with penetrable properties. The penetrable material can be applied by PVD, CVD, printing, spin coating, spray coating, slit coating, roller coating, lamination, or sintering.

[0045] exist Figure 5b In the embodiment, a plurality of electrical components 196a-196b are disposed over a surface 195 of a carrier 191. For example, electrical components 196a-196b are positioned over carrier 191 using a pick and place operation. In one embodiment, electrical components 196a and 196b may be similar to those from Figure 1c 1 and 10. The semiconductor die 104 is shown with the active surface 110 and the conductive pillars 112 oriented toward the surface 195 of the carrier 191. Alternatively, the electrical components 196a-196b may include other semiconductor dies, semiconductor packages, surface mount devices, discrete electrical devices, or IPDs.

[0046] Similar to Figure 4a , electrical components 196a-196b are brought into contact with bonding layer 199. Electrical components 196a-196b, such as direct metal bonded semiconductor die 104, are bonded to or embedded in layer 199 using a strip-level or cell-level bonding process under pressure from force F1.

[0047] exist Figure 5c In, from Figure 4b The semiconductor assembly 192 is disposed on the surface 195 of the carrier 191. An adhesive or bonding material 155 such as epoxy is deposited on the surface 108 of the electrical components 196a and 196b. The material 155 can also be an insulating or conductive material for heat dissipation or EMI shielding. Under the pressure from the force F2, the conductive layer 170 and / or the insulating layer 172 in the semiconductor assembly 192 are made to contact the bonding layer 199. Figure 5dSemiconductor assembly 192 is shown bonded to or embedded in layer 199. Adhesive material 155 is forced between antenna segment 157a and antenna segment 157b, and also between antenna segment 157c and antenna segment 157d, to maintain the structural integrity of antenna substrate 158. Interposer elements 186a and 186b are disposed on opposite sides of and adjacent to electrical component 196a, and interposer elements 186c and 186d are disposed on opposite sides of and adjacent to electrical component 196b. The cut joint antenna segment with interposer elements is attached to a temporary bonding tape on a carrier, with additional adhesive dispensed to bond the antenna to the back side of the die to aid in positioning the antenna in molding.

[0048] exist Figure 5e In the process, sealant or molding compound 200 is deposited on and around semiconductor assembly 192 and electrical components 196a-196b using paste printing, compression molding, transfer molding, liquid sealant molding, vacuum lamination, spin coating or other suitable applicators. In one embodiment, sealant 200 is applied using film-assisted vacuum pressure molding to seal the antenna segments, interposer unit and electrical components. Sealant 200 fills the gap between antenna segments 157a and 157b, and the gap between antenna segments 157c and 157d. Sealant 200 can be a polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with appropriate filler. Sealant 200 is non-conductive, provides structural support, and environmentally protects the semiconductor device from external elements and contaminants.

[0049] exist Figure 5f In the embodiment, the carrier 191 and the bonding layer 199 are removed by chemical etching, chemical mechanical polishing (CMP), mechanical stripping, mechanical grinding, thermal baking, ultraviolet (UV) light, or wet stripping to expose the conductive layer 170.

[0050] exist Figure 5g In the embodiment, an insulating layer 210 is formed over the electrical components 196a-196b and the encapsulant 200. The insulating layer 210 can be formed using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, or thermal oxidation. The insulating layer 210 includes one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO, and other materials having similar insulating and structural properties.

[0051] Conductive layer 212 is formed over insulating layer 210 and conductive layer 112 of electrical components 196a-196b using PVD, CVD, electrolytic plating, chemical plating process, or other suitable metal deposition process. Conductive layer 212 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. Portions of conductive layer 212 may be electrically shared or electrically isolated, depending on the design and function of the electrical components attached thereto. Conductive layer 212 is a redistribution layer (RDL) because it redistributes electrical signals across and over electrical components 196a-196b and encapsulant 200.

[0052] exist Figure 5h In the embodiment, insulating layer 214 is formed on insulating layer 210 and conductive layer 212. Insulating layer 214 can be formed using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, or thermal oxidation. Insulating layer 214 includes one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO, and other materials having similar insulating and structural properties.

[0053] Conductive layer 216 is formed over insulating layer 214 and conductive layer 212 using PVD, CVD, electrolytic plating, chemical plating process, or other suitable metal deposition process. Conductive layer 216 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. Portions of conductive layer 216 may be electrically shared or electrically isolated, depending on the design and function of the electrical components attached thereto. Conductive layer 216 is an RDL because it redistributes electrical signals across and over conductive layer 212.

[0054] Insulating layer 218 is formed over insulating layer 214 and conductive layer 216. Insulating layer 218 may be formed using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, or thermal oxidation. Insulating layer 218 may include one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO, and other materials having similar insulating and structural properties.

[0055] Conductive bump material is deposited on the conductive layer 216 using evaporation, electrolytic plating, chemical plating, ball drop or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder and combinations thereof, with optional flux solution. For example, the bump material can be eutectic Sn / Pb, high lead solder or lead-free solder. The bump material is bonded to the conductive layer 216 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a ball or bump 220. In one embodiment, the bump 220 is formed on the UBM having a wetting layer, a barrier layer and an adhesive layer. The bump 220 can also be compression bonded or thermocompressed bonded to the conductive layer 216. The bump 220 represents a type of interconnect structure that can be formed on the conductive layer 216. The interconnect structure can also use bonding wires, conductive pastes, columnar bumps, micro bumps or other electrical interconnects. The combination of the conductive layers 212 and 216 , the insulating layers 210 , 214 , and 218 , and the bumps 220 constitute an interconnect structure 221 .

[0056] exist Figure 5i In the process, a portion of the sealant 200 is removed by a grinding operation using a grinder 222 to planarize a surface 224 of the insulating layer 154 . Figure 5j A planarized surface 224 of the insulating layer 154 on the semiconductor assembly 226 is shown.

[0057] exist Figure 5k 2 , semiconductor assembly 226 is singulated between antenna sections 157b and 157c into individual antenna packages (AiPs) 230a and 230b using a saw blade or laser 228. AiP 230a has split antenna sections 157a and 157b, and AiP 230b has split antenna sections 157c and 157d.

[0058] Figure 6aAdditional details of AiP 230a with electrical component 196a are shown, which makes electrical connections to split antenna segments 157a and 157b through interconnect structure 226, interposer units 184a and 184b, conductive layer 146, and conductive vias 144. In a similar manner, AiP 230b with electrical component 196b makes electrical connections to split antenna segments 157c and 157d through interconnect structure 226, interposer units 184c and 184d, conductive layer 146, and conductive vias 144. It is worth noting that AiPs 230a-230b use split antenna segments 157a-157d made from laminate substrates or wafer / panel level processes. AiPs 230a-230b use interposer units 184a-184b made from laminate substrates or wafer / panel level processes. Antenna segments 157a-157d are fabricated separately from interposer units 186a-186d. Antenna segment 157a is split from antenna segment 157b. Antenna segment 157b is split from antenna segment 157c, and antenna segment 157c is split from antenna segment 157d. Antenna segments 157a-157b fan out of or overhang electrical component 196a, and antenna segments 157c-157d fan out of or overhang electrical component 196b. Antenna segments 157a-157d may be the same material or a different material than interposer units 186a-186d for warpage control, structural balance, and reliability. AiP 230a-230b includes split antenna segments 157a-157d, separated interposer units 186a-186d, separated electrical components 196a-196b as an over-molded, fan-out reconstructed wafer or panel or strip. The interconnect structure 221 with RDL and separated interposer units 186a-186d provides electrical communication between electrical components 196a-196b and antenna segments 157a-157d. Interposer units 186a-186d can provide signal conduction paths, as well as power and ground. Interposer unit 186 is an interconnect structure disposed adjacent to or around electrical components 196a-196b. Figure 6b is a top view of AiP 230 a having antenna segments 157 a and 157 b and conductive layer 152 .

[0059] In another embodiment, similar to Figure 6a , an AiP 244 having conductive pillars 240 formed through the encapsulant 200 replaces the interposer units 184a-184d, as shown Figure 7a. Components having similar functions are given the same reference numerals. Bump 242 enables electrical connection between conductive pillar 240 and conductive layer 146. AiP 244 with electrical component 196a enables electrical connection to split antenna segments 157a and 157b through interconnect structure 226, conductive pillar 240, bump 242, conductive layer 146 and conductive via 144. Conductive pillar 240 can provide a signal conduction path, as well as power and ground. Conductive pillar 240 is an interconnect structure disposed adjacent to or around electrical components 196a-196b. Figure 7b is a top view of AiP 244 having antenna segments 157 a and 157 b and conductive layer 152 .

[0060] At least two split antenna units and dies with interposers or Cu rods for interconnection are embedded and overmolded in a fan-out reconstructed wafer or panel / strip with the active side and interposer side facing down, in addition to adhesive on at least one side of the split antenna units and dies. Alternatively, split antenna units with flip-chip interposers or Cu strips, or plated Cu columns and IC dies with Cu columns are embedded and overmolded in a fan-out reconstructed wafer or panel / strip with the active side and interposer side facing up, and followed by grinding to expose the CuI / O pads. The RDL stack is stacked on the die and interposer to form a complete circuit between the die and the antenna. Prior to the RDL stacking process on the reconstructed wafer or panel, the active surface of the electrical components 196a-196b can be at the same level as the surface of the conductive column 240, recessed therein, or protruding above it using appropriate back grinding, strippable protective layer, or selective etching process.

[0061] In another embodiment, Figure 8a A cross-sectional view of an interconnect substrate 260 having a plurality of conductive layers 250 is shown, the plurality of conductive layers 250 being made of one or more layers of Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials. The conductive layer 250 may be formed using PVD, CVD, electrolytic plating, chemical plating processes or other suitable metal deposition processes. The conductive layer 250 provides horizontal electrical interconnections across the substrate 260 and vertical electrical interconnections through the substrate 260. Depending on the design and function of various subsequently formed electrical components, portions of the conductive layer 250 may be electrically shared or electrically isolated. The insulating layer 252 comprises one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO and other materials having similar insulating and structural properties. The insulating layer 252 may be formed using PVD, CVD, printing, lamination, spin coating, spray coating, sintering or thermal oxidation. The insulating layer 252 provides isolation between the conductive layers 250. There may be multiple conductive layers, such as 250 , separated by multiple insulating layers, such as 252 .

[0062] Insulating layer 256 is formed on surface 253 of interconnect layer 260. Insulating layer 256 can be formed using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, or thermal oxidation. Insulating layer 256 includes one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO, and other materials with similar insulating and structural properties. A portion of insulating layers 250 and 256 is removed by etching or LDA to form an opening and expose conductive layer 250.

[0063] Conductive layer 254 is formed in the opening of insulating layer 256 using PVD, CVD, electrolytic plating, chemical plating process or other suitable metal deposition process. Conductive layer 254 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials. Portions of conductive layer 254 can be electrically shared or electrically isolated, depending on the design and function of the electrical components attached thereto. Conductive layer 254 can be a conductive post for electrical interconnection.

[0064] exist Figure 8b In the embodiment, a plurality of electrical components 262a and 262b are disposed over the surface 255 of the interconnect substrate 260 using a pick and place operation. In one embodiment, the electrical components 262a and 262b may be similar to those from Figure 1e 1 and 2. The semiconductor die 126 of FIG. 1 may have bumps 124 oriented toward surface 255. Alternatively, electrical components 262a-262b may include other semiconductor dies, semiconductor packages, surface mount devices, discrete electrical devices, or IPDs. Figure 5c , an adhesive or bonding material 155 such as epoxy is deposited on the surface 108 of the electrical components 262a and 262b. Components having similar functions are given the same reference numerals. Under pressure from force F2, the conductive layer 170 and / or insulating layer 172 in the semiconductor assembly 192 is brought into contact with the bonding layer 199.

[0065] Figure 5dA semiconductor assembly 192 is shown bonded to or embedded in layer 199. Adhesive material 155 is forced between antenna segment 157a and antenna segment 157b, and also between antenna segment 157c and antenna segment 157d, to maintain the structural integrity of antenna substrate 158. Interposer units 190a and 190b are disposed on opposite sides of and adjacent to electrical component 262a, and interposer units 190c and 190d are disposed on opposite sides of and adjacent to electrical component 262b. Bumps 124, such as flip-chip semiconductor dies 126, of electrical components 262a-262b are brought into contact with conductive layer 250 and reflowed to mechanically and electrically connect to interconnect substrate 260 using a strip-level or unit-level bonding process. An optional underfill material 264, such as an epoxy, is deposited around and beneath electrical components 262a-262b.

[0066] Figure 8c A semiconductor assembly 266 is shown, similar to that from Figure 5c-5d A semiconductor assembly 192, wherein the semiconductor assembly 192 is Figure 3f The semiconductor assembly 266 is disposed on the surface 255 of the interconnect substrate 260, wherein the interposer units 190a and 190b are disposed on opposite sides of and adjacent to the electrical component 262a, and the interposer units 190c and 190d are disposed on opposite sides of and adjacent to the electrical component 262b.

[0067] exist Figure 8d In the process, sealant or molding compound 270 is deposited on and around semiconductor assembly 266, electrical components 262a-262b, and interconnect substrate 260 using paste printing, compression molding, transfer molding, liquid sealant molding, vacuum lamination, spin coating, or other suitable applicators. In one embodiment, sealant 270 is applied using film-assisted vacuum pressure molding to seal the antenna segments, interposer unit, and electrical components. Sealant 270 fills the gap between antenna segments 157a and 157b, and the gap between antenna segments 157c and 157d. Sealant 270 can be a polymer composite material, such as an epoxy resin with filler, an epoxy acrylate with filler, or a polymer with appropriate filler. Sealant 270 is non-conductive, provides structural support, and environmentally protects the semiconductor device from external elements and contaminants.

[0068] exist Figure 8e In the process, a portion of the sealant 270 is removed by a grinding operation using a grinder 272 to planarize a surface 274 of the insulating layer 154 . Figure 8f A planarized surface 274 of insulating layer 154 on semiconductor assembly 276 is shown.

[0069] Conductive bump material is deposited on conductive layer 254 using evaporation, electrolytic plating, chemical plating, ball drop or screen printing process. Bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder and combinations thereof, with optional flux solution. For example, bump material can be eutectic Sn / Pb, high lead solder or lead-free solder. Bump material is bonded to conductive layer 254 using a suitable attachment or bonding process. In one embodiment, bump material is reflowed by heating material above its melting point to form ball or bump 282. In one embodiment, bump 282 is formed on UBM having wetting layer, barrier layer and adhesive layer. Bump 282 can also be compression bonded or thermocompression bonded to conductive layer 254. Bump 282 represents a type of interconnect structure that can be formed on conductive layer 254. Interconnect structure can also use bonding wire, conductive paste, columnar bump, micro bump or other electrical interconnect. The combination of conductive layer 250 , insulating layer 252 , and bumps 282 form an interconnect structure 284 .

[0070] exist Figure 8g 2, semiconductor assembly 276 is singulated between antenna sections 157b and 157c into individual AiPs 280a and 280b using a saw blade or laser 288. AiP 280a has separate antenna sections 157a and 157b, and AiP 280b has separate antenna sections 157c and 157d.

[0071] Fig. 9 Additional details of AiP 280a with electrical component 262a are shown, which makes electrical connection to split antenna segments 157a and 157b through interconnect structure 284, interposer units 190a and 190b, conductive layer 146, and conductive via 144. In a similar manner, AiP 280b with electrical component 262b makes electrical connection to split antenna segments 157c and 157d through interconnect structure 284, interposer units 190c and 190d, conductive layer 146, and conductive via 144. Interposer unit 190 is an interconnect structure disposed adjacent to or around electrical components 262a-262b. Additional adhesive is applied between the IC and antenna segments to enhance bonding and position the antenna during reflow. Solder mask laminate or second molding material and thickness can be used for mechanical support and reliability improvement.

[0072] Fig.10 An electrical device 400 is illustrated having a chip carrier substrate or PCB 402 with a plurality of semiconductor packages, including AiPs 230a, 244, and 280a, disposed on a surface of the PCB 402. The electrical device 400 may have one type of semiconductor package, or multiple types of semiconductor packages, depending on the application.

[0073] The electrical device 400 may be a stand-alone system that uses a semiconductor package to perform one or more electrical functions. Alternatively, the electrical device 400 may be a subcomponent of a larger system. For example, the electrical device 400 may be part of a tablet device, a cellular phone, a digital camera, a communication system, or other electrical devices. Alternatively, the electrical device 400 may be a graphics card, a network interface card, or other signal processing cards that may be inserted into a computer. The semiconductor package may include a microprocessor, a memory, an ASIC, a logic circuit, an analog circuit, an RF circuit, a discrete device, or other semiconductor die or electrical components. Miniaturization and weight reduction are essential for the product to be accepted by the market. The distance between semiconductor devices may be reduced to achieve higher density.

[0074] exist Fig.10 In the embodiment of the present invention, PCB 402 provides a general substrate for structural support and electrical interconnection of semiconductor packages disposed on the PCB. Conductive signal traces 404 are formed on the surface or in layers of PCB 402 using evaporation, electrolytic plating, chemical plating, screen printing or other suitable metal deposition processes. Signal traces 404 provide electrical communication between each semiconductor package, mounted components and other external system components. Traces 404 also provide power and ground connections for each semiconductor package.

[0075] In some embodiments, the semiconductor device has two packaging levels. The first level packaging is a technology for mechanically and electrically attaching a semiconductor die to an intermediate substrate. The second level packaging involves mechanically and electrically attaching the intermediate substrate to a PCB. In other embodiments, the semiconductor device may have a first level packaging, wherein the die is mechanically and electrically disposed directly on the PCB. For purposes of illustration, several types of first level packaging are shown on PCB 402, including wire bonding packages 406 and flip chips 408. Additionally, several types of second level packaging including ball grid arrays (BGA) 410, bump chip carriers (BCC) 412, land grid arrays (LGA) 416, multi-chip modules (MCM) or SIP modules 418, quad flat no-lead packages (QFN) 420, quad flat packages 422, embedded wafer level ball grid arrays (eWLB) 424, and wafer level chip size packages (WLCSP) 426 are shown disposed on PCB 402. In one embodiment, eWLB 424 is a fan-out wafer level package (Fo-WLP) and WLCSP 426 is a fan-in wafer level package (Fi-WLP). Depending on the system requirements, any combination of semiconductor packages configured with any combination of first and second level package types, as well as other electrical components can be connected to PCB 402. In some embodiments, electrical device 400 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate prefabricated components into electrical devices and systems. Because semiconductor packages include complex functionality, electrical devices can be manufactured using less expensive components and streamlined manufacturing processes. The resulting device is less likely to fail and is less expensive to manufacture, resulting in lower costs to the consumer.

[0076] While one or more embodiments of the present invention have been described in detail, those skilled in the art will appreciate that modifications and adaptations may be made to those embodiments without departing from the scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor device, comprising: Electrical components; a first interconnect structure disposed adjacent to the electrical component; a split antenna disposed over the electrical component and the first interconnect structure; and A second interconnect structure is formed over the electrical component and the first interconnect structure.

2. The semiconductor device according to claim 1, wherein The split antenna includes a first antenna section and a second antenna section. 3 . The semiconductor device of claim 2 , further comprising an adhesive material disposed between the first antenna section and the second antenna section.

4. The semiconductor device according to claim 1, wherein: The first interconnect structure includes an interposer unit. 5 . The semiconductor device of claim 1 , further comprising an encapsulant deposited around the electrical component and the first interconnect structure.

6. A semiconductor device comprising: Electrical components; a first interconnect structure; and A split antenna is disposed over the electrical component and the first interconnect structure. 7 . The semiconductor device of claim 6 , further comprising a second interconnect structure formed over the electrical component and the first interconnect structure.

8. The semiconductor device according to claim 6, wherein: The split antenna includes a first antenna section and a second antenna section.

9. The semiconductor device according to claim 6, wherein: The first interconnect structure includes an interposer unit.

10. The semiconductor device of claim 6, further comprising an encapsulant deposited around the electrical component and the first interconnect structure.

11. A method for manufacturing a semiconductor device, comprising: Supply of electrical components; disposing a first interconnect structure adjacent to the electrical component; disposing a split antenna over the electrical component and the first interconnect structure; and A second interconnect structure is formed over the electrical component and the first interconnect structure.

12. The method according to claim 11, wherein: The split antenna includes a first antenna section and a second antenna section.

13. The method according to claim 11, wherein: The first interconnect structure includes an interposer unit.

14. The method according to claim 11, wherein: The first interconnect structure includes a conductive pillar.

15. The method of claim 11, further comprising depositing an encapsulant around the electrical component and the first interconnect structure.

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