Direct-current power supply protection circuit

Abstract

The embodiment of the invention provides a direct-current power supply protection circuit, which is characterized in that a drain electrode of a first PMOS (P-channel Metal Oxide Semiconductor) tube is connected with a first direct-current voltage input end of the direct-current power supply protection circuit, a source electrode of the first PMOS tube is connected with a first load end of the direct-current power supply protection circuit, and a grid electrode of the first PMOS tube is connected with a collector electrode of a first PNP (Positive-Negative-Positive) triode; the first PMOS transistor is used for outputting a direct current voltage input by a first direct current voltage input end to a first load end in a conduction state; one end of the first capacitor is connected with the first direct-current voltage input end and the base electrode of the first PNP triode, and the other end of the first capacitor is grounded; a base electrode of the first PNP triode is connected with a first direct current voltage input end, and an emitting electrode of the first PNP triode is connected with a source electrode of the first PMOS tube; the conduction voltage drop of the first PNP triode is lower than the conduction threshold voltage of the first PMOS transistor. The circuit has an anti-backflow function, is simple in structure, does not need an additional auxiliary power supply, and is lower in forward voltage drop and power consumption.

Description

Technical Field

[0001] The present application relates to the technical field of power supply protection, and in particular to a direct current power supply protection circuit. Background Art

[0002] The power circuit is the most critical link in circuit design. It is necessary not only to consider the corresponding functions, but also to consider power protection. In practical applications, there is often a situation where a large voltage is connected to the load end of the power supply, and the voltage at the load end is greater than the voltage at the input end of the power supply, resulting in current backflow and burning the equipment.

[0003] The commonly used method to prevent backflow is to connect a diode in series between the power input and the load, but the forward voltage drop of the diode is relatively large, and some circuits are sensitive to the voltage drop of the diode. For example, if the input is 5V, the diode voltage drop is 0.7V, and the output is only 4.3V. In other words, the smaller the voltage, the less suitable it is. If it is a high current occasion, the power consumption of the diode itself will also be very large. For example, when the output current is very large, the loss of the diode circuit is very large, which is obviously not suitable for high current occasions. In addition, MOS tubes are used to control the opening and closing of the output, but the control circuit of MOS tubes is often more complicated and even requires additional auxiliary power. Summary of the invention

[0004] The embodiment of the present application provides a DC power supply protection circuit to solve the problem in the prior art that a diode is connected in series between the power input terminal and the load terminal to prevent backflow, the forward voltage drop is large, and the power consumption of the diode is large in high current situations; and a MOS tube is used to prevent backflow, the control circuit of the MOS tube is relatively complex, and even an additional auxiliary power supply is required to solve the problem.

[0005] The embodiment of the present application provides a DC power protection circuit, the DC power protection circuit comprising a first PMOS tube, a first capacitor, and a first PNP transistor;

[0006] The drain of the first PMOS tube is connected to the first DC voltage input terminal of the DC power supply protection circuit, the source of the first PMOS tube is connected to the first load terminal of the DC power supply protection circuit, the gate of the first PMOS tube is connected to the collector of the first PNP transistor, and the first PMOS tube is used to output the DC voltage input from the first DC voltage input terminal to the first load terminal through the body diode of the first PMOS tube in the on state;

[0007] One end of the first capacitor is connected to the first DC voltage input terminal and the base of the first PNP transistor, and the other end of the first capacitor is grounded;

[0008] The base of the first PNP transistor is connected to the first DC voltage input terminal, and the emitter of the first PNP transistor is connected to the source of the first PMOS transistor;

[0009] The on-state voltage drop of the first PNP transistor is lower than the on-state threshold voltage of the first PMOS transistor.

[0010] In a possible design, the DC power supply protection circuit also includes a first voltage regulator tube, the anode of the first voltage regulator tube is connected to the gate of the first PMOS tube, the cathode of the first voltage regulator tube is connected to the source of the first PMOS tube, the voltage regulation value of the first voltage regulator tube is higher than the turn-on threshold voltage of the first PMOS tube, and the voltage regulation value of the first voltage regulator tube is lower than the maximum allowable value of the voltage difference between the gate voltage and the source voltage of the first PMOS tube.

[0011] In a possible design, the DC power supply protection circuit further includes a second PMOS transistor, a first NPN transistor, a second PNP transistor, and a first level input port;

[0012] The source of the second PMOS tube is connected to the second DC voltage input terminal of the DC power protection circuit, the drain of the second PMOS tube is connected to the second load terminal of the DC power protection circuit, the second DC voltage input terminal is connected to the first load terminal, and the second PMOS tube is used to output the DC voltage input from the second DC voltage input terminal to the second load terminal in the on state;

[0013] The base of the first NPN transistor is connected to the first level input port, the emitter of the first NPN transistor is grounded, the collector of the first NPN transistor is connected to the second DC voltage input terminal through a first resistor and a second resistor connected in series, the collector of the first NPN transistor is connected to one end of the first resistor, the other end of the first resistor is connected to the base of the second PNP transistor, one end of the second resistor is connected to the base of the second PNP transistor, and the other end of the second resistor is connected to the second DC voltage input terminal;

[0014] The emitter of the second PNP transistor is connected to the second DC voltage input terminal, the collector of the second PNP transistor is connected to the gate of the second PMOS transistor, and the conduction voltage drop of the second PNP transistor is lower than the conduction threshold voltage of the second PMOS transistor;

[0015] The DC power supply protection circuit is configured to input a high level to the first level input port if an overcurrent or a fault in the DC power supply protection circuit is detected, and otherwise input a low level to the first level input port.

[0016] In a possible design, the DC power supply protection circuit also includes a second voltage regulator tube, the anode of the second voltage regulator tube is connected to the gate of the second PMOS tube, the cathode of the second voltage regulator tube is connected to the source of the second PMOS tube, the voltage regulation value of the second voltage regulator tube is higher than the turn-on threshold voltage of the second PMOS tube, and the voltage regulation value of the second voltage regulator tube is lower than the maximum allowable value of the voltage difference between the gate voltage and the source voltage of the second PMOS tube.

[0017] In a possible design, the circuit further includes a sampling resistor and an overcurrent detection circuit;

[0018] The sampling resistor is connected in series in the DC power supply protection circuit, and the DC voltage output by the DC power supply reaches the load end of the DC power supply protection circuit through the sampling resistor;

[0019] The DC voltage input end of the sampling resistor is connected to the first port of the overcurrent detection circuit, and the DC voltage output end of the sampling resistor is connected to the second port of the overcurrent detection circuit;

[0020] The overcurrent detection circuit is configured to output a high level to the first level input port when the voltage difference between the DC voltage input terminal of the sampling resistor and the DC voltage output terminal of the sampling resistor is greater than a preset threshold, otherwise output a high level to the first level input port.

[0021] In one possible design, the overcurrent detection circuit includes an operational amplifier and a comparator;

[0022] The non-inverting input terminal of the operational amplifier is connected to the DC voltage input terminal of the sampling resistor, the inverting input terminal of the operational amplifier is connected to the DC voltage output terminal of the sampling resistor, the output terminal of the operational amplifier is connected to the inverting input terminal of the comparator, and the non-inverting input terminal of the comparator is connected to the reference voltage;

[0023] The operational amplifier is used to amplify the voltage difference between the voltage at the DC voltage input end of the sampling resistor and the voltage at the DC voltage output end of the sampling resistor into a proportional voltage, and output the proportional voltage to the inverting input end of the comparator;

[0024] The comparator is used to output a low level at the output end of the comparator when the proportional voltage is greater than the reference voltage, so as to control the overcurrent detection circuit to output a high level to the first level input port; otherwise, the comparator output end outputs a high level to control the overcurrent detection circuit to output a low level to the first level input port.

[0025] In a possible design, the overcurrent detection circuit further includes a second capacitor, one end of the second capacitor is connected to the DC voltage input end of the sampling resistor, and the other end of the second capacitor is grounded.

[0026] In one possible design, the overcurrent detection circuit further includes a fault latch circuit, and the fault latch circuit includes a second level input port and a third level input port;

[0027] The second level input port is connected to the comparator output terminal, and the fault latch circuit is configured as follows: when the third level input port inputs a high level, if the comparator output terminal inputs a low level to the second level input port, the overcurrent detection circuit is controlled to input a high level to the first level input port; when the third level input port inputs a low level, if the comparator output terminal inputs a high level to the second level input port, the overcurrent detection circuit is controlled to input a low level to the first level input port.

[0028] In one possible design, the fault latch circuit includes a second NPN transistor, a third PNP transistor, a fourth PNP transistor, a third NPN transistor, and a control port, wherein the control port is connected to a level conversion element, and the level conversion element is connected to the first level input port;

[0029] The base of the second NPN transistor is connected to the third level input port, the emitter of the second NPN transistor is grounded, and the collector of the second NPN transistor is connected to the base of the third PNP transistor;

[0030] The emitter of the third PNP transistor is connected to the power supply voltage of the DC power supply protection circuit, and the collector of the third PNP transistor is connected to the emitter of the fourth PNP transistor;

[0031] The base of the fourth PNP transistor is connected to the second level input port, and the collector of the fourth PNP transistor is connected to the base of the third NPN transistor;

[0032] The emitter of the third NPN transistor is grounded, and the collector of the third NPN transistor is connected to the control port;

[0033] The level conversion element is configured such that: when the control port outputs a low level to the level conversion element, the level conversion element outputs a high level to the first level input port; when the control port outputs a high level to the level conversion element, the level conversion element outputs a low level to the first level input port.

[0034] In a possible design, the level conversion element is a single chip microcomputer.

[0035] The DC power supply protection circuit provided in the embodiment of the present application has the following technical effects:

[0036] When a DC voltage is input to the first DC voltage input terminal, the DC voltage reaches the first load terminal through the body diode of the first PMOS tube. Since the first capacitor is connected to the first DC voltage input terminal, the first capacitor can be charged by the input DC voltage. Since the base of the first PNP transistor is connected to the first DC voltage input terminal and its emitter is connected to the source of the first PMOS tube, the base voltage of the first PNP transistor is greater than the emitter voltage and thus cannot be turned on. When the first load end is connected to a large voltage, causing the voltage of the first load end to be greater than the DC voltage input to the first DC voltage input end, since the voltage of the first capacitor cannot change suddenly, and one end of the first capacitor is connected to the base of the first PNP transistor, the base voltage of the first PNP transistor cannot change suddenly. At this time, the emitter voltage of the first PNP transistor is greater than the base voltage and is turned on, and the current can flow from the emitter to the collector of the first PNP transistor, thereby causing the gate voltage and source voltage difference of the first PMOS tube to be the conduction voltage drop of the first PNP transistor, which is lower than the conduction threshold voltage of the first PMOS tube. At this time, the first PMOS tube is cut off, preventing the current of the first load end from flowing back into the first DC voltage input end.

[0037] Since the forward voltage drop of the PMOS tube is much lower than the forward voltage drop of the diode, and the power consumption of the PMOS tube is also lower than that of the diode, the forward voltage drop and power consumption of the circuit are small when the circuit is used to prevent backflow. In addition, the circuit structure is simple, no additional auxiliary power supply is required, and the circuit cost is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0039] Figure 1 A schematic diagram of the DC power supply protection circuit structure provided in the embodiment of the present application Figure 1 ;

[0040] Figure 2 A schematic diagram of the structure of an overcurrent protection circuit provided in an embodiment of the present application;

[0041] Figure 3 A schematic diagram of the DC power supply protection circuit structure provided in the embodiment of the present application Figure 2 ;

[0042] Figure 4 A schematic diagram of the overcurrent detection circuit structure provided in an embodiment of the present application;

[0043] Figure 5A schematic diagram of the fault latch circuit structure provided in an embodiment of the present application.

[0044] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0045] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0046] In practical applications, the situation where a large voltage is connected to the load end of a power supply may be caused by a variety of reasons. For example, the device may be mistakenly connected to an external power supply with a higher voltage than its rated voltage. This wrong connection may cause the voltage at the load end to be higher than the voltage at the power input end, resulting in a current backflow that burns the device. In the prior art, diodes and MOS tubes are used to prevent current backflow. However, the forward voltage drop of the diode connected in series between the power input end and the load end is large, and the power consumption of the diode is large in high current situations. When using MOS tubes to prevent backflow, the control circuit of the MOS tube is relatively complicated and even requires an additional auxiliary power supply. Therefore, if the additional auxiliary power supply can be removed and the control circuit and control logic of the MOS tube can be simplified, the current backflow prevention function can be realized, and the types of components and PCB area can be reduced, thereby reducing circuit costs.

[0047] Therefore, in view of the problems of the prior art, the present application proposes a technical concept that the DC voltage input terminal is connected to the drain of the PMOS tube, and the source of the PMOS tube is connected to the load terminal; the DC voltage input terminal is connected to the base of the PNP transistor, one end of the capacitor is connected to the DC voltage input terminal and the base of the PNP transistor, and the other end of the capacitor is grounded. The collector of the PNP transistor is connected to the gate of the PMOS tube, and the emitter of the PNP transistor is connected to the source of the PMOS tube. The on-state voltage drop of the PNP transistor is lower than the on-state threshold voltage of the PMOS tube.

[0048] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0049] Figure 1 A schematic diagram of the DC power supply protection circuit structure provided in the embodiment of the present application Figure 1 ,like Figure 1 As shown, the DC power supply protection circuit includes:

[0050] The DC power supply protection circuit includes a first PMOS transistor Q1, a first capacitor C1, and a first PNP transistor Q2;

[0051] The drain of the first PMOS tube Q1 is connected to the first DC voltage input terminal Vin1 of the DC power supply protection circuit, the source of the first PMOS tube Q1 is connected to the first load terminal Load1 of the DC power supply protection circuit, the gate of the first PMOS tube Q1 is connected to the collector of the first PNP transistor Q2, the source of the first PMOS tube Q1 is also connected to the resistor R3, and the other end of the resistor R3 is grounded; the first PMOS tube Q1 is used to output the DC voltage input from the first DC voltage input terminal Vin1 to the first load terminal Load1 through the body diode of the first PMOS tube Q1 in the on state;

[0052] One end of the first capacitor C1 is connected to the first DC voltage input terminal Vin1 through the resistor R1, and the end of the first capacitor C1 connected to the resistor R1 is also connected to the base of the first PNP transistor Q2, and the other end of the first capacitor C1 is grounded;

[0053] The base of the first PNP transistor Q2 is connected to the first DC voltage input terminal Vin1, and the emitter of the first PNP transistor Q2 is connected to the source of the first PMOS transistor Q1;

[0054] The on-state voltage drop of the first PNP transistor Q2 is lower than the on-state threshold voltage of the first PMOS transistor Q1 .

[0055] The working principle of the above circuit is described below.

[0056] When a DC voltage is input to the first DC voltage input terminal Vin1, the DC voltage reaches the first load terminal Load1 through the body diode of the first PMOS transistor Q1. Since the first capacitor C1 is connected to the first DC voltage input terminal Vin1, the first capacitor C1 can be charged by the input DC voltage. Since the base of the first PNP transistor Q2 is connected to the first DC voltage input terminal Vin1 and its emitter is connected to the source of the first PMOS transistor Q1, the base voltage of the first PNP transistor Q2 is greater than the emitter voltage and thus cannot be turned on. When the first load terminal Load1 is connected to a large voltage, the voltage of the first load terminal Load1 is greater than the DC voltage input by the first DC voltage input terminal Vin1. Since the voltage of the first capacitor C1 cannot change suddenly, and one end of the first capacitor C1 is connected to the base of the first PNP transistor Q2, the base voltage of the first PNP transistor Q2 cannot change suddenly. At this time, the emitter voltage of the first PNP transistor Q2 is greater than the base voltage and is turned on. The current can flow from the emitter to the collector of the first PNP transistor Q2, resulting in the gate voltage and source voltage difference of the first PMOS tube Q1 being the conduction voltage drop of the first PNP transistor Q2, which is lower than the conduction threshold voltage of the first PMOS tube Q1. At this time, the first PMOS tube Q1 is cut off, preventing the current of the first load terminal Load1 from flowing back into the first DC voltage input terminal Vin1.

[0057] It should be noted that the voltage of the first capacitor C1 cannot change suddenly because of its physical properties. Since the voltage on the capacitor is determined by the amount of charge it stores, if the voltage on the capacitor is to change instantly, it means that the amount of charge needs to change instantly. Since current is the rate of charge change, instantaneous voltage change requires infinite current, which is impossible to achieve in actual circuits.

[0058] When Q2 is turned on, current can flow from the emitter of Q2 to the collector. Since the emitter of Q2 is connected to the source of Q1, and the collector is connected to the gate of Q1, this forms a path that pulls down the gate voltage of Q1. When Q2 is turned on, the gate voltage of Q1 will be close to its source voltage minus the conduction voltage drop of Q2 (usually a small positive value of about 0.7V, depending on the characteristics of Q2). Because the conduction of the first PMOS tube Q1Q1 depends on its gate-source voltage difference, when this voltage difference becomes very small (lower than the conduction threshold voltage of the first PMOS tube Q1), Q1 will be cut off to prevent the current of the first load terminal Load1 from flowing back to the first DC voltage input terminal Vin1.

[0059] Since traditional diodes have a fixed forward voltage drop (usually around 0.7V) when they are turned on, which is particularly significant in low-voltage applications, using diodes to prevent backflow will significantly reduce the output voltage. When using PMOS tubes instead of diodes, the forward voltage drop is mainly caused by the on-resistance of the PMOS tube. For a properly selected PMOS tube, this voltage drop can be very small (usually between tens of millivolts and hundreds of millivolts), which is much smaller than the forward voltage drop of the diode.

[0060] In addition, in high current applications, the power consumption of the diode is determined by the product of the current and the forward voltage drop, which may lead to large energy loss and heat generation. Since the on-resistance of the PMOS tube is small, its power consumption is much lower than that of the diode. This makes the circuit more efficient in high current applications.

[0061] At the same time, the circuit utilizes the characteristic that the voltage of the first capacitor C1 cannot change suddenly, and reduces the gate-source voltage difference of the first PMOS tube Q1 to the conduction voltage drop of the first PNP tube to cut off the first PMOS tube Q1. It has a simple structure and a small number of components, which can reduce the circuit cost and the area of ​​the PCB board.

[0062] Optional, such as Figure 1 As shown, the circuit also includes a first voltage regulator tube D1, the anode of the first voltage regulator tube D1 is connected to the gate of the first PMOS tube Q1, the cathode of the first voltage regulator tube D1 is connected to the source of the first PMOS tube Q1, the voltage regulation value of the first voltage regulator tube D1 is higher than the conduction threshold voltage of the first PMOS tube Q1, and the voltage regulation value of the first voltage regulator tube D1 is lower than the maximum allowable value of the voltage difference between the gate voltage and the source voltage of the first PMOS tube Q1. The gate of the first PMOS tube Q1 is also connected to a resistor R2, and the other end of the resistor R2 is grounded. Specifically, when the first DC voltage input terminal Vin1 inputs a DC voltage, the DC voltage reaches the first load terminal Load1 through the body diode of the first PMOS tube Q1. Since the base of the first PNP transistor Q2 is connected to the first DC voltage input terminal Vin1, and its emitter is connected to the source of the first PMOS tube Q1, the base voltage of the first PNP transistor Q2 is greater than the emitter voltage and thus cannot be turned on. At this time, the source voltage of the first PMOS tube Q1 is higher than the gate voltage, and the voltage difference is the voltage stabilization value of the first voltage regulator D1. Since the voltage stabilization value of the first voltage regulator D1 is greater than the conduction threshold voltage of the first PMOS tube Q1, the first PMOS tube Q1 can be turned on. When the gate-source voltage of the first PMOS tube Q1 is too high, the voltage stabilization value of the first voltage regulator D1 is lower than the maximum allowable voltage difference between the gate voltage and the source voltage of the first PMOS tube Q1, so the first PMOS tube can be protected from damage. The resistor R2 plays a role in current limiting.

[0063] exist Figure 1On the basis of the circuit shown, in order to prevent overcurrent or other faults from damaging the circuit, the DC power supply protection circuit provided in the embodiment of the present application may also include an overcurrent protection circuit. Figure 2 The schematic diagram of the overcurrent protection circuit structure provided in the embodiment of the present application is as follows: Figure 2 As shown, the overcurrent protection circuit includes:

[0064] A second PMOS transistor Q5, a first NPN transistor Q3, a second PNP transistor Q4, and a first level input port I01;

[0065] The source of the second PMOS tube Q5 is connected to the second DC voltage input terminal Vin2 of the DC power protection circuit, the drain of the second PMOS tube Q5 is connected to the second load terminal Load2 of the DC power protection circuit, the second DC voltage input terminal Vin2 is connected to the first load terminal Load1, and the gate of the second PMOS tube Q5 is grounded through the resistor R8; the second PMOS tube Q5 is used to output the DC voltage input from the second DC voltage input terminal Vin2 to the second load terminal Load2 in the on state;

[0066] The base of the first NPN transistor Q3 is connected to the first level input port I01 through the resistor R6, the emitter of the first NPN transistor Q3 is grounded, the emitter of the first NPN transistor Q3 is connected to the resistor R7, and the other end of the resistor R7 is connected to the base of the first NPN transistor Q3; the collector of the first NPN transistor Q3 is connected to the second DC voltage input terminal Vin2 through the first resistor R5 and the second resistor R4 connected in series, the collector of the first NPN transistor Q3 is connected to one end of the first resistor R5, the other end of the first resistor R5 is connected to the base of the second PNP transistor Q4, one end of the second resistor R4 is connected to the base of the second PNP transistor Q4, and the other end of the second resistor R4 is connected to the second DC voltage input terminal Vin2;

[0067] The emitter of the second PNP transistor Q4 is connected to the second DC voltage input terminal Vin2, the collector of the second PNP transistor Q4 is connected to the gate of the second PMOS transistor Q5, and the conduction voltage drop of the second PNP transistor Q4 is lower than the conduction threshold voltage of the second PMOS transistor Q5;

[0068] The DC power protection circuit is configured to input a high level to the first level input port I01 if an overcurrent or a DC power protection circuit fault is detected in the DC power protection circuit, and otherwise input a low level to the first level input port I01.

[0069] The working principle of the overcurrent protection circuit is described below.

[0070] During normal operation, the DC power supply protection circuit can input a low level to the first level input port I01 through the level output device. Since the emitter of the first NPN transistor Q3 is grounded, the first NPN transistor Q3 is turned off, one end of the first resistor R5 is connected to the base of the second PNP transistor Q4, and the other end is connected to the collector of the first NPN transistor. Since the first NPN transistor is turned off, no current passes through the first resistor R5 and the second resistor R4, and there is no voltage difference between the emitter voltage and the base voltage of the second PNP transistor Q4, and the second PNP transistor Q4 is turned off. Since the gate of the second PMOS transistor Q5 is grounded through the resistor R8, the source of the second PMOS transistor Q5 is connected to the second DC voltage input terminal Vin2, therefore, the source voltage of the second PMOS transistor Q5 is higher than the gate voltage, the second PMOS transistor Q5 is turned on, and the input DC voltage reaches the second load terminal Load2 through the second PMOS transistor Q5.

[0071] When overcurrent or fault is detected in the circuit, the DC power supply protection circuit can input a high level to the first level input port I01 through the level output device, the base voltage of the first NPN transistor Q3 is higher than the emitter voltage, the first NPN transistor Q3 is turned on, and the first resistor R5 is connected to the ground through the first NPN transistor Q3. At this time, the first resistor R5 and the second resistor R4 divide the voltage input by the second DC voltage input terminal Vin2, the base of the second PNP transistor Q4 is connected to the first resistor R5 and the second resistor R4, and the emitter is connected to the second DC voltage input terminal Vin2, the emitter voltage of the second PNP transistor Q4 is higher than the base voltage, the second PNP transistor Q4 is turned on, the voltage difference between the source and the gate of the second PMOS tube Q5 is the turn-on voltage of the second PNP transistor Q4, which is lower than the turn-on threshold voltage of the second PMOS tube Q5, and Q5 is cut off, thereby shutting down the power supply voltage output.

[0072] Optional, such as Figure 2 As shown, optional, such as Figure 1 As shown, the circuit also includes a second voltage regulator tube D2, the anode of the second voltage regulator tube D2 is connected to the gate of the second PMOS tube Q5, the cathode of the second voltage regulator tube D2 is connected to the source of the second PMOS tube Q5, the voltage regulation value of the second voltage regulator tube D2 is higher than the conduction threshold voltage of the second PMOS tube Q5, and the voltage regulation value of the second voltage regulator tube D2 is lower than the maximum allowable value of the voltage difference between the gate voltage and the source voltage of the second PMOS tube Q5. The function of the second voltage regulator tube D2 is to protect the second PMOS tube Q5 from being damaged due to excessive gate-source voltage difference, and its principle is the same as that of the first voltage regulator tube D1, which will not be repeated here.

[0073] To realize the function of overcurrent detection in the circuit, optionally, in the embodiment of the present application, the DC power supply protection circuit may further include an overcurrent detection circuit and a sampling resistor. Figure 3A schematic diagram of the DC power supply protection circuit structure provided in the embodiment of the present application Figure 2 ,like Figure 3 As shown, the sampling resistor R9 is connected in series in the DC power supply protection circuit, and the DC voltage output by the DC power supply reaches the load end of the DC power supply protection circuit through the sampling resistor R9. Figure 3 In the example, one end of the sampling resistor R9 is connected to the DC power supply DC, and the other end is connected to the first DC voltage input terminal Vin1 and the capacitor C2. The capacitor C2 can be used to filter out high-frequency noise in the voltage signal across the sampling resistor R9, stabilize the voltage across the sampling resistor R9, absorb transient voltage spikes, and reduce the impact of voltage fluctuations of the power supply or other circuit parts on overcurrent detection.

[0074] The DC voltage input end of the sampling resistor R9 is connected to the first port V+ of the overcurrent detection circuit, and the DC voltage output end of the sampling resistor R9 is connected to the second port V- of the overcurrent detection circuit;

[0075] The overcurrent detection circuit is configured to output a high level to the first level input port IO1 when the voltage difference between the DC voltage input terminal of the sampling resistor R9 and the DC voltage output terminal of the sampling resistor R9 is greater than a preset threshold, otherwise output a low level to the first level input port IO1.

[0076] It should be noted that when the circuit is working normally, there will be a voltage difference when the current flows through the two ends of the sampling resistor R9. The larger the current, the larger the voltage difference. Figure 3 It can be seen that the overcurrent detection circuit inputs the voltage of the DC voltage input end of the sampling resistor R9 through the first port V+, and inputs the voltage of the DC voltage output end of the sampling resistor R9 through the second port V-, thereby detecting the voltage difference across the sampling resistor R9. Therefore, when there is an overcurrent in the circuit, the larger current makes the voltage difference across the sampling resistor R9 greater than the preset threshold, and the overcurrent detection current can be controlled accordingly. In the above-mentioned overcurrent protection circuit, the power output can be turned off by outputting a high level to the first level input port IO1, and the circuit can work normally by outputting a low level to the first level input port IO1.

[0077] Figure 4 The schematic diagram of the overcurrent detection circuit structure provided in the embodiment of the present application is as follows: Figure 4 As shown, optionally, the overcurrent detection circuit includes an operational amplifier and a comparator;

[0078] The non-inverting input terminal of the operational amplifier U1 is connected to the DC voltage input terminal of the sampling resistor R9 through the first port V+, the inverting input terminal of the operational amplifier U1 is connected to the DC voltage output terminal of the sampling resistor R9 through the second port V-, the output terminal of the operational amplifier U1 is connected to the inverting input terminal of the comparator U2, and the non-inverting input terminal of the comparator U2 is connected to the reference voltage. Figure 4 As shown, the overcurrent detection circuit is also provided with a resistor R10, a resistor R11, a capacitor C5, a resistor R12, a resistor R13, a resistor R14, a resistor R15, a resistor R16, a resistor R17, a resistor R18, a resistor R19, a resistor R20, and a capacitor C6.

[0079] The operational amplifier U1 is used to amplify the voltage difference between the voltage at the DC voltage input terminal of the sampling resistor R9 and the voltage at the DC voltage output terminal of the sampling resistor R9 into a proportional voltage, and output the proportional voltage to the inverting input terminal of the comparator U2;

[0080] The comparator U2 is used to output a low level at the output terminal S1 of the comparator U2 when the proportional voltage is greater than the reference voltage, so as to control the overcurrent detection circuit to output a high level to the first level input port I01; otherwise, the output terminal S1 of the comparator U2 outputs a high level to control the overcurrent detection circuit to output a low level to the first level input port I01.

[0081] Specifically, the operational amplifier U1 is configured as a differential amplifier, whose non-inverting input terminal V+ is connected to the input terminal of the sampling resistor R9, and the inverting input terminal V- is connected to the output terminal of the sampling resistor R9. The operational amplifier U1 amplifies the voltage difference across the sampling resistor R9 into a proportional voltage. The inverting input terminal of the comparator U2 is connected to the output terminal of the operational amplifier U1 to receive the amplified proportional voltage. The non-inverting input terminal of the comparator U2 is connected to the reference voltage. When there is an overcurrent in the circuit, the voltage difference across the sampling resistor R9 increases, and the proportional voltage also increases. When the proportional voltage exceeds the reference voltage, the output terminal S1 of the comparator U2 outputs a low level to control the overcurrent detection circuit to output a high level to the first level input port I01, thereby shutting off the power output. When the circuit is working normally, the proportional voltage does not exceed the reference voltage, and the output terminal S1 of the comparator U2 outputs a high level to control the overcurrent detection circuit to output a low level to the first level input port I01, so that the circuit can work normally. Figure 4 As shown, the reference voltage can be obtained by dividing the voltage VCC by resistors R16 and R17.

[0082] like Figure 4 As shown, one end of the second capacitor C4 is connected to the DC voltage input end of the sampling resistor through the first port V+, and the other end of the second capacitor C4 is grounded. When the DC power supply protection circuit is powered on, the first port V+ will first charge the second capacitor C4, delaying the time for the voltage of the first port V+ to rise, so as to avoid the voltage difference between the first port V+ and the second port V- being too large to trigger the overcurrent protection when the circuit is powered on.

[0083] In the prior art, the overcurrent detection circuit usually turns on and off the power supply circuit by controlling the MOS tube on the power supply circuit. However, in practical applications, the MOS tube is often repeatedly turned on and off due to unstable circuit operation, resulting in damage to the MOS tube. Therefore, an embodiment of the present application provides a fault latch circuit. Figure 5 A schematic diagram of a fault latch circuit structure provided in an embodiment of the present application is shown in FIG. Figure 5 As shown, the structure of the fault latch circuit can be: including a second level input port CTL and a third level input port I03; the second level input port CTL is connected to the output terminal S1 of the comparator U2, and the fault latch circuit is configured as follows: when the third level input port I03 inputs a high level, if the output terminal S1 of the comparator U2 inputs a low level to the second level input port CTL, the overcurrent detection circuit is controlled to input a high level to the first level input port I01; when the third level input port I03 inputs a low level, if the output terminal S1 of the comparator U2 inputs a high level to the second level input port CTL, the overcurrent detection circuit is controlled to input a low level to the first level input port I01.

[0084] Specifically, the basic working principle of the fault latch circuit is that when a high level is input to the third level input port I03, the fault latch is enabled. If the output terminal S1 of the comparator U2 inputs a low level to the second level input port CTL, it indicates that there is an overcurrent in the circuit at this time, and the overcurrent detection circuit is controlled to input a high level to the first level input port I01, and the second PMOS tube Q5 is turned off to shut down the power output. When the circuit returns to normal but the circuit is unstable, if the current in the circuit is unstable at this time, the second level input port CTL may still input a low level, so the overcurrent detection circuit continues to be controlled to input a high level to the first level input port I01, and the second PMOS tube Q5 is turned off to shut down the power output. When the current in the circuit returns to stability, a low level is input to the third level input port I03 at this time. Since there is no overcurrent in the circuit, the output terminal S1 of the comparator U2 inputs a high level to the second level input port CTL, and the overcurrent detection circuit is controlled to input a low level to the first level input port I01, and the second PMOS tube Q5 is turned on to restore the power output.

[0085] Optionally, the third level input port I03 can be controlled by a single chip microcomputer to input a high level or a low level.

[0086] Below Figure 5 The working principle of the fault latch circuit structure shown is explained.

[0087] like Figure 5As shown, the fault latch circuit includes a second NPN transistor Q9, a third PNP transistor Q8, a fourth PNP transistor Q6, a third NPN transistor Q7, a control port I02, and resistors R21, R22, R23, R24, R25, R26, and R27; the control port I02 is connected to a level conversion element, and the level conversion element is connected to the first level input port I01;

[0088] The base of the second NPN transistor Q9 is connected to the third level input port I03, the emitter of the second NPN transistor Q9 is grounded, and the collector of the second NPN transistor Q9 is connected to the base of the third PNP transistor Q8;

[0089] The emitter of the third PNP transistor Q8 is connected to the power supply voltage VCC of the DC power supply protection circuit, and the collector of the third PNP transistor Q8 is connected to the emitter of the fourth PNP transistor Q6;

[0090] The base of the fourth PNP transistor Q6 is connected to the second level input port CTL, and the collector of the fourth PNP transistor Q6 is connected to the base of the third NPN transistor Q7;

[0091] The emitter of the third NPN transistor Q7 is grounded, and the collector of the third NPN transistor Q7 is connected to the control port I02.

[0092] Below Figure 5 The working principle of the fault latch circuit shown is explained.

[0093] When the third level input port I03 gives a high level to enable latching, since the base of Q9 is at a high level, the emitter is grounded, and the base voltage is higher than the emitter voltage, the second NPN transistor Q9 is turned on, causing the base of the third PNP transistor Q8 to be grounded. Since the emitter of Q8 is connected to VCC, the emitter voltage is higher than the base voltage, the third PNP transistor Q8 is turned on, causing the emitter of the fourth PNP transistor Q6 to be high level. When overcurrent occurs, since the second voltage input port CTL inputs a low level (the comparator U2 input is a low level when overcurrent occurs), the fourth PNP transistor The base of tube Q6 is at a low level, and the base voltage of Q6 is lower than the emitter voltage, so the fourth PNP transistor Q6 is turned on, causing the base of the third NPN transistor Q7 to be at a high level, and the emitter of the third NPN transistor Q7 is grounded, and the emitter voltage of Q7 is lower than the base voltage, so the third NPN transistor Q7 is turned on. At this time, since the current flows from the collector of Q7 to the emitter, the collector level is low, so the control port I02 outputs a low level, and through the level conversion element, such as a single-chip microcomputer, a high level is output to the first level input port I01, and the power output is turned off. When the power supply returns to normal but the current is unstable, the output terminal S1 of the comparator U2 may still input a low level to the second level input port CTL, and the control port I02 still maintains a low level to avoid the power supply circuit from being repeatedly turned on and off due to unstable current, which damages the MOS tube. When the fault is removed and the current is truly restored, the third level input port I03 resets the latch to a low level, and the output terminal S1 of the comparator U2 inputs a high level to the second level input port CTL (when there is no overcurrent in the circuit), and all transistors are cut off. When the third NPN transistor Q7 is cut off, no current flows to the ground from its collector, and the collector voltage remains at a high level. Therefore, the control port I02 outputs a high level, and through the level conversion element, a low level is output to the first level input port I01, and the power output is turned on.

[0094] Figure 5 The fault latch circuit shown can prevent the second PMOS tube Q5 in the circuit from being repeatedly turned on and off, thereby preventing the second PMOS tube Q5 from being damaged. At the same time, after the circuit returns to normal, the power output can be restored without restarting the device.

[0095] In a possible implementation, the fault latch circuit may further include a latch, the setting input of the latch is connected to the third level input port I03, when the third level input port I03 inputs a high level, the latch is set, and the latch function is enabled; the second level input port CTL is connected to the output terminal S1 of the comparator U2, the second level input port CTL is connected to the reset input of the latch, when the second level input port CTL inputs the low level output of the comparator U2, it indicates that an overcurrent is detected, and the latch maintains its state (if it has been set, it maintains the set state); the Q output port of the latch controls the overcurrent detection circuit, and the overcurrent detection circuit controls the first level input port I01. When the Q output port of the latch outputs a high level, the overcurrent detection circuit can be controlled by the above-mentioned level conversion element to input a high level to the first level input port I01 to shut down the power output, and when the Q output port of the latch outputs a low level, the overcurrent detection circuit can be controlled by the above-mentioned level conversion element to input a low level to the first level input port I01 to restore the power output.

[0096] Finally, it should be noted that those skilled in the art will readily conceive of other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. The present invention is intended to cover any variations, uses or adaptations of the present invention, which follow the general principles of the present invention and include common knowledge or customary technical means in the art not disclosed by the present invention, are not limited to the precise structure described above and shown in the drawings, and may be modified and changed in various ways without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

Claims

1. A DC power supply protection circuit, characterized in that: The DC power supply protection circuit includes a first PMOS tube, a first capacitor, and a first PNP transistor; The drain of the first PMOS tube is connected to the first DC voltage input terminal of the DC power supply protection circuit, the source of the first PMOS tube is connected to the first load terminal of the DC power supply protection circuit, the gate of the first PMOS tube is connected to the collector of the first PNP transistor, and the first PMOS tube is used to output the DC voltage input from the first DC voltage input terminal to the first load terminal through the body diode of the first PMOS tube in the on state; One end of the first capacitor is connected to the first DC voltage input terminal and the base of the first PNP transistor, and the other end of the first capacitor is grounded; The base of the first PNP transistor is connected to the first DC voltage input terminal, and the emitter of the first PNP transistor is connected to the source of the first PMOS transistor; The on-state voltage drop of the first PNP transistor is lower than the on-state threshold voltage of the first PMOS transistor.

2. The DC power supply protection circuit according to claim 1, characterized in that: The DC power supply protection circuit also includes a first voltage regulator tube, an anode of the first voltage regulator tube is connected to the gate of the first PMOS tube, a cathode of the first voltage regulator tube is connected to the source of the first PMOS tube, a voltage regulation value of the first voltage regulator tube is higher than a turn-on threshold voltage of the first PMOS tube, and a voltage regulation value of the first voltage regulator tube is lower than a maximum allowable value of a voltage difference between a gate voltage and a source voltage of the first PMOS tube.

3. The DC power supply protection circuit according to claim 1, characterized in that: The DC power supply protection circuit also includes a second PMOS transistor, a first NPN transistor, a second PNP transistor, and a first level input port; The source of the second PMOS tube is connected to the second DC voltage input terminal of the DC power protection circuit, the drain of the second PMOS tube is connected to the second load terminal of the DC power protection circuit, the second DC voltage input terminal is connected to the first load terminal, and the second PMOS tube is used to output the DC voltage input from the second DC voltage input terminal to the second load terminal in the on state; The base of the first NPN transistor is connected to the first level input port, the emitter of the first NPN transistor is grounded, the collector of the first NPN transistor is connected to the second DC voltage input terminal through a first resistor and a second resistor connected in series, the collector of the first NPN transistor is connected to one end of the first resistor, the other end of the first resistor is connected to the base of the second PNP transistor, one end of the second resistor is connected to the base of the second PNP transistor, and the other end of the second resistor is connected to the second DC voltage input terminal; The emitter of the second PNP transistor is connected to the second DC voltage input terminal, the collector of the second PNP transistor is connected to the gate of the second PMOS transistor, and the conduction voltage drop of the second PNP transistor is lower than the conduction threshold voltage of the second PMOS transistor; The DC power supply protection circuit is configured to input a high level to the first level input port if an overcurrent or a fault in the DC power supply protection circuit is detected, and otherwise input a low level to the first level input port.

4. The DC power supply protection circuit according to claim 3, characterized in that: The DC power supply protection circuit also includes a second voltage regulator tube, an anode of the second voltage regulator tube is connected to the gate of the second PMOS tube, a cathode of the second voltage regulator tube is connected to the source of the second PMOS tube, a voltage regulation value of the second voltage regulator tube is higher than a turn-on threshold voltage of the second PMOS tube, and a voltage regulation value of the second voltage regulator tube is lower than a maximum allowable value of a voltage difference between a gate voltage and a source voltage of the second PMOS tube.

5. The DC power supply protection circuit according to claim 3, characterized in that: The circuit also includes a sampling resistor and an overcurrent detection circuit; The sampling resistor is connected in series in the DC power supply protection circuit, and the DC voltage output by the DC power supply reaches the load end of the DC power supply protection circuit through the sampling resistor; The DC voltage input end of the sampling resistor is connected to the first port of the overcurrent detection circuit, and the DC voltage output end of the sampling resistor is connected to the second port of the overcurrent detection circuit; The overcurrent detection circuit is configured to output a high level to the first level input port when a voltage difference between a voltage at a DC voltage input terminal of the sampling resistor and a voltage at a DC voltage output terminal of the sampling resistor is greater than a preset threshold, and otherwise output a low level to the first level input port.

6. The DC power supply protection circuit according to claim 5, characterized in that: The overcurrent detection circuit includes an operational amplifier and a comparator; The non-inverting input terminal of the operational amplifier is connected to the DC voltage input terminal of the sampling resistor, the inverting input terminal of the operational amplifier is connected to the DC voltage output terminal of the sampling resistor, the output terminal of the operational amplifier is connected to the inverting input terminal of the comparator, and the non-inverting input terminal of the comparator is connected to the reference voltage; The operational amplifier is used to amplify the voltage difference between the voltage at the DC voltage input end of the sampling resistor and the voltage at the DC voltage output end of the sampling resistor into a proportional voltage, and output the proportional voltage to the inverting input end of the comparator; The comparator is used to output a low level at the output end of the comparator when the proportional voltage is greater than the reference voltage, so as to control the overcurrent detection circuit to output a high level to the first level input port; otherwise, the comparator output end outputs a high level to control the overcurrent detection circuit to output a low level to the first level input port.

7. The DC power supply protection circuit according to claim 5, characterized in that: The overcurrent detection circuit further includes a second capacitor, one end of the second capacitor is connected to the DC voltage input end of the sampling resistor, and the other end of the second capacitor is grounded.

8. The DC power supply protection circuit according to claim 6, characterized in that: The overcurrent detection circuit further includes a fault latch circuit, and the fault latch circuit includes a second level input port and a third level input port; The second level input port is connected to the comparator output terminal, and the fault latch circuit is configured as follows: when the third level input port inputs a high level, if the comparator output terminal inputs a low level to the second level input port, the overcurrent detection circuit is controlled to input a high level to the first level input port; when the third level input port inputs a low level, if the comparator output terminal inputs a high level to the second level input port, the overcurrent detection circuit is controlled to input a low level to the first level input port.

9. The DC power supply protection circuit according to claim 8, characterized in that: The fault latch circuit comprises a second NPN transistor, a third PNP transistor, a fourth PNP transistor, a third NPN transistor, and a control port, wherein the control port is connected to a level conversion element, and the level conversion element is connected to the first level input port; The base of the second NPN transistor is connected to the third level input port, the emitter of the second NPN transistor is grounded, and the collector of the second NPN transistor is connected to the base of the third PNP transistor; The emitter of the third PNP transistor is connected to the power supply voltage of the DC power supply protection circuit, and the collector of the third PNP transistor is connected to the emitter of the fourth PNP transistor; The base of the fourth PNP transistor is connected to the second level input port, and the collector of the fourth PNP transistor is connected to the base of the third NPN transistor; The emitter of the third NPN transistor is grounded, and the collector of the third NPN transistor is connected to the control port; The level conversion element is configured such that: when the control port outputs a low level to the level conversion element, the level conversion element outputs a high level to the first level input port; when the control port outputs a high level to the level conversion element, the level conversion element outputs a low level to the first level input port.

10. The DC power supply protection circuit according to claim 9, characterized in that: The level conversion element is a single chip microcomputer.

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