Full gallium nitride integrated half-bridge circuit, chip and electronic equipment

Abstract

The invention discloses a full gallium nitride integrated half-bridge circuit, a chip and electronic equipment, and the circuit comprises an undervoltage and overvoltage protection circuit, an overcurrent protection circuit, a dead time generation circuit, a signal control circuit, a level shift circuit, a high-side driving circuit, a low-side driving circuit, a high-side gallium nitride transistor and a low-side gallium nitride transistor. The half-bridge circuit has the following effects: the half-bridge circuit can automatically disconnect the level shift circuits of the high-side gallium nitride transistor and the low-side gallium nitride transistor by generating an automatic locking logic signal, so that the problems of mis-opening and mis-closing of a high-side power device in a high-frequency switching signal switching process are reduced; the driving circuit adopts a bootstrap driving structure to ensure rail-to-rail output and simultaneously has low transmission delay, and in addition, the driving circuit is integrated with overvoltage, undervoltage and overcurrent protection circuits to ensure high reliability of the half-bridge circuit during working.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular to a full gallium nitride integrated half-bridge circuit, chip and electronic device. Background Art

[0002] The third generation semiconductor material gallium nitride has superior properties such as high frequency, high efficiency, high power, high voltage resistance, high temperature resistance, and strong radiation resistance. Compared with silicon devices, gallium nitride power electronic devices have advantages such as higher operating voltage, higher switching frequency, and lower on-resistance. They have great development potential in the fields of new generation high efficiency, small size power conversion and management system, electric locomotives, industrial motors, etc.

[0003] However, due to the lack of p-type GaN devices, GaN circuits are mainly resistor transistor logic (RTL) circuits and cannot use CMOS complementary logic circuits. Therefore, current discrete GaN power devices usually require a separate external silicon-based drive circuit, which will generate large parasitic inductance and capacitance, which limits the characteristics of GaN devices working at higher switching frequencies. At the same time, the lack of peripheral protection circuits for GaN power devices also makes the reliability of current GaN power electronic systems poor. Summary of the invention

[0004] The purpose of this application is to provide a full gallium nitride integrated half-bridge circuit, chip and electronic device to solve the problem of low stability and reliability of traditional half-bridge circuits in related technologies.

[0005] In order to achieve the above objectives, this application provides the following technical solutions:

[0006] In a first aspect, the present application provides a full gallium nitride integrated half-bridge circuit, comprising: an undervoltage and overvoltage protection circuit, an overcurrent protection circuit, a dead time generation circuit, a signal control circuit, a level shift circuit, a high-side drive circuit, a low-side drive circuit, a high-side gallium nitride transistor, and a low-side gallium nitride transistor; the first input end of the undervoltage and overvoltage protection circuit is connected to an external power supply end, the second input end of the undervoltage and overvoltage protection circuit is connected to an external reference voltage end, and the output end of the undervoltage and overvoltage protection circuit is connected to the first input end of the signal control circuit; the overcurrent protection circuit The first input terminal of the overcurrent protection circuit is connected to the gate of the low-side gallium nitride transistor, the second input terminal of the overcurrent protection circuit is connected to the drain of the low-side gallium nitride transistor, the third input terminal of the overcurrent protection circuit is connected to the external power supply terminal, the fourth input terminal of the overcurrent protection circuit is connected to the reference voltage terminal, and the output terminal of the overcurrent protection circuit is connected to the fourth input terminal of the signal control circuit; the first input terminal of the dead time generating circuit is connected to the control signal terminal, the second input terminal of the dead time generating circuit is connected to the power supply terminal, The first output end of the dead time generating circuit is connected to the second input end of the signal control circuit, and the second output end of the dead time generating circuit is connected to the third input end of the signal control circuit; the fifth input end of the signal control circuit is connected to the power supply end, the first output end of the signal control circuit is connected to the third input end of the level shift circuit, and the second output end of the signal control circuit is connected to the first input end of the low side driving circuit; the first input end of the level shift circuit is connected to the power supply end, the second input end of the level shift circuit is connected to the external bootstrap voltage end, and the first output end of the level shift circuit is connected to the second input end of the high side driving circuit; the first input end of the high side driving circuit is connected to the bootstrap voltage end, and the first output end of the high side driving circuit is connected to the gate of the high side gallium nitride transistor; the second input end of the low side driving circuit is connected to the external power supply end, and the first output end of the low side driving circuit is the gate of the low side gallium nitride transistor; the drain of the high side gallium nitride transistor is connected to the external input voltage end; the source of the low side gallium nitride transistor is grounded.

[0007] Further, the undervoltage and overvoltage protection circuit includes: a first resistor, a second resistor, a third resistor, a first hysteresis comparator, a second hysteresis comparator, a first inverter, a first NAND gate and a second inverter; the first resistor, the second resistor and the third resistor are connected in series in sequence, the first end of the first resistor is connected to the power supply end, and the second end of the third resistor is grounded; the inverting input end of the first hysteresis comparator is connected to the common end of the first resistor and the second resistor, the non-inverting input end of the first hysteresis comparator is connected to the non-inverting input end of the second hysteresis comparator and the reference voltage end, and the output end of the first hysteresis comparator is connected to the input end of the first inverter; the inverting input end of the second hysteresis comparator is connected to the common end of the second resistor and the third resistor, and the output end of the second hysteresis comparator is connected to the second input end of the first NAND gate; the output end of the first inverter is connected to the first input end of the first NAND gate; the output end of the first NAND gate is connected to the input end of the second inverter; the output end of the second inverter is connected to the output end of the undervoltage and overvoltage protection circuit.

[0008] Further, the first hysteresis comparator includes: a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, a first enhancement-mode gallium nitride transistor, a second enhancement-mode gallium nitride transistor, a third enhancement-mode gallium nitride transistor, a fourth enhancement-mode gallium nitride transistor, a fifth enhancement-mode gallium nitride transistor, a sixth enhancement-mode gallium nitride transistor, a seventh enhancement-mode gallium nitride transistor, an eighth enhancement-mode gallium nitride transistor, a ninth enhancement-mode gallium nitride transistor, a tenth enhancement-mode gallium nitride transistor, a tenth enhancement-mode gallium nitride transistor, an eleventh enhancement-mode gallium nitride transistor, and a twelfth enhancement-mode gallium nitride transistor; a first end of the fourth resistor, a first end of the fifth resistor, a first end of the sixth resistor, and a first end of the seventh resistor one end of the fourth resistor is connected to the power supply terminal; the second end of the fourth resistor is connected to the drain of the first enhancement mode gallium nitride transistor and the gate of the fifth enhancement mode gallium nitride transistor, the second end of the fifth resistor is connected to the drain of the third enhancement mode gallium nitride transistor and the gate of the ninth enhancement mode gallium nitride transistor, the second end of the sixth resistor is connected to the drain of the eleventh enhancement mode gallium nitride transistor and the gate of the twelfth enhancement mode gallium nitride transistor, the second end of the seventh resistor is connected to the drain of the twelfth enhancement mode gallium nitride transistor and the output end of the first hysteresis comparator; the gate of the first enhancement mode gallium nitride transistor is connected to the reference voltage terminal, and the first enhancement mode gallium nitride transistor is connected to the reference voltage terminal. The source of the GaN transistor is connected to the drain of the second enhancement-mode GaN transistor, the source of the third enhancement-mode GaN transistor and the drain of the fourth enhancement-mode GaN transistor; the gate of the second enhancement-mode GaN transistor is connected to the gate of the eighth enhancement-mode GaN transistor, the gate of the tenth enhancement-mode GaN transistor, the gate of the eleventh enhancement-mode GaN transistor, the source of the ninth enhancement-mode GaN transistor and the drain of the seventh enhancement-mode GaN transistor; the gate of the third enhancement-mode GaN transistor is connected to the input voltage terminal; the gate of the fourth enhancement-mode GaN transistor is connected to the source of the fifth enhancement-mode GaN transistor and the drain of the sixth enhancement-mode GaN transistor , the gate of the sixth enhancement mode gallium nitride transistor, the gate of the seventh enhancement mode gallium nitride transistor and the drain of the eighth enhancement mode gallium nitride transistor; the drain of the fifth enhancement mode gallium nitride transistor and the drain of the ninth enhancement mode gallium nitride transistor are connected to the power supply terminal; the source of the second enhancement mode gallium nitride transistor, the source of the fourth enhancement mode gallium nitride transistor, the source of the sixth enhancement mode gallium nitride transistor, the source of the seventh enhancement mode gallium nitride transistor, the source of the eighth enhancement mode gallium nitride transistor, the source of the tenth enhancement mode gallium nitride transistor, the source of the eleventh enhancement mode gallium nitride transistor and the source of the twelfth enhancement mode gallium nitride transistor are grounded.

[0009] Further, the overcurrent protection circuit includes: a thirteenth enhancement-mode gallium nitride transistor, an eighth resistor, a ninth resistor, a tenth resistor, a third hysteresis comparator and a first leading edge blanking circuit; the eighth resistor, the ninth resistor and the tenth resistor are connected in series in sequence, the first end of the eighth resistor is connected to the power supply terminal, and the second end of the tenth resistor is connected to the source of the low-side gallium nitride transistor; the drain of the thirteenth enhancement-mode gallium nitride transistor is connected to the drain of the low-side gallium nitride transistor, the gate of the thirteenth enhancement-mode gallium nitride transistor is connected to the gate of the low-side gallium nitride transistor, and the source of the thirteenth enhancement-mode gallium nitride transistor is connected to the common end of the ninth resistor and the tenth resistor; the non-inverting input end of the third hysteresis comparator is connected to the common end of the eighth resistor and the ninth resistor, the inverting input end of the third hysteresis comparator is connected to the reference voltage terminal, and the output end of the third hysteresis comparator is connected to the input end of the first leading edge blanking circuit; the output end of the first leading edge blanking circuit is connected to the output end of the overcurrent protection circuit.

[0010] Furthermore, the first leading edge blanking circuit includes: a third inverter, a first low-pass filter, a first hysteresis inverter, and a second NAND gate; the input end of the third inverter and the first input end of the second NAND gate are connected to the output end of the third hysteresis comparator, and the output end of the third inverter is connected to the input end of the first low-pass filter; the output end of the first low-pass filter is connected to the input end of the first hysteresis inverter; the output end of the first hysteresis inverter is connected to the second input end of the second NAND gate, and the output end of the second NAND gate is connected to the output end of the first leading edge blanking circuit.

[0011] Further, the dead time generating circuit includes: a fourth inverter, a third NAND gate, a fourth NAND gate, a fourteenth enhancement-mode gallium nitride transistor, a fifteenth enhancement-mode gallium nitride transistor, a second hysteresis inverter, a third hysteresis inverter, a fifth inverter, a sixth inverter, a seventh inverter and an eighth inverter; the input end of the fourth inverter and the second input end of the fourth NAND gate are connected to the control signal end, and the output end of the fourth inverter is connected to the first input end of the third NAND gate; the second input end of the third NAND gate is connected to the gate of the fifteenth enhancement-mode gallium nitride transistor, the output end of the fourth NAND gate and the input end of the third hysteresis inverter, and the output end of the third NAND gate is connected to the gate of the fourteenth enhancement-mode gallium nitride transistor, the fourth a first input terminal of the NAND gate and an input terminal of the second hysteresis inverter; a source terminal of the fourteenth enhancement-mode gallium nitride transistor, a drain terminal of the fourteenth enhancement-mode gallium nitride transistor, a source terminal of the fifteenth enhancement-mode gallium nitride transistor, and a drain terminal of the fifteenth enhancement-mode gallium nitride transistor are grounded; an output terminal of the second hysteresis inverter is connected to an input terminal of the fifth inverter, an output terminal of the fifth inverter is connected to an input terminal of the sixth inverter, and an output terminal of the sixth inverter is connected to a first output terminal of the dead time generating circuit; an output terminal of the third hysteresis inverter is connected to an input terminal of the seventh inverter, an output terminal of the seventh inverter is connected to an input terminal of the eighth inverter, and an output terminal of the seventh inverter is connected to a second output terminal of the dead time generating circuit.

[0012] Further, the signal control circuit includes: a fifth NAND gate, a sixth NAND gate, a seventh NAND gate, a ninth inverter, a tenth inverter and an eleventh inverter; the first input end of the fifth NAND gate is connected to the first input end of the signal control circuit, the second input end of the fifth NAND gate is connected to the fourth input end of the signal control circuit, and the output end of the fifth NAND gate is connected to the input end of the ninth inverter; the output end of the ninth inverter is connected to the first input end of the sixth NAND gate and the first input end of the seventh NAND gate; the second input end of the sixth NAND gate is connected to the second input end of the signal control circuit, and the output end of the sixth NAND gate is connected to the input end of the tenth inverter; the output end of the tenth inverter is connected to the first output end of the signal control circuit; the second input end of the seventh NAND gate is connected to the third input end of the signal control circuit, and the output end of the seventh NAND gate is connected to the input end of the eleventh inverter; the output end of the eleventh inverter is connected to the second output end of the signal control circuit.

[0013] Further, the level shift circuit includes: an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a sixteenth enhancement-type gallium nitride transistor, a sixteenth enhancement-type gallium nitride transistor, a seventeenth enhancement-type gallium nitride transistor, an eighteenth enhancement-type gallium nitride transistor, a nineteenth enhancement-type gallium nitride transistor, a twentieth enhancement-type gallium nitride transistor, a twenty-first enhancement-type gallium nitride transistor, a twenty-second enhancement-type gallium nitride transistor, a twenty-third enhancement-type gallium nitride transistor, a twenty-fourth enhancement-type gallium nitride transistor, a twenty-fifth enhancement-type gallium nitride transistor, a twenty-sixth enhancement-type gallium nitride transistor, a twenty-seventh enhancement-type gallium nitride transistor, and a twenty-fifth enhancement-type gallium nitride transistor. a twenty-eighth enhancement mode gallium nitride transistor, a twenty-ninth enhancement mode gallium nitride transistor, a thirtieth enhancement mode gallium nitride transistor, a thirty-first enhancement mode gallium nitride transistor, a thirty-second enhancement mode gallium nitride transistor, and a twelfth inverter; a drain of the sixteenth enhancement mode gallium nitride transistor, a gate of the sixteenth enhancement mode gallium nitride transistor, a drain of the seventeenth enhancement mode gallium nitride transistor, a gate of the seventeenth enhancement mode gallium nitride transistor, a drain of the eighteenth enhancement mode gallium nitride transistor, a gate of the eighteenth enhancement mode gallium nitride transistor, a drain of the nineteenth enhancement mode gallium nitride transistor, a gate of the nineteenth enhancement mode gallium nitride transistor, and a first end of the fifteenth resistor are connected to the bootstrap voltage terminal; The source of the sixteenth enhancement-mode gallium nitride transistor is connected to the first end of the eleventh resistor and the gate of the twentieth enhancement-mode gallium nitride transistor; the source of the seventeenth enhancement-mode gallium nitride transistor is connected to the first end of the twelfth resistor; the source of the eighteenth enhancement-mode gallium nitride transistor is connected to the first end of the thirteenth resistor; the source of the nineteenth enhancement-mode gallium nitride transistor is connected to the first end of the fourteenth resistor and the gate of the twenty-third enhancement-mode gallium nitride transistor; the second end of the fifteenth resistor is connected to the drain of the twenty-fourth enhancement-mode gallium nitride transistor and the output end of the level shift circuit; the second end of the eleventh resistor is connected to the drain of the twenty-seventh enhancement-mode gallium nitride transistor the drain of the 20th enhancement-mode gallium nitride transistor is connected to the second end of the twelfth resistor, the drain of the 21st enhancement-mode gallium nitride transistor and the gate of the 22nd enhancement-mode gallium nitride transistor; the gate of the 21st enhancement-mode gallium nitride transistor is connected to the second end of the thirteenth resistor, the drain of the 22nd enhancement-mode gallium nitride transistor, the drain of the 23rd enhancement-mode gallium nitride transistor and the gate of the 24th enhancement-mode gallium nitride transistor, and the source of the 21st enhancement-mode gallium nitride transistor is connected to the drain of the 25th enhancement-mode gallium nitride transistor and the gate of the 25th enhancement-mode gallium nitride transistor;The source of the twenty-second enhancement-mode gallium nitride transistor is connected to the drain of the twenty-sixth enhancement-mode gallium nitride transistor and the gate of the twenty-sixth enhancement-mode gallium nitride transistor; the source of the twenty-third enhancement-mode gallium nitride transistor is connected to the second end of the fourteenth resistor and the drain of the twenty-eighth enhancement-mode gallium nitride transistor; the source of the twenty-fifth enhancement-mode gallium nitride transistor, the source of the twenty-sixth enhancement-mode gallium nitride transistor, and the source of the twenty-fourth enhancement-mode gallium nitride transistor are connected to the switch node of the half-bridge circuit; the gate of the twenty-seventh enhancement-mode gallium nitride transistor and the gate of the twenty-eighth enhancement-mode gallium nitride transistor are connected to the power supply terminal; the source of the twenty-seventh enhancement-mode gallium nitride transistor is connected to the drain of the twenty-ninth enhancement-mode gallium nitride transistor; the source of the twenty-eighth enhancement-mode gallium nitride transistor is connected to the The gate of the 29th enhancement-mode GaN transistor is connected to the output terminal of the 12th inverter, and the source of the 29th enhancement-mode GaN transistor is connected to the source of the 30th enhancement-mode GaN transistor and the drain of the 32nd enhancement-mode GaN transistor; the input terminal of the 12th inverter and the gate of the 30th enhancement-mode GaN transistor are connected to the third input terminal of the level shift circuit; the first terminal of the 16th resistor is connected to the power supply terminal, and the second terminal of the 16th resistor is connected to the drain of the 31st enhancement-mode GaN transistor, the gate of the 31st enhancement-mode GaN transistor and the gate of the 32nd enhancement-mode GaN transistor; the source of the 31st enhancement-mode GaN transistor and the source of the 32nd enhancement-mode GaN transistor are grounded. ;

[0014] Further, the high-side driving circuit includes: a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a twentieth resistor, a first capacitor, a second capacitor, a thirty-third enhancement-type gallium nitride transistor, a thirty-fourth enhancement-type gallium nitride transistor, a thirty-fifth enhancement-type gallium nitride transistor, a thirty-sixth enhancement-type gallium nitride transistor, a thirty-seventh enhancement-type gallium nitride transistor, a thirty-eighth enhancement-type gallium nitride transistor, a thirty-ninth enhancement-type gallium nitride transistor, a fortieth enhancement-type gallium nitride transistor, and a forty-first enhancement-type gallium nitride transistor; the seventeenth resistor and the eighteenth resistor are connected in series, and the first end of the seventeenth resistor is connected to the resistor. a first output terminal of the shift circuit, a second terminal of the eighteenth resistor connected to the drain of the thirty-seventh enhancement-mode gallium nitride transistor; a gate of the thirty-third enhancement-mode gallium nitride transistor, a drain of the thirty-third enhancement-mode gallium nitride transistor, a gate of the thirty-fourth enhancement-mode gallium nitride transistor, a drain of the thirty-fourth enhancement-mode gallium nitride transistor, a drain of the thirty-fifth enhancement-mode gallium nitride transistor, and a drain of the thirty-sixth enhancement-mode gallium nitride transistor connected to the bootstrap voltage terminal; a source of the thirty-third enhancement-mode gallium nitride transistor connected to the first terminal of the nineteenth resistor and the first terminal of the first capacitor; The source of the thirty-fourth enhancement-mode gallium nitride transistor is connected to the first end of the twentieth resistor and the first end of the second capacitor; the second end of the nineteenth resistor is connected to the gate of the thirty-fifth enhancement-mode gallium nitride transistor and the drain of the thirty-eighth enhancement-mode gallium nitride transistor; the second end of the first capacitor is connected to the source of the thirty-fifth enhancement-mode gallium nitride transistor, the drain of the thirty-ninth enhancement-mode gallium nitride transistor, the gate of the thirty-seventh enhancement-mode gallium nitride transistor, the gate of the fortieth enhancement-mode gallium nitride transistor and the gate of the forty-first enhancement-mode gallium nitride transistor; the second end of the twentieth resistor is connected to the gate ... The first end of the second capacitor is connected to the drain of the fortieth enhancement-mode gallium nitride transistor and the gate of the thirty-sixth enhancement-mode gallium nitride transistor, the second end of the second capacitor is connected to the source of the thirty-sixth enhancement-mode gallium nitride transistor, the drain of the forty-first enhancement-mode gallium nitride transistor and the output end of the high-side drive circuit; the source of the thirty-seventh enhancement-mode gallium nitride transistor, the source of the thirty-eighth enhancement-mode gallium nitride transistor, the source of the thirty-ninth enhancement-mode gallium nitride transistor, the source of the fortieth enhancement-mode gallium nitride transistor and the source of the forty-first enhancement-mode gallium nitride transistor are connected to the switch node of the half-bridge circuit.

[0015] Further, the low-side driving circuit includes: a twenty-first resistor, a twenty-second resistor, a twenty-third resistor, a twenty-fourth resistor, a third capacitor, a fourth capacitor, a forty-second enhancement-mode gallium nitride transistor, a forty-third enhancement-mode gallium nitride transistor, a forty-fourth enhancement-mode gallium nitride transistor, a forty-fifth enhancement-mode gallium nitride transistor, a forty-sixth enhancement-mode gallium nitride transistor, a forty-seventh enhancement-mode gallium nitride transistor, a forty-eighth enhancement-mode gallium nitride transistor, a forty-ninth enhancement-mode gallium nitride transistor, and a fiftieth enhancement-mode gallium nitride transistor; the twenty-first resistor and the twenty-second resistor are connected in series, and the first end of the twenty-first resistor is connected to the first end of the second resistor. The second end of the twenty-second resistor is connected to the drain of the forty-sixth enhancement-mode gallium nitride transistor; the gate of the forty-second enhancement-mode gallium nitride transistor, the drain of the forty-second enhancement-mode gallium nitride transistor, the gate of the forty-third enhancement-mode gallium nitride transistor, the drain of the forty-third enhancement-mode gallium nitride transistor, the drain of the forty-fourth enhancement-mode gallium nitride transistor, and the drain of the forty-fifth enhancement-mode gallium nitride transistor are connected to the power supply terminal; the source of the forty-second enhancement-mode gallium nitride transistor is connected to the first end of the twenty-third resistor and the drain of the third enhancement-mode gallium nitride transistor. a first end of the capacitor; the source of the forty-third enhancement mode gallium nitride transistor is connected to the first end of the twenty-fourth resistor and the first end of the fourth capacitor; the second end of the twenty-third resistor is connected to the gate of the forty-fourth enhancement mode gallium nitride transistor and the drain of the forty-seventh enhancement mode gallium nitride transistor; the second end of the third capacitor is connected to the source of the forty-fourth enhancement mode gallium nitride transistor, the drain of the forty-eighth enhancement mode gallium nitride transistor, the gate of the forty-sixth enhancement mode gallium nitride transistor, the gate of the forty-ninth enhancement mode gallium nitride transistor and the gate of the fiftieth enhancement mode gallium nitride transistor; the A second end of the twenty-fourth resistor is connected to the drain of the forty-ninth enhancement mode gallium nitride transistor and the gate of the forty-fifth enhancement mode gallium nitride transistor, a second end of the fourth capacitor is connected to the source of the forty-fifth enhancement mode gallium nitride transistor, the drain of the fiftieth enhancement mode gallium nitride transistor and the output end of the low-side drive circuit; a source of the forty-sixth enhancement mode gallium nitride transistor, a source of the forty-seventh enhancement mode gallium nitride transistor, a source of the forty-eighth enhancement mode gallium nitride transistor, a source of the forty-ninth enhancement mode gallium nitride transistor and a source of the fiftieth enhancement mode gallium nitride transistor are connected to ground.

[0016] In a second aspect, the present application further provides a chip, wherein the chip includes a full gallium nitride integrated half-bridge circuit as described above.

[0017] In a third aspect, the present application also provides an electronic device, wherein the electronic device includes the chip as described above.

[0018] The present application provides a full gallium nitride integrated half-bridge circuit, chip and electronic device, which have the following beneficial effects:

[0019] 1. The fully GaN-integrated high-reliability half-bridge circuit of the present invention integrates the GaN half-bridge drive circuit and the GaN high-side and low-side power devices, thereby reducing parasitic inductance and capacitance, and allowing the GaN power devices to operate at a higher switching frequency.

[0020] 2. The all-gallium nitride integrated high-reliability half-bridge circuit of the present invention integrates undervoltage protection and overcurrent protection while also including an overvoltage protection circuit to prevent excessive voltage applied to the gate of the gallium nitride power device from causing performance degradation or even damage to the device, thereby improving the reliability of the circuit.

[0021] 3. The fully gallium nitride integrated high-reliability half-bridge circuit of the present invention adopts an automatic locking logic signal to automatically disconnect the level shifting circuit between the high-side ground and the low-side ground, effectively reducing the risk of false start and shutdown of the high-side power device, and effectively improving the stability and reliability of the half-bridge circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a schematic diagram of the structure of a half-bridge circuit integrated with full gallium nitride according to an embodiment of the present application;

[0023] Figure 2 is a schematic diagram of the structure of the undervoltage and overvoltage protection circuit in the embodiment of the present application;

[0024] Figure 3 is a schematic diagram of the circuit structure of the first hysteresis comparator in an embodiment of the present application;

[0025] Figure 4 is a schematic diagram of the structure of an overcurrent protection circuit in an embodiment of the present application;

[0026] Figure 5 is a schematic structural diagram of a first leading edge blanking circuit in an embodiment of the present application;

[0027] Figure 6 is a schematic diagram of the circuit structure of the first low-pass filter in an embodiment of the present application;

[0028] Figure 7 is a schematic diagram of the circuit structure of the first hysteresis inverter in an embodiment of the present application;

[0029] Figure 8 is a schematic structural diagram of a dead time generating circuit in an embodiment of the present application;

[0030] Fig. 9 is a schematic diagram of the structure of the signal control circuit in an embodiment of the present application;

[0031] Fig.10 is a schematic diagram of the structure of a level shift circuit in an embodiment of the present application;

[0032] Fig.11 is a schematic structural diagram of a high-side driver circuit in an embodiment of the present application;

[0033] Fig.12 is a schematic structural diagram of a low-side driving circuit in an embodiment of the present application;

[0034] Figure numerals: 100, full gallium nitride integrated half-bridge circuit; 10, undervoltage and overvoltage protection circuit; 20, overcurrent protection circuit; 30, dead time generation circuit; 40, signal control circuit; 50, level shift circuit; 60, high-side drive circuit; 70, low-side drive circuit; 80, high-side gallium nitride transistor; 90, low-side gallium nitride transistor; 14, first hysteresis comparator; 15, second hysteresis comparator; 16, first inverter; 17, first NAND gate; 18, second inverter; 25, third hysteresis comparator; 26, first leading edge blanking circuit; 261, third inverter; 262, first low-pass filter; 263, first hysteresis inverter; 264, second NAND gate; 301 , the fourth inverter; 302, the third NAND gate; 303, the fourth NAND gate; 306, the second hysteresis inverter; 307, the third hysteresis inverter; 308, the fifth inverter; 309, the sixth inverter; 310, the seventh inverter; 311, the eighth inverter; 41, the fifth NAND gate; 42, the ninth inverter; 43, the sixth NAND gate; 44, the tenth inverter; 45, the seventh NAND gate; 46, the eleventh inverter; 506, the twelfth inverter; C1, the first capacitor; C2, the second capacitor; C3, the third capacitor; C4, the fourth capacitor; R1-R24, the first resistor to the twenty-fourth resistor; Q1-Q50, the first enhancement-mode gallium nitride transistor to the fiftieth enhancement-mode gallium nitride transistor. DETAILED DESCRIPTION

[0035] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes are not repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0036] See also Figure 1 , an all-gallium nitride integrated half-bridge circuit 100 provided in an embodiment of the present application includes: an undervoltage and overvoltage protection circuit 10, an overcurrent protection circuit 20, a dead time generation circuit 30, a signal control circuit 40, a level shift circuit 50, a high-side drive circuit 60, a low-side drive circuit 70, a high-side gallium nitride transistor 80, and a low-side gallium nitride transistor 90;

[0037] The first input terminal of the undervoltage and overvoltage protection circuit 10 is connected to the external power supply terminal, the second input terminal of the undervoltage and overvoltage protection circuit 10 is connected to the external reference voltage terminal, and the output terminal of the undervoltage and overvoltage protection circuit 10 is connected to the first input terminal of the signal control circuit 40; wherein the voltage output by the external power supply terminal is VCC, the voltage output by the external reference voltage terminal is VREF, and the output terminal of the undervoltage and overvoltage protection circuit 10 outputs the first target signal UVP&OVP;

[0038] The first input terminal of the overcurrent protection circuit 20 is connected to the gate of the low-side GaN transistor 90, the second input terminal of the overcurrent protection circuit 20 is connected to the drain of the low-side GaN transistor 90, the third input terminal of the overcurrent protection circuit 20 is connected to the external power supply terminal, the fourth input terminal of the overcurrent protection circuit 20 is connected to the reference voltage terminal, and the output terminal of the overcurrent protection circuit 20 is connected to the fourth input terminal of the signal control circuit 40; wherein the output terminal of the overcurrent protection circuit 20 outputs the second target signal OCP;

[0039] The first input terminal of the dead time generating circuit 30 is connected to the control signal terminal, the second input terminal of the dead time generating circuit 30 is connected to the power supply terminal, the first output terminal of the dead time generating circuit 30 is connected to the second input terminal of the signal control circuit 40, and the second output terminal of the dead time generating circuit 30 is connected to the third input terminal of the signal control circuit 40; wherein, the control signal terminal outputs the first external control signal PWM_IN, the first output terminal of the dead time generating circuit 30 outputs the third target signal PWM_INA, and the second output terminal of the dead time generating circuit 30 outputs the fourth target signal PWM_INB;

[0040] The fifth input terminal of the signal control circuit 40 is connected to the power supply terminal, the first output terminal of the signal control circuit 40 is connected to the third input terminal of the level shift circuit 50, and the second output terminal of the signal control circuit 40 is connected to the first input terminal of the low-side driving circuit 70; wherein the first output terminal of the signal control circuit 40 outputs the fifth target signal PWM_INH; the second output terminal of the signal control circuit 40 outputs the eighth target signal PWM_LS;

[0041] The first input terminal of the level shift circuit 50 is connected to the power supply terminal, the second input terminal of the level shift circuit 50 is connected to the external bootstrap voltage terminal, and the first output terminal of the level shift circuit 50 is connected to the second input terminal of the high-side driving circuit 60; wherein the first output terminal of the level shift circuit 50 outputs the sixth target signal PWM_HS;

[0042] The first input terminal of the high-side driving circuit 60 is connected to the bootstrap voltage terminal, and the first output terminal of the high-side driving circuit 60 is connected to the gate of the high-side GaN transistor 80; wherein the first output terminal of the high-side driving circuit 60 outputs the seventh target signal HS;

[0043] The second input terminal of the low-side driving circuit 70 is connected to the external power supply terminal, and the first output terminal of the low-side driving circuit 70 is connected to the gate of the low-side gallium nitride transistor 90; wherein the first output terminal of the low-side driving circuit 70 outputs a ninth target signal LS;

[0044] The drain of the high-side GaN transistor 80 is connected to the external input voltage terminal; the source of the low-side GaN transistor 90 is grounded.

[0045] In the half-bridge circuit of the present embodiment, by designing an undervoltage and overvoltage protection circuit 10 and an overcurrent protection circuit 20, effective protection is achieved for the high-side gallium nitride transistor 80 and the low-side gallium nitride transistor 90 in the circuit, thereby reducing the damage to the power device in an abnormal working state of the circuit; by designing a dead time generation circuit 30, the high-side gallium nitride transistor 80 and the low-side gallium nitride transistor 90 are prevented from being connected up and down, thereby improving the circuit reliability; by designing a level shift circuit 50, the input signal of the low-voltage domain is converted to the high-voltage domain, and the risk of the high-side gallium nitride transistor 80 being turned on and off by mistake is reduced; by designing a signal control circuit 40, it is ensured that the high-side gallium nitride transistor 80 and the low-side gallium nitride transistor 90 are turned off when the circuit works in an abnormal state, thereby further improving the stability and reliability of the half-bridge circuit.

[0046] See also Figure 2In one embodiment of the present application, the undervoltage and overvoltage protection circuit 10 includes: a first resistor R1, a second resistor R2, a third resistor R3, a first hysteresis comparator 14, a second hysteresis comparator 15, a first inverter 16, a first NAND gate 17 and a second inverter 18; the first resistor R1, the second resistor R2 and the third resistor R3 are connected in series in sequence, the first end of the first resistor R1 is connected to the power supply end, the external power supply end outputs the power supply voltage VCC, and the second end of the third resistor R3 is grounded; the inverting input end of the first hysteresis comparator 14 is connected to the common end of the first resistor R1 and the second resistor R2, and the non-inverting input end of the first hysteresis comparator 14 is connected to the non-inverting input end of the second hysteresis comparator 15. The output end of the first hysteresis comparator 14 is connected to the input end of the first inverter 16; the inverting input end of the second hysteresis comparator 15 is connected to the common end of the second resistor R2 and the third resistor R3, and the output end of the second hysteresis comparator 15 is connected to the second input end of the first NAND gate 17; the output end of the first inverter 16 is connected to the first input end of the first NAND gate 17; the output end of the first NAND gate 17 is connected to the input end of the second inverter 18; the output end of the second inverter 18 is connected to the output end of the undervoltage and overvoltage protection circuit 10, and the output end of the undervoltage and overvoltage protection circuit 10 outputs the first target signal UVP&OVP.

[0047] It is understandable that the high level of the gate signal of the power device is determined by the supply voltage of the output rail-to-rail drive. If the supply voltage of the drive is too low, the power device may not be fully turned on and the on-resistance is high. If the supply voltage of the drive is too high, exceeding the gate-source withstand voltage of the power device, it may cause the performance of the device to degrade or even cause the device to break down. The embodiment of the present invention improves the circuit reliability by designing the undervoltage and overvoltage protection circuit 10 to ensure that the supply voltage of the drive circuit is within the normal range.

[0048] In a specific embodiment of the present application, the input reference voltage VREF can be set to 1.5VTH-2VTH, where VTH is the threshold voltage of the enhancement mode gallium nitride transistor, the undervoltage protection point is VREF*(R1+R2+R3) / (R2+R3), and the overvoltage protection point is VREF*(R1+R2+R3) / R3. By adopting a hysteresis comparator, a certain hysteresis voltage is present at the undervoltage protection point and the overvoltage protection point during the power-on and power-off process, thereby ensuring the high reliability of the overall circuit.

[0049] See also Figure 3In one embodiment of the present application, the first hysteresis comparator 14 includes: a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a first enhancement-mode gallium nitride transistor Q1, a second enhancement-mode gallium nitride transistor Q2, a third enhancement-mode gallium nitride transistor Q3, a fourth enhancement-mode gallium nitride transistor Q4, a fifth enhancement-mode gallium nitride transistor Q5, a sixth enhancement-mode gallium nitride transistor Q6, a seventh enhancement-mode gallium nitride transistor Q7, an eighth enhancement-mode gallium nitride transistor Q8, a ninth enhancement-mode gallium nitride transistor Q9, a tenth enhancement-mode gallium nitride transistor Q10, a tenth enhancement-mode gallium nitride transistor Q11, a twelfth enhancement-mode gallium nitride transistor Q12, a twelfth enhancement-mode gallium nitride transistor Q13, a twelfth enhancement-mode gallium nitride transistor Q14, a twelfth enhancement-mode gallium nitride transistor Q15, a twelfth enhancement-mode gallium nitride transistor Q16, a twelfth enhancement-mode gallium nitride transistor Q17, a twelfth enhancement-mode gallium nitride transistor Q18, a twelfth enhancement-mode gallium nitride transistor Q19, a twelfth enhancement-mode gallium nitride transistor Q20, a twelfth enhancement-mode gallium nitride transistor Q21, a twelfth enhancement-mode gallium nitride transistor Q22, a twelfth enhancement-mode gallium nitride transistor Q23, a twelfth enhancement-mode gallium nitride transistor Q24, a twelfth enhancement-mode gallium nitride transistor Q25, a gallium nitride transistor Q12; a first end of the fourth resistor R4, a first end of the fifth resistor R5, a first end of the sixth resistor R6, and a first end of the seventh resistor R7 are connected to the power supply end; a second end of the fourth resistor R4 is connected to the drain of the first enhancement-mode gallium nitride transistor Q1 and the gate of the fifth enhancement-mode gallium nitride transistor Q5, a second end of the fifth resistor R5 is connected to the drain of the third enhancement-mode gallium nitride transistor Q3 and the gate of the ninth enhancement-mode gallium nitride transistor Q9, a second end of the sixth resistor R6 is connected to the drain of the eleventh enhancement-mode gallium nitride transistor Q11 and the gate of the twelfth enhancement-mode gallium nitride transistor Q12 The second end of the seventh resistor R7 is connected to the drain of the twelfth enhancement-mode GaN transistor Q12 and the output end of the first hysteresis comparator 14; the gate of the first enhancement-mode GaN transistor Q1 is connected to the reference voltage end, the source of the first enhancement-mode GaN transistor Q1 is connected to the drain of the second enhancement-mode GaN transistor Q2, the source of the third enhancement-mode GaN transistor Q3 and the drain of the fourth enhancement-mode GaN transistor Q4; the gate of the second enhancement-mode GaN transistor Q2 is connected to the gate of the eighth enhancement-mode GaN transistor Q8, the gate of the tenth enhancement-mode GaN transistor Q10, the gate of the eleventh enhancement-mode GaN transistor Q1 1, the source of the ninth enhancement-mode gallium nitride transistor Q9 and the drain of the seventh enhancement-mode gallium nitride transistor Q7; the gate of the third enhancement-mode gallium nitride transistor Q3 is connected to the input voltage terminal; the gate of the fourth enhancement-mode gallium nitride transistor Q4 is connected to the source of the fifth enhancement-mode gallium nitride transistor Q5, the drain of the sixth enhancement-mode gallium nitride transistor Q6, the gate of the sixth enhancement-mode gallium nitride transistor Q6, the gate of the seventh enhancement-mode gallium nitride transistor Q7 and the drain of the eighth enhancement-mode gallium nitride transistor Q8; the drain of the fifth enhancement-mode gallium nitride transistor Q5 and the drain of the ninth enhancement-mode gallium nitride transistor Q9 are connected to the power supply terminal;The source of the second enhancement-mode gallium nitride transistor Q2, the source of the fourth enhancement-mode gallium nitride transistor Q4, the source of the sixth enhancement-mode gallium nitride transistor Q6, the source of the seventh enhancement-mode gallium nitride transistor Q7, the source of the eighth enhancement-mode gallium nitride transistor Q8, the source of the tenth enhancement-mode gallium nitride transistor Q10, the source of the eleventh enhancement-mode gallium nitride transistor Q11, and the source of the twelfth enhancement-mode gallium nitride transistor Q12 are grounded. ;

[0050] Specifically, the hysteresis of the first hysteresis comparator 14 is caused by the positive feedback introduced by the seventh enhancement-mode gallium nitride transistor Q7 and the eighth enhancement-mode gallium nitride transistor Q8, and the magnitude of the hysteresis voltage can be changed by changing the width-to-length ratio of the sixth enhancement-mode gallium nitride transistor Q6 to the seventh enhancement-mode gallium nitride transistor Q7 and the width-to-length ratio of the tenth enhancement-mode gallium nitride transistor Q10 to the eighth enhancement-mode gallium nitride transistor Q8.

[0051] It should be noted that the structure of the second hysteresis comparator 15 is the same as that of the first hysteresis comparator 14 , and the specific description may refer to the first hysteresis comparator 14 .

[0052] See also Figure 4 In one embodiment of the present application, the overcurrent protection circuit 20 includes: a thirteenth enhancement-mode gallium nitride transistor Q13, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a third hysteresis comparator 25 and a first leading edge blanking circuit 26; the eighth resistor R8, the ninth resistor R9 and the tenth resistor R10 are connected in series in sequence, the first end of the eighth resistor R8 is connected to the power supply end, and the second end of the tenth resistor R10 is connected to the source of the low-side gallium nitride transistor 90; the drain of the thirteenth enhancement-mode gallium nitride transistor Q13 is connected to the drain of the low-side gallium nitride transistor 90, and the The gate of the thirteenth enhancement-mode gallium nitride transistor Q13 is connected to the gate of the low-side gallium nitride transistor 90, and the source of the thirteenth enhancement-mode gallium nitride transistor Q13 is connected to the common end of the ninth resistor R9 and the tenth resistor R10; the non-inverting input end of the third hysteresis comparator 25 is connected to the common end of the eighth resistor R8 and the ninth resistor R9, the inverting input end of the third hysteresis comparator 25 is connected to the reference voltage end, and the output end of the third hysteresis comparator 25 is connected to the input end of the first leading edge blanking circuit 26; the output end of the first leading edge blanking circuit is connected to the output end of the overcurrent protection circuit 20.

[0053] It should be noted that the structure of the third hysteresis comparator 25 is the same as that of the first hysteresis comparator 14 , and the details may refer to the related description of the first hysteresis comparator 14 .

[0054] It is understandable that the full gallium nitride integrated half-bridge circuit 100 generally operates at a relatively high frequency. When the switch is switched, the parasitic inductance and capacitance in the circuit will cause the power device to be mistakenly turned on, so that the power circuit generates a large current due to the upper and lower connections, or when the load is short-circuited, the power circuit will also generate a large current. The large current in the circuit will not only generate a large amount of power loss, but also damage the power device, affecting the normal operation of the circuit, or even damage it. Therefore, in this embodiment, an overcurrent protection circuit 20 is designed to detect the size of the power circuit current through current replication, and then convert the current signal into a voltage signal and compare it with the reference voltage to generate a detection signal. When the highway loop has a large current, the detection signal will flip from a high level to a low level, and the current burrs in the switch switching process will be eliminated through the blanking circuit, and finally a stable shutdown signal (OVP) will be generated to the drive circuit, thereby controlling the shutdown of the power device.

[0055] See also Figure 5 In a specific embodiment of the present application, the first leading edge blanking circuit 26 includes: a third inverter 261, a first low-pass filter 262, a first hysteresis inverter 263, and a second NAND gate 264; the input end of the third inverter 261 and the first input end of the second NAND gate 264 are connected to the output end of the third hysteresis comparator 25, and the output end of the third inverter 261 is connected to the input end of the first low-pass filter 262; the output end of the first low-pass filter 262 is connected to the input end of the first hysteresis inverter 263; the output end of the first hysteresis inverter 263 is connected to the second input end of the second NAND gate 264, and the output end of the second NAND gate 264 is connected to the output end of the first leading edge blanking circuit 26.

[0056] It should be noted that, in this embodiment, no specific restrictions are imposed on the circuit structures of the first low-pass filter 262 and the first hysteresis inverter 263. For example, the circuit structure of the first low-pass filter 262 may be as follows: Figure 6 As shown, the circuit structure of the first hysteresis inverter 263 can be as follows: Figure 7 shown.

[0057] See also Figure 8In one embodiment of the present application, the dead time generating circuit 30 comprises: a fourth inverter 301, a third NAND gate 302, a fourth NAND gate 303, a fourteenth enhancement-mode gallium nitride transistor Q14, a fifteenth enhancement-mode gallium nitride transistor Q15, a second hysteresis inverter 306, a third hysteresis inverter 307, a fifth inverter 308, a sixth inverter 309, a seventh inverter 310 and an eighth inverter 311; the input terminal of the fourth inverter 301 and the The second input terminal of the fourth NAND gate 303 is connected to the control signal terminal, the output terminal of the fourth inverter 301 is connected to the first input terminal of the third NAND gate 302; the second input terminal of the third NAND gate 302 is connected to the gate of the fifteenth enhancement-mode gallium nitride transistor Q15, the output terminal of the fourth NAND gate 303 and the input terminal of the third hysteresis inverter 307, the output terminal of the third NAND gate 302 is connected to the gate of the fourteenth enhancement-mode gallium nitride transistor Q15, the output terminal of the fourth NAND gate 303 and the input terminal of the third hysteresis inverter 307, the output terminal of the third NAND gate 302 is connected to the gate of the fifteen ... third NAND gate 302 is connected to the gate of the fifteenth enhancement-mode gallium nitride transistor Q15, the output terminal of the third The gate of the fourth NAND gate 303 is connected to the gate of the transistor Q14, the first input terminal of the fourth NAND gate 303 and the input terminal of the second hysteresis inverter 306; the source of the fourteenth enhancement-mode gallium nitride transistor Q14, the drain of the fourteenth enhancement-mode gallium nitride transistor Q14, the source of the fifteenth enhancement-mode gallium nitride transistor Q15 and the drain of the fifteenth enhancement-mode gallium nitride transistor Q15 are grounded; the output of the second hysteresis inverter 306 is connected to the input terminal of the fifth inverter, the output terminal of the fifth inverter 308 is connected to the input terminal of the sixth inverter 309, and the output terminal of the sixth inverter 309 is connected to the first output terminal of the dead time generating circuit 30; the output of the third hysteresis inverter 307 is connected to the input terminal of the seventh inverter 310, the output terminal of the seventh inverter 310 is connected to the input terminal of the eighth inverter 311, and the output terminal of the seventh inverter 310 is connected to the second output terminal of the dead time generating circuit 30.

[0058] It can be understood that, since the size of the high-side GaN transistor 80 and the low-side GaN transistor 90 is very large, the parasitic capacitance of the gate terminal is also very large. If the input signal has no dead time, even if it is a complementary signal, due to the delay of the circuit and the delay caused by the large capacitance of the gate terminal, the high-side GaN transistor 80 and the low-side GaN transistor 90 will be turned on at the same time. The high and low-side GaN transistors 90 will be connected up and down to generate a large current, thereby burning the power device. Therefore, in this embodiment, a dead time generating circuit 30 is designed, so that the gate signals reaching the high-side GaN transistor 80 and the low-side GaN transistor 90 have a certain dead time, ensuring that the high-side GaN transistor 80 and the low-side GaN transistor 90 are not turned on at the same time and connected up and down to cause the device to burn, thereby improving the stability of the circuit.

[0059] See also Fig. 9In one embodiment of the present application, the signal control circuit 40 includes: a fifth NAND gate 41, a sixth NAND gate 43, a seventh NAND gate 45, a ninth inverter 42, a tenth inverter 44, and an eleventh inverter 46; a first input end of the fifth NAND gate 41 is connected to the first input end of the signal control circuit 40, a second input end of the fifth NAND gate 41 is connected to the fourth input end of the signal control circuit 40, and an output end of the fifth NAND gate 41 is connected to the input end of the ninth inverter 42; an output end of the ninth inverter 42 is connected to the first input end of the sixth NAND gate 43 and the first input end of the seventh NAND gate 45. The output end of the ninth inverter 42 outputs the CONT signal; the second input end of the sixth NAND gate 43 is connected to the second input end of the signal control circuit 40, and the output end of the sixth NAND gate 43 is connected to the input end of the tenth inverter; the output end of the tenth inverter 44 is connected to the first output end of the signal control circuit 40; the second input end of the seventh NAND gate 45 is connected to the third input end of the signal control circuit 40, and the output end of the seventh NAND gate 45 is connected to the input end of the eleventh inverter 46; the output end of the eleventh inverter 46 is connected to the second output end of the signal control circuit 40.

[0060] In a specific embodiment, when any one of the first target signal (UVP&OVP) and the second target signal (OCP) is at a low level, the signal control circuit 40 sets the output third target signal (PWM_INA) and the fourth target signal (PWM_INB) to 0; when the first target signal (UVP&OVP) and the second target signal (OCP) are both at a high level, the signal control circuit 40 outputs the third target signal (PWM_INA) and the fourth target signal normally.

[0061] See also Fig.10In one embodiment of the present application, the level shift circuit 50 includes: an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a sixteenth enhancement-type gallium nitride transistor Q16, a sixteenth enhancement-type gallium nitride transistor Q16, a sixteenth enhancement-type gallium nitride transistor Q16, a seventeenth enhancement-type gallium nitride transistor Q17, an eighteenth enhancement-type gallium nitride transistor Q18, a nineteenth enhancement-type gallium nitride transistor Q19, a twentieth enhancement-type gallium nitride transistor Q20, a twenty-first enhancement-type gallium nitride transistor Q21, a twenty-second enhancement-type gallium nitride transistor Q22, a twenty-third enhancement-type gallium nitride transistor Q23, a twenty-fourth enhancement-type gallium nitride transistor Q24, a twenty-fifth enhancement-type gallium nitride transistor Q25, a twenty-fifth enhancement-type gallium nitride transistor Q26, a twenty-third enhancement-type gallium nitride transistor Q27, a twenty-fourth enhancement-type gallium nitride transistor Q28, a twenty-fifth enhancement-type gallium nitride transistor Q29, a twenty-fifth enhancement-type gallium nitride transistor Q21, a twenty-fifth enhancement-type gallium nitride transistor Q22, a twenty-third enhancement-type gallium nitride transistor Q23, a twenty-fourth enhancement-type gallium nitride transistor Q24, a twenty-fifth enhancement-type gallium nitride transistor Q25, a twenty-fifth enhancement-type gallium nitride transistor Q26, a twenty-fifth enhancement-type gallium nitride transistor Q27, a twenty-fifth enhancement-type gallium nitride transistor Q28, a twenty-fif the drain of the sixteenth enhancement mode gallium nitride transistor Q16, the gate of the sixteenth enhancement mode gallium nitride transistor Q16, the drain of the seventeenth enhancement mode gallium nitride transistor Q17, the gate of the seventeenth enhancement mode gallium nitride transistor Q17, the drain of the seventeenth enhancement mode gallium nitride transistor Q17, the gate of the eighteenth enhancement mode gallium nitride transistor Q17, the drain of the sixteenth enhancement mode gallium nitride transistor Q17, the drain of the seventeenth enhancement mode gallium nitride transistor Q17, the gate of the eighteenth enhancement mode gallium nitride transistor Q17, the drain of the sixteenth enhancement mode gallium nitride transistor Q17, the drain of the seventeenth enhancement mode gallium nitride transistor Q17, the drain of the seventeenth enhancement mode gallium nitride transistor Q17, the drain of the seventeenth enhancement mode gallium nitride transistor Q17, the drain of the seventeenth enhancement mode gallium nitride transistor Q17, the drain of the eighteenth enhancement mode gallium nitride transistor Q17, the drain of the six ... The drain of the eighteenth enhancement-mode gallium nitride transistor Q18, the gate of the eighteenth enhancement-mode gallium nitride transistor Q18, the drain of the nineteenth enhancement-mode gallium nitride transistor Q19, the gate of the nineteenth enhancement-mode gallium nitride transistor Q19 and the first end of the fifteenth resistor R15 are connected to the bootstrap voltage terminal; the source of the sixteenth enhancement-mode gallium nitride transistor Q16 is connected to the first end of the eleventh resistor R11 and the gate of the twentieth enhancement-mode gallium nitride transistor Q20; the source of the seventeenth enhancement-mode gallium nitride transistor Q17 is connected to the first end of the twelfth resistor R12; the source of the eighteenth enhancement-mode gallium nitride transistor Q18 is connected to the first end of the thirteenth resistor R13; the source of the nineteenth enhancement-mode gallium nitride transistor Q19 is connected to the first end of the thirteenth resistor R13; The source of the gallium nitride transistor Q19 is connected to the first end of the fourteenth resistor R14 and the gate of the twenty-third enhancement-mode gallium nitride transistor Q23; the second end of the fifteenth resistor R15 is connected to the drain of the twenty-fourth enhancement-mode gallium nitride transistor Q24 and the output end of the level shift circuit 50; the second end of the eleventh resistor R11 is connected to the drain of the twenty-seventh enhancement-mode gallium nitride transistor Q27 and the source of the twentieth enhancement-mode gallium nitride transistor Q20; the drain of the twentieth enhancement-mode gallium nitride transistor Q20 is connected to the second end of the twelfth resistor R12, the drain of the twenty-first enhancement-mode gallium nitride transistor Q21 and the gate of the twenty-second enhancement-mode gallium nitride transistor Q22;The gate of the twenty-first enhancement mode GaN transistor Q21 is connected to the second end of the thirteenth resistor R13, the drain of the twenty-second enhancement mode GaN transistor Q22, the drain of the twenty-third enhancement mode GaN transistor Q23, and the gate of the twenty-fourth enhancement mode GaN transistor Q24; the source of the twenty-first enhancement mode GaN transistor Q21 is connected to the drain of the twenty-fifth enhancement mode GaN transistor Q25 and the gate of the twenty-fifth enhancement mode GaN transistor Q25; the source of the twenty-second enhancement mode GaN transistor Q22 is connected to the drain of the twenty-sixth enhancement mode GaN transistor Q24. The drain of the transistor Q26 and the gate of the twenty-sixth enhancement-mode gallium nitride transistor Q26 are connected to the switch node of the half-bridge circuit; the gate of the twenty-seventh enhancement-mode gallium nitride transistor Q27 and the gate of the twenty-eighth enhancement-mode gallium nitride transistor Q28 are connected to the drain of the transistor Q26 and the gate of the twenty-sixth enhancement-mode gallium nitride transistor Q26; the source of the twenty-third enhancement-mode gallium nitride transistor Q23 is connected to the second end of the fourteenth resistor R14 and the drain of the twenty-eighth enhancement-mode gallium nitride transistor Q28; the source of the twenty-fifth enhancement-mode gallium nitride transistor Q25, the source of the twenty-sixth enhancement-mode gallium nitride transistor Q26, and the source of the twenty-fourth enhancement-mode gallium nitride transistor Q24 are connected to the switch node of the half-bridge circuit; the gate of the twenty-seventh enhancement-mode gallium nitride transistor Q27 and the gate of the twenty-eighth enhancement-mode gallium nitride transistor Q28 ... drain of the transistor Q26 and the gate of the twenty-sixth enhancement-mode gallium nitride transistor Q28; the source of the twenty-fifth enhancement-mode gallium nitride transistor Q25, the source of the twenty-sixth enhancement-mode gallium nitride transistor Q26, and the source of the twenty-fourth enhancement-mode gallium nitride transistor Q24 are connected to the switch node of the half-bridge circuit; the gate of the twenty-seventh enhancement-mode gallium nitride transistor Q27 and the gate of the twenty-eighth enhancement-mode gallium nitride transistor Q28 are connected The gate of the 27th enhancement mode GaN transistor Q27 is connected to the power supply terminal; the source of the 29th enhancement mode GaN transistor Q29 is connected to the drain of the 30th enhancement mode GaN transistor Q30; the gate of the 29th enhancement mode GaN transistor Q29 is connected to the output terminal of the twelfth inverter 506, and the source of the 29th enhancement mode GaN transistor Q29 is connected to the source of the 30th enhancement mode GaN transistor Q30 and the drain of the 32nd enhancement mode GaN transistor Q32. drain; the input terminal of the twelfth inverter 506 and the gate of the thirtieth enhancement-mode gallium nitride transistor Q30 are connected to the third input terminal of the level shift circuit 50; the first end of the sixteenth resistor R16 is connected to the power supply terminal, and the second end of the sixteenth resistor R16 is connected to the drain of the thirty-first enhancement-mode gallium nitride transistor Q31, the gate of the thirty-first enhancement-mode gallium nitride transistor Q31 and the gate of the thirty-second enhancement-mode gallium nitride transistor Q32; the source of the thirty-first enhancement-mode gallium nitride transistor Q31 and the source of the thirty-second enhancement-mode gallium nitride transistor Q32 are grounded. ;

[0062] It is understandable that the half-bridge circuit working at a high frequency is prone to erroneous opening or shutting down of the high-side power device due to the oscillation generated by the parasitic inductance and capacitance, which seriously affects the stability of the half-bridge circuit. Therefore, in this embodiment, a level shift circuit 50 is designed to isolate the low-voltage domain and the high-voltage domain of the circuit through a high-voltage tube. The circuit includes a complementary automatic shut-off device and an interlocking unit, which reduces the problem of erroneous opening and shutting down of the high-side power device during the switching process of the high-frequency switch signal through an automatic locking signal.

[0063] See also Fig.11In one embodiment of the present application, the high-side driving circuit 60 includes: a seventeenth resistor R17, an eighteenth resistor R18, a nineteenth resistor R19, a twentieth resistor R20, a first capacitor C1, a second capacitor C2, a thirty-third enhancement-type gallium nitride transistor Q33, a thirty-fourth enhancement-type gallium nitride transistor Q34, a thirty-fifth enhancement-type gallium nitride transistor Q35, a thirty-sixth enhancement-type gallium nitride transistor Q36, a thirty-seventh enhancement-type gallium nitride transistor Q37, a thirty-eighth enhancement-type gallium nitride transistor Q38, a thirty-ninth enhancement-type gallium nitride transistor Q39, a fortieth enhancement-type gallium nitride transistor Q40, and a forty-first enhancement-type gallium nitride transistor Q41. the seventeenth resistor R17 and the eighteenth resistor R18 are connected in series, the first end of the seventeenth resistor R17 is connected to the first output end of the level shift circuit 50, and the second end of the eighteenth resistor R18 is connected to the drain of the thirty-seventh enhancement-mode gallium nitride transistor Q37; the gate of the thirty-third enhancement-mode gallium nitride transistor Q33, the drain of the thirty-third enhancement-mode gallium nitride transistor Q33, the gate of the thirty-fourth enhancement-mode gallium nitride transistor Q34, the drain of the thirty-fourth enhancement-mode gallium nitride transistor Q34, the drain of the thirty-fifth enhancement-mode gallium nitride transistor Q35 and the drain of the thirty-sixth enhancement-mode gallium nitride transistor Q36. The drain of the GaN transistor Q36 is connected to the bootstrap voltage terminal; the source of the thirty-third enhancement-mode GaN transistor Q33 is connected to the first end of the nineteenth resistor R19 and the first end of the first capacitor C1; the source of the thirty-fourth enhancement-mode GaN transistor Q34 is connected to the first end of the twentieth resistor R20 and the first end of the second capacitor C2; the second end of the nineteenth resistor R19 is connected to the gate of the thirty-fifth enhancement-mode GaN transistor Q35 and the drain of the thirty-eighth enhancement-mode GaN transistor Q38; the second end of the first capacitor C1 is connected to the source of the thirty-fifth enhancement-mode GaN transistor Q35 , the drain of the thirty-ninth enhancement mode gallium nitride transistor Q39, the gate of the thirty-seventh enhancement mode gallium nitride transistor Q37, the gate of the fortieth enhancement mode gallium nitride transistor Q40 and the gate of the forty-first enhancement mode gallium nitride transistor Q41; the second end of the twentieth resistor R20 is connected to the drain of the fortieth enhancement mode gallium nitride transistor Q40 and the gate of the thirty-sixth enhancement mode gallium nitride transistor Q36, and the second end of the second capacitor C2 is connected to the source of the thirty-sixth enhancement mode gallium nitride transistor Q36, the drain of the forty-first enhancement mode gallium nitride transistor Q41 and the output end of the high-side drive circuit 60;The source of the thirty-seventh enhancement-mode gallium nitride transistor Q37, the source of the thirty-eighth enhancement-mode gallium nitride transistor Q38, the source of the thirty-ninth enhancement-mode gallium nitride transistor Q39, the source of the fortieth enhancement-mode gallium nitride transistor Q40, and the source of the forty-first enhancement-mode gallium nitride transistor Q41 are connected to the switch node of the half-bridge circuit. ;

[0064] It should be noted that, due to the lack of p-type gallium nitride devices in the current gallium nitride process, the pull-up of the inverter can only use a resistor. If an inverter chain drive is used, it will generate large power consumption and delay, and it is also impossible to output the drive signal rail-to-rail. Therefore, in this embodiment, the drive circuit feedback stage plus two-stage bootstrap drive stage are used. The bootstrap drive stage can output the drive signal rail-to-rail while having lower power consumption and delay. The feedback stage further reduces the delay of the circuit through positive feedback.

[0065] In a specific embodiment of the present application, for the bootstrap driving stage, when the input signal is at a high level, the thirty-eighth enhancement-type gallium nitride transistor 4Q38 and the thirty-ninth enhancement-type gallium nitride transistor Q39 are turned on, the thirty-fifth enhancement-type gallium nitride transistor Q35 is turned off, and the upper plate of the first capacitor C1 is charged to the power supply voltage VCC. When the input signal changes to a low level, the thirty-eighth enhancement-type gallium nitride transistor Q38 and the thirty-ninth enhancement-type gallium nitride transistor Q39 are turned off, the thirty-fifth enhancement-type gallium nitride transistor Q35 is turned on, and when the thirty-fifth enhancement-type gallium nitride transistor Q3 5 becomes VCC, due to the characteristic that the voltage across the capacitor cannot change suddenly, the source voltage of the thirty-third enhancement-mode gallium nitride transistor Q33 becomes VCC+VCC-VD=2VCC-VD, where VD is the on-voltage of the thirty-third enhancement-mode gallium nitride crystal Q33 connected in the form of a diode, so that the gate voltage of the thirty-fifth enhancement-mode gallium nitride crystal Q35 is greater than the source voltage VCC-VD, which can ensure that the thirty-fifth enhancement-mode gallium nitride crystal Q35 is normally turned on and the drive can output rail-to-rail. The feedback stage can make the drive circuit have a lower transmission delay.

[0066] See also Fig.12In one embodiment of the present application, the low-side driving circuit 70 includes: a twenty-first resistor R21, a twenty-second resistor R22, a twenty-third resistor R23, a twenty-fourth resistor R24, a third capacitor C3, a fourth capacitor C4, a forty-second enhancement type gallium nitride transistor Q42, a forty-third enhancement type gallium nitride transistor Q43, a forty-fourth enhancement type gallium nitride transistor Q44, a forty-fifth enhancement type gallium nitride transistor Q45, a forty-sixth enhancement type gallium nitride transistor Q46, a forty-seventh enhancement type gallium nitride transistor Q47, a forty-eighth enhancement type gallium nitride transistor Q48, a forty-ninth enhancement type gallium nitride transistor Q49, and a fiftieth enhancement type gallium nitride transistor Q41. the transistor Q50, the twenty-first resistor R21 and the twenty-second resistor R22 are connected in series, the first end of the twenty-first resistor R21 is connected to the second output end of the signal control circuit 40, the second end of the twenty-second resistor R22 is connected to the drain of the forty-sixth enhancement mode gallium nitride transistor Q46; the gate of the forty-second enhancement mode gallium nitride transistor Q42, the drain of the forty-second enhancement mode gallium nitride transistor Q42, the gate of the forty-third enhancement mode gallium nitride transistor Q43, the drain of the forty-third enhancement mode gallium nitride transistor Q43, the drain of the forty-fourth enhancement mode gallium nitride transistor Q44 and the forty-fifth enhancement mode gallium nitride transistor Q45 are connected to the drain of the forty-sixth enhancement mode gallium nitride transistor Q46; the gate of the forty-second enhancement mode gallium nitride transistor Q42, the drain of the forty-second enhancement mode gallium nitride transistor Q42, the gate of the forty-third enhancement mode gallium nitride transistor Q43, the drain of the forty-fourth enhancement mode gallium nitride transistor Q44 and the drain of the forty-fifth enhancement mode gallium nitride transistor Q45 are connected to the drain of the forty-sixth enhancement mode gallium nitride transistor Q4 ... The drain of the enhancement-mode gallium nitride transistor Q45 is connected to the power supply terminal; the source of the forty-second enhancement-mode gallium nitride transistor Q42 is connected to the first end of the twenty-third resistor R23 and the first end of the third capacitor C3; the source of the forty-third enhancement-mode gallium nitride transistor Q43 is connected to the first end of the twenty-fourth resistor R24 ​​and the first end of the fourth capacitor C4; the second end of the twenty-third resistor R23 is connected to the gate of the forty-fourth enhancement-mode gallium nitride transistor Q44 and the drain of the forty-seventh enhancement-mode gallium nitride transistor Q47; the second end of the third capacitor C ... a second end of the fourth capacitor C4 is connected to the source of the forty-fifth enhancement mode gallium nitride transistor Q45, the drain of the forty-fifth enhancement mode gallium nitride transistor Q50, and the output end of the low-side drive circuit 70; a second end of the twenty-fourth resistor R24 ​​is connected to the drain of the forty-ninth enhancement mode gallium nitride transistor Q49 and the gate of the forty-fifth enhancement mode gallium nitride transistor Q45, and a second end of the fourth capacitor C4 is connected to the source of the forty-fifth enhancement mode gallium nitride transistor Q45, the drain of the fiftieth enhancement mode gallium nitride transistor Q50, and the output end of the low-side drive circuit 70;The source of the forty-sixth enhancement-mode gallium nitride transistor Q46, the source of the forty-seventh enhancement-mode gallium nitride transistor Q47, the source of the forty-eighth enhancement-mode gallium nitride transistor Q48, the source of the forty-ninth enhancement-mode gallium nitride transistor Q49, and the source of the fiftieth enhancement-mode gallium nitride transistor Q50 are connected to the ground. ;

[0067] It should be noted that the low-side driving circuit 70 and the high-side driving circuit 60 have the same working principle, and the relevant description of the high-side driving circuit 60 may be referred to for details.

[0068] The present application provides a full gallium nitride integrated half-bridge circuit 100, which has the following beneficial effects:

[0069] 1. The fully gallium nitride integrated high-reliability half-bridge circuit of the present invention integrates the gallium nitride half-bridge drive circuit and the gallium nitride high- and low-side power devices, reducing parasitic inductance and capacitance, so that the gallium nitride power devices can operate at a higher switching frequency. 2. The fully gallium nitride integrated high-reliability half-bridge circuit of the present invention integrates undervoltage protection and overcurrent protection while also including an overvoltage protection circuit to prevent excessive voltage applied to the gate of the gallium nitride power device from causing performance degradation or even damage to the device, thereby improving the reliability of the circuit. 3. The fully gallium nitride integrated high-reliability half-bridge circuit of the present invention uses an automatic locking logic signal to automatically disconnect the level shifting circuit between the high-side ground and the low-side ground, effectively reducing the risk of false start and close of the high-side power device, and effectively improving the stability and reliability of the half-bridge circuit.

[0070] The present application also provides a chip, wherein the chip includes: the all-gallium nitride integrated half-bridge circuit 100 as described in any one of the above.

[0071] The present application also provides an electronic device, which includes: the chip as described above.

[0072] The above description is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.

Claims

1. A full gallium nitride integrated half-bridge circuit, characterized in that: include: Undervoltage and overvoltage protection circuit, overcurrent protection circuit, dead time generation circuit, signal control circuit, level shift circuit, high-side drive circuit, low-side drive circuit, high-side gallium nitride transistor and low-side gallium nitride transistor; The first input terminal of the undervoltage and overvoltage protection circuit is connected to an external power supply terminal, the second input terminal of the undervoltage and overvoltage protection circuit is connected to an external reference voltage terminal, and the output terminal of the undervoltage and overvoltage protection circuit is connected to the first input terminal of the signal control circuit; The first input terminal of the overcurrent protection circuit is connected to the gate of the low-side gallium nitride transistor, the second input terminal of the overcurrent protection circuit is connected to the drain of the low-side gallium nitride transistor, the third input terminal of the overcurrent protection circuit is connected to the external power supply terminal, the fourth input terminal of the overcurrent protection circuit is connected to the reference voltage terminal, and the output terminal of the overcurrent protection circuit is connected to the fourth input terminal of the signal control circuit; The first input terminal of the dead time generating circuit is connected to the control signal terminal, the second input terminal of the dead time generating circuit is connected to the power supply terminal, the first output terminal of the dead time generating circuit is connected to the second input terminal of the signal control circuit, and the second output terminal of the dead time generating circuit is connected to the third input terminal of the signal control circuit; The fifth input terminal of the signal control circuit is connected to the power supply terminal, the first output terminal of the signal control circuit is connected to the third input terminal of the level shift circuit, and the second output terminal of the signal control circuit is connected to the first input terminal of the low-side drive circuit; The first input end of the level shift circuit is connected to the power supply end, the second input end of the level shift circuit is connected to the external bootstrap voltage end, and the first output end of the level shift circuit is connected to the second input end of the high-side drive circuit; The first input terminal of the high-side driving circuit is connected to the bootstrap voltage terminal, and the first output terminal of the high-side driving circuit is connected to the gate of the high-side gallium nitride transistor; The second input terminal of the low-side driving circuit is connected to the external power supply terminal, and the first output terminal of the low-side driving circuit is connected to the gate of the low-side gallium nitride transistor; The drain of the high-side gallium nitride transistor is connected to an external input voltage terminal; the source of the low-side gallium nitride transistor is grounded.

2. The all-gallium nitride integrated half-bridge circuit according to claim 1, characterized in that: The undervoltage and overvoltage protection circuit comprises: a first resistor, a second resistor, a third resistor, a first hysteresis comparator, a second hysteresis comparator, a first inverter, a first NAND gate and a second inverter; The first resistor, the second resistor and the third resistor are connected in series in sequence, a first end of the first resistor is connected to the power supply end, and a second end of the third resistor is grounded; The inverting input terminal of the first hysteresis comparator is connected to the common terminal of the first resistor and the second resistor, the non-inverting input terminal of the first hysteresis comparator is connected to the non-inverting input terminal of the second hysteresis comparator and the reference voltage terminal, and the output terminal of the first hysteresis comparator is connected to the input terminal of the first inverter; The inverting input terminal of the second hysteresis comparator is connected to the common terminal of the second resistor and the third resistor, and the output terminal of the second hysteresis comparator is connected to the second input terminal of the first NAND gate; The output terminal of the first inverter is connected to the first input terminal of the first NAND gate; The output end of the first NAND gate is connected to the input end of the second inverter; the output end of the second inverter is connected to the output end of the undervoltage and overvoltage protection circuit.

3. The all-gallium nitride integrated half-bridge circuit according to claim 2, characterized in that: The first hysteresis comparator includes: a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, a first enhancement-mode gallium nitride transistor, a second enhancement-mode gallium nitride transistor, a third enhancement-mode gallium nitride transistor, a fourth enhancement-mode gallium nitride transistor, a fifth enhancement-mode gallium nitride transistor, a sixth enhancement-mode gallium nitride transistor, a seventh enhancement-mode gallium nitride transistor, an eighth enhancement-mode gallium nitride transistor, a ninth enhancement-mode gallium nitride transistor, a tenth enhancement-mode gallium nitride transistor, a tenth enhancement-mode gallium nitride transistor, an eleventh enhancement-mode gallium nitride transistor, and a twelfth enhancement-mode gallium nitride transistor; The first end of the fourth resistor, the first end of the fifth resistor, the first end of the sixth resistor and the first end of the seventh resistor are connected to the power supply end; The second end of the fourth resistor is connected to the drain of the first enhancement-mode gallium nitride transistor and the gate of the fifth enhancement-mode gallium nitride transistor, the second end of the fifth resistor is connected to the drain of the third enhancement-mode gallium nitride transistor and the gate of the ninth enhancement-mode gallium nitride transistor, the second end of the sixth resistor is connected to the drain of the eleventh enhancement-mode gallium nitride transistor and the gate of the twelfth enhancement-mode gallium nitride transistor, and the second end of the seventh resistor is connected to the drain of the twelfth enhancement-mode gallium nitride transistor and the output end of the first hysteresis comparator; The gate of the first enhancement-mode gallium nitride transistor is connected to the reference voltage terminal, and the source of the first enhancement-mode gallium nitride transistor is connected to the drain of the second enhancement-mode gallium nitride transistor, the source of the third enhancement-mode gallium nitride transistor, and the drain of the fourth enhancement-mode gallium nitride transistor; The gate of the second enhancement-mode gallium nitride transistor is connected to the gate of the eighth enhancement-mode gallium nitride transistor, the gate of the tenth enhancement-mode gallium nitride transistor, the gate of the eleventh enhancement-mode gallium nitride transistor, the source of the ninth enhancement-mode gallium nitride transistor, and the drain of the seventh enhancement-mode gallium nitride transistor; The gate of the third enhancement-mode gallium nitride transistor is connected to the input voltage terminal; The gate of the fourth enhancement-mode gallium nitride transistor is connected to the source of the fifth enhancement-mode gallium nitride transistor, the drain of the sixth enhancement-mode gallium nitride transistor, the gate of the sixth enhancement-mode gallium nitride transistor, the gate of the seventh enhancement-mode gallium nitride transistor, and the drain of the eighth enhancement-mode gallium nitride transistor; The drain of the fifth enhancement-mode gallium nitride transistor and the drain of the ninth enhancement-mode gallium nitride transistor are connected to the power supply terminal; A source of the second enhancement-mode gallium nitride transistor, a source of the fourth enhancement-mode gallium nitride transistor, a source of the sixth enhancement-mode gallium nitride transistor, a source of the seventh enhancement-mode gallium nitride transistor, a source of the eighth enhancement-mode gallium nitride transistor, a source of the tenth enhancement-mode gallium nitride transistor, a source of the eleventh enhancement-mode gallium nitride transistor, and a source of the twelfth enhancement-mode gallium nitride transistor are grounded.

4. The all-gallium nitride integrated half-bridge circuit according to claim 1, characterized in that: The overcurrent protection circuit comprises: a thirteenth enhancement-mode gallium nitride transistor, an eighth resistor, a ninth resistor, a tenth resistor, a third hysteresis comparator and a first leading edge blanking circuit; The eighth resistor, the ninth resistor and the tenth resistor are connected in series in sequence, a first end of the eighth resistor is connected to the power supply terminal, and a second end of the tenth resistor is connected to the source of the low-side gallium nitride transistor; The drain of the thirteenth enhancement-mode gallium nitride transistor is connected to the drain of the low-side gallium nitride transistor, the gate of the thirteenth enhancement-mode gallium nitride transistor is connected to the gate of the low-side gallium nitride transistor, and the source of the thirteenth enhancement-mode gallium nitride transistor is connected to the common end of the ninth resistor and the tenth resistor; The non-inverting input terminal of the third hysteresis comparator is connected to the common terminal of the eighth resistor and the ninth resistor, the inverting input terminal of the third hysteresis comparator is connected to the reference voltage terminal, and the output terminal of the third hysteresis comparator is connected to the input terminal of the first leading edge blanking circuit; The output end of the first leading edge blanking circuit is connected to the output end of the overcurrent protection circuit.

5. The all-gallium nitride integrated half-bridge circuit according to claim 4, characterized in that: The first leading edge blanking circuit comprises: a third inverter, a first low-pass filter, a first hysteresis inverter, and a second NAND gate; The input end of the third inverter and the first input end of the second NAND gate are connected to the output end of the third hysteresis comparator, and the output end of the third inverter is connected to the input end of the first low-pass filter; the output end of the first low-pass filter is connected to the input end of the first hysteresis inverter; the output end of the first hysteresis inverter is connected to the second input end of the second NAND gate, and the output end of the second NAND gate is connected to the output end of the first leading edge blanking circuit.

6. The all-gallium nitride integrated half-bridge circuit according to claim 1, characterized in that: The dead time generating circuit comprises: a fourth inverter, a third NAND gate, a fourth NAND gate, a fourteenth enhancement-mode gallium nitride transistor, a fifteenth enhancement-mode gallium nitride transistor, a second hysteresis inverter, a third hysteresis inverter, a fifth inverter, a sixth inverter, a seventh inverter and an eighth inverter; The input end of the fourth inverter and the second input end of the fourth NAND gate are connected to the control signal end, and the output end of the fourth inverter is connected to the first input end of the third NAND gate; The second input terminal of the third NAND gate is connected to the gate of the fifteenth enhancement-mode gallium nitride transistor, the output terminal of the fourth NAND gate, and the input terminal of the third hysteresis inverter, and the output terminal of the third NAND gate is connected to the gate of the fourteenth enhancement-mode gallium nitride transistor, the first input terminal of the fourth NAND gate, and the input terminal of the second hysteresis inverter; A source of the fourteenth enhancement-mode gallium nitride transistor, a drain of the fourteenth enhancement-mode gallium nitride transistor, a source of the fifteenth enhancement-mode gallium nitride transistor, and a drain of the fifteenth enhancement-mode gallium nitride transistor are grounded; The output of the second hysteresis inverter is connected to the input of the fifth inverter, the output of the fifth inverter is connected to the input of the sixth inverter, and the output of the sixth inverter is connected to the first output of the dead time generating circuit; The output of the third hysteresis inverter is connected to the input of the seventh inverter, the output of the seventh inverter is connected to the input of the eighth inverter, and the output of the seventh inverter is connected to the second output of the dead time generating circuit.

7. The all-gallium nitride integrated half-bridge circuit according to claim 1, characterized in that: The signal control circuit comprises: a fifth NAND gate, a sixth NAND gate, a seventh NAND gate, a ninth inverter, a tenth inverter, and an eleventh inverter; The first input terminal of the fifth NAND gate is connected to the first input terminal of the signal control circuit, the second input terminal of the fifth NAND gate is connected to the fourth input terminal of the signal control circuit, and the output terminal of the fifth NAND gate is connected to the input terminal of the ninth inverter; The output end of the ninth inverter is connected to the first input end of the sixth NAND gate and the first input end of the seventh NAND gate; The second input terminal of the sixth NAND gate is connected to the second input terminal of the signal control circuit, and the output terminal of the sixth NAND gate is connected to the input terminal of the tenth inverter; The output end of the tenth inverter is connected to the first output end of the signal control circuit; The second input terminal of the seventh NAND gate is connected to the third input terminal of the signal control circuit, and the output terminal of the seventh NAND gate is connected to the input terminal of the eleventh inverter; The output end of the eleventh inverter is connected to the second output end of the signal control circuit.

8. The all-gallium nitride integrated half-bridge circuit according to claim 1, characterized in that: The level shift circuit includes: an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a sixteenth enhancement-mode gallium nitride transistor, a sixteenth enhancement-mode gallium nitride transistor, a seventeenth enhancement-mode gallium nitride transistor, an eighteenth enhancement-mode gallium nitride transistor, a nineteenth enhancement-mode gallium nitride transistor, a twentieth enhancement-mode gallium nitride transistor, a twenty-first enhancement-mode gallium nitride transistor, a twenty-second enhancement-mode gallium nitride transistor, a twenty-third enhancement-mode gallium nitride transistor, a twenty-fourth enhancement-mode gallium nitride transistor, a twenty-fifth enhancement-mode gallium nitride transistor, a twenty-sixth enhancement-mode gallium nitride transistor, a twenty-seventh enhancement-mode gallium nitride transistor, a twenty-eighth enhancement-mode gallium nitride transistor, a twenty-ninth enhancement-mode gallium nitride transistor, a thirtieth enhancement-mode gallium nitride transistor, a thirty-first enhancement-mode gallium nitride transistor, a thirty-second enhancement-mode gallium nitride transistor, and a twelfth inverter; The drain of the sixteenth enhancement-mode gallium nitride transistor, the gate of the sixteenth enhancement-mode gallium nitride transistor, the drain of the seventeenth enhancement-mode gallium nitride transistor, the gate of the seventeenth enhancement-mode gallium nitride transistor, the drain of the eighteenth enhancement-mode gallium nitride transistor, the gate of the eighteenth enhancement-mode gallium nitride transistor, the drain of the nineteenth enhancement-mode gallium nitride transistor, the gate of the nineteenth enhancement-mode gallium nitride transistor, and the first end of the fifteenth resistor are connected to the bootstrap voltage terminal; The source of the sixteenth enhancement-mode gallium nitride transistor is connected to the first end of the eleventh resistor and the gate of the twentieth enhancement-mode gallium nitride transistor; the source of the seventeenth enhancement-mode gallium nitride transistor is connected to the first end of the twelfth resistor; the source of the eighteenth enhancement-mode gallium nitride transistor is connected to the first end of the thirteenth resistor; the source of the nineteenth enhancement-mode gallium nitride transistor is connected to the first end of the fourteenth resistor and the gate of the twenty-third enhancement-mode gallium nitride transistor; the second end of the fifteenth resistor is connected to the drain of the twenty-fourth enhancement-mode gallium nitride transistor and the output end of the level shift circuit; The second end of the eleventh resistor is connected to the drain of the twenty-seventh enhancement-mode gallium nitride transistor and the source of the twentieth enhancement-mode gallium nitride transistor; The drain of the 20th enhancement-mode gallium nitride transistor is connected to the second end of the twelfth resistor, the drain of the 21st enhancement-mode gallium nitride transistor, and the gate of the 22nd enhancement-mode gallium nitride transistor; The gate of the twenty-first enhancement-mode gallium nitride transistor is connected to the second end of the thirteenth resistor, the drain of the twenty-second enhancement-mode gallium nitride transistor, the drain of the twenty-third enhancement-mode gallium nitride transistor, and the gate of the twenty-fourth enhancement-mode gallium nitride transistor, and the source of the twenty-first enhancement-mode gallium nitride transistor is connected to the drain of the twenty-fifth enhancement-mode gallium nitride transistor and the gate of the twenty-fifth enhancement-mode gallium nitride transistor; The source of the twenty-second enhancement-mode gallium nitride transistor is connected to the drain of the twenty-sixth enhancement-mode gallium nitride transistor and the gate of the twenty-sixth enhancement-mode gallium nitride transistor; A source of the twenty-third enhancement-mode gallium nitride transistor is connected to the second end of the fourteenth resistor and a drain of the twenty-eighth enhancement-mode gallium nitride transistor; A source of the twenty-fifth enhancement-mode gallium nitride transistor, a source of the twenty-sixth enhancement-mode gallium nitride transistor, and a source of the twenty-fourth enhancement-mode gallium nitride transistor are connected to a switch node of the half-bridge circuit; The gate of the twenty-seventh enhancement-mode gallium nitride transistor and the gate of the twenty-eighth enhancement-mode gallium nitride transistor are connected to a power supply terminal; the source of the twenty-seventh enhancement-mode gallium nitride transistor is connected to the drain of the twenty-ninth enhancement-mode gallium nitride transistor; and the source of the twenty-eighth enhancement-mode gallium nitride transistor is connected to the drain of the thirtieth enhancement-mode gallium nitride transistor; The gate of the twenty-ninth enhancement-mode gallium nitride transistor is connected to the output terminal of the twelfth inverter, and the source of the twenty-ninth enhancement-mode gallium nitride transistor is connected to the source of the thirtieth enhancement-mode gallium nitride transistor and the drain of the thirty-second enhancement-mode gallium nitride transistor; The input terminal of the twelfth inverter and the gate of the thirtieth enhancement-mode gallium nitride transistor are connected to the third input terminal of the level shift circuit; A first end of the sixteenth resistor is connected to the power supply terminal, and a second end of the sixteenth resistor is connected to the drain of the thirty-first enhancement-mode gallium nitride transistor, the gate of the thirty-first enhancement-mode gallium nitride transistor, and the gate of the thirty-second enhancement-mode gallium nitride transistor; A source of the thirty-first enhancement-mode gallium nitride transistor and a source of the thirty-second enhancement-mode gallium nitride transistor are grounded.

9. The all-gallium nitride integrated half-bridge circuit according to claim 1, characterized in that: The high-side driving circuit comprises: a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a twentieth resistor, a first capacitor, a second capacitor, a thirty-third enhancement-type gallium nitride transistor, a thirty-fourth enhancement-type gallium nitride transistor, a thirty-fifth enhancement-type gallium nitride transistor, a thirty-sixth enhancement-type gallium nitride transistor, a thirty-seventh enhancement-type gallium nitride transistor, a thirty-eighth enhancement-type gallium nitride transistor, a thirty-ninth enhancement-type gallium nitride transistor, a fortieth enhancement-type gallium nitride transistor, and a forty-first enhancement-type gallium nitride transistor; The seventeenth resistor and the eighteenth resistor are connected in series, a first end of the seventeenth resistor is connected to the first output end of the level shift circuit, and a second end of the eighteenth resistor is connected to the drain of the thirty-seventh enhancement-mode gallium nitride transistor; The gate of the thirty-third enhancement-mode gallium nitride transistor, the drain of the thirty-third enhancement-mode gallium nitride transistor, the gate of the thirty-fourth enhancement-mode gallium nitride transistor, the drain of the thirty-fourth enhancement-mode gallium nitride transistor, the drain of the thirty-fifth enhancement-mode gallium nitride transistor, and the drain of the thirty-sixth enhancement-mode gallium nitride transistor are connected to the bootstrap voltage terminal; the source of the thirty-third enhancement-mode gallium nitride transistor is connected to the first end of the nineteenth resistor and the first end of the first capacitor; the source of the thirty-fourth enhancement-mode gallium nitride transistor is connected to the first end of the twentieth resistor and the first end of the second capacitor; The second end of the nineteenth resistor is connected to the gate of the thirty-fifth enhancement-mode gallium nitride transistor and the drain of the thirty-eighth enhancement-mode gallium nitride transistor; the second end of the first capacitor is connected to the source of the thirty-fifth enhancement-mode gallium nitride transistor, the drain of the thirty-ninth enhancement-mode gallium nitride transistor, the gate of the thirty-seventh enhancement-mode gallium nitride transistor, the gate of the fortieth enhancement-mode gallium nitride transistor, and the gate of the forty-first enhancement-mode gallium nitride transistor; The second end of the 20th resistor is connected to the drain of the 40th enhancement-mode gallium nitride transistor and the gate of the 36th enhancement-mode gallium nitride transistor, and the second end of the second capacitor is connected to the source of the 36th enhancement-mode gallium nitride transistor, the drain of the 41st enhancement-mode gallium nitride transistor and the output end of the high-side driving circuit; A source of the thirty-seventh enhancement-mode gallium nitride transistor, a source of the thirty-eighth enhancement-mode gallium nitride transistor, a source of the thirty-ninth enhancement-mode gallium nitride transistor, a source of the fortieth enhancement-mode gallium nitride transistor, and a source of the forty-first enhancement-mode gallium nitride transistor are connected to a switch node of the half-bridge circuit.

10. The all-gallium nitride integrated half-bridge circuit according to claim 1, characterized in that: The low-side driving circuit includes: a twenty-first resistor, a twenty-second resistor, a twenty-third resistor, a twenty-fourth resistor, a third capacitor, a fourth capacitor, a forty-second enhancement-type gallium nitride transistor, a forty-third enhancement-type gallium nitride transistor, a forty-fourth enhancement-type gallium nitride transistor, a forty-fifth enhancement-type gallium nitride transistor, a forty-sixth enhancement-type gallium nitride transistor, a forty-seventh enhancement-type gallium nitride transistor, a forty-eighth enhancement-type gallium nitride transistor, a forty-ninth enhancement-type gallium nitride transistor, and a fiftieth enhancement-type gallium nitride transistor, The twenty-first resistor and the twenty-second resistor are connected in series, a first end of the twenty-first resistor is connected to the second output end of the signal control circuit, and a second end of the twenty-second resistor is connected to the drain of the forty-sixth enhancement-mode gallium nitride transistor; The gate of the forty-second enhancement-mode gallium nitride transistor, the drain of the forty-second enhancement-mode gallium nitride transistor, the gate of the forty-third enhancement-mode gallium nitride transistor, the drain of the forty-third enhancement-mode gallium nitride transistor, the drain of the forty-fourth enhancement-mode gallium nitride transistor, and the drain of the forty-fifth enhancement-mode gallium nitride transistor are connected to the power supply terminal; the source of the forty-second enhancement-mode gallium nitride transistor is connected to the first end of the twenty-third resistor and the first end of the third capacitor; the source of the forty-third enhancement-mode gallium nitride transistor is connected to the first end of the twenty-fourth resistor and the first end of the fourth capacitor; A second end of the twenty-third resistor is connected to the gate of the forty-fourth enhancement-mode gallium nitride transistor and the drain of the forty-seventh enhancement-mode gallium nitride transistor; a second end of the third capacitor is connected to the source of the forty-fourth enhancement-mode gallium nitride transistor, the drain of the forty-eighth enhancement-mode gallium nitride transistor, the gate of the forty-sixth enhancement-mode gallium nitride transistor, the gate of the forty-ninth enhancement-mode gallium nitride transistor, and the gate of the fiftieth enhancement-mode gallium nitride transistor; The second end of the twenty-fourth resistor is connected to the drain of the forty-ninth enhancement-mode gallium nitride transistor and the gate of the forty-fifth enhancement-mode gallium nitride transistor, and the second end of the fourth capacitor is connected to the source of the forty-fifth enhancement-mode gallium nitride transistor, the drain of the fiftieth enhancement-mode gallium nitride transistor, and the output end of the low-side driver circuit; A source of the forty-sixth enhancement mode gallium nitride transistor, a source of the forty-seventh enhancement mode gallium nitride transistor, a source of the forty-eighth enhancement mode gallium nitride transistor, a source of the forty-ninth enhancement mode gallium nitride transistor, and a source of the fiftieth enhancement mode gallium nitride transistor are connected to the ground.

11. A chip, characterized in that: The chip includes: a full gallium nitride integrated half-bridge circuit as described in any one of claims 1-10.

12. An electronic device, characterized in that: The electronic device comprises: the chip as claimed in claim 11.

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