Current sharing control circuit and control method

Abstract

The invention discloses a current sharing control circuit and a current sharing control method. The current sharing control circuit comprises a first power unit, a second power unit, a detection unit and a control unit. The first power unit comprises a first switch unit and a first output branch; the second power unit comprises a second switch unit and a second output branch; the detection unit is used for detecting a first current on the first output branch, a second current on the second output branch and a total current on the first output end; the control unit generates a first control signal based on the first adjustment signal and the second adjustment signal, and generates a second control signal based on the first adjustment signal and the third adjustment signal. According to the current sharing control circuit and the control method, the current dynamic balance of each switch unit is realized, the output voltage balance and the output power balance of the first power unit and the second power unit which are connected in series are ensured, the temperature rise of each power module is consistent, and the reliability of the power supply is greatly improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of current control, and in particular relates to a current sharing control circuit and a control method. Background Art

[0002] In battery testing equipment, with the explosive growth of energy storage battery scale, there are more and more test equipment for high-voltage and high-current energy storage systems. The output voltage level has been continuously increased from 1000V to 1500V, 1600V and even 2000V, and the output power has been continuously increased from hundreds of kilowatts to several megawatts. With the increase of voltage and current levels, multiple IGBT or Sic power modules need to be connected in parallel to increase the output current capacity, and the single power supply after parallel connection is connected in series to increase the output voltage capacity. The traditional module parallel connection method cannot guarantee the current balance of the module. In order to ensure reliability, it is necessary to reduce the module's current usage, resulting in a certain amount of waste.

[0003] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention and should not be regarded as an acknowledgment or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the invention

[0004] The object of the present invention is to provide a current balancing control circuit and a control method, which can realize current dynamic balancing when outputting high voltage and large current.

[0005] In order to achieve the above-mentioned purpose, a technical solution provided by a specific embodiment of the present invention is as follows: A current sharing control circuit includes: a first power unit, a second power unit, a detection unit and a control unit.

[0006] The first power unit includes a plurality of first switch units and a plurality of first output branches, each of the first switch units is connected between a first input terminal and a second input terminal, a first terminal of each of the first output branches is connected to a corresponding first switch unit, and second terminals of the first output branches are connected to form a first output terminal, and each of the first switch units controls the connection between the first input terminal and the first output branch or controls the connection between the second input terminal and the first output branch based on a set of first control signals;

[0007] The second power unit includes a plurality of second switch units and a plurality of second output branches, each of the second switch units is connected between a third input terminal and a fourth input terminal, the third input terminal is connected to the second input terminal, a first end of each of the second output branches is connected to a corresponding second switch unit, and second ends of the second output branches are connected to form a second output terminal, and each of the second switch units controls the third input terminal to be connected to the second output branch or controls the fourth input terminal to be connected to the second output branch based on a set of second control signals;

[0008] The detection unit is used to detect and obtain a first current on each first output branch, a second current on each second output branch, and a total current on the first output terminal or the second output terminal;

[0009] The control unit is used to generate a first adjustment signal within a first limiting range based on the deviation between the total current and the total preset current, generate a second adjustment signal within a second limiting range based on the deviation between each first current and the corresponding first preset current, generate a third adjustment signal within the second limiting range based on the deviation between each second current and the corresponding second preset current, and generate a group of first control signals based on the first adjustment signal and each second adjustment signal, and generate a group of second control signals based on the first adjustment signal and each third adjustment signal.

[0010] In one or more embodiments of the present invention, the control unit includes: a first regulating module, a plurality of second regulating modules, a plurality of third regulating modules, a plurality of first output modules, and a plurality of second output modules;

[0011] The first regulating module generates a first regulating signal within a first limiting range based on a deviation between the total current and the total preset current;

[0012] Each of the second regulating modules generates a corresponding second regulating signal within a second limiting range based on a deviation between a corresponding first current and a corresponding first preset current, and each of the first output modules generates a corresponding set of first control signals within the first limiting range based on the first regulating signal and the corresponding second regulating signal;

[0013] Each of the third regulation modules generates a corresponding third regulation signal within a second limiting range based on a deviation between a corresponding second current and a corresponding second preset current, and each of the second output modules generates a corresponding set of second control signals within the first limiting range based on the first regulation signal and the corresponding third regulation signal.

[0014] In one or more embodiments of the present invention, the first regulation module includes a first PI regulator and a first saturation limiter, the first input end of the first PI regulator is used to receive the total current, the second input end of the first PI regulator is used to receive the total preset current, the input end of the first saturation limiter is connected to the output end of the first PI regulator, the output end of the first saturation limiter is used to output a first regulation signal, and the first saturation limiter is used to limit the output signal of the first PI regulator to a first limiting range.

[0015] In one or more embodiments of the present invention, the second regulation module includes a first multiplier, a second PI regulator and a second saturation limiter, the first multiplier is used to obtain a first preset current based on a total preset current, the first input end of the second PI regulator is used to receive the first preset current, the second input end of the second PI regulator is used to receive the first current, the input end of the second saturation limiter is connected to the output end of the second PI regulator, the output end of the second saturation limiter is used to output a second regulation signal, and the second saturation limiter is used to limit the output signal of the second PI regulator to a second limiting range; and / or

[0016] The third regulation module includes a second multiplier, an inverter, a third PI regulator and a fourth saturation limiter, wherein the second multiplier is used to obtain a second preset current based on the total preset current, the first input end of the third PI regulator is used to receive the second preset current, the inverter is used to invert the second current, the second input end of the third PI regulator is used to receive the inverted second current, the input end of the fourth saturation limiter is connected to the output end of the third PI regulator, the output end of the fourth saturation limiter is used to output a third regulation signal, and the fourth saturation limiter is used to limit the output signal of the third PI regulator to a second limiting range.

[0017] In one or more embodiments of the present invention, the first output module includes a first adder, a third saturation limiter and a first processing module, the first input end of the first adder is connected to the first adjustment module to receive the first adjustment signal, the second input end of the first adder is connected to the second adjustment module to receive the second adjustment signal, the third saturation limiter is connected to the output end of the first adder to limit the signal generated by the sum of the first adjustment signal and the second adjustment signal to the within a limiting range, and the first processing module is connected to the third saturation limiter to process the signal output by the third saturation limiter to generate a set of first control signals; and / or

[0018] The second output module includes a second adder, a fifth saturation limiter and a second processing module, the first input end of the second adder is connected to the first adjustment module to receive a first adjustment signal, the second input end of the second adder is connected to the third adjustment module to receive a third adjustment signal, the fifth saturation limiter is connected to the output end of the second adder to limit the signal generated by the sum of the first adjustment signal and the third adjustment signal within a first limiting range, and the second processing module is connected to the fifth saturation limiter to process the signal output by the fifth saturation limiter to generate a set of second control signals.

[0019] In one or more embodiments of the present invention, the first switch unit includes a first transistor and a second transistor, the second end of the first transistor is connected to the first input end, the first end of the first transistor is connected to the second end of the second transistor and the first end of the first output branch, the first end of the second transistor is connected to the second input end, and the control end of the first transistor and the control end of the second transistor are used to receive a group of first control signals, and the group of first control signals is used to control the first transistor to turn on and the second transistor to turn off, or to control the second transistor to turn on and the first transistor to turn off; and / or

[0020] The second switch unit includes a third transistor and a fourth transistor, the second end of the third transistor is connected to the third input end, the first end of the third transistor is connected to the second end of the fourth transistor and the first end of the second output branch, the first end of the fourth transistor is connected to the fourth input end, and the control end of the third transistor and the control end of the fourth transistor are used to receive a group of second control signals, and the group of second control signals is used to control the third transistor to turn on and the fourth transistor to turn off, or to control the fourth transistor to turn on and the third transistor to turn off.

[0021] In one or more embodiments of the present invention, the first output branch includes a first inductor, a first end of the first inductor is a first end of the first output branch, and a second end of the first inductor is a second end of the first output branch; and / or

[0022] The second output branch includes a second inductor, a first end of the second inductor is a first end of the second output branch, and a second end of the second inductor is a second end of the second output branch.

[0023] In one or more embodiments of the present invention, the first power unit further includes a first capacitor and / or a second capacitor, a first end of the first capacitor is connected to the first input end, a second end of the first capacitor is connected to the second input end, a first end of the second capacitor is connected to the first output end, and a second end of the second capacitor is connected to the second input end; and / or

[0024] The second power unit also includes a third capacitor and / or a fourth capacitor, the first end of the third capacitor is connected to the third input terminal, the second end of the third capacitor is connected to the fourth input terminal, the first end of the fourth capacitor is connected to the third input terminal, and the second end of the fourth capacitor is connected to the second output terminal.

[0025] The present invention also discloses a current sharing control method. Based on the current sharing control circuit, the current sharing control method includes:

[0026] Detect and obtain, by a detection unit, a first current on each first output branch, a second current on each second output branch, and a total current on the first output terminal or the second output terminal;

[0027] Generate a first adjustment signal within a first limiting range based on a deviation between the total current and the total preset current by a control unit;

[0028] The control unit generates a second regulating signal within a second limiting range based on a deviation between each first current and a corresponding first preset current, and generates a group of first control signals based on the first regulating signal and each second regulating signal, and controls the action of each first switch unit through each group of first control signals;

[0029] A control unit generates a third adjustment signal within a second limiting range based on the deviation between each second current and the corresponding second preset current, generates a group of second control signals based on the first adjustment signal and each third adjustment signal, and controls the action of each second switch unit through each group of second control signals.

[0030] In one or more embodiments of the present invention, the current sharing control method includes:

[0031] The total current and the total preset current are processed by a first PI regulator to generate a corresponding first control amount, and the first control amount is limited within a limiting range by a first saturation limiter to output a first adjustment signal;

[0032] Obtain a first preset current based on the total preset current by a first multiplier, process the first preset current and the first current by a second PI regulator to generate a corresponding second control amount, and limit the second control amount within a second limiting range by a second saturation limiter to output a second adjustment signal;

[0033] The first adjustment signal and the second adjustment signal are summed by a first adder, a signal generated by the sum of the first adjustment signal and the second adjustment signal is limited within a first limiting range by a third saturation limiter, and a signal output by the third saturation limiter is processed by a first processing module to generate a set of first control signals;

[0034] Obtaining a second preset current based on the total preset current through a second multiplier, inverting the second current through an inverter, processing the second preset current and the inverted second current through a third PI regulator to generate a third control amount, and limiting the third control amount within a second limiting range through a fourth saturation limiter to output a third adjustment signal;

[0035] The first adjustment signal and the third adjustment signal are summed by a second adder, a signal generated by the sum of the first adjustment signal and the third adjustment signal is limited within a first limiting range by a fifth saturation limiter, and a signal output by the fifth saturation limiter is processed by a second processing module to generate a set of second control signals.

[0036] Compared with the prior art, the current equalization control circuit and control method of the present invention connect multiple first switch units and first output branches in parallel, connect multiple second switch units and second output branches in parallel, and then connect the connected first power units and second power units in series, thereby generating the ability to output high voltage and large current; the detection unit detects and obtains the first current on each first output branch, the second current on each second output branch and the total current on the first output end or the second output end, and the control unit generates a control signal of the switch unit based on the total current and the divided current on each output branch, and the first adjustment module is respectively combined with the second adjustment module and the third adjustment module to limit the output range of each signal, thereby achieving dynamic current balance of each switch unit, and also ensuring the output voltage balance and output power balance of the first power unit and the second power unit connected in series, so that the temperature rise of each power module (transistor) is consistent, which greatly improves the reliability of the power supply and the utilization rate of each power module (transistor). BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0038] Figure 1 The schematic diagram is a circuit diagram of a first power unit, a second power unit and a detection unit of a current sharing control circuit in one embodiment of the present invention.

[0039] Figure 2 It is a partial circuit schematic diagram of a control unit of a current sharing control circuit in one embodiment of the present invention.

[0040] Figure 3 1 is another circuit schematic diagram of a control unit of a current sharing control circuit in an embodiment of the present invention.

[0041] Figure 4 1 is a waveform diagram of each first control signal and each first current when charging a battery unit according to an embodiment of the present invention.

[0042] Figure 5FIG. 4 is a waveform diagram of each second control signal and each second current when charging a battery unit according to an embodiment of the present invention.

[0043] Figure 6 It is a waveform diagram of balancing the first current by adjusting the duty cycle of each first control signal and balancing the second current by adjusting the duty cycle of each second control signal when charging the battery unit in one embodiment of the present invention.

[0044] Figure 7 The waveform diagram of the first regulating signal, the second regulating signal and the third regulating signal when charging the battery unit in one embodiment of the present invention.

[0045] Figure 8 FIG. 4 is a waveform diagram of each first control signal and each first current when a battery unit is discharged according to an embodiment of the present invention.

[0046] Fig. 9 FIG. 4 is a waveform diagram of each second control signal and each second current when the battery unit is discharging according to an embodiment of the present invention.

[0047] Fig.10 The waveform diagram is a schematic diagram of balancing the first current by adjusting the duty cycle of each first control signal and balancing the second current by adjusting the duty cycle of each second control signal when the battery unit is discharged in one embodiment of the present invention.

[0048] Fig.11 1 is a waveform diagram of the first regulating signal, the second regulating signal and the third regulating signal when the battery unit is discharging in one embodiment of the present invention. DETAILED DESCRIPTION

[0049] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0050] "Coupled" or "connected" or "connected" in the specification includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrically conductive medium, which may have parasitic inductance or parasitic capacitance; indirect connection may also include connection through other active or passive devices on the basis of achieving the same or similar functional purposes, such as connection through circuits or components such as switches and follower circuits. In addition, in the invention, words such as "first" and "second" are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply that there is a certain actual relationship, quantity or order between these technical features.

[0051] In the detailed description of the specification, reference is made to the accompanying drawings forming a part thereof, wherein like reference numerals refer to like parts throughout, and wherein are shown by way of exemplary embodiments that may be implemented. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be considered in a limiting sense.

[0052] The various operations in the specification may be described in turn as multiple discrete actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be interpreted as implying that these operations must be order-dependent. Specifically, these operations may not be performed in the order presented. The described operations may be performed in an order different from the described embodiments. Various additional operations may be performed and / or the described operations may be omitted in additional embodiments.

[0053] For purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0054] Various components and devices may be referred to or shown in the singular form in this document (for example, "MOS tube", "transistor", "switch", etc.), but this is only for convenience of discussion, and any element mentioned in the singular form may include multiple such elements according to the teachings of this document.

[0055] The specification describes the use of the phrases "in one embodiment" or "in other embodiments" or "in some embodiments", which may each refer to one or more of the same or different embodiments. In addition, the terms "including", "comprising", "having", etc. used in relation to the embodiments of the present disclosure are synonymous.

[0056] like Figure 1 , Figure 2 and Figure 3As shown, a current sharing control circuit in an embodiment of the present invention includes: a first power unit 10, a second power unit 20, a detection unit 30 and a control unit.

[0057] The first power unit 10 includes multiple first switch units and multiple first output branches, each first switch unit is connected between the first input terminal a1 and the second input terminal a2, the first end of each first output branch is connected to the corresponding first switch unit, and the second ends of the first output branches are connected to form the first output terminal O1. Each first switch unit controls the connection between the first input terminal a1 and the first output branch or controls the connection between the second input terminal a2 and the first output branch based on a set of first control signals.

[0058] The second power unit 20 includes multiple second switch units and multiple second output branches, each second switch unit is connected between the third input terminal b1 and the fourth input terminal b2, the third input terminal b1 is connected to the second input terminal a2, the first end of each second output branch is connected to the corresponding second switch unit, and the second ends of the second output branches are connected to form the second output terminal O2. Each second switch unit controls the connection between the third input terminal b1 and the second output branch or controls the connection between the fourth input terminal b2 and the second output branch based on a set of second control signals.

[0059] The first input terminal a1 and the second input terminal a2 are connected to the first power module AC-DC1 at the same time, the third input terminal b1 and the fourth input terminal b2 are connected to the second power module AC-DC2 at the same time, and the first output terminal O1 and the second output terminal O2 are connected to the battery unit BATTERY at the same time.

[0060] The detection unit 30 is used to detect and obtain the first current on each first output branch, the second current on each second output branch, and the total current Isum on the first output terminal O1 or the second output terminal O2.

[0061] The control unit is used to generate a first adjustment signal within a first limiting range based on the deviation between the total current Isum and the total preset current Iset, generate a second adjustment signal within a second limiting range based on the deviation between each first current and the corresponding first preset current, generate a third adjustment signal within the second limiting range based on the deviation between each second current and the corresponding second preset current, and generate a group of first control signals based on the first adjustment signal and each second adjustment signal, and generate a group of second control signals based on the first adjustment signal and each third adjustment signal.

[0062] The control unit includes: a first regulating module, a plurality of second regulating modules, a plurality of third regulating modules, a plurality of first output modules and a plurality of second output modules.

[0063] The first regulating module generates a first regulating signal within a first limiting range based on a deviation between the total current Isum and the total preset current Iset.

[0064] Each second regulating module generates a corresponding second regulating signal within a second limiting range based on a deviation between a corresponding first current and a corresponding first preset current, and each first output module generates a corresponding set of first control signals within the first limiting range based on the first regulating signal and the corresponding second regulating signal.

[0065] Each third regulation module generates a corresponding third regulation signal within a second limiting range based on a deviation between a corresponding second current and a corresponding second preset current, and each second output module generates a corresponding set of second control signals within the first limiting range based on the first regulation signal and the corresponding third regulation signal.

[0066] In different application scenarios, the number of the first switch unit, the first output branch, the second switch unit, and the second output branch can be set as required, such as Figure 1 As shown, in one embodiment, the number of the first switch unit, the first output branch, the second switch unit and the second output branch are all set to three. The following is a detailed description taking three first switch units 11, 12, 13, three first output branches 14, 15, 16, three second switch units 21, 22, 23, and three second output branches 24, 25, 26 as examples.

[0067] Each of the first switch unit and the second switch unit includes two transistors. To facilitate differentiation, the transistors are labeled differently.

[0068] like Figure 1 As shown, the first switch unit 11 includes a first transistor Q1 and a second transistor Q2, the second end of the first transistor Q1 is connected to the first input end a1, the first end of the first transistor Q1 is connected to the second end of the second transistor Q2 and the first end of the first output branch 14, the first end of the second transistor Q2 is connected to the second input end a2, the control end of the first transistor Q1 and the control end of the second transistor Q2 are used to receive a group of first control signals PWM1, PWM2, and the group of first control signals PWM1, PWM2 are used to control the first transistor Q1 to turn on and the second transistor Q2 to turn off, or to control the second transistor Q2 to turn on and the first transistor Q1 to turn off.

[0069] The first switch unit 12 includes a first transistor Q3 and a second transistor Q4, the second end of the first transistor Q3 is connected to the first input end a1, the first end of the first transistor Q3 is connected to the second end of the second transistor Q4 and the first end of the first output branch 15, the first end of the second transistor Q4 is connected to the second input end a2, and the control end of the first transistor Q3 and the control end of the second transistor Q4 are used to receive a group of first control signals PWM3 and PWM4, and the group of first control signals PWM3 and PWM4 are used to control the first transistor Q3 to turn on and the second transistor Q4 to turn off, or to control the second transistor Q4 to turn on and the first transistor Q3 to turn off.

[0070] The first switch unit 13 includes a first transistor Q5 and a second transistor Q6, the second end of the first transistor Q5 is connected to the first input end a1, the first end of the first transistor Q5 is connected to the second end of the second transistor Q6 and the first end of the first output branch 16, the first end of the second transistor Q6 is connected to the second input end a2, and the control end of the first transistor Q5 and the control end of the second transistor Q6 are used to receive a group of first control signals PWM5 and PWM6, and the group of first control signals PWM5 and PWM6 are used to control the first transistor Q5 to turn on and the second transistor Q6 to turn off, or to control the second transistor Q6 to turn on and the first transistor Q5 to turn off.

[0071] The second switch unit 21 includes a third transistor Q7 and a fourth transistor Q8, the second end of the third transistor Q7 is connected to the third input end b1, the first end of the third transistor Q7 is connected to the second end of the fourth transistor Q8 and the first end of the second output branch 24, the first end of the fourth transistor Q8 is connected to the fourth input end b2, and the control end of the third transistor Q7 and the control end of the fourth transistor Q8 are used to receive a group of second control signals PWM7 and PWM8, and the group of second control signals PWM7 and PWM8 are used to control the third transistor Q7 to turn on and the fourth transistor Q8 to turn off, or to control the fourth transistor Q8 to turn on and the third transistor Q7 to turn off.

[0072] The second switch unit 22 includes a third transistor Q9 and a fourth transistor Q10, the second end of the third transistor Q9 is connected to the third input end b1, the first end of the third transistor Q9 is connected to the second end of the fourth transistor Q10 and the first end of the second output branch 25, the first end of the fourth transistor Q10 is connected to the fourth input end b2, and the control end of the third transistor Q9 and the control end of the fourth transistor Q10 are used to receive a group of second control signals PWM9 and PWM10, and the group of second control signals PWM9 and PWM10 are used to control the third transistor Q9 to turn on and the fourth transistor Q10 to turn off, or to control the fourth transistor Q10 to turn on and the third transistor Q9 to turn off.

[0073] The second switch unit 23 includes a third transistor Q11 and a fourth transistor Q12, the second end of the third transistor Q11 is connected to the third input end b1, the first end of the third transistor Q11 is connected to the second end of the fourth transistor Q12 and the first end of the second output branch 26, the first end of the fourth transistor Q12 is connected to the fourth input end b2, and the control end of the third transistor Q11 and the control end of the fourth transistor Q12 are used to receive a group of second control signals PWM11 and PWM12, and the group of second control signals PWM11 and PWM12 are used to control the third transistor Q11 to turn on and the fourth transistor Q12 to turn off, or to control the fourth transistor Q12 to turn on and the third transistor Q11 to turn off.

[0074] The first transistor Q1, Q3, Q5, the second transistor Q2, Q4, Q6, the third transistor Q7, Q9, Q11, and the fourth transistor Q8, Q10, Q12 are all N-channel MOS transistors, in which case the first end of each transistor is the source, the second end is the drain, and the control end is the gate. In other embodiments, the first transistor Q1, Q3, Q5, the second transistor Q2, Q4, Q6, the third transistor Q7, Q9, Q11, and the fourth transistor Q8, Q10, Q12 are all insulated gate bipolar transistors, in which case the first end of each transistor is the emitter, the second end is the collector, and the control end is the gate. Alternatively, each transistor may also be a P-channel MOS transistor.

[0075] In one embodiment, the first control signals PWM1 and PWM2 are a group of inverted signals with dead time, the first control signals PWM3 and PWM4 are a group of inverted signals with dead time, the first control signals PWM5 and PWM6 are a group of inverted signals with dead time, the second control signals PWM7 and PWM8 are a group of inverted signals with dead time, the second control signals PWM9 and PWM10 are also a group of inverted signals with dead time, and the second control signals PWM11 and PWM12 are also a group of inverted signals with dead time.

[0076] Each of the first output branch and the second output branch includes an inductor. To facilitate differentiation, the inductors are labeled differently.

[0077] like Figure 1 As shown, the first output branch 14 includes a first inductor L11, a first end of the first inductor L11 is a first end of the first output branch 14, and a second end of the first inductor L11 is a second end of the first output branch 14. The first end of the first inductor L11 is connected to the first end of the first transistor Q1 and the second end of the second transistor Q2.

[0078] The first output branch 15 includes a first inductor L12, a first end of the first inductor L12 is a first end of the first output branch 15, and a second end of the first inductor L12 is a second end of the first output branch 15. The first end of the first inductor L12 is connected to the first end of the first transistor Q3 and the second end of the second transistor Q4.

[0079] The first output branch 16 includes a first inductor L13, a first end of the first inductor L13 is a first end of the first output branch 16, and a second end of the first inductor L13 is a second end of the first output branch 16. The first end of the first inductor L13 is connected to the first end of the first transistor Q5 and the second end of the second transistor Q6.

[0080] The second end of the first inductor L11 , the second end of the first inductor L12 , and the second end of the first inductor L13 are connected to form a first output end O1 .

[0081] The second output branch 24 includes a second inductor L21, a first end of the second inductor L21 being the first end of the second output branch 24, and a second end of the second inductor L21 being the second end of the second output branch 24. The first end of the second inductor L21 is connected to the first end of the third transistor Q7 and the second end of the fourth transistor Q8.

[0082] The second output branch 25 includes a second inductor L22, a first end of the second inductor L22 being the first end of the second output branch 25, and a second end of the second inductor L22 being the second end of the second output branch 25. The first end of the second inductor L22 is connected to the first end of the third transistor Q9 and the second end of the fourth transistor Q10.

[0083] The second output branch 26 includes a second inductor L23, a first end of the second inductor L23 being the first end of the second output branch 26, and a second end of the second inductor L23 being the second end of the second output branch 26. The first end of the second inductor L23 is connected to the first end of the third transistor Q11 and the second end of the fourth transistor Q12.

[0084] The second end of the second inductor L21 , the second end of the second inductor L22 , and the second end of the second inductor L23 are connected to form a second output end O2 .

[0085] The first power unit 10 further includes a first capacitor C1 and a second capacitor C2, wherein a first end of the first capacitor C1 is connected to the first input terminal a1, a second end of the first capacitor C1 is connected to the second input terminal a2, a first end of the second capacitor C2 is connected to the first output terminal O1, and a second end of the second capacitor C2 is connected to the second input terminal a2. In other embodiments, the first capacitor C1 or the second capacitor C2 may not be provided.

[0086] The second power unit 20 further includes a third capacitor C3 and a fourth capacitor C4, wherein a first end of the third capacitor C3 is connected to the third input terminal b1, a second end of the third capacitor C3 is connected to the fourth input terminal b2, a first end of the fourth capacitor C4 is connected to the third input terminal b1, and a second end of the fourth capacitor C4 is connected to the second output terminal O2. In other embodiments, the third capacitor C3 or the fourth capacitor C4 may not be provided.

[0087] like Figure 1 As shown, the detection unit 30 is composed of 7 Hall elements or shunts, and current detection is performed through the 7 Hall elements to obtain the first currents I11, I12, I13 on the first output branches 14, 15, 16 and the second currents I21, I22, I23 on the second output branches 24, 25, 26 and the total current Isum at the first output terminal O1.

[0088] Since there are three first currents and three second currents, and each of the first currents and the second currents needs to be processed with the total current, three second regulating modules and three third regulating modules are also provided, and correspondingly three first output modules and three second output modules are provided.

[0089] Specifically, Figure 2 As shown, the first regulation module 41 includes a first PI regulator PI_1 and a first saturation limiter Saturation1, the first input end of the first PI regulator PI_1 is used to receive the total current Isum, the second input end of the first PI regulator PI_1 is used to receive the total preset current Iset, the input end of the first saturation limiter Saturation1 is connected to the output end of the first PI regulator PI_1, the output end of the first saturation limiter Saturation1 is used to output the first regulation signal Iout_1, and the first saturation limiter Saturation1 is used to limit the output signal of the first PI regulator PI_1 within a first limiting range.

[0090] The second regulation module 421 includes a first multiplier X11, a second PI regulator PI_21 and a second saturation limiter Saturation21. The first multiplier X11 is used to obtain a first preset current Is11 based on the total preset current Iset. The first input end of the second PI regulator PI_21 is used to receive the first preset current Is11. The second input end of the second PI regulator PI_21 is used to receive the first current I11. The input end of the second saturation limiter Saturation21 is connected to the output end of the second PI regulator PI_21. The output end of the second saturation limiter Saturation21 is used to output a second regulation signal Iout_21. The second saturation limiter Saturation21 is used to limit the output signal of the second PI regulator PI_21 within a second limiting range to obtain the second regulation signal Iout_21.

[0091] The first output module 424 includes a first adder A11, a third saturation limiter Saturation31 and a first processing module NV11. The first input end of the first adder A11 is connected to the first regulating module 41 to receive the first regulating signal Iout_1, the second input end of the first adder A11 is connected to the second regulating module 421 to receive the second regulating signal Iout_21, the third saturation limiter Saturation31 is connected to the output end of the first adder A11 to limit the signal generated by the sum of the first regulating signal Iout_1 and the second regulating signal Iout_21 within a first limiting range, and the first processing module NV11 is connected to the third saturation limiter Saturation31 to process the signal output by the third saturation limiter Saturation31 to generate a group of first control signals PWM1 and PWM2.

[0092] The second regulation module 422 includes a first multiplier X12, a second PI regulator PI_22 and a second saturation limiter Saturation22. The first multiplier X12 is used to obtain a first preset current Is12 based on the total preset current Iset. The first input end of the second PI regulator PI_22 is used to receive the first preset current Is12. The second input end of the second PI regulator PI_22 is used to receive the first current I12. The input end of the second saturation limiter Saturation22 is connected to the output end of the second PI regulator PI_22. The output end of the second saturation limiter Saturation22 is used to output a second regulation signal Iout_22. The second saturation limiter Saturation22 is used to limit the output signal of the second PI regulator PI_22 within a second limiting range to obtain the second regulation signal Iout_22.

[0093] The first output module 425 includes a first adder A12, a third saturation limiter Saturation32 and a first processing module NV12. The first input end of the first adder A12 is connected to the first adjustment module 41 to receive the first adjustment signal Iout_1. The second input end of the first adder A11 is connected to the second adjustment module 422 to receive the second adjustment signal Iout_22. The third saturation limiter Saturation32 is connected to the output end of the first adder A12 to limit the signal generated by the sum of the first adjustment signal Iout_1 and the second adjustment signal Iout_22 within a first limiting range. The first processing module NV12 is connected to the third saturation limiter Saturation32 to process the signal output by the third saturation limiter Saturation32 to generate a group of first control signals PWM3 and PWM4.

[0094] The second regulation module 423 includes a first multiplier X13, a second PI regulator PI_23 and a second saturation limiter Saturation23. The first multiplier X13 is used to obtain a first preset current Is13 based on the total preset current Iset. The first input end of the second PI regulator PI_23 is used to receive the first preset current Is13. The second input end of the second PI regulator PI_23 is used to receive the first current I13. The input end of the second saturation limiter Saturation23 is connected to the output end of the second PI regulator PI_23. The output end of the second saturation limiter Saturation23 is used to output a second regulation signal Iout_23. The second saturation limiter Saturation23 is used to limit the output signal of the second PI regulator PI_23 within a second limiting range to obtain the second regulation signal Iout_23.

[0095] The first output module 426 includes a first adder A13, a third saturation limiter Saturation33 and a first processing module NV13. The first input end of the first adder A13 is connected to the first regulating module 41 to receive the first regulating signal Iout_1. The second input end of the first adder A13 is connected to the second regulating module 423 to receive the second regulating signal Iout_23. The third saturation limiter Saturation33 is connected to the output end of the first adder A13 to limit the signal generated by the sum of the first regulating signal Iout_1 and the second regulating signal Iout_23 within a first limiting range. The first processing module NV13 is connected to the third saturation limiter Saturation33 to process the signal output by the third saturation limiter Saturation33 to generate a group of first control signals PWM5 and PWM6.

[0096] like Figure 3As shown, the third regulation module 431 includes a second multiplier X21, an inverter N1, a third PI regulator PI_31 and a fourth saturation limiter Saturation41, the second multiplier X21 is used to obtain a second preset current Is21 based on the total preset current Iset, the first input end of the third PI regulator PI_31 is used to receive the second preset current Is21, the inverter N1 is used to invert the second current I21, the second input end of the third PI regulator PI_31 is used to receive the inverted second current I21, the input end of the fourth saturation limiter Saturation41 is connected to the output end of the third PI regulator PI_31, the output end of the fourth saturation limiter Saturation41 is used to output a third regulation signal Iout_31, and the fourth saturation limiter Saturation41 is used to limit the output signal of the third PI regulator PI_31 within the second limiting range to obtain the third regulation signal Iout_31.

[0097] The second output module 434 includes a second adder A21, a fifth saturation limiter Saturation51 and a second processing module NV21. The first input end of the second adder A21 is connected to the first adjustment module 41 to receive the first adjustment signal Iout_1. The second input end of the second adder A21 is connected to the third adjustment module 431 to receive the third adjustment signal Iout_31. The fifth saturation limiter Saturation51 is connected to the output end of the second adder A21 to limit the signal generated by the sum of the first adjustment signal Iout_1 and the third adjustment signal Iout_31 within the first limiting range. The second processing module NV21 is connected to the fifth saturation limiter Saturation51 to process the signal output by the fifth saturation limiter Saturation51 to generate a group of second control signals PWM7 and PWM8.

[0098] The third regulation module 432 includes a second multiplier X22, an inverter N2, a third PI regulator PI_32 and a fourth saturation limiter Saturation42, the second multiplier X22 is used to obtain a second preset current Is22 based on the total preset current Iset, the first input end of the third PI regulator PI_32 is used to receive the second preset current Is22, the inverter N2 is used to invert the second current I22, the second input end of the third PI regulator PI_32 is used to receive the inverted second current I22, the input end of the fourth saturation limiter Saturation42 is connected to the output end of the third PI regulator PI_32, the output end of the fourth saturation limiter Saturation42 is used to output a third regulation signal Iout_32, and the fourth saturation limiter Saturation42 is used to limit the output signal of the third PI regulator PI_32 within the second limiting range to obtain the third regulation signal Iout_32.

[0099] The second output module 435 includes a second adder A22, a fifth saturation limiter Saturation52 and a second processing module NV22. The first input end of the second adder A22 is connected to the first adjustment module 41 to receive the first adjustment signal Iout_1. The second input end of the second adder A21 is connected to the third adjustment module 432 to receive the third adjustment signal Iout_32. The fifth saturation limiter Saturation52 is connected to the output end of the second adder A22 to limit the signal generated by the sum of the first adjustment signal Iout_1 and the third adjustment signal Iout_32 within the first limiting range. The second processing module NV22 is connected to the fifth saturation limiter Saturation52 to process the signal output by the fifth saturation limiter Saturation52 to generate a set of second control signals PWM9 and PWM10.

[0100] The third regulation module 433 includes a second multiplier X23, an inverter N3, a third PI regulator PI_33 and a fourth saturation limiter Saturation43. The second multiplier X23 is used to obtain a second preset current Is23 based on the total preset current Iset. The first input end of the third PI regulator PI_33 is used to receive the second preset current Is23. The inverter N3 is used to invert the second current I23. The second input end of the third PI regulator PI_33 is used to receive the inverted second current I23. The input end of the fourth saturation limiter Saturation43 is connected to the output end of the third PI regulator PI_33. The output end of the fourth saturation limiter Saturation43 is used to output a third regulation signal Iout_33. The fourth saturation limiter Saturation43 is used to limit the output signal of the third PI regulator PI_33 within the second limiting range to obtain the third regulation signal Iout_33.

[0101] The second output module 436 includes a second adder A23, a fifth saturation limiter Saturation53 and a second processing module NV23. The first input end of the second adder A23 is connected to the first adjustment module 41 to receive the first adjustment signal Iout_1. The second input end of the second adder A23 is connected to the third adjustment module 433 to receive the third adjustment signal Iout_33. The fifth saturation limiter Saturation53 is connected to the output end of the second adder A23 to limit the signal generated by the sum of the first adjustment signal Iout_1 and the third adjustment signal Iout_33 within the first limiting range. The second processing module NV23 is connected to the fifth saturation limiter Saturation53 to process the signal output by the fifth saturation limiter Saturation53 to generate a group of second control signals PWM11 and PWM12.

[0102] The present application also discloses a current sharing control method, based on the above Figure 1 , Figure 2 and Figure 3 The current sharing control circuit and the current sharing control method include:

[0103] The first current on each first output branch, the second current on each second output branch, and the total current Isum on the first output terminal O1 or the second output terminal O2 are detected and obtained by the detection unit 30 .

[0104] The control unit generates a first adjustment signal Iout_1 within a first limiting range based on a deviation between the total current Isum and the total preset current Iset.

[0105] A control unit generates a second adjustment signal within a second limiting range based on the deviation between each first current and the corresponding first preset current, and generates a group of first control signals based on the first adjustment signal Iout_1 and each second adjustment signal, and controls the action of each first switch unit through each group of first control signals.

[0106] The control unit generates a third adjustment signal within the second limiting range based on the deviation between each second current and the corresponding second preset current, generates a group of second control signals based on the first adjustment signal Iout_1 and each third adjustment signal, and controls the action of each second switch unit through each group of second control signals.

[0107] Furthermore, the current sharing control method includes: processing the total current Isum and the total preset current Iset by a first PI regulator PI_1 to generate a corresponding first control variable, limiting the first control variable within a first limiting range by a first saturation limiter Saturation1 to output a first adjustment signal Iout_1.

[0108] The first preset currents Is11, Is12, Is13 are obtained based on the total preset current Iset through the first multipliers X11, X12, X13, the first preset currents Is11, Is12, Is13 and the first currents I11, I12, I13 are processed by the second PI regulators PI_21, PI_22, PI_23 to generate corresponding second control quantities, and the second control quantities are limited within the second limiting range by the second saturation limiters Saturation21, Saturation22, Saturation23 to output second adjustment signals Iout_21, Iout_22, Iout_23.

[0109] The first adjustment signal Iout_1 and the second adjustment signal Iout_21, Iout_22, Iout_23 are summed respectively by the first adders A11, A12, A13, and the signals generated by the sum of the first adjustment signal Iout_1 and the second adjustment signals Iout_21, Iout_22, Iout_23 are limited within the first limiting range by the third saturation limiters Saturation31, Saturation32, Saturation33. The signals output by the third saturation limiters Saturation31, Saturation32, Saturation33 are processed by the first processing modules NV11, NV12, NV13 to generate the first control signals PWM1 and PWM2, PWM3 and PWM4, PWM5 and PWM6.

[0110] The second preset currents Is21, Is22, Is23 are obtained based on the total preset current Iset through the second multipliers X21, X22, X23, the second preset currents Is21, Is22, Is23 and the second currents I21, I22, I23 are processed by the third PI regulator PI_31 to generate corresponding third control quantities, and the third control quantities are limited within the second limiting range by the fourth saturation limiters Saturation41, Saturation42, Saturation43 to output corresponding third adjustment signals Iout_31, Iout_32, Iout_33.

[0111] The first adjustment signal Iout_1 is summed with the third adjustment signal Iout_31, Iout_32, Iout_33 respectively through the second adders A21, A22, A23, and the signal generated by the sum of the first adjustment signal Iout_1 and the third adjustment signal Iout_31, Iout_32, Iout_33 is limited within the first limiting range through the fifth saturation limiter Saturation51, Saturation52, Saturation53, and the signals output by the fifth saturation limiter Saturation51, Saturation52, Saturation53 are processed through the second processing modules NV21, NV22, NV23 to generate groups of second control signals PWM7 and PWM8, PWM9 and PWM10, PWM11 and PWM12.

[0112] Combination Figure 1 , Figure 2 and Figure 3 The topology of the current sharing control circuit in the present invention is as follows: two groups of independent AC-DC power modules are connected at the input end, and then two groups of power units (a first power unit 10 and a second power unit 20) are connected. The power units are in the form of DC-DC, and the inputs of the two groups of power units are connected in series (i.e., the input negative end of the first power unit 10 is connected to the input positive end of the second power unit 20 of the second group). The output ends of the two groups of power units are connected to the battery unit BATTERY to charge and discharge the battery unit BATTERY.

[0113] Each group of power units may be composed of multiple switch units and output branches. Each switch unit is composed of a half-bridge consisting of two upper and lower IGBTs (insulated gate bipolar transistors) or MOSFETs (insulated gate field effect transistors). Each output branch is composed of a filter inductor connected to the midpoint of the half-bridge. The output current of each half-bridge switch unit (i.e., the current on the output branch) is sampled by the Hall to obtain the current signals I1~I6 output by each half-bridge switch unit. The outputs of the three half-bridge switch units are connected in parallel through the output branches and then filtered by the second capacitor C2 and the fourth capacitor C4 to obtain the total current Isum. The total current Isum is also sampled by the Hall, and the voltage signal on the battery unit BATTERY is sampled at the same time.

[0114] The control block diagram of the circuit constant current charging and discharging is as follows Figure 2 and Figure 3 As shown, Iset is the set total preset current. The total preset current Iset and the sampled total current Isum pass through the first PI regulator PI_1 to output the first pre-adjustment value I_preout1, and then pass through the first saturation limiter Saturation1 to output the first adjustment signal Iout_1, wherein the first limiting range of the first saturation limiter Saturation1 is 0.02~0.98 (the dead time accounts for 0.02, and all the first limiting ranges in one embodiment are 0.02~0.98).

[0115] In one embodiment, since each power unit group is composed of three output branches, each first preset current is preset to 1 / 3*Iset, that is, the total preset current Iset is evenly divided into three parts corresponding to three first preset currents, and the first preset current Is11 and the first current I11 (actual current) of the first switch unit 11 are passed through the second PI regulator PI_21 to output the second pre-adjustment amount I_preout21, and then pass through the second saturation limiter Saturation21 to output the second adjustment signal I_out21, wherein the second saturation limiter Sat The second limiting range of uration21 is -0.01 to 0.01 (all second limiting ranges in one embodiment are -0.01 to 0.01), the second adjustment signal I_out21 is added to the first adjustment signal Iout_1 and then limited by the third saturation limiter Saturation31, and finally a group of first control signals PWM1 and PWM2 are output through the first processing module NV11, and the first limiting range of the third saturation limiter Saturation31 is 0.02 to 0.98 (the dead time accounts for 0.02).

[0116] Since the first limiting range of the first saturation limiter Saturation1 is larger, and the second limiting range of the second saturation limiter Saturation21 is smaller, it is equivalent to realizing coarse adjustment of the duty cycle through the first adjustment signal Iout_1 and combining it with fine adjustment of the duty cycle through the second adjustment signal I_out21, so as to obtain a set of first control signals PWM1 and PWM2 with stable duty cycles. Similarly, the first output modules 424, 425, 426 and the second output modules 434, 435, 436 also output first control signals PWM3 and PWM4 with stable duty cycles, first control signals PWM5 and PWM6 with stable duty cycles, second control signals PWM7 and PWM8 with stable duty cycles, second control signals PWM9 and PWM10 with stable duty cycles, and second control signals PWM11 and PWM12 with stable duty cycles, respectively, to realize constant current charging and discharging.

[0117] Due to the range limitations of the second saturation limiter Saturation21, Saturation22, Saturation23 and the fourth saturation limiter Saturation41, Saturation42, Saturation43, the final difference between the first control signal PWM1, PWM3, PWM5 and the second control signal PWM8, PWM10, PWM12 is only 2% at most, that is, the maximum voltage difference between the output voltage of the first power unit 10 and the output voltage of the second power unit 20 is only 2% of the input bus voltage. Since the output currents of the first power unit 10 and the second power unit 20 are the same, the output powers of the first power unit 10 and the second power unit 20 differ by only 2% at most.

[0118] In one embodiment, when charging the battery cell BATTERY, the waveforms of the first control signals PWM1, PWM3, PWM5 of the first transistors Q1, Q3, Q5, the first control signals PWM2, PWM4, PWM6 of the second transistors Q2, Q4, Q6, the second control signals PWM7, PWM9, PWM11 of the third transistors Q7, Q9, Q11, the second control signals PWM8, PWM10, PWM12 of the fourth transistors Q8, Q10, Q12, and the first currents I11, I12, I13 and the second currents I21, I22, I23 are as follows: Figure 4 and Figure 5As shown, the duty cycle of the first control signals PWM1, PWM3, and PWM5 corresponds to the turn-on time of the first transistors Q1, Q3, and Q5. For example, if the duty cycle of the first control signals PWM1, PWM3, and PWM5 is 0.8, the turn-on time of the first transistors Q1, Q3, and Q5 is 80%, and the corresponding duty cycle of the first control signals PWM2, PWM4, and PWM6 is 0.2, and the turn-on time of the second transistors Q2, Q4, and Q6 is 20% (excluding dead time); the duty cycle of the second control signals PWM8, PWM10, and PWM12 corresponds to the turn-on time of the fourth transistors Q8, Q10, and Q12. For example, if the duty cycle of the second control signals PWM8, PWM10, and PWM12 is 0.8, the turn-on time of the fourth transistors Q8, Q10, and Q12 is 80%, the duty cycle of the second control signals PWM7, PWM9, and PWM11 is 0.2, and the turn-on time of the third transistors Q7, Q9, and Q11 is 20%.

[0119] When charging the battery cell BATTERY, when the first transistor Q1 is turned on, the current on the first inductor L11 rises in the positive direction (the current direction is positive from left to right), and when the first transistor Q1 is turned off, the current on the first inductor L11 decreases in the positive direction, and the same applies to the first transistors Q3 and Q5. When the fourth transistor Q8 is turned on, the current on the second inductor L21 rises in the reverse direction (the current direction is positive from left to right), and when the fourth transistor Q8 is turned off, the current on the second inductor L21 decreases in the reverse direction, and the same applies to the fourth transistors Q10 and Q12.

[0120] In one embodiment, if Figure 6 and Figure 7 As shown, current balancing is performed when charging the battery cell BATTERY, and the total preset current Iset is set to 300A. Before 0.15s, the duty cycle D11 of the first control signal PWM1, the duty cycle D12 of the first control signal PWM3, and the duty cycle D13 of the first control signal PWM5 have the same value. However, since the parameters of the components in the circuit are not completely consistent, the currents on the first inductors L11, L12, and L13 have large deviations. Long-term operation like this will cause uneven heating of the three groups of transistors Q1~Q6 and the first inductors L11, L12, and L13, affecting the temperature reliability of the equipment.

[0121] If the first current I11 on the first current I11 is less than 1 / 3*Iset (i.e. 100A), that is, the reference current in the second PI regulator PI_21 is greater than the actual first current I11, the second adjustment signal Iout_21 is positive after adjustment calculation by the second PI regulator PI_21 (e.g. Figure 7), after the second adjustment signal Iout_21 is added to the first adjustment signal Iout_1, the duty cycle D11 of the first control signal PWM1 is increased, and the on-time of the first transistor Q1 is increased, so that the first current I11 flowing through the first inductor L11 increases continuously and finally reaches the set 1 / 3*Iset.

[0122] If the first current I12 on the first inductor L12 is greater than 1 / 3*Iset, the reference current in the second PI regulator PI_22 is less than the actual first current I12, and the second PI regulator PI_22 adjusts the second adjustment signal Iout_22 to be negative (e.g. Figure 7 ), after the second regulating signal Iout_22 is added to the first regulating signal Iout_1, the duty cycle D12 of the first control signal PWM3 is reduced, and the on-time of the first transistor Q3 is reduced, so that the first current I12 flowing through the first inductor L12 is continuously reduced and finally reaches the set 1 / 3*Iset.

[0123] If the first current I13 on the first inductor L13 is substantially the same as 1 / 3*Iset, then the reference current in the second PI regulator PI_23 is equal to the actual first current I13, and after calculation by the second PI regulator PI_23, the second adjustment signal Iout_23 output is close to 0 (e.g. Figure 7 ), after the second adjustment signal Iout_23 is added to the first adjustment signal Iout_1, the duty cycle D13 of the first control signal PWM5 is basically kept unchanged, and finally reaches the set 1 / 3*Iset. Finally, the first currents I11, I12, and I13 on the first inductors L11, L12, and L13 tend to be balanced.

[0124] The second currents I21, I22, I23 on the second inductors L21, L22, L23 are balanced in the same way. It should be noted that the second currents I21, I22, I23 on the second inductors L21, L22, L23 need to be inverted after sampling.

[0125] In one embodiment, when the battery cell BATTERY is discharged, the waveforms of the first control signals PWM1, PWM3, PWM5 of the first transistors Q1, Q3, Q5, the first control signals PWM2, PWM4, PWM6 of the second transistors Q2, Q4, Q6, the second control signals PWM7, PWM9, PWM11 of the third transistors Q7, Q9, Q11, the second control signals PWM8, PWM10, PWM12 of the fourth transistors Q8, Q10, Q12, and the first currents I11, I12, I13 and the second currents I21, I22, I23 are as follows: Figure 8 and Fig. 9As shown, the duty cycle of the first control signals PWM1, PWM3, and PWM5 corresponds to the turn-on time of the first transistors Q1, Q3, and Q5. For example, if the duty cycle of the first control signals PWM1, PWM3, and PWM5 is 0.8, the turn-on time of the first transistors Q1, Q3, and Q5 is 80%, and the corresponding duty cycle of the first control signals PWM2, PWM4, and PWM6 is 0.2, and the turn-on time of the second transistors Q2, Q4, and Q6 is 20% (excluding dead time); the duty cycle of the second control signals PWM8, PWM10, and PWM12 corresponds to the turn-on time of the fourth transistors Q8, Q10, and Q12. For example, if the duty cycle of the second control signals PWM8, PWM10, and PWM12 is 0.8, the turn-on time of the fourth transistors Q8, Q10, and Q12 is 80%, the duty cycle of the second control signals PWM7, PWM9, and PWM11 is 0.2, and the turn-on time of the third transistors Q7, Q9, and Q11 is 20%.

[0126] When the battery cell BATTERY is discharged, when the first transistor Q1 is turned on, the first current I11 on the first inductor L11 decreases in the reverse direction (the current direction is positive from left to right), and when the first transistor Q1 is turned off, the first current I11 on the first inductor L11 increases in the reverse direction, and the first transistor Q3 and the first transistor Q5 are the same. When the fourth transistor Q8 is turned on, the second current I21 on the second inductor L21 decreases in the forward direction (the current direction is positive from left to right), and when the fourth transistor Q8 is turned off, the second current I21 on the second inductor L21 increases in the forward direction, and the fourth transistor Q10 and the fourth transistor Q12 are the same.

[0127] In one embodiment, if Fig.10 and Fig.11 As shown, current balancing is performed on the battery cell BATTERY when it is discharged, and the total preset current Iset is set to -300A. Before 0.15s, the duty cycle D11 of the first control signal PWM1, the duty cycle D12 of the first control signal PWM3, and the duty cycle D13 of the first control signal PWM5 have the same value. However, since the parameters of the components in the circuit are not completely consistent, the currents on the first inductors L11, L12, and L13 have large deviations. Long-term operation like this will cause uneven heating of the three groups of transistors Q1~Q6 and the first inductors L11, L12, and L13, affecting the temperature reliability of the equipment.

[0128] If the first current I11 on the first current I11 is greater than 1 / 3*Iset (ie -100A), that is, the reference current in the second PI regulator PI_21 is less than the actual first current I11, the second adjustment signal Iout_21 is output as negative after adjustment calculation by the second PI regulator PI_21 (eg Fig.11), after the second adjustment signal Iout_21 is added to the first adjustment signal Iout_1, the duty cycle D11 of the first control signal PWM1 is reduced, and the on-time of the first transistor Q1 is reduced, so that the current flowing through the first inductor L11 is continuously reduced (increased in the negative direction), and finally reaches the set 1 / 3*Iset.

[0129] If the first current I12 on the first inductor L12 is less than 1 / 3*Iset, the reference current in the second PI regulator PI_22 is greater than the actual first current I12, and the second PI regulator PI_22 adjusts the second adjustment signal Iout_22 to be positive after adjustment (e.g. Fig.11 ), after the second adjustment signal Iout_22 is added to the first adjustment signal Iout_1, the duty cycle D12 of the first control signal PWM3 is increased, and the turn-on time of the first transistor Q3 is increased, so that the first current I12 flowing through the first inductor L12 is continuously increased (negatively decreased), and finally reaches the set 1 / 3*Iset.

[0130] If the first current I13 on the first inductor L13 is less than 1 / 3*Iset, the reference current in the second PI regulator PI_23 is greater than the actual first current I13, and the second adjustment signal Iout_23 is output as positive after calculation by the second PI regulator PI_23 (e.g. Fig.11 ), after the second adjustment signal Iout_23 is added to the first adjustment signal Iout_1, the duty cycle D13 of the first control signal PWM5 is increased, and the on-time of the first transistor Q5 is increased, so that the first current I13 flowing through the first inductor L13 is continuously increased (negatively decreased), and finally reaches the set 1 / 3*Iset.

[0131] Finally, the first currents I11, I12, I13 on the first inductors L11, L12, L13 tend to be balanced. The second currents I21, I22, I23 on the second inductors L21, L22, L23 are balanced in the same way. It should be noted that the second currents I21, I22, I23 on the second inductors L21, L22, L23 need to be inverted after sampling.

[0132] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0133] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A current sharing control circuit, characterized in that: include: a first power unit, comprising a plurality of first switch units and a plurality of first output branches, each of the first switch units being connected between a first input terminal and a second input terminal, a first terminal of each of the first output branches being connected to a corresponding first switch unit, and second terminals of the first output branches being connected to form a first output terminal, and each of the first switch units controlling the first input terminal to be connected to the first output branch or controlling the second input terminal to be connected to the first output branch based on a set of first control signals; a second power unit, comprising a plurality of second switch units and a plurality of second output branches, each of the second switch units being connected between a third input terminal and a fourth input terminal, the third input terminal being connected to the second input terminal, a first end of each of the second output branches being connected to a corresponding second switch unit, and second ends of the second output branches being connected to form a second output terminal, and each of the second switch units controlling the third input terminal to be connected to the second output branch or controlling the fourth input terminal to be connected to the second output branch based on a set of second control signals; A detection unit, used for detecting and obtaining a first current on each first output branch, a second current on each second output branch, and a total current on the first output terminal or the second output terminal; A control unit, used to generate a first adjustment signal within a first limiting range based on the deviation between the total current and the total preset current, generate a second adjustment signal within a second limiting range based on the deviation between each first current and the corresponding first preset current, generate a third adjustment signal within the second limiting range based on the deviation between each second current and the corresponding second preset current, and generate a group of first control signals based on the first adjustment signal and each second adjustment signal, and generate a group of second control signals based on the first adjustment signal and each third adjustment signal.

2. The current sharing control circuit according to claim 1, characterized in that: The control unit comprises: a first regulating module, a plurality of second regulating modules, a plurality of third regulating modules, a plurality of first output modules and a plurality of second output modules; The first regulating module generates a first regulating signal within a first limiting range based on a deviation between the total current and the total preset current; Each of the second regulating modules generates a corresponding second regulating signal within a second limiting range based on a deviation between a corresponding first current and a corresponding first preset current, and each of the first output modules generates a corresponding set of first control signals within the first limiting range based on the first regulating signal and the corresponding second regulating signal; Each of the third regulation modules generates a corresponding third regulation signal within a second limiting range based on a deviation between a corresponding second current and a corresponding second preset current, and each of the second output modules generates a corresponding set of second control signals within the first limiting range based on the first regulation signal and the corresponding third regulation signal.

3. The current sharing control circuit according to claim 2, characterized in that: The first regulation module includes a first PI regulator and a first saturation limiter, the first input end of the first PI regulator is used to receive the total current, the second input end of the first PI regulator is used to receive the total preset current, the input end of the first saturation limiter is connected to the output end of the first PI regulator, the output end of the first saturation limiter is used to output a first regulation signal, and the first saturation limiter is used to limit the output signal of the first PI regulator to a first limiting range.

4. The current sharing control circuit according to claim 2, characterized in that: The second regulation module includes a first multiplier, a second PI regulator and a second saturation limiter, the first multiplier is used to obtain a first preset current based on a total preset current, the first input end of the second PI regulator is used to receive the first preset current, the second input end of the second PI regulator is used to receive the first current, the input end of the second saturation limiter is connected to the output end of the second PI regulator, the output end of the second saturation limiter is used to output a second regulation signal, and the second saturation limiter is used to limit the output signal of the second PI regulator to a second limiting range; and / or The third regulation module includes a second multiplier, an inverter, a third PI regulator and a fourth saturation limiter, wherein the second multiplier is used to obtain a second preset current based on the total preset current, the first input end of the third PI regulator is used to receive the second preset current, the inverter is used to invert the second current, the second input end of the third PI regulator is used to receive the inverted second current, the input end of the fourth saturation limiter is connected to the output end of the third PI regulator, the output end of the fourth saturation limiter is used to output a third regulation signal, and the fourth saturation limiter is used to limit the output signal of the third PI regulator to a second limiting range.

5. The current sharing control circuit according to claim 2, characterized in that: The first output module includes a first adder, a third saturation limiter and a first processing module, the first input end of the first adder is connected to the first adjustment module to receive a first adjustment signal, the second input end of the first adder is connected to the second adjustment module to receive a second adjustment signal, the third saturation limiter is connected to the output end of the first adder to limit the signal generated by the sum of the first adjustment signal and the second adjustment signal to a within a limiting range, and the first processing module is connected to the third saturation limiter to process the signal output by the third saturation limiter to generate a set of first control signals; and / or The second output module includes a second adder, a fifth saturation limiter and a second processing module, the first input end of the second adder is connected to the first adjustment module to receive a first adjustment signal, the second input end of the second adder is connected to the third adjustment module to receive a third adjustment signal, the fifth saturation limiter is connected to the output end of the second adder to limit the signal generated by the sum of the first adjustment signal and the third adjustment signal within a first limiting range, and the second processing module is connected to the fifth saturation limiter to process the signal output by the fifth saturation limiter to generate a set of second control signals.

6. The current sharing control circuit according to claim 1, characterized in that: The first switch unit includes a first transistor and a second transistor, the second end of the first transistor is connected to the first input end, the first end of the first transistor is connected to the second end of the second transistor and the first end of the first output branch, the first end of the second transistor is connected to the second input end, and the control end of the first transistor and the control end of the second transistor are used to receive a group of first control signals, and the group of first control signals is used to control the first transistor to turn on and the second transistor to turn off, or to control the second transistor to turn on and the first transistor to turn off; and / or The second switch unit includes a third transistor and a fourth transistor, the second end of the third transistor is connected to the third input end, the first end of the third transistor is connected to the second end of the fourth transistor and the first end of the second output branch, the first end of the fourth transistor is connected to the fourth input end, and the control end of the third transistor and the control end of the fourth transistor are used to receive a group of second control signals, and the group of second control signals is used to control the third transistor to turn on and the fourth transistor to turn off, or to control the fourth transistor to turn on and the third transistor to turn off.

7. The current sharing control circuit according to claim 1, characterized in that: The first output branch includes a first inductor, a first end of the first inductor is a first end of the first output branch, and a second end of the first inductor is a second end of the first output branch; and / or The second output branch includes a second inductor, a first end of the second inductor is a first end of the second output branch, and a second end of the second inductor is a second end of the second output branch.

8. The current sharing control circuit according to claim 1, characterized in that: The first power unit further includes a first capacitor and / or a second capacitor, wherein a first end of the first capacitor is connected to the first input end, a second end of the first capacitor is connected to the second input end, a first end of the second capacitor is connected to the first output end, and a second end of the second capacitor is connected to the second input end; and / or The second power unit also includes a third capacitor and / or a fourth capacitor, the first end of the third capacitor is connected to the third input terminal, the second end of the third capacitor is connected to the fourth input terminal, the first end of the fourth capacitor is connected to the third input terminal, and the second end of the fourth capacitor is connected to the second output terminal.

9. A current sharing control method, characterized in that: Based on the current sharing control circuit according to any one of claims 1 to 8, the current sharing control method comprises: Detect and obtain, by a detection unit, a first current on each first output branch, a second current on each second output branch, and a total current on the first output terminal or the second output terminal; Generate a first adjustment signal within a first limiting range based on a deviation between the total current and the total preset current by a control unit; The control unit generates a second regulating signal within a second limiting range based on a deviation between each first current and a corresponding first preset current, and generates a group of first control signals based on the first regulating signal and each second regulating signal, and controls the action of each first switch unit through each group of first control signals; A control unit generates a third adjustment signal within a second limiting range based on the deviation between each second current and the corresponding second preset current, generates a group of second control signals based on the first adjustment signal and each third adjustment signal, and controls the action of each second switch unit through each group of second control signals.

10. The current sharing control method according to claim 9, characterized in that: The current sharing control method comprises: The total current and the total preset current are processed by a first PI regulator to generate a corresponding first control amount, and the first control amount is limited within a limiting range by a first saturation limiter to output a first adjustment signal; Obtain a first preset current based on the total preset current by a first multiplier, process the first preset current and the first current by a second PI regulator to generate a corresponding second control amount, and limit the second control amount within a second limiting range by a second saturation limiter to output a second adjustment signal; The first adjustment signal and the second adjustment signal are summed by a first adder, a signal generated by the sum of the first adjustment signal and the second adjustment signal is limited within a first limiting range by a third saturation limiter, and a signal output by the third saturation limiter is processed by a first processing module to generate a set of first control signals; Obtaining a second preset current based on the total preset current through a second multiplier, inverting the second current through an inverter, processing the second preset current and the inverted second current through a third PI regulator to generate a third control amount, and limiting the third control amount within a second limiting range through a fourth saturation limiter to output a third adjustment signal; The first adjustment signal and the third adjustment signal are summed by a second adder, a signal generated by the sum of the first adjustment signal and the third adjustment signal is limited within a first limiting range by a fifth saturation limiter, and a signal output by the fifth saturation limiter is processed by a second processing module to generate a set of second control signals.

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