Silicon carbide power device parallel drive oscillation suppression circuit and control method

Abstract

The present application provides a parallel drive oscillation suppression circuit and control method for silicon carbide power devices, belonging to the field of power electronics technology. The circuit includes a dual-pull drive chip, multiple silicon carbide power devices, and multiple pull-down modules. Multiple silicon carbide power devices and multiple pull-down modules are respectively controlled by the first chip drive end and the second chip drive end of the dual-pull drive chip. Each silicon carbide power device is connected to a pull-down module, ensuring that the drive pull-down circuit of each silicon carbide power device is independent and does not flow through the parasitic inductance of the first chip drive end and the second chip drive end of the dual-pull drive chip, eliminating the influence of the parasitic inductance of the Miller clamp circuit, solving the problem of repeated oscillation of the gate voltage of all parallel silicon carbide power devices, and ensuring the normal operation of all parallel silicon carbide power devices.

Description

Technical Field

[0001] The present application belongs to the field of power electronics technology, and in particular relates to a parallel drive oscillation suppression circuit and a control method for a silicon carbide power device. Background Art

[0002] With the continuous development of power electronics technology, the performance requirements for power devices are becoming increasingly stringent. Traditional silicon-based power devices are increasingly unable to meet the demands of modern power systems in terms of voltage resistance, switching speed, conduction loss, and high-temperature performance. Compared to silicon-based power devices, silicon carbide (SiC) power devices have begun to be widely used due to their low power consumption, wide bandgap, and high thermal conductivity.

[0003] However, when a driver chip drives multiple parallel-connected SiC power devices, it cannot take into account the drive wiring of all parallel-connected SiC power devices, resulting in an increase in parasitic parameters between the driver chip and all parallel-connected SiC power devices. As a result, the increased parasitic parameters cause LC resonance in the entire circuit, causing the gate voltage of all parallel-connected SiC power devices to oscillate repeatedly, resulting in the SiC power devices being erroneously turned on, affecting their normal operation. Summary of the Invention

[0004] The purpose of this application is to provide a parallel drive oscillation suppression circuit and control method for silicon carbide power devices, aiming to solve the problem of repeated oscillation of gate voltage when a traditional driver chip drives multiple parallel silicon carbide power devices.

[0005] The present application provides a parallel drive oscillation suppression circuit for a silicon carbide power device, comprising:

[0006] Dual pull driver chip;

[0007] A plurality of silicon carbide power devices, wherein the first ends of the plurality of silicon carbide power devices are connected, the second ends of the plurality of silicon carbide power devices are connected, and the driving ends of the plurality of silicon carbide power devices are connected to the first chip driving end of the dual-pull driving chip;

[0008] A plurality of pull-down modules, wherein the driving ends of the plurality of pull-down modules are connected to the second chip driving end of the dual-pull driving chip, the first end of each of the pull-down modules is connected to the driving end of each of the silicon carbide power devices, and the second ends of the plurality of pull-down modules are connected to a negative power supply;

[0009] The voltage of the first end of the silicon carbide power device is greater than the voltage of the second end of the silicon carbide power device, and the voltage of the second end of the silicon carbide power device is greater than the voltage of the second end of the pull-down module.

[0010] In one embodiment, the circuit further comprises:

[0011] A plurality of negative pressure stabilization modules are provided, wherein the first end of each of the negative pressure stabilization modules is connected to the second end of each of the pull-down modules, and the second end of each of the negative pressure stabilization modules is connected to the second end of each of the silicon carbide power devices.

[0012] In one embodiment, each of the pull-down modules includes:

[0013] A clamping power device, wherein the driving end of the clamping power device is connected to the second chip driving end of the dual-pull driving chip, the first end of the clamping power device is connected to the driving end of the silicon carbide power device, and the second end of the clamping power device is connected to the negative power supply.

[0014] In one embodiment, the circuit further comprises:

[0015] A first driving module, wherein a first end of the first driving module is connected to the driving end of the first chip, and a second end of the first driving module is connected to the driving ends of the plurality of silicon carbide power devices and the first ends of the plurality of pull-down modules.

[0016] In one embodiment, the circuit further comprises:

[0017] A second driving module, wherein a first end of the second driving module is connected to the driving end of the second chip, and a second end of the second driving module is connected to the driving ends of the plurality of pull-down modules.

[0018] In one embodiment, the dual-pull driver chip, the plurality of silicon carbide power devices, and the plurality of pull-down modules form an upper bridge arm or a lower bridge arm of a circuit.

[0019] The present application provides a control method for a parallel-driven oscillation suppression circuit for a silicon carbide power device, which is applied to the parallel-driven oscillation suppression circuit for a silicon carbide power device according to any one of the above embodiments. The control method includes:

[0020] The dual-pull driver chip generates a first drive signal according to the input signal to control the on and off of the multiple silicon carbide power devices;

[0021] The dual-pull driving chip acquires the input signal and generates a second driving signal according to the input signal to control the on and off of the multiple pull-down modules;

[0022] The first drive signal and the second drive signal are pulse width modulation signals, the falling edge of the second drive signal is located before the rising edge of the first drive signal, and the rising edge of the second drive signal is located after the falling edge of the first drive signal.

[0023] In one embodiment, the time difference between the rising edge of the first drive signal and the rising edge of the input signal is the drive transmission delay, and the time difference between the falling edge of the second drive signal and the rising edge of the input signal is less than the drive transmission delay.

[0024] In one embodiment, between the falling edge of the first driving signal and the rising edge of the second driving signal, the first driving signal is a low-level signal and the voltage of the first driving signal is less than a turn-on voltage threshold of the silicon carbide power device.

[0025] In one embodiment, the time difference between the rising edge of the second drive signal and the falling edge of the first drive signal is determined according to the drive resistance between the dual-pull drive chip and the silicon carbide power device and the parasitic capacitance between the drive end and the second end of the silicon carbide power device.

[0026] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0027] The voltage at the first end of the silicon carbide power device (which can be understood as Figure 1 The voltage at node A and the voltage at node B) are greater than the voltage at the second end of the silicon carbide power device (which can be understood as Figure 1 (The voltage at node F in FIG1 is used to represent the voltage at node F in FIG2 ). The current from nodes A, B, and C to node D splits into two paths. One path passes through node F and reaches the second terminals of the multiple silicon carbide power devices. The voltage at the second terminals of the silicon carbide power devices is greater than the voltage at the second terminal of the pull-down module. The other path passes through node E and the pull-down module and reaches the second terminal of the pull-down module.

[0028] The first chip driving end and the second chip driving end of the dual-pull driver chip are respectively connected to the driving ends of multiple silicon carbide power devices and the driving ends of multiple pull-down modules, and can respectively control the conduction or shutdown of multiple silicon carbide power devices and multiple pull-down modules, so that the current flowing out from node A flows directly to the second ends of the multiple silicon carbide power devices and the second ends of the multiple pull-down modules through node B, node C, node D, node E, and node F, respectively, and will not flow through the parasitic parameters between the dual-pull driver chip and all parallel silicon carbide power devices. It can also be understood as not flowing through the parasitic inductance of the first chip driving end and the second chip driving end of the dual-pull driver chip.

[0029] The first end of each pull-down module is connected to the driving end of each silicon carbide power device. The second chip driving end of the dual-pull driving chip controls the conduction of multiple pull-down modules, and can pull the driving end of the silicon carbide power device down to the negative power supply VEE.

[0030] By controlling multiple silicon carbide power devices and multiple pull-down modules through the first and second chip driver terminals of the dual-pull driver chip, respectively, the control process is more flexible and the number of pull-down modules is not restricted. Each silicon carbide power device can be connected to a pull-down module. Each silicon carbide power device is connected to a pull-down module, ensuring that the drive pull-down circuit of each silicon carbide power device is independent. The current does not flow through the parasitic inductance of the first and second chip driver terminals of the dual-pull driver chip, but directly reaches the negative power supply VEE. This eliminates the influence of the parasitic inductance of the Miller clamp circuit, solves the problem of repeated oscillation of the gate voltage of all parallel silicon carbide power devices, and ensures the normal operation of all parallel silicon carbide power devices. Furthermore, each silicon carbide power device is connected to a pull-down module, ensuring that the drive pull-down circuit of each silicon carbide power device is independent, solving the problem of crosstalk between the drive circuits of silicon carbide power devices and effectively ensuring the safe and reliable operation of the entire circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments or exemplary technical descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0032] Figure 1 This is a schematic structural diagram of a parallel drive oscillation suppression circuit for silicon carbide power devices in some embodiments provided in this application.

[0033] Figure 2 This is a schematic diagram of the connection structure of parasitic inductance and parasitic capacitance in a parallel drive oscillation suppression circuit of a silicon carbide power device in some embodiments provided in this application.

[0034] Figure 3 This is a schematic diagram of the connection structure of the clamping power device, the negative voltage stabilization module, the first driving module and the second driving module in the parallel driving oscillation suppression circuit of the silicon carbide power device in some embodiments provided in this application.

[0035] Figure 4 This is a schematic diagram of the connection structure between the upper bridge arm of the circuit and the lower bridge arm of the circuit in some embodiments provided in this application.

[0036] Figure 5 This is a schematic diagram of the timing control of the upper bridge arm or the lower bridge arm of the circuit in the parallel drive oscillation suppression circuit of the silicon carbide power device in some embodiments provided in the present application.

[0037] Figure 6This is a schematic diagram of the overall timing control of the parallel drive oscillation suppression circuit of the silicon carbide power device in some embodiments provided in this application.

[0038] Figure 7 Schematic diagram of the pull-down path in traditional technology.

[0039] Figure 8 This is a schematic diagram of the pull-down path of the parallel-driven oscillation suppression circuit of the silicon carbide power device provided in this application. DETAILED DESCRIPTION

[0040] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, this application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0041] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0042] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0043] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0044] In traditional technology, silicon carbide power devices are subject to the limitations of the silicon carbide substrate's own production process, and their cost is higher than that of silicon-based power devices. To reduce cost and area, traditional technology typically uses a single Miller clamp driver chip to drive multiple parallel silicon carbide power devices. However, when using a single Miller clamp driver chip to drive multiple parallel silicon carbide power devices, the single Miller clamp driver chip cannot take into account the drive wiring of all parallel silicon carbide power devices, which increases the parasitic parameters between the single Miller clamp driver chip and all parallel silicon carbide power devices. The function of the Miller clamp of the Miller clamp driver chip is to add an extremely low-impedance pull-down circuit to provide a large current to pull down the gate voltage. However, due to the increase in parasitic inductance in the parasitic parameters, it will have a suppressive effect on the pull-down current, reducing the clamping effect. Moreover, the increase in parasitic parameters will also cause LC resonance in the entire circuit, resulting in repeated oscillation of the gate voltage of all parallel-connected silicon carbide power devices, causing the silicon carbide power devices to be falsely turned on, affecting the normal use of the silicon carbide power devices.

[0045] Therefore, for the above problems, please refer to Figure 1 The present application provides a parallel drive oscillation suppression circuit 100 for silicon carbide power devices. The parallel drive oscillation suppression circuit 100 for silicon carbide power devices includes a dual-pull driver chip 10, multiple silicon carbide power devices 210, and multiple pull-down modules 30. The first ends of the multiple silicon carbide power devices 210 are connected. The second ends of the multiple silicon carbide power devices 210 are connected. The driving ends of the multiple silicon carbide power devices 210 are connected to the first chip driving end of the dual-pull driver chip 10. The driving ends of the multiple pull-down modules 30 are connected to the second chip driving end of the dual-pull driver chip 10. The first end of each pull-down module 30 is connected to the driving end of each silicon carbide power device 210. The second ends of the multiple pull-down modules 30 are connected to a negative power supply VEE. The voltage at the first end of the silicon carbide power device 210 is greater than the voltage at the second end of the silicon carbide power device 210, and the voltage at the second end of the silicon carbide power device 210 is greater than the voltage at the second end of the pull-down module 30.

[0046] In this embodiment, the first terminals of the plurality of silicon carbide power devices 210 are connected to form a first common connection terminal of the plurality of silicon carbide power devices 210. The voltage of the first terminal of the silicon carbide power device 210 (which can be understood as Figure 1 The voltage at the A node and the voltage at the B node) are greater than the voltage at the second end of the silicon carbide power device 210 (which can be understood as Figure 1(The voltage at node F in FIG1 is used to represent the voltage at node F in FIG1 ). The current flows from nodes A, B, and C to node D, splitting into two paths. One path passes through node F and reaches the second terminals of the multiple silicon carbide power devices 210, which is the second common connection terminal of the multiple silicon carbide power devices 210. The voltage at the second terminals of the silicon carbide power devices 210 is greater than the voltage at the second terminal of the pull-down module 30. The other path passes through node E and the pull-down module 30 and reaches the second terminal of the pull-down module 30, which is the first common connection terminal of the multiple pull-down modules 30.

[0047] The first chip driving end and the second chip driving end of the dual-pull driver chip 10 are respectively connected to the driving ends of multiple silicon carbide power devices 210 and the driving ends of multiple pull-down modules 30, and can respectively control the conduction or shutdown of multiple silicon carbide power devices 210 and multiple pull-down modules 30, so that the current flowing out from node A flows directly to the second ends of the multiple silicon carbide power devices 210 and the second ends of the multiple pull-down modules 30 through nodes B, C, D, E, and F, respectively, and will not flow through the parasitic parameters between the dual-pull driver chip 10 and all parallel-connected silicon carbide power devices 210, which can also be understood as not flowing through the parasitic inductance of the first chip driving end and the second chip driving end of the dual-pull driver chip 10.

[0048] The first end of each pull-down module 30 is connected to the driving end of each silicon carbide power device 210. The second chip driving end of the dual-pull driving chip 10 controls the conduction of multiple pull-down modules 30, and can pull the driving end of the silicon carbide power device 210 down to the negative power supply VEE.

[0049] The first chip driver terminal and the second chip driver terminal of the dual-pull driver chip 10 respectively control multiple silicon carbide power devices 210 and multiple pull-down modules 30, making the control process more flexible and not limiting the number of pull-down modules 30. Each silicon carbide power device 210 can be connected to a pull-down module 30. Each silicon carbide power device 210 is connected to a pull-down module 30, ensuring that the driving pull-down circuit of each silicon carbide power device 210 is independent. The current does not flow through the parasitic inductance of the first chip driver terminal and the second chip driver terminal of the dual-pull driver chip 10, but directly reaches the negative power supply VEE. This eliminates the influence of the parasitic inductance of the Miller clamp circuit, solves the problem of repeated oscillation of the gate voltage of all parallel-connected silicon carbide power devices 210, and ensures the normal operation of all parallel-connected silicon carbide power devices 210. Furthermore, each silicon carbide power device 210 is connected to a pull-down module 30, ensuring that the driving pull-down circuit of each silicon carbide power device 210 is independent, solving the problem of driving circuit crosstalk between silicon carbide power devices 210 and silicon carbide power devices 210, and effectively ensuring the safe and reliable operation of the entire circuit.

[0050] See Figure 2In one embodiment, the driving end of the pull-down module 30 is connected to the second chip driving end of the dual-pull driver chip 10 to form a first parasitic inductor 610. The driving end of the silicon carbide power device 210 is connected to the first chip driving end of the dual-pull driver chip 10 to form a second parasitic inductor 620 and a third parasitic inductor 630. The second ends of the plurality of silicon carbide power devices 210 are connected to form a fourth parasitic inductor 640. A first parasitic capacitor 710 is formed between the first end and the driving end of the silicon carbide power device 210. A second parasitic capacitor 720 is formed between the second end and the driving end of the silicon carbide power device 210.

[0051] In this embodiment, the first parasitic inductor 610 is the parasitic inductance formed by the printed circuit board (PCB) traces between the driving end of the pull-down module 30 and the second chip driving end of the dual-pull driver chip 10. The second parasitic inductor 620 is the parasitic inductance formed by the PCB traces between the driving end of the silicon carbide power device 210 and the first chip driving end of the dual-pull driver chip 10. The third parasitic inductor 630 and the fourth parasitic inductor 640 are both the bonding parasitic inductance and the pin parasitic inductance of the driving end of the silicon carbide power device 210. The second parasitic capacitor 720 is the parasitic capacitance between the driving end and the second end of the silicon carbide power device 210. The first parasitic capacitor 710 is the parasitic capacitance (also known as Miller capacitance) between the driving end and the first end of the silicon carbide power device 210.

[0052] In one embodiment, the first terminal of the silicon carbide power device 210 is a drain terminal, and the second terminal of the silicon carbide power device 210 is a source terminal. The second parasitic capacitor 720 is a gate-source parasitic capacitor of the silicon carbide power device 210. The first parasitic capacitor 710 is a gate-drain parasitic capacitor of the silicon carbide power device 210.

[0053] Due to the presence of the first parasitic capacitor 710, the basic principle of C*V=I*t can be used to explain that a current will pass through the first parasitic capacitor 710 and reach the C node, which is the node at the driving end of the silicon carbide power device 210. Furthermore, after the current reaches the D node, it is divided into two branches. One branch current goes through the second parasitic capacitor 720, reaches the F node, and then flows through the fourth parasitic inductor 640. The other branch current goes through the third parasitic inductor 630 and reaches the E node, enters the first end of the pull-down module 30, passes through the pull-down module 30, reaches the second end of the pull-down module 30, and reaches the negative power supply VEE. Through the silicon carbide power device parallel drive oscillation suppression circuit 100 provided in the present application, the two branch currents divided by the D node will not flow through the first parasitic inductor 610 and the second parasitic inductor 620, will not affect the driving signal between the driving end of the pull-down module 30 and the second chip driving end of the dual-pull driving chip 10, and will not affect the driving signal between the driving end of the silicon carbide power device 210 and the first chip driving end of the dual-pull driving chip 10.

[0054] Furthermore, through the parallel drive oscillation suppression circuit 100 for silicon carbide power devices provided in the present application, the pull-down path of the Miller clamp does not pass through the first parasitic inductor 610 and the second parasitic inductor 620, eliminating the influence of the first parasitic inductor 610 and the second parasitic inductor 620 on the pull-down path, so that the position of the dual-pull driver chip 10 can be placed without distance restrictions. Thus, through the parallel drive oscillation suppression circuit 100 for silicon carbide power devices provided in the present application, the influence of the first parasitic inductor 610 and the second parasitic inductor 620 on the parallel drive of multiple silicon carbide power devices 210 is eliminated, and the driving end signal of the silicon carbide power device 210 and the driving end signal of the pull-down module 30 are not affected, which can ensure the accurate conduction or shutdown of the silicon carbide power device 210. Through the parallel drive oscillation suppression circuit 100 for silicon carbide power devices provided in the present application, the problem of repeated oscillation of the gate voltage existing in the conventional technology when the driver chip drives multiple parallel silicon carbide power devices is solved.

[0055] Furthermore, the silicon carbide power device parallel drive oscillation suppression circuit 100 provided in the present application can solve the problem of repeated oscillation of the gate voltage when the driver chip drives multiple parallel silicon carbide power devices in traditional technology through a dual-pull driver chip 10, without the need to add multiple driver chips, thereby reducing the cost and area of the overall circuit.

[0056] Furthermore, each SiC power device 210 is connected to a pull-down module 30, ensuring that the driver pull-down loop of each SiC power device 210 is independent. Therefore, the pull-down module 30 can be placed close to the SiC power device 210 and away from the dual-pull driver chip 10, thereby achieving a shorter pull-down wiring loop and reducing wiring parasitic inductance, thereby achieving a very good Miller clamping effect.

[0057] In one embodiment, the silicon carbide power device parallel drive oscillation suppression circuit 100 is applied to electronic integrated circuits capable of driving power devices, such as non-isolated gate driver chips and isolated gate driver chips.

[0058] See Figure 2 In one embodiment, the silicon carbide power device parallel drive oscillation suppression circuit 100 further includes a plurality of negative voltage stabilization modules 40. The first end of each negative voltage stabilization module 40 is connected to the second end of each pull-down module 30. The second end of each negative voltage stabilization module 40 is connected to the second end of each silicon carbide power device 210.

[0059] In this embodiment, multiple negative voltage stabilization modules 40 are connected in parallel between the second end of the pull-down module 30 and the second end of the silicon carbide power device 210. The second ends of the multiple pull-down modules 30 are connected to a negative power supply VEE. A voltage difference is generated between the second end of the pull-down module 30 and the second end of the silicon carbide power device 210. Current flows from node A through nodes B, C, D, E, and the pull-down module 30 before reaching the negative power supply VEE. This ensures that the voltage drop path at node C (also understood as the gate) corresponding to the driver end of the silicon carbide power device 210 bypasses the parasitic inductances of the first and second driver ends of the dual-pull driver chip 10, such as the first and second parasitic inductors 610 and 620. Consequently, the parasitic inductances of the first and second driver ends of the dual-pull driver chip 10 do not affect the gate voltage drop path, making the gate voltage at the driver end of the silicon carbide power device 210 more stable. This solves the problem of repeated gate voltage oscillation in conventional technologies and improves overall reliability.

[0060] The negative voltage stabilization module 40 stabilizes the voltage between the second terminal of the pull-down module 30 and the second terminal of the silicon carbide power device 210. Furthermore, when the pull-down module 30 and the silicon carbide power device 210 switch from the on state to the off state, the negative voltage stabilization module 40 stabilizes the signal quality of the negative voltage level, ensuring reliable shutdown of the pull-down module 30 and the silicon carbide power device 210, preventing false triggering and avoiding problems such as malfunction or device damage caused by unstable negative voltage. Thus, the negative voltage stabilization module 40 helps the pull-down module 30 resolve the problem of repeated gate voltage oscillation in traditional technologies, contributing to long-term stable circuit operation and reducing the occurrence of faults.

[0061] In one embodiment, the negative voltage stabilization module 40 includes at least one capacitor. A first end of the capacitor is connected to the second end of the pull-down module 30 and to the negative power supply VEE. A second end of the capacitor is connected to the second end of the silicon carbide power device 210. The capacitor parameters can be set based on the actual application scenario.

[0062] In one embodiment, the dual-pull driver chip 10 includes a first power pin VCC1, a second power pin VCC2, a first input pin IN+, a second input pin IN-, a negative power pin VEE2, a ground pin GND1, a first chip driver terminal OUT, and a second chip driver terminal Clamp_OUT. The first input pin IN+ and the second input pin IN- can be combined into a single input pin IN. The second power pin VCC2 is connected to the positive power supply VCC. The second power pin VCC2 is connected to the positive terminal of the first polarity capacitor 810. The negative terminal of the first polarity capacitor 810 is connected to the positive terminal of the second polarity capacitor 820. The negative terminal of the second polarity capacitor 820 is connected to the negative power supply VEE.

[0063] The first end of the negative voltage stabilization module 40 is connected to the second end of the pull-down module 30 and to the negative power supply VEE. The second end of the negative voltage stabilization module 40 is connected to the second end of the silicon carbide power device 210 and to the positive terminal of the second polarity capacitor 820. The first polarity capacitor 810 and the second polarity capacitor 820 provide high capacity and can store a large amount of electrical energy, which helps stabilize the voltage across the negative voltage stabilization module 40, promote long-term stable operation of the circuit, and reduce the risk of failure.

[0064] See Figure 3 In one embodiment, each pull-down module 30 includes a clamping power device 310. A driving terminal of the clamping power device 310 is connected to the second chip driving terminal of the dual-pull driver chip 10. A first terminal of the clamping power device 310 is connected to a driving terminal of the silicon carbide power device 210. A second terminal of the clamping power device 310 is connected to a negative power supply VEE.

[0065] In this embodiment, the clamped power device 310 can be a metal-oxide-semiconductor field-effect transistor (MOSFET), which can be either P-type or N-type. The driving terminal of the clamped power device 310 is the gate terminal, which is connected to the second chip driving terminal of the dual-pull driver chip 10. In one embodiment, the first terminal of the clamped power device 310 is the drain terminal, and the second terminal of the clamped power device 310 is the source terminal.

[0066] Through the clamping power device 310 in the pull-down module 30, the two branch currents divided by the D node are divided, and one branch current passes through the E node to reach the clamping power device 310. After the clamping power device 310 is turned on, the branch current is introduced into the negative power supply VEE. Furthermore, through the interlocking control between the dual-pull driver chip 10, the clamping power device 310, and the silicon carbide power device 210, the pull-down path of the Miller clamp does not pass through the first parasitic inductor 610 and the second parasitic inductor 620, eliminating the influence of the first parasitic inductor 610 and the second parasitic inductor 620 on the pull-down path. Thus, through the clamping power device 310 in the silicon carbide power device parallel drive oscillation suppression circuit 100 provided in the present application, the influence of the first parasitic inductor 610 and the second parasitic inductor 620 on the parallel drive of multiple silicon carbide power devices 210 is eliminated, solving the problem of repeated oscillation of the gate voltage when the driver chip drives multiple parallel silicon carbide power devices in the traditional technology.

[0067] In one embodiment, the anode terminal of the first diode 320 is connected to the second terminal of the clamped power device 310 . The cathode terminal of the first diode 320 is connected to the first terminal of the clamped power device 310 . The first diode 320 is a parasitic diode of the clamped power device 310 .

[0068] In one embodiment, the silicon carbide power device parallel drive oscillation suppression circuit 100 further includes a first driving module 510. A first end of the first driving module 510 is connected to the first chip driving end, and a second end of the first driving module 510 is connected to the driving ends of the plurality of silicon carbide power devices 210 and the first ends of the plurality of pull-down modules 30.

[0069] In this embodiment, the first driver module 510 is connected between the driving terminals of the multiple silicon carbide power devices 210 and the first chip driving terminal of the dual-pull driver chip 10. When the first chip driving terminal of the dual-pull driver chip 10 drives the multiple silicon carbide power devices 210, the switching speed of the multiple silicon carbide power devices 210 can be controlled to avoid excessively fast or slow switching, thereby protecting the components in the circuit. Furthermore, when the first chip driving terminal of the dual-pull driver chip 10 drives the multiple silicon carbide power devices 210, damping can be increased to suppress oscillations caused by gate voltage fluctuations, helping the auxiliary pull-down module 30 solve the problem of repeated gate voltage oscillations in traditional technologies.

[0070] The second end of the first driver module 510 is also connected to the first ends of the multiple pull-down modules 30, so that the first driver module 510 is connected between the first ends of the multiple pull-down modules 30 and the first chip driving end of the dual-pull driver chip 10. The first driver module 510 acts as a damper, consuming oscillation energy and suppressing the amplitude and frequency of the oscillation. This stabilizes the voltage at the connection point between the driving end of the silicon carbide power device 210 and the first end of the pull-down module 30, further assisting the pull-down module 30 in resolving the problem of repeated gate voltage oscillation in conventional technologies.

[0071] Therefore, the first driving module 510 can assist in solving the oscillation problem in the circuit where the silicon carbide power device 210 and the pull-down module 30 are located, thereby improving the overall reliability of the silicon carbide power device parallel driving oscillation suppression circuit 100.

[0072] In one embodiment, the SiC power device parallel drive oscillation suppression circuit 100 further includes a second driving module 520 . A first end of the second driving module 520 is connected to the second chip driving end, and a second end of the second driving module 520 is connected to the driving ends of the plurality of pull-down modules 30 .

[0073] In this embodiment, the second driver module 520 is connected between the driving terminals of the multiple pull-down modules 30 and the second chip driving terminal of the dual-pull driver chip 10. When the second chip driving terminal of the dual-pull driver chip 10 drives the multiple pull-down modules 30, the switching speed of the multiple pull-down modules 30 can be controlled to avoid excessively fast or slow switching, thereby protecting the components in the circuit.

[0074] Furthermore, in the process of the second chip driving end of the dual-pull driving chip 10 driving multiple pull-down modules 30, damping can be increased to suppress oscillations caused by gate voltage fluctuations, which is beneficial for assisting the pull-down module 30 to solve the problem of repeated gate voltage oscillations in traditional technologies.

[0075] Therefore, the second driving module 520 can assist in solving the oscillation problem in the circuit where the silicon carbide power device 210 and the pull-down module 30 are located, thereby improving the overall reliability of the silicon carbide power device parallel drive oscillation suppression circuit 100.

[0076] In one embodiment, the first driving module 510 includes at least one driving resistor. The second driving module 520 includes at least one driving resistor.

[0077] See Figure 4 In one embodiment, the dual-pull driver chip 10 , the plurality of silicon carbide power devices 210 , and the plurality of pull-down modules 30 form an upper bridge arm 101 or a lower bridge arm 102 of the circuit.

[0078] In this embodiment, the second end of each silicon carbide power device 210 in the upper bridge arm 101 of the circuit is connected to the second end of each negative voltage stabilization module 40, and is connected to the first end of each silicon carbide power device 210 in the lower bridge arm 102 of the circuit. The second end of each pull-down module 30 in the upper bridge arm 101 of the circuit is connected to the first end of each negative voltage stabilization module 40, and is connected to the first negative power supply VEEH.

[0079] The second end of each silicon carbide power device 210 in the circuit lower bridge arm 102 is connected to the second end of each negative voltage stabilization module 40 and is grounded. The second end of each pull-down module 30 in the circuit lower bridge arm 102 is connected to the first end of each negative voltage stabilization module 40 and is connected to the second negative power supply VEEL.

[0080] The circuit structure of the upper bridge arm 101 is the same as that of the lower bridge arm 102. The upper bridge arm 101 and the lower bridge arm 102 are connected to form a multi-phase full-bridge circuit.

[0081] See Figure 5 The present application provides a control method for a parallel drive oscillation suppression circuit for a silicon carbide power device, which is applied to the parallel drive oscillation suppression circuit 100 for a silicon carbide power device in any of the above embodiments. The control method includes:

[0082] Step S10: The dual-pull driver chip 10 generates a first drive signal according to the input signal to control the on and off of the plurality of silicon carbide power devices 210;

[0083] Step S20: The dual-pull driving chip 10 obtains an input signal and generates a second driving signal according to the input signal to control the on and off of the plurality of pull-down modules 30;

[0084] The first drive signal and the second drive signal are pulse width modulation signals, the falling edge of the second drive signal is located before the rising edge of the first drive signal, and the rising edge of the second drive signal is located after the falling edge of the first drive signal.

[0085] In this embodiment, the falling edge of the second driving signal is the second time t2, the rising edge of the first driving signal is the third time t3, the rising edge of the second driving signal is the fifth time t5, and the falling edge of the first driving signal is the fourth time t4.

[0086] The dual-pull driver chip 10 receives an input signal at a first time t1 and, at a second time t2, outputs a second drive signal Clamp_OUT in response to the input signal, thereby turning off the multiple pull-down modules 30. At a third time t3, the dual-pull driver chip 10 outputs a first drive signal OUT in response to the input signal, thereby turning on the multiple silicon carbide power devices 210. At a fourth time t4, the dual-pull driver chip 10 turns off the multiple silicon carbide power devices 210.

[0087] At the fifth time t5 , the dual-pull driving chip 10 outputs the second driving signal Clamp_OUT following the first driving signal OUT to control the plurality of pull-down modules 30 to be turned on.

[0088] The input signal is Figure 5 At the first moment t1, the second driving signal Clamp_OUT is a low-level signal, which controls the plurality of pull-down modules 30 to be turned off.

[0089] At the third time t3, the first drive signal OUT is a high level signal, controlling the multiple silicon carbide power devices 210 to be turned on. At the fourth time t4, the first drive signal OUT is a low level signal, controlling the multiple silicon carbide power devices 210 to be turned off.

[0090] At the fifth time t5, following the first drive signal OUT, the second drive signal Clamp_OUT is output. The second drive signal Clamp_OUT is a high level signal, which controls the multiple pull-down modules 30 to be turned on, realizing the auxiliary pull-down function, and pulling the driving end of the silicon carbide power device 210 down to the negative power supply VEE.

[0091] Through the control method of the parallel drive oscillation suppression circuit of the silicon carbide power device provided in the present application, interlocking control can be achieved between the first drive signal OUT and the second drive signal Clamp_OUT, thereby preventing the first drive signal OUT and the second drive signal Clamp_OUT from being high-level signals at the same time, thereby ensuring that the first drive signal OUT is applied to the silicon carbide power device 210 and ensuring that the silicon carbide power device 210 switches normally.

[0092] Through the control method of the parallel drive oscillation suppression circuit of the silicon carbide power device provided by the present application, the first drive signal OUT and the second drive signal Clamp_OUT share the same input signal IN, and are interlocked to prevent the two drive signal outputs from being turned on at the same time. Through the control method of the parallel drive oscillation suppression circuit of the silicon carbide power device provided by the present application, in combination with the circuit structure of the peripheral pull-down module 30, the V of the silicon carbide power device 210 is pulled down with the minimum Miller clamp pull-down current loop. GS , achieving a pull-down function. Thus, the control method for the parallel drive oscillation suppression circuit for silicon carbide power devices provided in this application, combined with the parallel drive oscillation suppression circuit 100 for silicon carbide power devices, enables the drive pull-down circuit of each silicon carbide power device 210 to be independent. The current does not flow through the parasitic inductance of the first chip drive terminal and the second chip drive terminal of the dual-pull driver chip 10, but directly reaches the negative power supply VEE. This eliminates the influence of the parasitic inductance of the Miller clamp circuit and solves the problem of repeated oscillation of the gate voltage of all parallel silicon carbide power devices 210.

[0093] In one embodiment, the time difference between the rising edge of the first driving signal and the rising edge of the input signal is the driving transmission delay, and the time difference between the falling edge of the second driving signal and the rising edge of the input signal is less than the driving transmission delay.

[0094] In this embodiment, the time difference between the rising edge of the first drive signal and the rising edge of the input signal is the drive transmission delay, which can also be understood as the time difference between the third time t3 and the first time t1 being the drive transmission delay. The time difference between the falling edge of the second drive signal and the rising edge of the input signal is less than the drive transmission delay, which can also be understood as the time difference between the second time t2 and the first time t1 being less than the drive transmission delay.

[0095] The first drive signal OUT completely follows the timing of the input signal IN, with a phase difference of one drive transmission delay, namely the time difference between the first moment t1 and the third moment t3. In one embodiment, the time difference between the second moment t2 and the first moment t1 can be 20ns. That is, 20ns after the input signal IN becomes a high-level signal, the second drive signal Clamp_OUT becomes a low-level signal, waiting for the first drive signal OUT to become a high-level signal. The time difference between the second moment t2 and the first moment t1 can be set according to the actual application scenario, ensuring that the time difference between the second moment t2 and the first moment t1 is less than the drive transmission delay.

[0096] By setting the time between the first moment t1, the second moment t2, and the third moment t3, an interlocking mechanism can be formed between the first drive signal OUT and the second drive signal Clamp_OUT, thereby avoiding conflicts and failures, preventing misoperation, and achieving precise signal control, thereby ensuring stable and reliable operation of the silicon carbide power device parallel drive oscillation suppression circuit 100.

[0097] In one embodiment, between the falling edge of the first drive signal and the rising edge of the second drive signal, which can also be understood as between the fourth time t4 and the fifth time t5, the first drive signal OUT is a low-level signal and the voltage of the first drive signal OUT is less than the turn-on voltage threshold of the silicon carbide power device. The time difference between the rising edge of the second drive signal and the falling edge of the first drive signal, which can also be understood as the time difference between the fifth time t5 and the fourth time t4, is determined based on the drive resistance between the dual-pull driver chip 10 and the silicon carbide power device 210 and the parasitic capacitance between the driving terminal and the second terminal of the silicon carbide power device 210.

[0098] In this embodiment, at the fourth moment t4, the first drive signal OUT becomes a low-level signal and is less than the on-voltage threshold of the silicon carbide power device. This ensures that the silicon carbide power device 210 is in the off state at this time, prevents false triggering, reduces power consumption, and protects the silicon carbide power device 210.

[0099] At the fifth time t5 , the second driving signal Clamp_OUT becomes a high-level signal, turning on the pull-down module 30 , achieving the effect of Miller clamping.

[0100] The driving resistance between the dual-pull driver chip 10 and the silicon carbide power device 210, and the parasitic capacitance between the driving terminal and the second terminal of the silicon carbide power device 210, form an RC discharge circuit. The time required for the RC discharge circuit is the time difference between the fifth moment t5 and the fourth moment t4. The time difference between the fifth moment t5 and the fourth moment t4 is determined by the driving resistance between the dual-pull driver chip 10 and the silicon carbide power device 210, and the parasitic capacitance between the driving terminal and the second terminal of the silicon carbide power device 210, and can be set to 50 ns. The time difference between the fifth moment t5 and the fourth moment t4 can be set according to the actual application scenario.

[0101] See Figure 6By using the control method of the parallel drive oscillation suppression circuit for silicon carbide power devices provided in the present application, when the upper bridge arm 101 and the lower bridge arm 102 of the circuit are controlled together, the IN1 input signal of the upper bridge arm 101 and the IN2 input signal of the lower bridge arm 102 are 180° apart, the OUT1 signal and the Clamp_OUT1 signal follow the IN1 input signal, and the OUT2 signal and the Clamp_OUT2 signal follow the IN2 input signal. By using the control method of the parallel drive oscillation suppression circuit for silicon carbide power devices provided in the present application, combined with the parallel drive oscillation suppression circuit for silicon carbide power devices 100, the drive pull-down circuit of each silicon carbide power device 210 is independent, and does not flow through the parasitic inductance of the first chip drive end and the second chip drive end of the dual-pull driver chip 10, but directly reaches the negative power supply VEE, eliminating the influence of the parasitic inductance of the Miller clamp circuit and solving the problem of repeated oscillation of the gate voltage of all parallel silicon carbide power devices 210.

[0102] See Figure 7 and Figure 8 , Figure 7 The multiple arrow paths at the white circle position are schematic diagrams of the Miller clamp pull-down path in traditional technology. Figure 8 The multiple arrow paths at the white circle position are schematic diagrams of the Miller clamp pull-down path of the parallel drive oscillation suppression circuit 100 of the silicon carbide power device provided by this application. Figure 7 and Figure 8 As can be clearly seen from the comparison diagram, the Miller clamp pull-down path of the parallel-driven oscillation suppression circuit 100 for silicon carbide power devices provided by the present application is shorter than that of conventional technology, effectively reducing the length of the Miller clamp pull-down loop by 80%. Therefore, it can also be seen that the parallel-driven oscillation suppression circuit 100 for silicon carbide power devices provided by the present application reduces the parasitic parameters of the Miller clamp pull-down loop, helping to solve the problem of repeated oscillation of the gate voltage of all parallel-driven silicon carbide power devices in conventional technology, and ensuring the stable and reliable operation of the parallel-driven oscillation suppression circuit 100 for silicon carbide power devices.

[0103] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0104] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0105] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0106] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0107] In the embodiments provided in this application, it should be understood that the disclosed devices / terminal equipment and methods can be implemented in other ways. For example, the device / terminal equipment embodiments described above are merely illustrative. For example, the division of the modules or units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0108] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0109] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0110] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A parallel drive oscillation suppression circuit for silicon carbide power devices, characterized in that: include: Double pull driver chip (10); A plurality of silicon carbide power devices (210), wherein first ends of the plurality of silicon carbide power devices (210) are connected, second ends of the plurality of silicon carbide power devices (210) are connected, and driving ends of the plurality of silicon carbide power devices (210) are connected to the first chip driving end of the dual-pull driving chip (10); A plurality of pull-down modules (30), wherein the driving ends of the plurality of pull-down modules (30) are connected to the second chip driving end of the dual-pull driving chip (10), the first end of each pull-down module (30) is connected to the driving end of each silicon carbide power device (210), and the second ends of the plurality of pull-down modules (30) are connected to a negative power supply; wherein the voltage at the first end of the silicon carbide power device (210) is greater than the voltage at the second end of the silicon carbide power device (210), and the voltage at the second end of the silicon carbide power device (210) is greater than the voltage at the second end of the pull-down module (30); a plurality of negative pressure stabilization modules (40), wherein a first end of each negative pressure stabilization module (40) is connected to a second end of each pull-down module (30) and the negative power supply, and a second end of each negative pressure stabilization module (40) is connected to a second end of each silicon carbide power device (210); A first polarity capacitor (810), wherein a positive terminal of the first polarity capacitor (810) is connected to a power supply terminal of the dual-pull driver chip (10); A second polarity capacitor (820), wherein the positive terminal of the second polarity capacitor (820) is connected to the negative terminal of the first polarity capacitor (810) and the second end of the negative voltage stabilization module (40), and the negative terminal of the second polarity capacitor (820) is connected to the negative power supply.

2. The silicon carbide power device parallel drive oscillation suppression circuit according to claim 1, characterized in that: Each of the pull-down modules (30) comprises: A clamping power device (310) having a driving end connected to the second chip driving end of the dual-pull driving chip (10), a first end of the clamping power device (310) connected to the driving end of the silicon carbide power device (210), and a second end of the clamping power device (310) connected to the negative power supply.

3. The silicon carbide power device parallel drive oscillation suppression circuit according to any one of claims 1 to 2, characterized in that: The circuit further comprises: A first driving module (510), wherein a first end of the first driving module (510) is connected to a driving end of the first chip, and a second end of the first driving module (510) is connected to driving ends of a plurality of the silicon carbide power devices (210) and first ends of a plurality of the pull-down modules (30).

4. The silicon carbide power device parallel drive oscillation suppression circuit according to any one of claims 1 to 2, characterized in that: The circuit further comprises: A second driving module (520), wherein a first end of the second driving module (520) is connected to the driving end of the second chip, and a second end of the second driving module (520) is connected to the driving ends of the plurality of pull-down modules (30).

5. The silicon carbide power device parallel drive oscillation suppression circuit according to any one of claims 1 to 2, characterized in that: The dual-pull driving chip (10), the plurality of silicon carbide power devices (210), and the plurality of pull-down modules (30) form an upper bridge arm (101) or a lower bridge arm (102) of a circuit.

6. A control method for a parallel drive oscillation suppression circuit for a silicon carbide power device, characterized in that: Applied to the parallel drive oscillation suppression circuit for a silicon carbide power device according to any one of claims 1 to 5, the control method comprises: A dual-pull driving chip (10) generates a first driving signal according to an input signal to control the on and off of a plurality of silicon carbide power devices (210); The dual-pull driving chip (10) acquires the input signal and generates a second driving signal according to the input signal to control the on and off of multiple pull-down modules (30); Wherein, the first drive signal and the second drive signal are pulse width modulation signals, the falling edge of the second drive signal is located before the rising edge of the first drive signal, and the rising edge of the second drive signal is located after the falling edge of the first drive signal; The time difference between the rising edge of the first driving signal and the rising edge of the input signal is the driving transmission delay, and the time difference between the falling edge of the second driving signal and the rising edge of the input signal is less than the driving transmission delay.

7. The control method for a parallel drive oscillation suppression circuit for a silicon carbide power device according to claim 6, wherein: Between the falling edge of the first driving signal and the rising edge of the second driving signal, the first driving signal is a low-level signal and a voltage of the first driving signal is less than a turn-on voltage threshold of the silicon carbide power device.

8. The control method for a parallel drive oscillation suppression circuit for a silicon carbide power device according to claim 6, wherein: The time difference between the rising edge of the second drive signal and the falling edge of the first drive signal is determined according to the drive resistance between the dual-pull drive chip (10) and the silicon carbide power device (210) and the parasitic capacitance between the drive end and the second end of the silicon carbide power device (210).

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