Circuit for improving BOOST input range and power supply chip

Abstract

The invention relates to the technical field of integrated circuits, and provides a circuit for improving the BOOST input range and a power chip, and the circuit for improving the BOOST input range comprises a basic BOOST circuit, a control signal generation circuit, an expansion circuit and a plurality of switches. The basic BOOST circuit is arranged to receive a low-voltage input voltage and provide a high-voltage output voltage; the control signal generation circuit is used for comparing the input voltage with the output voltage and outputting a first control signal and a second control signal which are opposite in level, and the first control signal and the second control signal are used for controlling the on and off of the corresponding switches; when the output voltage is greater than the input voltage, under the control of the first control signal and the second control signal, the basic BOOST circuit works normally, and the expansion circuit does not work; when the output voltage is smaller than the input voltage, under the control of the first control signal and the second control signal, one part of the basic BOOST circuit does not work, and the expansion circuit works.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and particularly to a circuit for improving the BOOST input range and a power supply chip. Background Art

[0002] The boost-type power conversion chip BOOST is widely used in electronic devices. It can convert low voltage into high voltage to meet the system's requirement for a higher power supply voltage, rather than being limited to a lower power supply voltage. A simple Boost circuit is as follows Figure 1 As shown, by controlling the conduction time of NFET and PFET, the charging and discharging of the inductor are controlled, and then the output voltage and the load current are controlled.

[0003] Figure 1 The circuit in [reference] controls the charging and discharging of the inductor by periodically controlling the conduction time of NFET and PFET, and then controls the output voltage and the load current. During one period, the conduction time of NFET is D*Tsw, the inductor is charged, the conduction time of PFET is (1 - D)*Tsw, the inductor is discharged, and power is supplied to OUT. Tsw is a charging and discharging cycle of the inductor, and D is called the duty cycle, which represents the proportion of the conduction time in one cycle. It is easy to obtain VOUT = VIN / (1 - D). Since D < 1, VOUT > VIN.

[0004] In most applications, VOUT > VIN is a normal working condition, but there are some applications that require VOUT < VIN under special circumstances or extreme conditions. For example, when the BOOST VOUT drives an LED string, the number of normal lights satisfies the condition of VOUT > VIN. However, if some of the LED beads are short-circuited, the remaining lights require VOUT < VIN, and at this time, the system requires the remaining lights to still work normally until the system detects the short circuit. Figure 1 This traditional BOOST cannot meet this application. Therefore, in some similar extreme applications, the above BOOST cannot work when VOUT < VIN.

[0005] Therefore, how to make the BOOST circuit have a larger input voltage range is a problem that needs to be solved currently. Summary of the Invention

[0006] The object of the present invention is to provide a circuit for improving the BOOST input range and a power supply chip, which can increase the input voltage range of the BOOST circuit and enable it to work stably and controllably when the input voltage is greater than the output voltage.

[0007] To achieve the above object, the present invention provides a circuit for improving the BOOST input range, including: Basic BOOST circuit, control signal generation circuit, expansion circuit and several switches; The basic BOOST circuit is configured to receive a low voltage input voltage and provide a high voltage output voltage; The control signal generating circuit is used to compare the input voltage and the output voltage, and output a first control signal and a second control signal of opposite levels, wherein the first control signal and the second control signal are used to control the closing and opening of the corresponding switch; When the output voltage is greater than the input voltage, under the control of the first control signal and the second control signal, the basic BOOST circuit works normally, and the expansion circuit does not work; When the output voltage is lower than the input voltage, under the control of the first control signal and the second control signal, a part of the basic BOOST circuit does not work, and the expansion circuit works.

[0008] In an optional solution, the switch includes a first switch, a second switch, a third switch and a fourth switch; the basic BOOST circuit includes an NMOS tube, a PMOS tube, an inductor and a driving module; the first switch and the third switch are controlled by the second control signal, and the second switch and the fourth switch are controlled by the first control signal; When the output voltage is lower than the input voltage, the Nbody of the PMOS tube is connected to the input voltage through the first switch; when the output voltage is higher than the input voltage, the Nbody of the PMOS tube is connected to the output voltage through the second switch; The drain of the PMOS tube is connected to one end of the inductor, the other end of the inductor is used to input the input voltage, and the source of the PMOS tube serves as the output end of the basic BOOST circuit; The first output end of the driving module is connected to the gate of the NMOS tube, and the second output end is connected to the gate of the PMOS tube through the fourth switch; the driving module is used to output a PWM signal; The gate of the PMOS tube is connected to the expansion circuit through the third switch; When the output voltage is lower than the input voltage, the expansion circuit controls the gate voltage of the PMOS tube and limits the current of the PMOS tube.

[0009] In an optional solution, the basic BOOST circuit further includes a first resistor, a second resistor, a filter capacitor, an error amplifier, a single-ended to differential circuit, a second comparator, and a DFF trigger; One end of the first resistor is connected to the output voltage, and the other end is connected to the second resistor, and the other end of the second resistor is grounded; the source of the PMOS tube is grounded through the filter capacitor; The positive input terminal of the error amplifier is connected to the reference voltage, the negative input terminal is connected to the connection between the first resistor and the second resistor, the output terminal of the error amplifier is connected to the input terminal of the single-ended to differential circuit, one output terminal of the single-ended to differential circuit is connected to the expansion circuit, and the other output terminal is connected to the negative input terminal of the second comparator, and the positive input terminal of the second comparator is used to input a ramp signal; The output end of the second comparator is connected to the R end of the DFF trigger, the S end of the DFF trigger is used to input a clock signal, and the output end of the DFF trigger is connected to the input end of the driving module.

[0010] In an optional solution, the basic BOOST circuit further includes a third resistor and a first capacitor, one end of the third resistor is connected to the negative input terminal of the second comparator, and the other end is grounded through the first capacitor.

[0011] In an optional solution, the control signal generating circuit includes a first comparator and a first NOT gate, the positive input terminal and the negative input terminal of the first comparator are respectively used to input the output voltage and the input voltage, and the output terminal of the first comparator is used to output the first control signal; The NOT gate is connected to the output end of the first comparator, and the output end of the NOT gate outputs the second control signal.

[0012] In an optional solution, the charging expansion circuit includes: a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a bias current source and a second NOT gate; The source of the fifth MOS tube is connected to the input voltage, and the drain is connected to the source of the fourth MOS tube; the gate and drain of the fourth MOS tube are short-circuited and connected to the drain of the third MOS tube, and connected to the gate of the PMOS tube through the third switch; The first control signal is input to the gate of the fifth MOS tube, and is input to the gate of the third MOS tube through the second NOT gate; the source of the third MOS tube is connected to the drain of the second MOS tube; the source of the second MOS tube is connected to the drain of the first MOS tube, and the gate of the second MOS tube is connected to the basic BOOST circuit; The gate of the first MOS transistor is connected to the output end of the bias current source, and the source of the first MOS transistor is grounded.

[0013] In an optional solution, the expansion circuit further includes a fourth resistor and a second capacitor, one end of the fourth resistor is connected to the gate of the second MOS tube, and the other end is grounded through the second capacitor.

[0014] In an optional solution, the expansion circuit further includes a fifth resistor, and the fifth resistor is connected between the input voltage and the source of the fifth MOS tube.

[0015] The present invention also provides a power chip, comprising the above-mentioned circuit for improving the BOOST input range.

[0016] The beneficial effects of the present invention are: The present invention can improve the input voltage range of the boost type BOOST circuit, and can enable the circuit to work stably and under control when the input voltage is greater than the output voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other objects, features and advantages of the present invention will become more apparent through a more detailed description of exemplary embodiments of the present invention in conjunction with the accompanying drawings, in which like reference numerals generally represent like components.

[0018] Figure 1 It is a schematic diagram of a simple BOOST circuit in the prior art.

[0019] Figure 2 FIG. 4 is a structural diagram of a circuit for improving the BOOST input range in one embodiment of the present invention.

[0020] Figure 3 FIG. 1 is a working waveform diagram of a circuit for improving the BOOST input range in an embodiment of the present invention. DETAILED DESCRIPTION

[0021] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description and drawings, the advantages and features of the present invention will become clearer. However, it should be noted that the concept of the technical solution of the present invention can be implemented in a variety of different forms and is not limited to the specific embodiments described herein. The drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0022] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0023] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0024] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0025] Example 1 Reference Figure 2 and Figure 3 , this embodiment provides a circuit for improving the BOOST input range, including: Basic BOOST circuit, control signal generation circuit, expansion circuit and several switches; The basic BOOST circuit is configured to receive a low voltage input voltage VIN and provide a high voltage output voltage VOUT; The control signal generating circuit is used to compare the input voltage VIN and the output voltage VOUT, and output a first control signal SMAX and a second control signal SMAXB with opposite levels, wherein the first control signal SMAX and the second control signal SMAX are used to control the closing and opening of the corresponding switch; When the output voltage VOUT is greater than the input voltage VIN, under the control of the first control signal SMAX and the second control signal SMAXB, the basic BOOST circuit works normally, and the expansion circuit does not work; When the output voltage VOUT is lower than the input voltage VIN, under the control of the first control signal SMAX and the second control signal SMAXB, a part of the basic BOOST circuit does not work, and the expansion circuit works.

[0026] In this embodiment, the switches include a first switch S1, a second switch S2, a third switch S3 and a fourth switch S4; the basic BOOST circuit includes an NMOS transistor MN, a PMOS transistor MP, a filter capacitor C OUT , an inductor and a driving module driver; the first switch S1 and the third switch S3 are controlled by the second control signal SMAXB, and the second switch S2 and the fourth switch S4 are controlled by the first control signal SMAX; when the output voltage VOUT is less than the input voltage VIN, the Nbody of the PMOS tube MP is connected to the input voltage VIN through the first switch S1, and when the output voltage VOUT is greater than the input voltage VIN, the Nbody of the PMOS tube MP is connected to the output voltage VOUT through the second switch S2; the drain of the PMOS tube MP is connected to one end of the inductor, and the other end of the inductor is used to input the input voltage VIN, and the source of the PMOS tube MP is connected to the filter capacitor C OUTThe first output terminal of the driver module driver is connected to the gate of the NMOS tube MN, and the second output terminal is connected to the gate of the PMOS tube MP through the fourth switch S4; the driver module driver is used to output a PWM signal; the gate of the PMOS tube MP is connected to the expansion circuit through the third switch S3; when the output voltage VOUT is less than the input voltage VIN, the expansion circuit controls the gate voltage of the PMOS tube MP and limits the current of the PMOS tube MP to prevent the output load from being too large.

[0027] In this embodiment, the basic BOOST circuit further includes a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, an error amplifier EA, a single-ended to differential circuit S2D, a second comparator CMP2, and a DFF trigger DFF; one end of the first resistor R1 is connected to the output voltage VOUT, and the other end is connected to the second resistor R2, and the other end of the second resistor R2 is grounded; the positive input end of the error amplifier EA is connected to the reference voltage VREF, and the negative input end is connected to the connection between the first resistor R1 and the second resistor R2, and the The output end of the error amplifier EA is connected to the input end of the single-ended to differential circuit S2D, one output end of the single-ended to differential circuit S2D is connected to the expansion circuit, and the other output end is connected to the negative input end of the second comparator CMP2, and the positive input end of the second comparator CMP2 is used to input the ramp signal ramp; the output end of the second comparator CMP2 is connected to the R end of the DFF trigger, the S end of the DFF trigger is used to input the clock signal clk, and the output end of the DFF trigger is connected to the input end of the driver module driver. One end of the third resistor R3 is connected to the negative input end of the second comparator CMP2, and the other end is grounded through the first capacitor C1.

[0028] In this embodiment, the control signal generating circuit includes a first comparator CMP1 and a first NOT gate, the positive input terminal and the negative input terminal of the first comparator CMP1 are respectively used to input the output voltage VOUT and the input voltage VIN, and the output terminal of the first comparator CMP1 is used to output the first control signal SMAX; the NOT gate is connected to the output terminal of the first comparator CMP1, and the output terminal of the NOT gate outputs the second control signal SMAXB.

[0029] The expansion circuit includes: a first MOS tube M1 (an NMOS tube), a second MOS tube M2 (an NMOS tube), a third MOS tube M3 (an NMOS tube), a fourth MOS tube M4 (a PMOS tube), a fifth MOS tube M5 (a PMOS tube), a fourth resistor R4, a fifth resistor R5, a second capacitor C2, a bias current source ibias and a second NOT gate; the source of the fifth MOS tube M5 is connected to the input voltage VIN, and the drain is connected to the source of the fourth MOS tube M4; the gate and drain of the fourth MOS tube M4 are short-circuited and connected to the drain of the third MOS tube M3, and through the first The three switches S3 are connected to the gate of the PMOS tube; the first control signal SMAX is input to the gate of the fifth MOS tube M5, and is input to the gate of the third MOS tube M3 through the second NOT gate; the source of the third MOS tube M3 is connected to the drain of the second MOS tube M2; the source of the second MOS tube M2 is connected to the drain of the first MOS tube M1, and the gate of the second MOS tube M2 is connected to an output end of the single-ended to differential circuit S2D; the gate of the first MOS tube M1 is connected to the output end of the bias current source ibias, and the source of the first MOS tube M1 is grounded. One end of the fourth resistor R4 is connected to the gate of the second MOS tube M2, and the other end is grounded through the second capacitor C2. The fifth resistor R5 is connected between the input voltage VIN and the source of the fifth MOS tube M5.

[0030] Reference Figure 2 , the circuit of this embodiment is divided into the following modules: Comp1, Comp2, Comp3, Comp4, Comp5, and basic components such as inductance, capacitance, and resistance.

[0031] Among them, Comp1 consists of a first comparator CMP1, a first NOT gate, a first switch S1, and a second switch S2, and is used to control the Nbody of the PMOS transistor. When VOUT > VIN, the Nbody is connected to VOUT; when VOUT < VIN, the Nbody is connected to VIN. Comp2 is a logic control circuit, consisting of a DFF flip-flop, a second comparator CMP2, a third resistor R3, and a first capacitor C1, and is used to control the switches of the NMOS and PMOS transistors when BOOST is working properly. Comp3 consists of an error amplifier EA and a single-ended to differential circuit S2D, and is used to amplify the voltage difference between the reference voltage VREF and the feedback voltage VFB and provide the input for the subsequent single-ended to differential S2D. Comp5 includes a driver module driver, a third switch S3, and a fourth switch S4. The two output terminals of the driver module driver respectively output PWM signals to the gates of the PMOS and NMOS transistors. Comp4 includes a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a fourth resistor R4, a fifth resistor R5, a second capacitor C2, a second NOT gate, and a bias current source ibias. When the circuit is working, the current on the PMOS transistor MP or the current isense on the fourth MOS transistor M4 is monitored. Comp4 is used to control the gate voltage PGATE of the PMOS transistor MP when VOUT < VIN. When the current Isense is greater than the current of the bias current source ibias, the gate voltage of the first MOS transistor M1 is pulled down, and the gate voltage of the PMOS transistor MP rises, realizing current limiting for the PMOS transistor MP. When the current Isense is less than the current of the bias current source ibias, the working state of the PMOS transistor MP is determined by the loop composed of Comp3, Comp4, the third switch s3, the PMOS transistor PM, the first resistor R1, and the second resistor R2.

[0032] When VOUT > VIN, the first control signal SMAX is high. Comp1 controls the second switch S2 to conduct, the first switch S1 to turn off, the fourth switch S4 to conduct, and the third switch S3 to turn off. At the same time, Comp4 does not work. The working states of the NMOS transistor and the PMOS transistor are the same as those in normal BOOST. Specifically, when the high level of the clock signal clk comes, the DFF flip-flop outputs high, and then through the driver module driver, the NMOS transistor MN is turned on and the PMOS transistor MP is turned off. At this time, the inductor current rises, and the ramp signal is the same as the inductor current signal. Following the rise of the inductor current, when the ramp signal rises to be the same as the other input of the second comparator CMP2, the second comparator CMP2 outputs a high level. This high level causes the DFF flip-flop to output low, and then through the driver module driver, the NMOS transistor MN is turned off and the PMOS transistor MP is turned on. When VOUT < VIN, the first control signal SMAX is low. Comp1 controls the first switch S1 to conduct, the second switch S2 to turn off, the third switch S3 to conduct, and the fourth switch S4 to turn off, making the driver module driver of Comp5 not work. The NMOS transistor is turned off, and the working state of the PMOS transistor is controlled by Comp3 and Comp4. At this time, the loop composed of Comp3, Comp4, the third switch S3, the PMOS transistor MP, the first resistor R1, and the second resistor R2 determines the output voltage VOUT, and the output current is limited by the current of the bias current source ibias and the current Isense.

[0033] The extended circuit of this embodiment can increase the input voltage range of the boost-type BOOST circuit and enable it to work stably and controllably when the input voltage is greater than the output voltage.

[0034] Embodiment 2 This embodiment provides a power chip, including the circuit for increasing the BOOST input range described in Embodiment 1.

[0035] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure fall within the protection scope of the claims.

Claims

1. A circuit for improving the BOOST input range, characterized in that: include: Basic BOOST circuit, control signal generation circuit, expansion circuit and several switches; The basic BOOST circuit is configured to receive a low voltage input voltage and provide a high voltage output voltage; The control signal generating circuit is used to compare the input voltage and the output voltage, and output a first control signal and a second control signal of opposite levels, wherein the first control signal and the second control signal are used to control the closing and opening of the corresponding switch; When the output voltage is greater than the input voltage, under the control of the first control signal and the second control signal, the basic BOOST circuit works normally, and the expansion circuit does not work; When the output voltage is lower than the input voltage, under the control of the first control signal and the second control signal, a part of the basic BOOST circuit does not work, and the expansion circuit works.

2. The circuit for improving the BOOST input range as claimed in claim 1, characterized in that: The switches include a first switch, a second switch, a third switch and a fourth switch; the basic BOOST circuit includes an NMOS tube, a PMOS tube, an inductor and a driving module; the first switch and the third switch are controlled by the second control signal, and the second switch and the fourth switch are controlled by the first control signal; When the output voltage is lower than the input voltage, the Nbody of the PMOS tube is connected to the input voltage through the first switch; when the output voltage is higher than the input voltage, the Nbody of the PMOS tube is connected to the output voltage through the second switch; The drain of the PMOS tube is connected to one end of the inductor, the other end of the inductor is used to input the input voltage, and the source of the PMOS tube serves as the output end of the basic BOOST circuit; The first output end of the driving module is connected to the gate of the NMOS tube, and the second output end is connected to the gate of the PMOS tube through the fourth switch; the driving module is used to output a PWM signal; The gate of the PMOS tube is connected to the expansion circuit through the third switch; When the output voltage is lower than the input voltage, the expansion circuit controls the gate voltage of the PMOS tube and limits the current of the PMOS tube.

3. The circuit for improving BOOST input range as claimed in claim 2, characterized in that: The basic BOOST circuit also includes a first resistor, a second resistor, a filter capacitor, an error amplifier, a single-ended to differential circuit, a second comparator, and a DFF trigger; One end of the first resistor is connected to the output voltage, and the other end is connected to the second resistor, and the other end of the second resistor is grounded; the source of the PMOS tube is grounded through the filter capacitor; The positive input terminal of the error amplifier is connected to the reference voltage, the negative input terminal is connected to the connection between the first resistor and the second resistor, the output terminal of the error amplifier is connected to the input terminal of the single-ended to differential circuit, one output terminal of the single-ended to differential circuit is connected to the expansion circuit, and the other output terminal is connected to the negative input terminal of the second comparator, and the positive input terminal of the second comparator is used to input a ramp signal; The output end of the second comparator is connected to the R end of the DFF trigger, the S end of the DFF trigger is used to input a clock signal, and the output end of the DFF trigger is connected to the input end of the driving module.

4. The circuit for improving BOOST input range as claimed in claim 3, characterized in that: The basic BOOST circuit further includes a third resistor and a first capacitor, one end of the third resistor is connected to the negative input end of the second comparator, and the other end of the third resistor is grounded through the first capacitor.

5. The circuit for improving BOOST input range as claimed in claim 2, characterized in that: The control signal generating circuit comprises a first comparator and a first NOT gate, wherein the positive input terminal and the negative input terminal of the first comparator are respectively used to input the output voltage and the input voltage, and the output terminal of the first comparator is used to output a first control signal; The NOT gate is connected to the output end of the first comparator, and the output end of the NOT gate outputs the second control signal.

6. The circuit for improving BOOST input range as claimed in claim 2, characterized in that: The charging expansion circuit comprises: a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a bias current source and a second NOT gate; The source of the fifth MOS tube is connected to the input voltage, and the drain is connected to the source of the fourth MOS tube; the gate and drain of the fourth MOS tube are short-circuited and connected to the drain of the third MOS tube, and connected to the gate of the PMOS tube through the third switch; The first control signal is input to the gate of the fifth MOS tube, and is input to the gate of the third MOS tube through the second NOT gate; the source of the third MOS tube is connected to the drain of the second MOS tube; the source of the second MOS tube is connected to the drain of the first MOS tube, and the gate of the second MOS tube is connected to the basic BOOST circuit; The gate of the first MOS transistor is connected to the output end of the bias current source, and the source of the first MOS transistor is grounded.

7. The circuit for improving BOOST input range as claimed in claim 6, characterized in that: The expansion circuit further includes a fourth resistor and a second capacitor, one end of the fourth resistor is connected to the gate of the second MOS tube, and the other end is grounded through the second capacitor.

8. The circuit for improving BOOST input range as claimed in claim 6, characterized in that: The expansion circuit further includes a fifth resistor, and the fifth resistor is connected between the input voltage and the source of the fifth MOS tube.

9. A power chip, characterized in that: A circuit for improving the BOOST input range comprising any one of claims 1-8.

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