Power supply synchronous step-down circuit

Abstract

The invention discloses a power supply synchronous step-down circuit, which relates to the technical field of computers, and is characterized in that the first end of a first group of capacitors is connected to the first end of a first switch, the second end of the first group of capacitors is connected to the second end of a second switch, the second end of the first switch is connected with the first end of the second switch, and the first group of capacitors comprises N capacitors connected in parallel, n is an integer greater than 0; the first end of the absorption loop is connected between the first switch and the second switch, the second end of the absorption loop is connected to the second end of the second switch, the second group of capacitors comprises M capacitors connected in parallel, and M is an integer greater than 0. According to the invention, the problem that noise generated by rapid change of MOS switching current in the power supply synchronous step-down circuit affects signals around the power supply module is solved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a power supply synchronous buck circuit. Background Art

[0002] In the context of digital transformation, the requirements for power supply are getting higher and higher. For example, as massive data continues to grow, the power density and power supply reliability of the power modules of unified storage systems are becoming higher and higher.

[0003] In the synchronous buck circuit of the board-level power supply, the rise and fall time of the metal oxide semiconductor field effect transistor (MOS switch) is in the nanosecond level, and the current changes sharply when the MOS switches. The sharp change in current causes the MOS switch to ring. This ringing brings various effects as high-frequency switching noise, and the high-frequency switching noise is transmitted to the power supply end as common-mode noise. Common-mode noise affects the signals around the power module and reduces the reliability of power supply.

[0004] There is currently no effective solution to the above problems. Summary of the invention

[0005] The present application provides a power synchronous buck circuit to at least solve the problem in the related art that the noise generated by the sharp change of MOS switch current in the power synchronous buck circuit affects the signals around the power module.

[0006] According to one embodiment of the present application, a power supply synchronous buck circuit is provided, comprising: a first end of a first group of capacitors is connected to a first end of a first switch, a second end of the first group of capacitors is connected to a second end of a second switch, the second end of the first switch is connected to a first end of the second switch, the first group of capacitors comprises N capacitors connected in parallel, N is an integer greater than 0; a first end of an absorption loop is connected between the first switch and the second switch, and a second end of the absorption loop is connected to a second end of the second switch.

[0007] In an exemplary embodiment, the absorption circuit includes an absorption resistor and an absorption capacitor; the first end of the absorption resistor is the first end of the absorption circuit, and the second end of the absorption capacitor is the second end of the absorption circuit; the second end of the absorption resistor is connected to the first end of the absorption capacitor.

[0008] In an exemplary embodiment, the first end of the absorption loop is also connected to the first end of the filter inductor, and the second end of the absorption loop is also connected to a second group of capacitors, wherein the second group of capacitors includes M capacitors connected in parallel, and M is an integer greater than 0.

[0009] In an exemplary embodiment, the second end of the absorption loop is connected to the second end of the second group of capacitors; the first end of the second group of capacitors is connected to the second end of the filter inductor; and the first end of the second group of capacitors is also connected to the output end.

[0010] In an exemplary embodiment, the first switch and the second switch are metal oxide semiconductor field effect transistors (N-MOSFETs), the first end of the first switch is a drain, the second end of the first switch is a source, the first end of the second switch is a drain, and the second end of the second switch is a source.

[0011] In an exemplary embodiment, a first end of the magnetic bead is connected to the input end; and a second end of the magnetic bead is connected to a first end of the first group of capacitors.

[0012] In an exemplary embodiment, the selection of the magnetic beads satisfies the following formula:

[0013]

[0014] Where z is the equivalent impedance of the magnetic bead, is the equivalent resistance of the bead, is the switching frequency of the first switch and the second switch.

[0015] In an exemplary embodiment, the selection of the first group of parallel capacitors satisfies the following formula:

[0016]

[0017] in, is the total capacitance of the first set of parallel capacitors, is the maximum current, is the switching duty cycle of the first switch and the second switch, is the switching frequency of the first switch and the second switch, is the peak-to-peak value of the input ripple voltage.

[0018] In an exemplary embodiment, the selection of the absorption resistor satisfies the following formula:

[0019]

[0020] in, is the resistance value of the absorption resistor, is the output voltage, is the maximum current, is the switching duty cycle of the first switch and the second switch, is the switching frequency of the first switch and the second switch.

[0021] In an exemplary embodiment, the selection of the absorption capacitor satisfies the following formula:

[0022]

[0023] in, The capacitance value of the absorption capacitor, is the switching duty cycle of the first switch and the second switch, is the switching period of the first switch and the second switch, is the output voltage, is the input voltage, is the maximum current.

[0024] In an exemplary embodiment, the first group of capacitors includes a first capacitor and a second capacitor, the first capacitor and the second capacitor are bypass capacitors, the first capacitor is a nanofarad-level capacitor, and the second capacitor is a microfarad-level capacitor.

[0025] In an exemplary embodiment, the first switch and the second switch are arranged on a target chip, and the N capacitors in the first group of capacitors are located in the same target layer as the layout and wiring of the target chip.

[0026] In an exemplary embodiment, the layout and wiring of the first capacitor and the second capacitor are respectively located on both sides of the target chip and are closest to the target chip, and other capacitors in the first group of capacitors except the first capacitor and the second capacitor are arranged on both sides of the target chip.

[0027] In an exemplary embodiment, the distance between the key signal via on the target layer and the input terminal is greater than or equal to a first distance threshold, and the input terminal is disposed on the target chip.

[0028] In an exemplary embodiment, a power ground via is provided between the input terminal and the key signal via.

[0029] Through the present application, the first end of the first group of capacitors included in the power synchronous buck circuit is connected to the first end of the first switch, the second end of the first group of capacitors is connected to the second end of the second switch, the second end of the first switch is connected to the first end of the second switch, the first group of capacitors includes N parallel capacitors, N is an integer greater than 0; the first end of the absorption loop is connected between the first switch and the second switch, the second end of the absorption loop is connected to the second end of the second switch, and the second group of capacitors includes M parallel capacitors, M is an integer greater than 0. Since the noise generated by the first switch and the second switch can be absorbed by the absorption loop, the problem of the noise generated by the sharp change of the MOS switch current in the power synchronous buck circuit in the related art affecting the signals around the power module can be solved, so as to achieve the effect of reducing the noise generated by the sharp change of the MOS switch current in the power synchronous buck circuit affecting the signals around the power module. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0031] Figure 1 A schematic diagram of a power synchronous buck circuit provided in an embodiment of the present application;

[0032] Figure 2 The figure is a schematic diagram of the noise layout and wiring of the synchronous buck circuit of the server power supply according to the embodiment of the present application. DETAILED DESCRIPTION

[0033] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0034] It should be noted that, in the description of this application, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in this application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0035] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0036] According to one embodiment of the present application, a power supply synchronous buck circuit is provided, comprising: a first end of a first group of capacitors is connected to a first end of a first switch, a second end of the first group of capacitors is connected to a second end of a second switch, the second end of the first switch is connected to a first end of the second switch, the first group of capacitors comprises N capacitors connected in parallel, N is an integer greater than 0; a first end of an absorption loop is connected between the first switch and the second switch, and a second end of the absorption loop is connected to a second end of the second switch.

[0037] by Figure 1 Taking the power synchronous buck circuit shown in the figure as an example, the first group of capacitors includes C1, C2, C3, C4, C5, and C6 connected in parallel as shown in the figure. Figure 1 The C1, C2, C3, C4, C5, and C6 connected in parallel are only for illustrating the present application, and the specific number N of capacitors connected in parallel can be determined according to actual conditions.

[0038] Figure 1 The first switch and the second switch are metal oxide semiconductor field effect transistors (N-MOSFETs), the first end of the first switch is a drain, the second end of the first switch is a source, the first end of the second switch is a drain, and the second end of the second switch is a source.

[0039] like Figure 1 As shown in the figure, the first end (1) of the first group of capacitors is connected to the first end (drain) of the first switch Q1, the second end (2) of the first group of capacitors is connected to the second end (source) of the second switch Q2, and the second end (source) of the first switch Q1 is connected to the first end (drain) of the second switch.

[0040] In an exemplary embodiment, the absorption circuit includes an absorption resistor and an absorption capacitor; the first end of the absorption resistor is the first end of the absorption circuit, and the second end of the absorption capacitor is the second end of the absorption circuit; the second end of the absorption resistor is connected to the first end of the absorption capacitor.

[0041] like Figure 1 As shown in the figure, the absorption circuit includes an absorption resistor R3 and an absorption capacitor C7, the absorption resistor R3 and the first end of the absorption circuit are (3) in the figure, the absorption capacitor C7 and the second end of the absorption circuit are (4) in the figure, and the second end (4) of the absorption resistor R3 is connected to the first end (5) of the absorption capacitor C7.

[0042] In an exemplary embodiment, the first end of the absorption loop is also connected to the first end of the filter inductor, and the second end of the absorption loop is also connected to a second group of capacitors, wherein the second group of capacitors includes M capacitors connected in parallel, and M is an integer greater than 0.

[0043] like Figure 1 The filter inductor shown in the figure is L1, the first end (3) of the absorption resistor R3 is connected to the first end (7) of the filter inductor L1, and the second end (8) of the filter inductor L1 is connected to the second group of capacitors ( Figure 1 In the figure, the number of the second group of capacitors C10, C11, C12, C13 is only for illustrating the present application, and the number M of capacitors connected in parallel in the second group of capacitors can be determined according to actual conditions.

[0044] In an exemplary embodiment, the second end of the absorption loop is connected to the second end of the second group of capacitors; the first end of the second group of capacitors is connected to the second end of the filter inductor; and the first end of the second group of capacitors is also connected to the output end.

[0045] like Figure 1 As shown in the figure, the second end (6) of the absorption loop is connected to the second end (9) of the second group of capacitors, the first end (10) of the second group of capacitors is connected to the second end (8) of the filter inductor, and the first end (10) of the second group of capacitors is also connected to the output end VOUT.

[0046] In an exemplary embodiment, a first end of the magnetic bead is connected to the input end; and a second end of the magnetic bead is connected to a first end of the first group of capacitors.

[0047] like Figure 1 The magnetic bead shown in the figure is L1, the first end (11) of the magnetic bead L1 is connected to the input end VIN, and the second end of the magnetic bead is connected to the first end (1) of the first group of capacitors.

[0048] In an exemplary embodiment, a magnetic bead is connected in series at the VIN input terminal to prevent noise leakage from affecting surrounding circuits or other source modules. The selection of the magnetic bead satisfies the following formula:

[0049]

[0050] Where z is the equivalent impedance of the magnetic bead, is the equivalent resistance of the bead, is the switching frequency of the first switch and the second switch.

[0051] Select input capacitors C1, C2, C3, C4, C5, and C6 based on the input ripple voltage at the maximum input current.

[0052] In an exemplary embodiment, the selection of the first group of parallel capacitors satisfies the following formula:

[0053]

[0054] in, is the total capacitance of the first set of parallel capacitors, is the maximum current, is the switching duty cycle of the first switch and the second switch, is the switching frequency of the first switch and the second switch, is the peak-to-peak value of the input ripple voltage.

[0055] A common-mode noise RC absorption circuit is designed before the output inductor. The RC absorption circuit will affect the conversion efficiency of the power module, so it is necessary to reasonably design and select the resistors and capacitors.

[0056] In an exemplary embodiment, the selection of the absorption resistor satisfies the following formula:

[0057]

[0058] in, is the resistance value of the absorption resistor, is the output voltage, is the maximum current, is the switching duty cycle of the first switch and the second switch, is the switching frequency of the first switch and the second switch.

[0059] In an exemplary embodiment, the selection of the absorption capacitor satisfies the following formula:

[0060]

[0061] in, The capacitance value of the absorption capacitor, is the switching duty cycle of the first switch and the second switch, is the switching period of the first switch and the second switch, is the output voltage, is the input voltage, is the maximum current.

[0062] In an exemplary embodiment, the first group of capacitors includes a first capacitor and a second capacitor, the first capacitor and the second capacitor are bypass capacitors, the first capacitor is a nanofarad-level capacitor, and the second capacitor is a microfarad-level capacitor.

[0063] like Figure 1The input terminal VIN of the power synchronous buck circuit shown in the figure uses multiple low ESL capacitors in parallel. C1, C2, C3, C4, C5, and C6 are input capacitors to maintain the stability of the VIN voltage when the MOS is quickly turned off. Multiple low ESL capacitors are connected in parallel to reduce the parasitic ESL of the input capacitor. The first capacitor C1 and the second capacitor C2 are used as input bypass capacitors. C1 is a nF capacitor and C2 is a 0.1uF capacitor, which can filter out the common mode interference of VIN in different frequency bands.

[0064] In the above embodiment, multiple low ESL capacitors are selected in parallel at the input end, electromagnetic beads are connected in series, and a common-mode noise absorption circuit is designed before the output inductor to prevent noise leakage from affecting surrounding circuits.

[0065] The present application optimizes the design of a printed circuit board (PCB) of a power synchronous buck circuit. In an exemplary embodiment, the first switch and the second switch are arranged on a target chip, and the N capacitors in the first group of capacitors are located on the same target layer as the layout and wiring of the target chip.

[0066] like Figure 2 As shown, the first switch and the second switch are Figure 2 The first set of capacitors is Figure 2 The input capacitors C1, C2, C3, C4, C5, and C6 are placed reasonably, and the input bypass capacitors C1 (first capacitor) and C2 (second capacitor) are close to the chip and placed on the same layer as the chip.

[0067] In an exemplary embodiment, the layout and wiring of the first capacitor and the second capacitor are respectively located on both sides of the target chip and are closest to the target chip, and other capacitors in the first group of capacitors except the first capacitor and the second capacitor are arranged on both sides of the target chip.

[0068] like Figure 2 As shown, the first capacitor C1 and the second capacitor C2 are arranged on both sides of the chip, C3 and C5 are arranged on the side of C1 away from the chip, and C4 and C6 are arranged on the side of C2 away from the chip.

[0069] In an exemplary embodiment, the distance between the key signal via on the target layer and the input terminal is greater than or equal to a first distance threshold, and the input terminal is disposed on the target chip.

[0070] The maximum distance from the key signal via to VIN is not less than XX mil (the first distance threshold), and the ideal distance from the surrounding key signal vias to VIN is not less than XX mil.

[0071] In an exemplary embodiment, a power ground via is provided between the input terminal and the key signal via.

[0072] To reduce the impact of power supply noise on key signals in high power density scenarios, a power ground via (PGND via) is designed between the key signal via and VIN, and the PGND via is close to VIN; the key signal receiving end is filtered by capacitors, and the filter capacitor is close to the receiving end. This further reduces the impact of VIN common mode noise on key signals and improves the stability of the storage system.

[0073] The bootstrap capacitor CBoot of BOOT is on the same side of the chip, close to BOOT, far away from SW and inductor, and the path is as short as possible; SS capacitor Css is placed close to the chip pin; FB pin resistors R1 and R2 are required to be close to the chip and far away from SW and inductor. The point of feedback signal FB is required to be near the output capacitor pads C12 and C13. The FB line is far away from the SW point and does not cross under the inductor. It is as short as possible. The feedback pull-down resistor R2 is connected to AGND, and AGND / PGND is grounded at a single point. Reduce the power switch noise, reduce the impact of the switching noise on the power module itself, and improve the reliability of the power supply module.

[0074] In the above embodiment, the layout of the synchronous buck circuit is optimized by optimizing the PCB wiring to reduce the switching noise. The distance from the surrounding key signals to the input terminal VIN and the capacitor filter circuit at the key signal receiving end are standardized; the distance from the key signal via to VIN, and the GND via is designed between the key signal via and VIN, and the GND via is close to VIN. Reduce the impact of power supply noise on key signals, improve storage performance and power supply reliability.

[0075] This application optimizes the board-level power supply circuit by optimizing the layout and wiring of the power module itself and key signals around the power module, reducing the switching noise of the board-level power module, suppressing the common-mode noise on the board-level power supply VIN, and eliminating the impact of the common-mode noise of the board-level power supply VIN on surrounding key signals, so as to meet the high-power density power supply requirements of the storage system, and has the following advantages over the conventional storage system power supply system: In terms of performance, it has a high-power density and low-noise power supply module; in terms of stability, it has low switching noise and low common-mode noise, eliminating the impact of power supply noise on the power module itself and peripheral key signals, and preventing power supply noise from causing abnormal power-off of the device. In terms of safety, the power supply noise has no impact on the surrounding key signals, and the storage system downtime caused by noise is eliminated. It has low cost, high power density, stable and reliable performance, and saves manpower and material costs. It is compatible with all server models.

[0076] The present application optimizes the synchronous buck circuit of the board-level power supply, connects multiple low-ESL input capacitors in parallel to reduce the power switch noise, designs input bypass capacitors with different capacitance values ​​to absorb the common-mode interference of VIN in different frequency bands; designs an RC absorption circuit before the output filter inductor to absorb the common-mode noise of VIN; connects a magnetic bead in series at the VIN input end to control the common-mode noise of VIN within a certain area, thereby reducing the impact of the common-mode noise of VIN on other power modules and surrounding key signals. The calculation formula of the input filter inductor, input capacitor, and output filter inductor RC absorption circuit of the board-level power supply synchronous buck circuit can achieve the purpose of reducing the power switch noise and suppressing the common-mode noise of VIN at the expense of limited conversion efficiency. Shorten the high current path, select capacitors, MOS, and inductors with low parasitic parameters to reduce the power switch noise; reasonably layout the input capacitors and output filter capacitors to absorb the common-mode noise of VIN; route the power sampling signal and control signal in partitions, away from interference sources. Eliminate the impact of power supply noise on itself. Standardize the maximum distance from the surrounding key signal vias to VIN, and provide an optimization plan to add GND vias between the key signal vias and VIN, with the GND vias close to VIN; use capacitor filtering at the key signal receiving end, and place the filter capacitor close to the receiving end to completely eliminate the impact of power module noise on key signals.

[0077] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0078] The above is a detailed introduction to a power synchronous buck circuit provided by the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A power synchronous buck circuit, characterized in that: include: A first end of a first group of capacitors is connected to a first end of a first switch, a second end of the first group of capacitors is connected to a second end of a second switch, the second end of the first switch is connected to a first end of the second switch, and the first group of capacitors includes N capacitors connected in parallel, where N is an integer greater than 0; The first end of the absorption loop is connected between the first switch and the second switch, and the second end of the absorption loop is connected to the second end of the second switch.

2. The power synchronous buck circuit according to claim 1, characterized in that: Also includes: The absorption circuit includes an absorption resistor and an absorption capacitor; The first end of the absorption resistor is the first end of the absorption loop, and the second end of the absorption capacitor is the second end of the absorption loop; The second end of the absorption resistor is connected to the first end of the absorption capacitor.

3. The power synchronous buck circuit according to claim 1 or 2, characterized in that: Also includes: The first end of the absorption loop is also connected to the first end of the filter inductor, and the second end of the absorption loop is also connected to a second group of capacitors, wherein the second group of capacitors includes M capacitors connected in parallel, and M is an integer greater than 0.

4. The power synchronous buck circuit according to claim 3, characterized in that: Also includes: The second end of the absorption loop is connected to the second end of the second group of capacitors; The first end of the second group of capacitors is connected to the second end of the filter inductor; The first end of the second group of capacitors is also connected to the output end.

5. The power synchronous buck circuit according to claim 1, characterized in that: Also includes: The first switch and the second switch are metal oxide semiconductor field effect transistors (N-MOSFETs), the first end of the first switch is a drain, the second end of the first switch is a source, the first end of the second switch is a drain, and the second end of the second switch is a source.

6. The power synchronous buck circuit according to claim 1, characterized in that: Also includes: The first end of the magnetic bead is connected to the input end; The second end of the magnetic bead is connected to the first end of the first group of capacitors.

7. The power synchronous buck circuit according to claim 6, characterized in that: Also includes: The selection of the magnetic beads satisfies the following formula: ； Where z is the equivalent impedance of the magnetic bead, is the equivalent resistance of the bead, is the switching frequency of the first switch and the second switch.

8. The power synchronous buck circuit according to claim 1, characterized in that: Also includes: The selection of the first group of parallel capacitors satisfies the following formula: ； in, is the total capacitance of the first set of parallel capacitors, is the maximum current, is the switching duty cycle of the first switch and the second switch, is the switching frequency of the first switch and the second switch, is the peak-to-peak value of the input ripple voltage.

9. The power synchronous buck circuit according to claim 2, characterized in that: Also includes: The selection of the absorption resistor satisfies the following formula: ； in, is the resistance value of the absorption resistor, is the output voltage, is the maximum current, is the switching duty cycle of the first switch and the second switch, is the switching frequency of the first switch and the second switch.

10. The power synchronous buck circuit according to claim 2, characterized in that: Also includes: The selection of the absorption capacitor satisfies the following formula: ； in, The capacitance value of the absorption capacitor, is the switching duty cycle of the first switch and the second switch, is the switching period of the first switch and the second switch, is the output voltage, is the input voltage, is the maximum current.

11. The power synchronous buck circuit according to claim 1, characterized in that: Also includes: The first group of capacitors includes a first capacitor and a second capacitor, the first capacitor and the second capacitor are bypass capacitors, the first capacitor is a nanofarad-level capacitor, and the second capacitor is a microfarad-level capacitor.

12. The power synchronous buck circuit according to claim 11, characterized in that: Also includes: The first switch and the second switch are arranged on a target chip, and the N capacitors in the first group of capacitors are located in the same target layer as the layout and wiring of the target chip.

13. The power synchronous buck circuit according to claim 12, characterized in that: The layout and wiring of the first capacitor and the second capacitor are respectively located on both sides of the target chip and are closest to the target chip. The other capacitors in the first group of capacitors except the first capacitor and the second capacitor are arranged on both sides of the target chip.

14. The power synchronous buck circuit according to claim 12, characterized in that: Also includes: The distance between the key signal via on the target layer and the input terminal is greater than or equal to a first distance threshold, and the input terminal is arranged on the target chip.

15. The power synchronous buck circuit according to claim 14, characterized in that: Also includes: A power grounding via is provided between the input terminal and the key signal via.

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