Motor engine control circuit and method, motor control system and vehicle

Abstract

The invention provides a motor engine control circuit and method, a motor control system and a vehicle, and the motor engine control circuit comprises at least two calculation modules which are used for calculating the same signal to be processed at the same time and outputting a calculation result; the calculation result checking module is used for carrying out consistency comparison on all calculation results; the at least two state sequence controllers simultaneously generate an operation state signal and a register sequence selection signal; the state checking and selecting module is used for respectively carrying out consistency comparison on each operation state signal and each register sequence selecting signal; the check code storage module is used for carrying out check coding on the calculation result and storing the calculation result into a corresponding register based on an operation state signal and the register sequence selection signal; and the verification decoding module is used for selecting the data in the corresponding register based on the operation state signal and the register sequence selection signal, and decoding and verifying the selected data. The area and the cost of the circuit are effectively reduced, the instruction execution and operation efficiency is improved, and the circuit is safer, more stable and more reliable.

Description

Technical Field

[0001] The present invention relates to the field of motor control, and in particular to a motor engine control circuit, method, motor control system and vehicle. Background Art

[0002] In the field of automotive control applications, the motor control system is a key core system for new energy vehicles. It controls the motor output drive torque and brake torque, which not only determines the power performance of the vehicle, but is also closely related to the safe operation of the vehicle. How to prevent system risks caused by system failure and random hardware failure has become an important issue that needs to be solved at present; how to ensure system safety and reliability needs to be taken as a key design indicator in the automotive-grade motor drive design stage.

[0003] Traditional functional safety methods use multi-drive backup to control the computing storage unit, integrating multiple computing control units to operate simultaneously, one of which serves as the main control unit, and the other backup algorithm storage control units serve the purpose of real-time comparison and monitoring. Figure 1 As shown, the first operation control unit 1a, the second operation control unit 1b and the third operation control unit 1c are three symmetrical modules (with the same structure and function). The input data is sent to the first operation control unit 1a, the second operation control unit 1b and the third operation control unit 1c at the same time, and the consistency of their output results is compared. The comparison results are selected by majority decision, that is, when two of the three operation control units have equal operation results and the other is not equal, the majority decision principle is followed to select two equal operation results; if the operation results of the three operation control units are different, the system fault error is reported; this can capture and eliminate random errors caused by changes in the environment, temperature, etc. to a certain extent, and improve the stability of the system. Considering the circuit area and cost issues, the functional safety method in most application scenarios chooses to integrate two symmetrical control modules, and judges the stability of the control system by comparing the consistency of their operation results. Only in occasions with particularly high safety such as aviation will three symmetrical control modules be integrated at the same time.

[0004] However, since the backup control unit and the main control unit are from the same company, there may be a common hardware defect problem (i.e., the design defect of the first operation control unit 1a also exists in the second operation control unit 1b and the third operation control unit 1c), so the use of this functional safety control method has safety defects. At the same time, the addition of backup operation control units (each equipped with a computing unit and a corresponding storage unit) increases the area of ​​the hardware control unit by several times (equivalent to multiple design redundancy), affecting instruction execution and operation efficiency; with the development trend of terminal miniaturization and lightweight, higher requirements are placed on the area and safety of motor control chips.

[0005] Therefore, how to remove redundant designs, reduce the area of ​​motor engine control circuits, reduce costs, and improve computing efficiency has become one of the problems that technicians in this field need to solve urgently.

[0006] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present invention and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology section of the present invention. Summary of the invention

[0007] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a motor engine control circuit, method, motor control system and vehicle, which are used to solve the problems of large area, high cost and low computing efficiency of the motor engine control circuit in the prior art.

[0008] To achieve the above objectives and other related objectives, the present invention provides a motor engine control circuit, the motor engine control circuit comprising:

[0009] A calculation result checking module, a state checking selection module, a check code storage module, a check decoding module, at least two calculation modules and at least two state sequence controllers;

[0010] Each calculation module receives the same signal to be processed, calculates the signal to be processed at the same time, and outputs the calculation result; wherein each calculation module backs up each other;

[0011] The calculation result checking module is connected to the output end of each calculation module, and performs consistency comparison on the calculation results output by each calculation module; when the calculation results are consistent, the calculation result is output; when the calculation results are inconsistent, a first interruption alarm signal is output;

[0012] Each state sequence controller generates a calculation state signal and a register sequence selection signal according to the current working state at the same time, wherein each state sequence controller backs up each other;

[0013] The state check selection module is connected to the output end of each state sequence controller, and performs consistency comparison on the operation state signal and the register sequence selection signal output by each state sequence controller; when the operation state signals are consistent, the operation state signal is output; when the register sequence selection signals are consistent, the register sequence selection signal is output; when the operation state signals and / or the register sequence selection signals are inconsistent, the second interrupt alarm signal is output;

[0014] The check code storage module is connected to the output ends of the calculation result checking module and the state checking selection module, performs check coding on the calculation result, and stores the calculation result in a corresponding register based on the operation state signal and the register sequence selection signal;

[0015] The check decoding module is connected to the output ends of the check coding storage module and the status check selection module, selects the data in the corresponding register based on the operation status signal and the register sequence selection signal, decodes and checks the selected data, and outputs or feeds back the correct data to each calculation module as a signal to be processed to perform the next step of calculation.

[0016] Optionally, the calculation module performs at least one of coordinate transformation, proportional integral regulation, phase locking or filtering calculation in time-sharing.

[0017] Optionally, the check code storage module includes an ECC encoder, a storage selection unit and N registers; wherein N is the number of bits of the operation status signal;

[0018] The ECC encoder receives the calculation result output by the calculation result checking module, and performs ECC encoding on the calculation result;

[0019] The storage selection circuit receives the operation state signal and the register sequence selection signal output by the state check selection module, and generates a register selection signal accordingly;

[0020] Each register is connected to the output end of the ECC encoder and the storage selection circuit, selects the corresponding register based on the register selection signal, and stores the output signal of the ECC encoder in the selected register.

[0021] More optionally, the check decoding module includes a multi-channel data selector and M ECC decoders;

[0022] The multi-channel data selector is connected to the output ends of the check code storage module and the state check selection module, and selects data in M ​​registers to read based on the operation state signal and the register sequence selection signal; wherein M is a natural number greater than 1 and less than N;

[0023] Each ECC decoder is connected to the output end of the multi-channel data selector and simultaneously performs ECC decoding on the M channels of data read out by the multi-channel data selector.

[0024] More optionally, the check decoding module also includes an error reporting unit, which is connected to the output end of the ECC decoder, and sends out a warning signal when a 1-bit error occurs in the decoded data, and sends out an alarm signal and a reset signal when 2 or more bits of error occur in the decoded data.

[0025] To achieve the above objectives and other related objectives, the present invention further provides a motor engine control method, the motor engine control method at least comprising:

[0026] Step 1) generating a synchronous operation state according to the working state of the motor engine, and performing corresponding synchronous calculation on the signal to be processed; performing consistency comparison on the calculation result and the operation state respectively; if the calculation result or the operation state is inconsistent, interrupting and reporting an error; if the calculation result and the operation state are consistent, executing the next step;

[0027] Step 2) verifying and encoding the equal calculation results and storing them in corresponding registers;

[0028] Step 3) reads the data in the register corresponding to the current operation state, performs verification decoding and verification on the read calculation result, and takes protective action if an error is detected; if there is no error, outputs the correct data or returns to step 1) to perform the next calculation on the correct data.

[0029] Optionally, in step 1), coordinate transformation, proportional-integral regulation, phase locking or filtering calculation are performed in a time-sharing manner according to the working state of the motor engine.

[0030] Optionally, the check encoding in step 2) adopts ECC encoding, and the check decoding in step 3) adopts ECC decoding.

[0031] More optionally, in step 3), when a 1-bit error occurs in the decoded data, the error is corrected and an early warning is issued; when 2 or more bits of error occur in the decoded data, an error is reported and an abnormal reset action is performed.

[0032] More optionally, in step 3), the data in at least two registers are checked and decoded simultaneously.

[0033] In order to achieve the above-mentioned object and other related objects, the present invention further provides a motor control system, which at least includes:

[0034] Motor driver, motor and control circuit of the motor engine;

[0035] The motor engine control circuit generates a motor control signal based on the motor sampling signal;

[0036] The motor driver is connected to the output end of the motor engine control circuit and generates a drive signal based on the motor control signal;

[0037] The motor is connected to the output terminal of the motor driver and operates based on the driving signal.

[0038] To achieve the above-mentioned object and other related objects, the present invention provides a vehicle, which at least includes: the above-mentioned motor control system.

[0039] As described above, the motor engine control circuit, method, motor control system and vehicle of the present invention have the following beneficial effects:

[0040] 1. The motor engine control circuit, motor control system and vehicle of the present invention independently separate the computing module and the register, and only one set of registers is provided to eliminate redundant design, which can effectively reduce the area of ​​the motor control engine circuit, reduce costs, and improve hardware execution efficiency and integration.

[0041] 2. The motor engine control circuit, method, motor control system and vehicle of the present invention improve safety through a symmetry calculation module and a symmetry state sequence controller, and also have a self-correction function and a fault-tolerant mechanism, thereby improving the reliability of the motor drive system.

[0042] 3. The motor engine control circuit, method, motor control system and vehicle of the present invention also have error detection and early warning functions, which further improves safety. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 Shown is a schematic diagram of the principles of a traditional functional safety approach.

[0044] Figure 2 Shown is a structural schematic diagram of the motor engine control circuit of the present invention.

[0045] Figure 3 Shown is a schematic diagram of the structure of the motor control engine of the present invention.

[0046] Figure 4 It is a flow chart of the motor engine control method of the present invention.

[0047] Figure 5 Shown is a schematic structural diagram of the motor control system of the present invention.

[0048] Component number description

[0049] 1a First operation control unit

[0050] 1b Second operation control unit

[0051] 1c Third operation control unit

[0052] 2 Motor engine control circuit

[0053] 21 Calculation result check module

[0054] 22 Status Check Selection Module

[0055] 23. Check code storage module

[0056] 231 ECC Encoder

[0057] 232 Storage Selection Unit

[0058] 233 Registers

[0059] 24 Checksum decoding module

[0060] 241 Multi-channel data selector

[0061] 242 ECC Decoder

[0062] 243 Error reporting unit

[0063] 251 First Computing Module

[0064] 252 Second computing module

[0065] 261 First State Sequence Controller

[0066] 262 Second State Sequence Controller

[0067] 2a First coordinate transformation module

[0068] 2b Sliding Mode Observer

[0069] 2c Low pass filter

[0070] 2d Phase-Locked Loop

[0071] 2e Proportional Integral Module

[0072] 2f Proportional-integral regulation module

[0073] 2g Second coordinate transformation module

[0074] 2h Control signal generation module

[0075] 3 Motor Driver

[0076] 4 Motor DETAILED DESCRIPTION

[0077] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0078] See also Figure 2 to Figure 5 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0079] like Figure 2 As shown, the present invention provides a motor engine control circuit 2, and the motor engine control circuit 2 includes:

[0080] The calculation result checking module 21, the state checking selection module 22, the check code storage module 23, the check decoding module 24, at least two calculation modules and at least two state sequence controllers. In this example, the calculation module and the state sequence controller are configured as two, namely, a first calculation module 251, a second calculation module 252, a first state sequence controller 261 and a second state sequence controller 262; in actual use, it can be configured as three or more as needed to improve security, but the more the number of configurations, the higher the cost, therefore, the corresponding number can be configured as needed, not limited to this embodiment.

[0081] like Figure 2 As shown, each calculation module receives the same signal Data to be processed, calculates the signal Data to be processed at the same time, and outputs the calculation result; wherein each calculation module backs up each other.

[0082] Specifically, each calculation module is used to calculate various operations in the motor control engine (vector engine). The calculation module is a common module, including but not limited to addition, subtraction, multiplication and other operations, which are not described here one by one. As an example, the first calculation module 251 and the second calculation module 252 perform at least one of coordinate transformation, proportional integral regulation, phase locking or filtering calculation in a time-sharing manner, and the first calculation module 251 outputs a first calculation result calOut0[k:0], and the second calculation module 252 outputs a second calculation result calOut1[k:0]; k is a natural number greater than or equal to 1.

[0083] Specifically, Figure 3As shown, in this embodiment, the motor control engine includes a first coordinate conversion module 2a, a sliding mode observer 2b, a low-pass filter 2c, a phase-locked loop 2d, a proportional-integral module 2e, a proportional-integral adjustment module 2f, a second coordinate conversion module 2g and a control signal generation module 2h; wherein the first coordinate conversion module 2a is used to convert the sampled motor current signal I a ,I b Perform Clarke transformation to obtain the two-phase current signal I in the two-phase stationary coordinate system α ,I β , and then the two-phase current signal I in the two-phase rotating coordinate system is obtained through Park transformation d ,I q The sliding mode observer 2b is based on the two-phase current signal I in the two-phase stationary coordinate system α ,I β The motor energy is observed; the low-pass filter 2c filters the output signal of the sliding mode observer 2b; the phase-locked loop 2d is connected to the output end of the low-pass filter 2c, based on the sliding mode observer

[0084] The motor energy observed by the detector 2b and the sine and cosine feedback signals of the estimated angle of the previous cycle are used to extract the estimated angle and estimated angular frequency The proportional-integral module 2e is based on the angular frequency reference ω ref and estimated angular frequency Get the quadrature axis reference current I qref The proportional-integral regulation module 2f is based on the direct-axis current I d , direct axis reference current I dref , quadrature axis current I q and quadrature axis reference current I qref Perform proportional integral regulation operation to obtain the direct axis voltage U d and the quadrature axis voltage U q The second coordinate conversion module 2g is used to convert the direct axis voltage U d and the quadrature axis voltage U q Perform inverse Park transformation to obtain the two-phase voltage signal u in the two-phase stationary coordinate system α 、u β The control signal generating module 2h is based on the two-phase voltage signal u in the two-phase stationary coordinate system α 、u β Generate a space vector pulse width modulation signal SVPWM of the motor. In actual use, any structure that can realize a vector engine is applicable to the present invention, and is not limited to this embodiment.

[0085] Furthermore, in this embodiment, the same operations in each module in the motor control engine are implemented by the same operator in the computing module. For example, the multiplication operations in the first coordinate transformation module 2a and the second coordinate transformation module 2b are both implemented by the same multiplier in the computing module, but the execution time periods are different, thereby further reducing the area and cost of the computing module.

[0086] like Figure 2 As shown, the calculation result checking module 21 is connected to the output end of each calculation module to perform consistency comparison on the calculation results output by each calculation module; when the calculation results are consistent, the calculation result calOut[k:0] is output; when the calculation results are inconsistent, the first interrupt alarm signal IN1 is output.

[0087] Specifically, in this embodiment, the calculation result checking module 21 compares the corresponding bit signals of the first calculation result calOut0[k:0] and the second calculation result calOut1[k:0] one by one. If all are consistent, the two are determined to be equal; if one bit is inconsistent, the two are determined to be unequal, and a first interrupt alarm signal IN1 is output. The first interrupt alarm signal IN1 is used to control system interrupts and issue an alarm.

[0088] like Figure 2 As shown, each state sequence controller generates a calculation state signal and a register sequence selection signal according to the current working state at the same time, wherein each state sequence controller backs up each other.

[0089] Specifically, in this embodiment, the first state sequence controller 261 generates a first operation state signal State0[n:0] (state machine state bit) and a first register sequence selection signal sel0 based on the working state of the motor; the second state sequence controller 262 generates a second operation state signal State1[n:0] and a second register sequence selection signal sel1 based on the working state of the motor; theoretically, since they are in the same working state, the first operation state signal State0[n:0] and the second operation state signal State1[n:0] should be the same, and the first register sequence selection signal sel0 and the second register sequence selection signal sel1 should also be the same, where n is a natural number greater than or equal to 1.

[0090] like Figure 2As shown, the state check selection module 22 is connected to the output end of each state sequence controller, and performs consistency comparison on the operation state signal and the register sequence selection signal output by each state sequence controller; when the operation state signals are consistent, the operation state signal State[n:0] is output; when the register sequence selection signals are consistent, the register sequence selection signal sel is output; when the operation state signals and / or the register sequence selection signals are inconsistent, the second interrupt alarm signal INT2 is output.

[0091] Specifically, in this embodiment, the state check selection module 22 compares the corresponding bit signals of the first operation state signal State0[n:0] and the second operation state signal State1[n:0] one by one, and if all are consistent, the two are determined to be equal; if there is one bit inconsistent, the two are determined to be unequal, and a second interrupt alarm signal IN2 is output, and the second interrupt alarm signal IN2 is used to control the system interrupt and issue an alarm. The state check selection module 22 also compares the corresponding bit signals of the first register sequence selection signal sel0 and the second register sequence selection signal sel1 one by one, and if all are consistent, the two are determined to be equal; if there is one bit inconsistent, the two are determined to be unequal, and a second interrupt alarm signal IN2 is output.

[0092] like Figure 2 As shown, the check code storage module 23 is connected to the output ends of the calculation result check module 21 and the state check selection module 22, performs check coding on the calculation result calOut[k:0], and stores the calculation result calOut[k:0] in the corresponding register based on the operation state signal State[n:0] and the register sequence selection signal sel.

[0093] Specifically, in this embodiment, the check code storage module 23 includes an ECC encoder 231, a storage selection unit 232 and N registers 233; wherein N is the number of bits of the operation state signal State[n:0], that is, N=n+1. The ECC encoder 231 receives the calculation result calOut[k:0] output by the calculation result check module 21, and performs ECC encoding on the calculation result calOut[k:0]; as an example, the ECC-encoded data includes a 6-bit check code checkBits[5:0] and a k+1-bit data enCalOut[k:0], where k+1 is set to 16 / 24 bits. The storage selection circuit 232 receives the operation state signal State[n:0] output by the state check selection module 22 and the register sequence selection signal sel, and generates a register selection signal accordingly. Each register is connected to the output end of the ECC encoder 231 and the storage selection circuit 232, selects the corresponding register based on the register selection signal, and stores the output signal of the ECC encoder 231 in the selected register. Different operation states and register sequences correspond to different registers, and the calculation result corresponds to the operation state through the register selection signal.

[0094] It should be noted that the use of ECC coding in this embodiment can further improve security and reliability. In actual use, the way of checking coding can be set as needed. In addition, the number of bits of the check code and the calculation result can be set as needed, not limited to this embodiment.

[0095] like Figure 2 As shown, the check decoding module 24 is connected to the output end of the check code storage module 23 and the state check selection module 22, selects the data in the corresponding register based on the operation state signal State[n:0] and the register sequence selection signal sel, decodes and checks the selected data, and outputs or feeds back the correct data to each calculation module as a signal to be processed to perform the next step of calculation.

[0096] Specifically, in this embodiment, the check decoding module 24 includes a multi-channel data selector 241 and M ECC decoders 242. The multi-channel data selector 241 is connected to the output end of the check code storage module 23 and the state check selection module 22, and selects the data in M ​​registers to read based on the operation state signal State[n:0] and the register sequence selection signal sel; wherein M is a natural number greater than 1 and less than N; as an example, the calculation module of the present invention needs to take out the data of three registers at most once for calculation, so M is set to 3. In actual use, it can be set as needed, not limited to this embodiment. Each ECC decoder 242 is connected to the output end of the multi-channel data selector 241, and simultaneously performs ECC decoding on the M-channel data read out by the multi-channel data selector 241; ECC decoding can realize one-bit error correction and two-bit error detection, greatly improving the safety performance; that is, when the data in the memory is erroneous during the communication and storage process after ECC encoding, the ECC decoder can automatically correct the error for the error of one bit and send out a corresponding first prompt signal; when the ECC decoder detects that two bits of data are wrong, it will send out a corresponding second prompt signal.

[0097] Specifically, as another implementation method of the present invention, the check decoding module 24 also includes an error reporting unit 243, and the error reporting unit 243 is connected to the output end of the ECC decoder 242. When the first prompt signal is valid, a warning signal is issued; when the second prompt signal is valid, an alarm signal and a reset signal are issued, and the alarm signal is used to issue an alarm, and the reset signal is used to reset the motor engine control circuit 2 and indicate that an abnormal reset action has been performed.

[0098] It should be noted that the data output from the verification decoding module 24 is used for subsequent motor control; or fed back to the calculation module for subsequent calculation, for example, a multiplication operation is first performed in the calculation module, and then the result of the multiplication operation is stored in a register, and then the result of the multiplication operation is decoded from the register and fed back to the calculation module for addition operation, until the required calculation is completed and the output is output.

[0099] In the entire motor engine control circuit, the computing part occupies about 20% of the area of ​​the entire engine control circuit, and the storage part occupies about 80% of the area. Therefore, the present invention combines the inherent characteristics of the motor engine control module, separates the computing module and the register, optimizes the register control logic, and reduces the use of registers; at the same time, two symmetrical computing modules and a state sequence controller are used for consistency comparison to ensure the stability of the operation of the motor engine control module.

[0100] like Figure 4As shown, the present invention further provides a motor engine control method. In this embodiment, the motor engine control method is implemented based on the motor engine control circuit 2 of the present invention. In actual use, any circuit that can implement this method is applicable, not limited to this embodiment. The motor engine control method includes:

[0101] Step 1) Generate a synchronous operation state according to the working state of the motor engine, and perform corresponding synchronous calculation on the signal to be processed; perform consistency comparison on the calculation result and the operation state respectively; if the calculation result or the operation state is inconsistent, interrupt and report an error; if the calculation result and the operation state are consistent, execute the next step.

[0102] Specifically, in this embodiment, in step 1), coordinate transformation, proportional-integral regulation, phase locking or filtering calculation are performed in a time-sharing manner according to the working state of the motor engine. Therefore, the calculation module can be reused in a time-sharing manner; at the same time, the same operation method in different calculation steps (including but not limited to multiplication, addition, subtraction) can also be implemented by the same operator, further reducing circuit area and cost.

[0103] Specifically, in this embodiment, two groups of calculation results are compared, two groups of operation status signals are compared, and two groups of storage sequence selection signals are compared to determine whether the calculation results and the operation status are respectively consistent. If one is inconsistent, an alarm is issued and the system is interrupted.

[0104] Step 2) Check and encode the equal calculation results and store them in the corresponding registers.

[0105] Specifically, if the calculation result and the operation state are consistent, the calculation result is checked and coded, and in this example, ECC coding is used with a 6-bit check code. The corresponding register is selected according to the operation state, and the calculation result is stored in the register.

[0106] Step 3) reads the data in the register corresponding to the current operation state, performs verification decoding and verification on the read calculation result, and takes protective action if an error is detected; if there is no error, outputs the correct data or returns to step 1) to perform the next calculation on the correct data.

[0107] Specifically, if the data in the register completes the required calculation, the data is read and decoded before outputting. If the data in the register needs to be calculated in the next step, the data is read and decoded before returning to step 1) to continue the calculation.

[0108] Specifically, in this embodiment, the check decoding adopts ECC decoding (consistent with the encoding method). When a 1-bit error occurs in the decoded data, the error is corrected automatically and a warning interrupt event is reported after the automatic error correction function is completed, reminding the application developer that the system stores an abnormal warning; when 2 or more bits of error occur in the decoded data, the system generates a reset signal to reset the motor engine control circuit, and reports an error to remind the application developer that the system has performed an abnormal reset action.

[0109] It should be noted that in actual use, the check code and the corresponding check decoding method can be set as needed, and are not limited to this embodiment.

[0110] As another implementation of the present invention, in step 3), the data in at least two registers are checked and decoded simultaneously.

[0111] like Figure 5 As shown, the present invention also provides a motor control system, the motor control system comprising:

[0112] The motor engine control circuit 2 , the motor driver 3 and the motor 4 .

[0113] like Figure 5 As shown, the motor engine control circuit 2 generates a motor control signal SVPWM based on the motor sampling signal.

[0114] Specifically, the structure and working principle of the motor engine control circuit 2 are as mentioned above and will not be elaborated here.

[0115] like Figure 5 As shown, the motor driver 3 is connected to the output end of the motor engine control circuit 2 and generates a driving signal based on the motor control signal SVPWM.

[0116] Specifically, in this embodiment, the motor driver 3 is a PMD module, which converts the motor control signal SVPWM into a PWM signal, and then inverts the PWM signal to obtain a three-phase drive voltage. In actual use, the motor driver 3 can be configured as needed, and can generate a drive signal for controlling the motor based on the motor control signal SVPWM.

[0117] like Figure 5 As shown, the motor 4 is connected to the output end of the motor driver 3 and operates based on the driving signal.

[0118] Specifically, the motor 4 includes but is not limited to a single-phase motor and a three-phase motor.

[0119] The present invention also provides a vehicle, comprising the motor control system, wherein the motor control system is used to provide kinetic energy for the vehicle.

[0120] The present invention independently separates the calculation module and register in the motor engine control circuit, and simultaneously performs calculations, controls and synchronously compares the results through the symmetry calculation module and the symmetry state sequence controller to determine whether the motor engine control circuit is running stably; at the same time, an ECC algorithm with an error correction function is introduced to make the system operation more stable and reliable; in addition, only one set of registers is needed, which reduces the area of ​​the register storage part by nearly 40% and the chip area by nearly 30%, achieving a two-way improvement in improving system integration and safety.

[0121] In summary, the present invention provides a motor engine control circuit, method, motor control system and vehicle, including: a calculation result checking module, a state checking selection module, a check code storage module, a check decoding module, at least two calculation modules and at least two state sequence controllers; each calculation module receives the same signal to be processed, calculates the signal to be processed at the same time, and outputs the calculation result; wherein the calculation modules back up each other; the calculation result checking module is connected to the output end of each calculation module, and performs consistency comparison on the calculation results output by each calculation module; when the calculation results are consistent, the calculation result is output, and when the calculation results are inconsistent, a first interrupt alarm signal is output; each state sequence controller generates a calculation state signal and a storage sequence selection signal according to the current working state at the same time, wherein the state sequence controllers back up each other; the state checking selection module is connected to the output end of each state sequence controller, and performs consistency comparison on the calculation results output by each state sequence controller The calculation state signal and the register sequence selection signal are respectively compared for consistency; when the calculation state signals are consistent, the calculation state signal is output, when the register sequence selection signals are consistent, the register sequence selection signal is output, and when the calculation state signals and / or the register sequence selection signals are inconsistent, a second interrupt alarm signal is output; the check code storage module is connected to the output end of the calculation result inspection module and the state inspection selection module, the calculation result is check-coded, and based on the calculation state signal and the register sequence selection signal, the calculation result is stored in the corresponding register; the check decoding module is connected to the check code storage module and the output end of the state inspection selection module, the data in the corresponding register is selected based on the calculation state signal and the register sequence selection signal, the selected data is decoded and checked, and the correct data is output or fed back to each calculation module as a signal to be processed to perform the next step of calculation. The present invention reduces the area of ​​the motor control engine circuit by removing redundant design, optimizing the functional safety module, improving the instruction execution and operation efficiency, and reducing the chip design, development and manufacturing costs. At the same time, the added error detection and error correction circuit makes the motor control system safer, more stable and reliable. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0122] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A motor engine control circuit, characterized in that: The motor engine control circuit comprises: A calculation result checking module, a state checking selection module, a check code storage module, a check decoding module, at least two calculation modules and at least two state sequence controllers; Each calculation module receives the same signal to be processed, calculates the signal to be processed at the same time, and outputs the calculation result; wherein each calculation module backs up each other; The calculation result checking module is connected to the output end of each calculation module, and performs consistency comparison on the calculation results output by each calculation module; when the calculation results are consistent, the calculation result is output; when the calculation results are inconsistent, a first interruption alarm signal is output; Each state sequence controller generates a calculation state signal and a register sequence selection signal according to the current working state at the same time, wherein each state sequence controller backs up each other; The state check selection module is connected to the output end of each state sequence controller, and performs consistency comparison on the operation state signal and the register sequence selection signal output by each state sequence controller; when the operation state signals are consistent, the operation state signal is output; when the register sequence selection signals are consistent, the register sequence selection signal is output; when the operation state signals and / or the register sequence selection signals are inconsistent, the second interrupt alarm signal is output; The check code storage module is connected to the output ends of the calculation result checking module and the state checking selection module, performs check coding on the calculation result, and stores the calculation result in a corresponding register based on the operation state signal and the register sequence selection signal; The check decoding module is connected to the output ends of the check coding storage module and the status check selection module, selects the data in the corresponding register based on the operation status signal and the register sequence selection signal, decodes and checks the selected data, and outputs or feeds back the correct data to each calculation module as a signal to be processed to perform the next step of calculation.

2. The motor engine control circuit according to claim 1, characterized in that: The calculation module performs at least one of coordinate transformation, proportional integral regulation, phase locking or filtering calculation in a time-sharing manner.

3. The motor engine control circuit according to claim 1, characterized in that: The check code storage module includes an ECC encoder, a storage selection unit and N registers; wherein N is the number of bits of the operation status signal; The ECC encoder receives the calculation result output by the calculation result checking module, and performs ECC encoding on the calculation result; The storage selection circuit receives the operation state signal and the register sequence selection signal output by the state check selection module, and generates a register selection signal accordingly; Each register is connected to the output end of the ECC encoder and the storage selection circuit, selects the corresponding register based on the register selection signal, and stores the output signal of the ECC encoder in the selected register.

4. The motor engine control circuit according to claim 3, characterized in that: The check decoding module includes a multi-channel data selector and M ECC decoders; The multi-channel data selector is connected to the output ends of the check code storage module and the state check selection module, and selects data in M ​​registers to read based on the operation state signal and the register sequence selection signal; Wherein, M is a natural number greater than 1 and less than N; Each ECC decoder is connected to the output end of the multi-channel data selector and performs ECC decoding on M channels of data read out by the multi-channel data selector at the same time.

5. The motor engine control circuit according to claim 4, characterized in that: The check decoding module also includes an error reporting unit, which is connected to the output end of the ECC decoder. When a 1-bit error occurs in the decoded data, a warning signal is issued, and when 2 or more bits of error occur in the decoded data, an alarm signal and a reset signal are issued.

6. A motor engine control method, characterized in that: The motor engine control method at least comprises: Step 1) generating a synchronous operation state according to the working state of the motor engine, and performing corresponding synchronous calculation on the signal to be processed; performing consistency comparison on the calculation result and the operation state respectively; if the calculation result or the operation state is inconsistent, interrupting and reporting an error; if the calculation result and the operation state are consistent, executing the next step; Step 2) verifying and encoding the equal calculation results and storing them in corresponding registers; Step 3) reads the data in the register corresponding to the current operation state, performs verification decoding and verification on the read calculation result, and takes protective action if an error is detected; if there is no error, outputs the correct data or returns to step 1) to perform the next calculation on the correct data.

7. The motor engine control method according to claim 6, characterized in that: In step 1), coordinate transformation, proportional integral regulation, phase locking or filtering calculation are performed in a time-sharing manner according to the working state of the motor engine.

8. The motor engine control method according to claim 6, characterized in that: The check encoding in step 2) adopts ECC encoding, and the check decoding in step 3) adopts ECC decoding.

9. The motor engine control method according to claim 8, characterized in that: In step 3), when a 1-bit error occurs in the decoded data, the error is corrected and an early warning is issued; when 2 or more bits of error occur in the decoded data, an error is reported and an abnormal reset action is performed.

10. The motor engine control method according to any one of claims 6 to 9, characterized in that: In step 3), the data in at least two registers are checked and decoded simultaneously.

11. A motor control system, characterized in that: The motor control system at least comprises: A motor driver, a motor, and a motor engine control circuit as claimed in any one of claims 1 to 5; The motor engine control circuit generates a motor control signal based on the motor sampling signal; The motor driver is connected to the output end of the motor engine control circuit and generates a drive signal based on the motor control signal; The motor is connected to the output terminal of the motor driver and operates based on the driving signal.

12. A vehicle, characterized in that: The vehicle at least includes: the motor control system as claimed in claim 11.

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