Cascade J-type radio frequency power amplifier circuit with pulse shaping function

Abstract

The invention provides a cascaded J-class radio frequency power amplifier circuit with a pulse shaping function. The cascaded J-class radio frequency power amplifier circuit comprises an input matching circuit, a harmonic pulse control matching circuit, a J-class output matching circuit and a phase detection compensation circuit, the input matching circuit is connected with the harmonic pulse control matching circuit through a transistor T1; the harmonic pulse control matching circuit is connected with the J-type output matching circuit through a transistor T2; and a phase detection compensation circuit is also arranged between the output end of the input matching circuit and the output end of the J-type output matching circuit. According to the invention, the defect of low efficiency of a multi-stage radio frequency power amplifier is made up, and the defect of phase adaptation of a nonlinear harmonic power amplifier is made up through a phase compensation circuit; an output signal is converted into a direct-current component, the direct-current component is compared with a threshold value set by AMP, and the phase of an input signal is controlled by controlling a capacitor array; according to the invention, the voltage and current overlapping area is greatly reduced, and the system efficiency is improved.

Description

Technical Field

[0001] The invention relates to the technical field of amplifier circuits, in particular to a cascaded class-J radio frequency power amplifier circuit with pulse shaping. Background Art

[0002] Class J RF power amplifier is a type of power amplifier designed to address the broadband and efficiency issues in future wireless communication systems. In the design, in order to reduce the impact of harmonic impedance on efficiency, a harmonic control unit is used in the output matching network, and a better matching network is synthesized by simplifying the transistor model. In the input matching network, a π-shaped matching network with mixed concentrated and distributed elements with broadband effect is used.

[0003] For example, patent CN113422579A discloses a class J Doherty power amplifier, comprising: a preamplifier for receiving an input signal and providing the amplified input signal to a power divider; a power divider, a main power amplifier which is configured to operate in a class J amplifier mode to receive a main signal distributed from the power divider and amplify the main signal, and an auxiliary power amplifier which is configured to operate in a class J amplifier mode to receive a bypass signal distributed from the power divider and amplify the auxiliary signal, wherein the main power amplifier and the auxiliary power amplifier are amplifiers with a common source and common gate structure.

[0004] However, the patented Class J mode can only be used in a single-stage power amplifier. This structure has low gain and has extremely strict restrictions on the power of the input signal. The output power of the current mainstream transmitting and receiving chips is about 10dBm. If it is necessary to achieve application scenarios such as WIFI and base stations, a single-stage PA is obviously not enough. However, the ordinary multi-stage PA matching method is bound to reduce its efficiency.

[0005] Patent CN115664347A discloses a radio frequency power amplifier, an input matching circuit and an inter-stage matching circuit, including: a first DC blocking capacitor, a first inductor and a first impedance reduction resistor; the first DC blocking capacitor is arranged between the radio frequency input signal and the first power transistor; the first inductor and the first impedance reduction resistor are connected in series and arranged between the first bias voltage and the first power transistor; and also includes a first balancing capacitor connected in parallel with the first impedance reduction resistor to compensate for the gain roll-off effect of the first power transistor to achieve gain balancing.

[0006] However, the patent focuses on the multi-stage matching of the AB class. For RF power amplifiers, most of the power is consumed by the overlap of the transistor drain voltage and current. Therefore, many nonlinear amplifier operating modes are derived, which rely on the processing of harmonics to shape the waveform and reduce the voltage and current overlap to improve the system efficiency. Summary of the invention

[0007] In view of the deficiencies in the prior art, the present invention provides a cascaded class J radio frequency power amplifier circuit with pulse shaping, which makes up for the shortcomings of low efficiency of multi-stage radio frequency power amplifiers and the shortcomings of phase adaptation of nonlinear harmonic power amplifiers.

[0008] The technical solution of the present invention is: a cascaded class J radio frequency power amplifier circuit with pulse shaping, comprising an input matching circuit, a harmonic pulse control matching circuit, a class J output matching circuit, and a phase detection compensation circuit; one end of the input matching circuit is connected to a signal input end F IN The other end of the input matching circuit is connected to the harmonic pulse control matching circuit through the transistor T1; the other end of the harmonic pulse control matching circuit is connected to the J-type output matching circuit through the transistor T2; the J-type output matching circuit is connected to the signal output terminal F OUT connection; a phase detection compensation circuit is also provided between the output end of the input matching circuit and the output end of the J-type output matching circuit.

[0009] As a preferred embodiment, the input matching circuit comprises a capacitor C1, a capacitor C2, and an inductor L1; one end of the capacitor C1 is connected to the inductor L1 through a gold wire. BW With the signal input terminal F IN The other end of the capacitor C1 is connected in parallel with the inductor L1 and the capacitor C2, respectively, and the other end of the inductor L1 is grounded; the other end of the capacitor C2 is connected to the gate of the transistor T1.

[0010] Preferably, the harmonic pulse control matching circuit includes a secondary harmonic control network and a voltage waveform shaping network connected in series.

[0011] Preferably, the second harmonic control network includes an inductor L2, an inductor L3, and a capacitor C3;

[0012] The inductor L2, inductor L3 and capacitor C3 are connected in parallel to the drain of transistor T1; the other end of the capacitor C3 is grounded; the other end of the inductor L2 is connected to the drain voltage; the other end of the inductor L3 is connected to the voltage waveform shaping network.

[0013] Preferably, the voltage waveform shaping network includes an inductor L4, a capacitor C4, and a capacitor C5; one end of the capacitor C4 is connected to the other end of the inductor L3; the other end of the capacitor C4 is connected in parallel with one end of the inductor L4 and the capacitor C5, and the other end of the inductor L4 is connected to a bias voltage; the other end of the capacitor C5 is grounded; and the other end of the capacitor C4 is also connected to the gate of the transistor T2.

[0014] Preferably, the J-type output matching circuit includes a second harmonic phase control circuit and a fundamental impedance conversion circuit connected in series, wherein the second harmonic phase control circuit is connected to the drain of the transistor T2; the other end of the fundamental impedance conversion circuit is connected to the signal output terminal F OUT connect.

[0015] Preferably, the second harmonic phase control circuit includes a capacitor C6 and an inductor L5; the capacitor C6 and the inductor L5 are connected in parallel to the drain of the transistor T2; the other end of the capacitor C6 is grounded; the other end of the inductor L5 is connected to the fundamental impedance transformation circuit.

[0016] As a preferred embodiment, the fundamental impedance conversion circuit includes an inductor L6 and a capacitor C7, wherein the inductor L6 and the capacitor C7 are connected in parallel to the other end of the inductor L5; the other end of the inductor L6 is connected to a 5V driving voltage; the other end of the capacitor C7 is connected to the inductor L6 via a gold wire. BW With signal output terminal F OUT connect.

[0017] Preferably, the phase detection compensation circuit comprises a phase detection circuit, an error amplifier AMP, and a capacitor array control circuit; one end of the phase detection circuit is connected to the capacitor C7 and the signal output terminal F OUT The other end of the phase detection circuit is connected to the negative electrode of the error amplifier AMP; the positive electrode of the error amplifier AMP is connected to the external power supply; the output end of the error amplifier AMP is connected to one end of the capacitor array control circuit; the other end of the capacitor array control circuit is connected to the output end of the input matching circuit.

[0018] As a preferred embodiment, the phase detection circuit comprises a transistor T3, a capacitor C8, and a resistor R1; the gate of the transistor T3 is connected between the capacitor C7 and the signal output terminal F OUT the source of the transistor T3 is grounded; the drain of the transistor T3 is connected in parallel with the capacitor C8 and the resistor R1; and the drain of the transistor T3 is also connected to the negative electrode of the error amplifier AMP.

[0019] Preferably, the capacitor array control circuit includes a plurality of capacitors C9 connected in parallel.

[0020] The beneficial effects of the present invention are:

[0021] 1. The present invention makes up for the disadvantage of low efficiency of multi-stage radio frequency power amplifiers, and makes up for the disadvantage of phase adaptation of nonlinear harmonic power amplifiers through a phase compensation circuit;

[0022] 2. The present invention converts the output signal into a DC component, compares it with the threshold value set by the AMP, and controls the phase of the input signal by controlling the capacitor array; and compensates for poor adaptation by performing phase detection on the output signal;

[0023] 3. The present invention greatly reduces the overlapping area of ​​voltage and current, and improves system efficiency; and the highest bit of the S21 gain of the present invention is 29dB, which ensures the high gain of the cascade PA. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a circuit diagram of the amplifier of the present invention;

[0025] Figure 2 It is a circuit diagram of the phase detection compensation circuit of the present invention;

[0026] Figure 3 Schematic diagram of simulation results of the gain S21 of the amplifier of the present invention;

[0027] Figure 4 It is a schematic diagram of simulation results of the gain S11 of the amplifier of the present invention;

[0028] Figure 5 Schematic diagram of simulation results of the gain S22 of the amplifier of the present invention;

[0029] Figure 6 Schematic diagram of simulation results of the gain S12 of the amplifier of the present invention;

[0030] Figure 7 It is a schematic diagram of the efficiency simulation result of the amplifier of the present invention. DETAILED DESCRIPTION

[0031] The specific implementation of the present invention will be further described below in conjunction with the accompanying drawings:

[0032] like Figure 1 As shown, this embodiment provides a cascaded class J RF power amplifier circuit with pulse shaping, including an input matching circuit, a harmonic pulse control matching circuit, a class J output matching circuit, and a phase detection compensation circuit; one end of the input matching circuit is connected to the signal input end F IN The other end of the input matching circuit is connected to the harmonic pulse control matching circuit through the transistor T1; the other end of the harmonic pulse control matching circuit is connected to the J-type output matching circuit through the transistor T2; the J-type output matching circuit is connected to the signal output terminal F OUT connection; a phase detection compensation circuit is also provided between the output end of the input matching circuit and the output end of the J-type output matching circuit.

[0033] As a preferred embodiment of the present invention, the input matching circuit includes a capacitor C1, a capacitor C2, and an inductor L1; one end of the capacitor C1 is connected to the inductor L1 through a gold wire. BW With the signal input terminal F IN The other end of the capacitor C1 is connected in parallel with the inductor L1 and the capacitor C2 respectively, and the other end of the inductor L1 is grounded; the other end of the capacitor C2 is connected to the gate of the transistor T1. The drain of the transistor T1 is connected to the harmonic pulse control matching circuit; the source of the transistor T1 is grounded.

[0034] As a preferred embodiment of the present invention, the harmonic pulse control matching circuit includes a second harmonic control network and a voltage waveform shaping network connected in series. The third harmonic is open-circuited by the harmonic pulse control matching circuit to make its voltage waveform a square wave. For the gate voltage of transistor T1, the square wave can greatly reduce the voltage-current overlap time of transistor T1 compared to the sine wave.

[0035] As a preferred embodiment of the present invention, the second harmonic control network includes an inductor L2, an inductor L3, and a capacitor C3; the inductor L2, the inductor L3, and the capacitor C3 are connected in parallel to the drain of the transistor T1; the other end of the capacitor C3 is grounded; the other end of the inductor L2 is connected to the drain voltage; and the other end of the inductor L3 is connected to the voltage waveform shaping network.

[0036] As a preferred embodiment of the present invention, the voltage waveform shaping network includes an inductor L4, a capacitor C4, and a capacitor C5; one end of the capacitor C4 is connected to the other end of the inductor L3; the other end of the capacitor C4 is connected in parallel with one end of the inductor L4 and the capacitor C5, and the other end of the inductor L4 is connected to a bias voltage; the other end of the capacitor C5 is grounded; the other end of the capacitor C4 is also connected to the gate of the transistor T2. The drain of the transistor T2 is connected to the J-type output matching circuit, and the source of the transistor T2 is grounded.

[0037] As a preferred embodiment of the present invention, the J-type output matching circuit includes a second harmonic phase control circuit and a fundamental impedance conversion circuit connected in series, wherein the second harmonic phase control circuit is connected to the drain of the transistor T2; the other end of the fundamental impedance conversion circuit is connected to the signal output terminal F OUT connect.

[0038] As a preferred embodiment of the present invention, the second harmonic phase control circuit includes a capacitor C6 and an inductor L5; the capacitor C6 and the inductor L5 are connected in parallel to the drain of the transistor T2; the other end of the capacitor C6 is grounded; the other end of the inductor L5 is connected to the fundamental impedance transformation circuit.

[0039] As a preferred embodiment of the present invention, the fundamental impedance conversion circuit includes an inductor L6 and a capacitor C7, wherein the inductor L6 and the capacitor C7 are connected in parallel to the other end of the inductor L5; the other end of the inductor L6 is connected to a 5V driving voltage; the other end of the capacitor C7 is connected to the inductor L6 via a gold wire. BW With signal output terminal F OUT When the load is 50 ohms, the inductor L6 and the capacitor C7 move the impedance to the upper half of the Smith circle to ensure the optimal impedance of the fundamental wave. The capacitor C6 and the inductor L5 control the second harmonic impedance to be located on the imaginary axis of the Smith circle, ensuring that the real part is between 0 and 3 ohms.

[0040] As preferred in this embodiment, Figure 1 and 2 As shown, the phase detection compensation circuit includes a phase detection circuit, an error amplifier AMP, and a capacitor array control circuit; one end of the phase detection circuit is connected to the capacitor C7 and the signal output terminal F OUT The other end of the phase detection circuit is connected to the negative electrode of the error amplifier AMP; the positive electrode of the error amplifier AMP is connected to the external power supply; the output end of the error amplifier AMP is connected to one end of the capacitor array control circuit; the other end of the capacitor array control circuit is connected to the output end of the input matching circuit.

[0041] In this embodiment, the output signal of the class J output matching circuit is converted into a DC component through a phase detection circuit; and is input into an error amplifier AMP for comparison with a preset threshold value, and the output of the error amplifier AMP is used to control the input capacitor array to control the phase of the input signal.

[0042] As a preferred embodiment of the present invention, the phase detection circuit includes a transistor T3, a capacitor C8, and a resistor R1; the gate of the transistor T3 is connected to the capacitor C7 and the signal output terminal F OUT the source of the transistor T3 is grounded; the drain of the transistor T3 is connected in parallel with the capacitor C8 and the resistor R1; and the drain of the transistor T3 is also connected to the negative electrode of the error amplifier AMP.

[0043] As a preferred embodiment of the present invention, the capacitor array control circuit includes a plurality of capacitors C9 connected in parallel.

[0044] In this embodiment, the J-type RF power amplifier is simulated and the results are as follows: Figure 3-7 shown; from Figure 3 It can be seen that the highest level of S21 is 29dB, which ensures the high gain of the cascaded PA. Figure 4 It can be seen that the lowest level of S11 is lower than -30dB. Figure 5It can be seen that the output reflection coefficient can easily reach below -10dB at the center frequency. This ensures system stability. Figure 6 It can be seen that the isolation of the Level 2 PA reaches -70dB, providing favorable stability for mass production. Figure 7 It can be seen that under the two-stage PA structure, the system additional efficiency reaches an astonishing 67%, which is almost close to the theoretical Class B efficiency of 78.5. This embodiment synthesizes the second harmonic current components, greatly reducing the overlapping area of ​​voltage and current, and improving system efficiency.

[0045] The above embodiments and descriptions are only for illustrating the principles and best embodiments of the present invention. Without departing from the spirit and scope of the present invention, the present invention may be subject to various changes and improvements, all of which fall within the scope of the present invention to be protected.

Claims

1. A cascaded class J radio frequency power amplifier circuit with pulse shaping, characterized in that: It includes an input matching circuit, a harmonic pulse control matching circuit, a J-type output matching circuit, and a phase detection compensation circuit; one end of the input matching circuit is connected to the signal input end F IN The other end of the input matching circuit is connected to the harmonic pulse control matching circuit through the transistor T1; the other end of the harmonic pulse control matching circuit is connected to the J-type output matching circuit through the transistor T2; the J-type output matching circuit is connected to the signal output terminal F OUT A phase detection compensation circuit is also provided between the output end of the input matching circuit and the output end of the class J output matching circuit.

2. The cascaded class-J radio frequency power amplifier circuit with pulse shaping according to claim 1, characterized in that: The input matching circuit includes capacitor C1, capacitor C2, and inductor L1; one end of the capacitor C1 is connected to the inductor L1 through a gold wire. BW With the signal input terminal F IN The other end of the capacitor C1 is connected in parallel with the inductor L1 and the capacitor C2, respectively, and the other end of the inductor L1 is grounded; the other end of the capacitor C2 is connected to the gate of the transistor T1.

3. The cascaded class-J radio frequency power amplifier circuit with pulse shaping according to claim 1, characterized in that: The harmonic pulse control matching circuit comprises a secondary harmonic control network and a voltage waveform shaping network connected in series.

4. The cascaded class-J radio frequency power amplifier circuit with pulse shaping according to claim 3, characterized in that: The second harmonic control network includes an inductor L2, an inductor L3, and a capacitor C3; the inductor L2, the inductor L3, and the capacitor C3 are connected in parallel to the drain of the transistor T1; the other end of the capacitor C3 is grounded; the other end of the inductor L2 is connected to the drain voltage; and the other end of the inductor L3 is connected to the voltage waveform shaping network.

5. The cascaded class-J radio frequency power amplifier circuit with pulse shaping according to claim 4, characterized in that: The voltage waveform shaping network includes an inductor L4, a capacitor C4, and a capacitor C5; one end of the capacitor C4 is connected to the other end of the inductor L3; the other end of the capacitor C4 is connected in parallel with one end of the inductor L4 and the capacitor C5, and the other end of the inductor L4 is connected to a bias voltage; the other end of the capacitor C5 is grounded; and the other end of the capacitor C4 is also connected to the gate of the transistor T2.

6. The cascaded class-J radio frequency power amplifier circuit with pulse shaping according to claim 1, characterized in that: The J-type output matching circuit includes a second harmonic phase control circuit and a fundamental impedance conversion circuit connected in series. The second harmonic phase control circuit is connected to the drain of the transistor T2; the other end of the fundamental impedance conversion circuit is connected to the signal output terminal F OUT connect.

7. The cascaded class-J radio frequency power amplifier circuit with pulse shaping according to claim 6, characterized in that: The second harmonic phase control circuit includes a capacitor C6 and an inductor L5; the capacitor C6 and the inductor L5 are connected in parallel to the drain of the transistor T2; the other end of the capacitor C6 is grounded; the other end of the inductor L5 is connected to the fundamental impedance conversion circuit.

8. The cascaded class-J radio frequency power amplifier circuit with pulse shaping according to claim 7, characterized in that: The fundamental impedance conversion circuit includes an inductor L6 and a capacitor C7, wherein the inductor L6 and the capacitor C7 are connected in parallel to the other end of the inductor L5; the other end of the inductor L6 is connected to a 5V driving voltage; the other end of the capacitor C7 is connected to the inductor L6 via a gold wire. BW With signal output terminal F OUT connect.

9. The cascaded class-J radio frequency power amplifier circuit with pulse shaping according to claim 1, characterized in that: The phase detection compensation circuit includes a phase detection circuit, an error amplifier AMP, and a capacitor array control circuit; one end of the phase detection circuit is connected to the capacitor C7 and the signal output terminal F OUT The other end of the phase detection circuit is connected to the negative electrode of the error amplifier AMP; the positive electrode of the error amplifier AMP is connected to an external power supply; the output end of the error amplifier AMP is connected to one end of the capacitor array control circuit; the other end of the capacitor array control circuit is connected to the output end of the input matching circuit; the output signal of the class J output matching circuit is converted into a DC component by the phase detection circuit; and is input into the error amplifier AMP for comparison with a preset threshold value, and the input capacitor array is controlled by the output of the error amplifier AMP to control the phase of the input signal.

10. The cascaded class-J radio frequency power amplifier circuit with pulse shaping according to claim 9, characterized in that: The phase detection circuit includes a transistor T3, a capacitor C8, and a resistor R1; the gate of the transistor T3 is connected to the capacitor C7 and the signal output terminal F OUT the source of the transistor T3 is grounded; the drain of the transistor T3 is connected in parallel with the capacitor C8 and the resistor R1; and the drain of the transistor T3 is also connected to the negative electrode of the error amplifier AMP.

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