High-pass filter circuit and high-speed instrumentation amplifier with low noise and high common mode rejection ratio

Abstract

The invention relates to the technical field of integrated circuits, and discloses a high-pass filter circuit and a low-noise and high-common-mode-rejection-ratio high-speed instrument amplifier, and the low-noise and high-common-mode-rejection-ratio high-speed instrument amplifier comprises a high-pass filter circuit which is used for providing a high-pass filtering function; the input end of the current feedback instrument amplifier circuit is connected with the high-pass filter circuit and used for providing high input impedance and a high common-mode rejection ratio, and the input end of the transconductance amplifier circuit is connected with the output end of the current feedback instrument amplifier circuit and used for improving the load driving capacity; wherein the high-pass filtering circuit adopts a connection mode of a small-capacitance capacitor and an adjustable pseudo resistor to realize high-pass filtering, and the small-capacitance capacitor refers to an on-chip capacitor of which the capacitance value is less than 100pF so as to realize complete integration. The instrument amplifier effectively solves the problem that a traditional instrument amplifier cannot have high speed, low noise, high common-mode rejection ratio and direct-current voltage offset suppression at the same time.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to the field of high-speed instrumentation amplifier technology. Background Art

[0002] Electrical Impedance Tomography (EIT) is a non-invasive imaging and detection technology that infers the impedance distribution inside the object by inputting a small alternating current into the object and measuring the voltage at different positions, thereby achieving non-contact detection of the internal structure and properties of the object. Figure 1 The basic principle of EIT is shown, and this technology has broad application prospects in medicine and industry.

[0003] In the medical field, electrical impedance imaging can be used for monitoring lung function and ventilation, non-invasive cardiac imaging, breast cancer detection, brain function localization, etc. In the industrial field, it can be used for the detection of multiphase flow, non-destructive detection of material defects, etc. Unlike other medical imaging technologies such as CT and MRI, electrical impedance imaging has the advantages of no radiation, no trauma, and low cost.

[0004] The core component of the electrical impedance tomography system is the instrumentation amplifier, which amplifies and filters weak impedance signals. However, the instrumentation amplifier used for electrical impedance tomography needs to have performance indicators such as wide bandwidth, low noise, high linearity, and high common mode rejection ratio, but it is difficult for existing amplifiers to meet these requirements at the same time.

[0005] Therefore, designing a high-performance, low-noise instrument amplifier for electrical impedance imaging technology has important application value. Summary of the invention

[0006] The purpose of the present application is to provide a high-pass filter circuit and a high-speed instrument amplifier with low noise and high common-mode rejection ratio to solve the problems raised in the above-mentioned background technology.

[0007] The present application discloses a high-pass filter circuit, comprising:

[0008] A first capacitor, a second capacitor, a first adjustable pseudo resistor, and a second adjustable pseudo resistor;

[0009] The first terminal of the first capacitor is used as a non-inverting input terminal, and the second terminal is respectively connected to the non-inverting input terminal of the current feedback instrumentation amplifier circuit and the first node of the first adjustable pseudo-resistance;

[0010] The first terminal of the second capacitor is used as a negative phase input terminal, and the second terminal is respectively connected to the negative phase input terminal of the current feedback instrument amplifier circuit and the first node of the second adjustable pseudo resistor;

[0011] The second node of the first adjustable pseudo resistor and the second adjustable pseudo resistor is connected to the common mode signal input terminal;

[0012] The control terminals of the first adjustable pseudo resistor and the second adjustable pseudo resistor are connected to an adjustable voltage to adjust the value of the pseudo resistor; wherein,

[0013] The high-pass filter circuit realizes high-pass filtering by connecting a small-capacitance capacitor and an adjustable pseudo-resistance, wherein the small-capacitance capacitor refers to a capacitor with a capacitance value less than 100pF.

[0014] In a preferred example, the high-pass filter circuit uses a connection method of a small-capacitance capacitor and an adjustable pseudo-resistance to achieve high-pass filtering. The small-capacitance capacitor refers to a capacitor with a capacitance value less than 100pF, which can realize a fully integrated on-chip capacitor (on-chip capacitance is in the order of fF-pF).

[0015] In a preferred example, the high-pass filter circuit can be used in the front end of an analog circuit such as an instrument amplifier to provide a high-pass filter function.

[0016] The present application also discloses a high-speed instrument amplifier with low noise and high common mode rejection ratio, including:

[0017] A high-pass filter circuit, used for providing a high-pass filter function;

[0018] A current feedback instrument amplifier circuit, whose input end is connected to the high-pass filter circuit, is used to provide high input impedance and high common mode rejection ratio, wherein the high input impedance refers to an input impedance greater than 1MΩ;

[0019] and a transconductance amplifier circuit, whose input end is connected to the output end of the current feedback instrumentation amplifier circuit, for improving the load driving capability;

[0020] The high-pass filter circuit uses a connection method of a small-capacitance capacitor and an adjustable pseudo-resistance to achieve high-pass filtering. The small-capacitance capacitor refers to a capacitor with a capacitance value less than 100pF to achieve a fully integrated on-chip capacitor.

[0021] In a preferred example, the high-pass filter circuit includes:

[0022] A first capacitor, a second capacitor, a first adjustable pseudo resistor, and a second adjustable pseudo resistor;

[0023] The first terminal of the first capacitor is used as a non-inverting input terminal, and the second terminal is respectively connected to the non-inverting input terminal of the current feedback instrumentation amplifier circuit and the first node of the first adjustable pseudo-resistance;

[0024] The first terminal of the second capacitor is used as a negative phase input terminal, and the second terminal is respectively connected to the negative phase input terminal of the current feedback instrument amplifier circuit and the first node of the second adjustable pseudo resistor;

[0025] The second node of the first adjustable pseudo resistor and the second adjustable pseudo resistor is connected to the common mode signal input terminal;

[0026] Control terminals of the first adjustable pseudo resistor and the second adjustable pseudo resistor are connected to an adjustable voltage to adjust the value of the pseudo resistor.

[0027] In a preferred example, the current feedback instrument amplifier circuit adopts a current feedback structure to provide high input impedance and high common mode rejection ratio.

[0028] In a preferred example, the current feedback instrument amplifier circuit includes: a first resistor R1, a second resistor R2, a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a seventh PMOS transistor PM7, an eighth PMOS transistor PM8, a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a third capacitor C3, a sensor amplifier A1, and a high gain amplifier A2; wherein,

[0029] The gate end of the first PMOS transistor PM1 is used as the non-inverting input end (VIP) of the current feedback instrument amplifier circuit (IA); the drain end of the first PMOS transistor PM1 is connected to the drain end of the first NMOS transistor NM1, and is also connected to the gate end of the first NMOS transistor NM1, and is also connected to the gate end of the second NMOS transistor NM2, and is also connected to the negative input end of the sensing amplifier A1; the source end of the first PMOS transistor PM1 is connected to the left end of the first resistor R1, and is also connected to the drain end of the third PMOS transistor PM3;

[0030] The gate end of the second PMOS transistor PM2 is used as the negative input end (VIN) of the current feedback instrument amplifier circuit (IA); the drain end of the second PMOS transistor PM2 is connected to the drain end of the second NMOS transistor NM2 and is also connected to the positive input end of the sensing amplifier A1; the source end of the second PMOS transistor PM2 is connected to the right end of the first resistor R1 and is also connected to the drain end of the fourth PMOS transistor PM4;

[0031] The gate end of the third PMOS transistor PM3 is connected to the negative output end of the sensing amplifier A1 and is also connected to the gate end of the seventh PMOS transistor PM7; the drain end of the third PMOS transistor PM3 is connected to the left end of the first resistor R1 and is also connected to the source end of the first PMOS transistor PM1; the source end of the third PMOS transistor PM3 is connected to the high power signal VDD;

[0032] The gate end of the fourth PMOS transistor PM4 is connected to the positive output end of the sensing amplifier A1 and is also connected to the gate end of the eighth PMOS transistor PM8; the drain end of the fourth PMOS transistor PM4 is connected to the right end of the first resistor R1 and is also connected to the source end of the second PMOS transistor PM2; the source end of the fourth PMOS transistor PM4 is connected to the high power signal VDD;

[0033] The gate end of the first NMOS transistor NM1 is connected to the gate end of the second NMOS transistor NM2, and is also connected to the drain end of the first NMOS transistor NM1, and is also connected to the drain end of the first PMOS transistor PM1, and is also connected to the negative input end of the sensing amplifier A1; the source end of the first NMOS transistor NM1 is connected to the power ground signal GND;

[0034] The gate end of the second NMOS tube NM2 is connected to the gate end of the first NMOS tube NM1, and is also connected to the drain end of the first NMOS tube NM1, and is also connected to the drain end of the first PMOS tube PM1, and is also connected to the negative input end of the sensing amplifier A1; the drain end of the second NMOS tube NM2 is connected to the positive input end of the sensing amplifier A1, and is also connected to the drain end of the second PMOS tube PM2; the source end of the second NMOS tube NM2 is connected to the power ground signal GND;

[0035] The gate end of the fifth PMOS transistor PM5 is connected to the output end of the high-gain amplifier A2, and also serves as the output end (Vout) of the current feedback instrument amplifier circuit (IA); the drain end of the fifth PMOS transistor PM5 is connected to the drain end of the third NMOS transistor NM3, and is also connected to the gate end of the third NMOS transistor NM3, and is also connected to the positive input end of the high-gain amplifier A2; the source end of the fifth PMOS transistor PM5 is connected to the left end of the first resistor R2, and is also connected to the left end of the third capacitor C2, and is also connected to the drain end of the seventh PMOS transistor PM7;

[0036] The gate terminal of the sixth PMOS transistor PM6 is connected to the external output common mode voltage (Vout); the drain terminal of the sixth PMOS transistor PM6 is connected to the drain terminal of the fourth NMOS transistor NM4, and is also connected to the gate terminal of the fourth NMOS transistor NM4, and is also connected to the negative input terminal of the high gain amplifier A2; the source terminal of the sixth PMOS transistor PM6 is connected to the right end of the first resistor R2, and is also connected to the right end of the third capacitor C2, and is also connected to the drain terminal of the eighth PMOS transistor PM8;

[0037] The gate end of the seventh PMOS transistor PM7 is connected to the negative output end of the sensing amplifier A1 and the gate end of the third PMOS transistor PM3; the drain end of the seventh PMOS transistor PM7 is connected to the source end of the fifth PMOS transistor PM5 and the left end of the second resistor R2 and the left end of the third capacitor C3; the source end of the seventh PMOS transistor PM7 is connected to the high power signal VDD;

[0038] The gate end of the eighth PMOS transistor PM8 is connected to the positive output end of the sensing amplifier A1 and the gate end of the fourth PMOS transistor PM4; the drain end of the eighth PMOS transistor PM8 is connected to the source end of the sixth PMOS transistor PM6 and the right end of the second resistor R2 and the right end of the third capacitor C3; the source end of the eighth PMOS transistor PM8 is connected to the high power signal VDD;

[0039] The gate end of the third NMOS tube NM3 is connected to the drain end of the third NMOS tube NM3, and is also connected to the drain end of the fifth PMOS tube PM5, and is also connected to the positive input end of the high gain amplifier A2; the source end of the third NMOS tube NM3 is connected to the power ground signal GND;

[0040] The gate end of the fourth NMOS transistor NM4 is connected to the drain end of the fourth NMOS transistor NM4, and is also connected to the drain end of the sixth PMOS transistor PM6, and is also connected to the negative input end of the high gain amplifier A2; the source end of the fourth NMOS transistor NM4 is connected to the power ground signal GND;

[0041] In the current feedback instrument amplifier circuit (IA), the substrates of all NMOS tubes are connected to the power ground signal GND; and the substrates of all PMOS tubes are connected to the high power signal VDD.

[0042] In a preferred example, the transconductance amplifier circuit is connected in a unit gain negative feedback mode to improve the driving capability.

[0043] In a preferred embodiment, the transconductance amplifier circuit comprises:

[0044] A first transconductance pair of PMOS transistors includes a ninth PMOS transistor PM9 and a tenth PMOS transistor PM10;

[0045] The second transconductance pair of PMOS transistors includes an eleventh PMOS transistor PM11 and a twelfth PMOS transistor PM12;

[0046] and a voltage controlled current source VCVS;

[0047] The gate of the ninth PMOS transistor PM9 is used as a positive phase input terminal, and the gate of the tenth PMOS transistor PM10 is used as a negative phase input terminal;

[0048] The drain of the first transconductance pair PMOS tube is connected to the voltage-controlled current source VCVS;

[0049] The gates of the second transconductance pair of PMOS tubes are connected to each other, and the drains of the second transconductance pair of PMOS tubes are connected to the sources of the first transconductance pair of PMOS tubes;

[0050] The drain of the PMOS tube of the second transconductor pair serves as an output terminal.

[0051] In a preferred embodiment, the high-speed instrumentation amplifier is used in electrical impedance imaging technology.

[0052] In a preferred example, the electrical impedance imaging technology includes medical imaging and industrial imaging.

[0053] In a preferred embodiment, the medical imaging includes one of the following or any combination thereof: lung ventilation monitoring, cardiac imaging, bladder filling monitoring, breast cancer monitoring, stroke monitoring, brain edema identification, epilepsy imaging, real-time positioning of brain functional activities, bioimpedance analysis; and / or

[0054] The industrial imaging includes one of the following or any combination thereof: fluid flow monitoring, liquid level detection, solid particle distribution monitoring, material defect detection, and non-destructive detection.

[0055] In a preferred example, the transconductance amplifier circuit (OTA) comprises: a first transconductance pair of PMOS tubes, a second transconductance pair of PMOS tubes, and a voltage-controlled current source VCVS, wherein:

[0056] The first transconductance pair of PMOS transistors includes: a ninth PMOS transistor PM9 and a tenth PMOS transistor PM10, wherein the gate of the ninth PMOS transistor PM9 is used as a positive phase input terminal, and the drain is connected to a current source, and the gate of the tenth PMOS transistor PM10 is used as a negative phase input terminal, and the drain is connected to a current source;

[0057] The second transconductance pair of PMOS transistors includes: an eleventh PMOS transistor PM11 and a twelfth PMOS transistor PM12, wherein the gate of the eleventh PMOS transistor PM11 is connected to the gate of the twelfth PMOS transistor PM12, the drain of the eleventh PMOS transistor PM11 is connected to the source of the ninth PMOS transistor PM9, and the drain of the twelfth PMOS transistor PM12 serves as an output terminal; and

[0058] Two ends of the voltage-controlled current source VCVS are respectively connected to the drains of the ninth PMOS transistor PM9 and the tenth PMOS transistor PM10 of the first transconductance pair, and the drains of the eleventh PMOS transistor PM11 and the twelfth PMOS transistor PM12 of the second transconductance pair.

[0059] In a preferred example, the common mode rejection ratio of the current feedback instrument amplifier circuit is not less than 100 dB.

[0060] In a preferred example, the equivalent input noise of the high-speed instrumentation amplifier within the passband range is no more than 20 μV.

[0061] In a preferred embodiment, a high-speed instrumentation amplifier with low noise and high common-mode rejection ratio comprises: a high-pass filter circuit, a current feedback instrumentation amplifier circuit (IA), and a transconductance amplifier circuit (OTA), wherein:

[0062] The high-pass filter circuit comprises: a first capacitor CIN1, a second capacitor CIN2, a first adjustable pseudo resistor, and a second adjustable pseudo resistor, wherein the left plate of the first capacitor CIN1 is used as a positive phase input terminal (VP), and the right plate is respectively connected to the positive phase input terminal of the current feedback instrument amplifier circuit (IA) and the drain of the MOS tube MR11 in the first adjustable pseudo resistor; the left plate of the second capacitor CIN2 is used as a negative phase input terminal (VN), and the right plate is respectively connected to the negative phase input terminal of the current feedback instrument amplifier circuit (IA) and the drain of the MOS tube MR21 in the first adjustable pseudo resistor; The first adjustable pseudo resistor comprises a MOS transistor MR11 and a MOS transistor MR12 connected to each other at their sources, wherein the drain of the MOS transistor MR12 is connected to an input common mode signal VCM; the second adjustable pseudo resistor comprises a MOS transistor MR21 and a MOS transistor MR2 connected to each other at their sources, wherein the drain of the MOS transistor MR22 is connected to an input common mode signal VCM; and the gates of the MOS transistors MR11 and MR12 in the first adjustable pseudo resistor, and the gates of the MOS transistors MR21 and MR22 in the second adjustable pseudo resistor are respectively connected to a gate adjustable bias voltage Vg;

[0063] The output terminal of the current feedback instrumentation amplifier circuit (IA) is connected to the non-inverting input terminal of the transconductance amplifier circuit (OTA);

[0064] The negative phase input terminal of the transconductance amplifier circuit (OTA) is connected to its own output terminal, so that it forms a buffer in the form of unit gain negative feedback, and also serves as the output terminal of the entire circuit architecture.

[0065] In a preferred example, the transconductance amplifier circuit (OTA) includes: a ninth PMOS transistor PM9, a tenth PMOS transistor PM10, an eleventh PMOS transistor PM11, a twelfth PMOS transistor PM12, and a voltage-controlled current source VCVS, wherein:

[0066] The gate end of the ninth PMOS tube PM9 serves as the non-inverting input end (Vin+) of the transconductance amplifier circuit (OTA); the drain end of the ninth PMOS tube PM9 is connected to one end of the voltage-controlled current source VCVS, and is also connected to the drain end of the tenth PMOS tube PM10; the source end of the ninth PMOS tube PM9 is connected to the drain end of the eleventh PMOS tube PM11, and is also connected to the gate end of the eleventh PMOS tube PM11, and is also connected to the gate end of the twelfth PMOS tube PM12;

[0067] The gate end of the tenth PMOS transistor PM10 serves as the negative phase input end (Vin-) of the transconductance amplifier circuit (OTA); the drain end of the tenth PMOS transistor PM10 is connected to one end of the voltage-controlled current source VCVS and is also connected to the drain end of the ninth PMOS transistor PM9; the source end of the tenth PMOS transistor PM10 is connected to the drain end of the twelfth PMOS transistor PM12 and also serves as the output end (Vo) of the transconductance amplifier circuit (OTA);

[0068] The gate end of the eleventh PMOS transistor PM11 is connected to the gate end of the twelfth PMOS transistor PM12, and is also connected to the drain end of the eleventh PMOS transistor PM11, and is also connected to the source end of the ninth PMOS transistor PM9; the source end of the eleventh PMOS transistor PM11 is connected to the high power signal VDD;

[0069] The gate end of the twelfth PMOS transistor PM12 is connected to the gate end of the eleventh PMOS transistor PM11, and is also connected to the drain end of the eleventh PMOS transistor PM11, and is also connected to the source end of the ninth PMOS transistor PM9; the drain end of the twelfth PMOS transistor PM12 is connected to the source end of the tenth PMOS transistor PM10, and also serves as the output end (Vo) of the transconductance amplifier circuit (OTA); the source end of the twelfth PMOS transistor PM12 is connected to the high power signal VDD;

[0070] One end of the voltage-controlled current source VCVS is connected to the drain end of the ninth PMOS transistor PM9 and the drain end of the tenth PMOS transistor PM10 ; the other end is connected to the power ground signal GND.

[0071] In a preferred example, in the integrated circuit implementation of the high-pass filter circuit, the capacitance values ​​of the first capacitor CIN1 and the second capacitor CIN2 are the same and symmetrically matched, the parameter values ​​of the MOS tubes MR11 and MR12 in the first adjustable pseudo-resistor and the MOS tubes MR21 and MR22 in the second adjustable pseudo-resistor are the same and symmetrically matched, and one of the following integrated circuit layout methods or any combination thereof is used to achieve high matching of the first capacitor CIN1, the second capacitor CIN2, and the first adjustable pseudo-resistor and the second adjustable pseudo-resistor: two-dimensional common centroid symmetrical matching layout, symmetrical layout of redundant devices on the periphery of the MOS tube device, completely symmetrical signal routing, and ensuring equal length and width; the symmetrical matching of the first capacitor CIN1, the second capacitor CIN2, and the first adjustable pseudo-resistor and the second adjustable pseudo-resistor in the high-pass filter circuit is achieved through the integrated circuit layout design to ensure that their electrical performance is the same.

[0072] In a preferred example, the high-pass filter circuit is composed of a small-capacitance capacitor and an adjustable symmetrical pseudo-resistor with a gate bias voltage Vg, wherein the small-capacitance capacitor in the high-pass filter circuit refers to a first capacitor CIN1 and a second capacitor CIN2, and the adjustable symmetrical pseudo-resistor refers to a structure composed of a first adjustable pseudo-resistor and a second adjustable pseudo-resistor, and the first adjustable pseudo-resistor and the second adjustable pseudo-resistor each include two MOS tubes, and the gates of the MOS tubes are connected to the adjustable gate bias voltage Vg, and the cutoff frequency of the high-pass filter circuit is effectively adjusted by adjusting one of the following parameters or any combination thereof: adjusting the width of the MOS tube in the adjustable symmetrical pseudo-resistor, adjusting the length of the MOS tube in the adjustable symmetrical pseudo-resistor, and adjusting the size of the adjustable gate bias voltage Vg.

[0073] In the implementation of the present application, unlike the traditional instrumentation amplifier circuit for bioimpedance imaging, the high-speed instrumentation amplifier described in the present application includes three parts: a high-pass filter circuit, a current feedback instrumentation amplifier circuit (IA), and a transconductance amplifier circuit (OTA), which solves the problem that the traditional instrumentation amplifier cannot have high speed, low noise, high common mode rejection ratio, and DC voltage offset suppression at the same time. As the core module of the voltage acquisition system, the high-speed instrumentation amplifier can operate in a wide frequency band from several kHz to several MHz, providing high-quality voltage signals for the subsequent image reconstruction system.

[0074] Furthermore, the high-pass filter circuit can set the high-pass node fHPF at 10kHz, and its corresponding time constant τ is only 16uS, which well meets the needs of high speed. And the frequency of the high-pass node fHPF can be effectively adjusted by adjusting the width and length of the MOS tube in the adjustable symmetrical pseudo-resistance, or adjusting the gate adjustable bias voltage Vg. While suppressing the DC offset voltage, the input noise contributed by the high-pass filter circuit is also small; thus, the equivalent input noise of the entire high-speed instrument amplifier within the corresponding bandwidth is less than the 20uVrms required by the design index, which meets the low noise requirement. The current feedback instrument amplifier circuit (IA) achieves the performance requirements of high common-mode rejection ratio. The common-mode rejection ratio of the entire high-speed instrument amplifier within the bandwidth is higher than 100dB, and the common-mode rejection ratio is even higher than 120dB in the frequency range of 50kHz-500kHz of the effective signal. The transconductance amplifier circuit (OTA) is connected as a buffer in the form of unit gain negative feedback, which realizes the function of improving the overall load capacity of the circuit.

[0075] Therefore, the embodiments of the present application can not only take into account high speed, low noise, and high common mode rejection ratio at the same time, but also solve the problem of suppressing the DC offset voltage from the electrode.

[0076] A large number of technical features are recorded in the specification of this application, which are distributed in various technical solutions. If all possible combinations of technical features of this application (i.e., technical solutions) are to be listed, the specification will be too long. In order to avoid this problem, the various technical features disclosed in the above-mentioned invention content of this application, the various technical features disclosed in the various embodiments and examples below, and the various technical features disclosed in the accompanying drawings can be freely combined with each other to form various new technical solutions (these technical solutions are all deemed to have been recorded in this specification), unless the combination of such technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed, and features C and D are equivalent technical means that play the same role. Technically, only one can be used, and it is impossible to use them at the same time. Feature E can be combined with feature C technically. Then, the solution of A+B+C+D should not be deemed to have been recorded because it is technically infeasible, and the solution of A+B+C+E should be deemed to have been recorded. BRIEF DESCRIPTION OF THE DRAWINGS

[0077] Figure 1 It is a schematic diagram of the principle of the EIT measurement system;

[0078] Figure 2 is a schematic structural diagram of a high-speed instrumentation amplifier with low noise and high common-mode rejection ratio according to the first embodiment of the present application;

[0079] Figure 3 It is a specific structural schematic diagram of a high-speed instrumentation amplifier with low noise and high common-mode rejection ratio according to the first embodiment of the present application;

[0080] Figure 4 It is a schematic diagram of the specific structure of a high-speed instrumentation amplifier with low noise and high common-mode rejection ratio according to the first embodiment of the present application. DETAILED DESCRIPTION

[0081] In the following description, many technical details are provided to help readers better understand the present application. However, those skilled in the art can understand that the technical solution claimed in the present application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0082] Description of some concepts:

[0083] Electrical impedance tomography: a non-invasive imaging and detection technology that infers the impedance distribution inside the object by inputting a tiny alternating current into the object and measuring the voltage response at different positions, thereby achieving non-contact detection of the internal structure and properties of the object.

[0084] Instrumentation amplifier: An amplifier circuit composed of an operational amplifier and a feedback circuit that can provide high input impedance and low output impedance and is used to amplify and process weak signals output by sensors.

[0085] Common-mode rejection ratio (CMRR): A parameter that measures the ability of an instrument amplifier to suppress common-mode signal interference. It indicates the amplifier's amplification ratio for differential-mode signals and common-mode signals, expressed in dB.

[0086] Common-mode signal: A signal that acts on both input terminals of an instrumentation amplifier simultaneously.

[0087] Differential mode signal: The difference between the signals applied to the two input terminals of the instrumentation amplifier.

[0088] DC Rejection: The ability of an instrumentation amplifier to reject the DC component of the bias at its input.

[0089] Low Frequency Cutoff: The frequency point at which the low-frequency response of an instrumentation amplifier drops off.

[0090] Bandwidth: The frequency range over which an instrumentation amplifier has a relatively flat frequency response.

[0091] In order to make the objectives, technical solutions and advantages of the present application more clear, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0092] The first embodiment of the present application relates to a high-speed instrumentation amplifier with low noise and high common-mode rejection ratio, and its structure is as follows: Figure 2 As shown, it includes: a high-pass filter circuit, a current feedback instrument amplifier circuit (IA), and a transconductance amplifier circuit (OTA).

[0093] The high-pass filter circuit comprises: a first capacitor CIN1, a second capacitor CIN2, a first adjustable pseudo resistor, and a second adjustable pseudo resistor, wherein the left plate of the first capacitor CIN1 is used as a positive phase input terminal (VP), and the right plate is respectively connected to the positive phase input terminal of the current feedback instrument amplifier circuit (IA) and the drain of the MOS tube MR11 in the first adjustable pseudo resistor; the left plate of the second capacitor CIN2 is used as a negative phase input terminal (VN), and the right plate is respectively connected to the negative phase input terminal of the current feedback instrument amplifier circuit (IA) and the drain of the MOS tube MR21 in the first adjustable pseudo resistor; The first adjustable pseudo-resistor includes a MOS transistor MR11 and a MOS transistor MR12 connected to their sources, wherein the drain of the MOS transistor MR12 is connected to an input common-mode signal VCM; the second adjustable pseudo-resistor includes a MOS transistor MR21 and a MOS transistor MR2 connected to their sources, wherein the drain of the MOS transistor MR22 is connected to an input common-mode signal VCM; and the gates of the MOS transistors MR11 and MR12 in the first adjustable pseudo-resistor, and the gates of the MOS transistors MR21 and MR22 in the second adjustable pseudo-resistor are respectively connected to a gate adjustable bias voltage Vg.

[0094] Furthermore, the output terminal of the current feedback instrument amplifier circuit (IA) is connected to the non-inverting input terminal of the transconductance amplifier circuit (OTA).

[0095] Furthermore, the negative phase input terminal of the transconductance amplifier circuit (OTA) is connected to its own output terminal, so that it forms a buffer in the form of unit gain negative feedback, and also serves as the output terminal of the entire circuit architecture.

[0096] The circuit structure of the high-speed instrumentation amplifier with low noise and high common-mode rejection ratio of this embodiment is further described in detail below.

[0097] High pass filter circuit

[0098] In general, the current feedback instrument amplifier circuit (IA) includes: an input differential amplifier circuit, an input-stage current mirror source extension circuit, a secondary amplifier circuit, and an output buffer circuit. The input differential amplifier circuit includes: a first PMOS tube PM1 and a second PMOS tube PM2, wherein the drain of the first PMOS tube PM1 is connected to the drain of the first NMOS tube NM1, and the drain of the second PMOS tube PM2 is connected to the drain of the second NMOS tube NM2. The input-stage current mirror source extension circuit includes: a third PMOS tube PM3 and a fourth PMOS tube PM4, wherein the drain of the third PMOS tube PM3 is connected to the source of the first PMOS tube PM1, and the drain of the fourth PMOS tube PM4 is connected to the source of the second PMOS tube PM2. The secondary amplifier circuit comprises: a fifth PMOS tube PM5, a sixth PMOS tube PM6, a third NMOS tube NM3, a fourth NMOS tube NM4, and a high-gain amplifier A2, wherein the drain of the fifth PMOS tube PM5 is connected to the drain of the third NMOS tube NM3 and the positive input terminal of the high-gain amplifier A2, and the drain of the sixth PMOS tube PM6 is connected to the drain of the fourth NMOS tube NM4 and the negative input terminal of the high-gain amplifier A2. The output buffer circuit comprises: a seventh PMOS tube PM7 and an eighth PMOS tube PM8, wherein the drain of the seventh PMOS tube PM7 is connected to the source of the fifth PMOS tube PM5, and the drain of the eighth PMOS tube PM8 is connected to the source of the sixth PMOS tube PM6.

[0099] More specifically, the high-pass filter circuit includes a first capacitor C IN1 , the second capacitor C IN2 , the first adjustable pseudo-resistance M R11 and M R12 , the second adjustable pseudo resistor M R21 and M R22 ,like Figure 2 shown.

[0100] The first capacitor C IN1 The left plate is used as the positive input terminal (V P ), the right side plate of which is respectively connected to the positive phase input terminal of the current feedback instrument amplifier circuit (IA) and the MOS tube M in the first adjustable pseudo resistor R11 The drain

[0101] The second capacitor C IN2 The left plate is used as the negative input terminal (V N ), the right side plate of which is respectively connected to the negative input terminal of the current feedback instrument amplifier circuit (IA) and the MOS tube M in the first adjustable pseudo resistor R21 The drain end;

[0102] The MOS tube M in the first adjustable pseudo resistor R11and the MOS tube M in the first adjustable pseudo resistor R12 The source end of the second adjustable pseudo resistor is connected to the MOS tube M R12 The drain terminal is connected to an input common-mode signal V CM ; MOS tube M in the second adjustable pseudo resistor R21 and the MOS tube M in the second adjustable pseudo resistor R22 The source end of the second adjustable pseudo resistor is connected to the MOS tube M R22 The drain terminal is connected to an input common-mode signal V CM ;

[0103] The first adjustable pseudo resistor M R11 and M R12 , the second adjustable pseudo resistor M R21 and M R22 The gate terminals are all connected to the gate adjustable bias voltage Vg;

[0104] The output end of the current feedback instrument amplifier circuit (IA) is connected to the non-inverting input end of the transconductance amplifier circuit (OTA);

[0105] It should be noted that the negative input of the transconductance amplifier circuit (OTA) is connected to its own output, and also serves as the output of the entire circuit architecture. This connection method constitutes a buffer in the form of unit gain negative feedback (a buffer refers to an operational amplifier circuit in a negative feedback connection method of "connecting the output of the operational amplifier directly to the inverting input of the operational amplifier").

[0106] Unlike the traditional instrumentation amplifier circuit, this application uses a low-noise, high common-mode rejection ratio high-speed instrumentation amplifier, including a high-pass filter circuit, a current feedback instrumentation amplifier circuit (IA), and a transconductance amplifier circuit (OTA). Among them, the realization of the high-speed high-pass pole in the high-pass filter circuit is particularly critical. The following is a specific typical value f that can be applied to the EIT system HPF =10kHz as an example, the corresponding time constant τ is only 16uS. This paper explains the problems existing in the previous circuit and proposes our new solution.

[0107] After in-depth research and analysis, the inventor of this application found that by building a high-pass filter circuit and setting f HPF =10kHz high-speed high-pass node, the following problems exist:

[0108] (1) If the traditional RC high-pass filter circuit is used:

[0109] When a resistor with a smaller resistance value is selected, there will be a problem that the capacitance value is large, resulting in a too large capacitance area (for example, the resistance R is 10kΩ, and the corresponding required capacitance C is 1600pF), which is difficult to implement on chip;

[0110] When a capacitor with a smaller resistance value is selected, there will be a problem that the larger resistance value causes excessive noise at the circuit input end, thereby drowning out the minimum effective signal (for example, if the capacitor C is 10pF, the required resistance R is 1600kΩ, because the equivalent input noise it generates has exceeded 70% of the equivalent input noise of the overall circuit), which cannot meet the circuit's low noise requirements.

[0111] (2) If the traditional high-pass filter circuit with pseudo-resistance plus capacitor is used, the equivalent resistance value of the pseudo-resistance will be too large (10 12 ~10 14 Ω), even if the lowest capacitance value that can be achieved by the capacitor in the process library is used, only a low-frequency high-pass pole can be achieved, which cannot meet the high-speed requirements of the EIT acquisition system. The use of a DC-Servo Loop and a ripple suppression loop (RRL) also has the problem of being unable to achieve a high-speed high-pass pole, and will also increase the complexity of the circuit and increase power consumption.

[0112] In this regard, the inventor of the present application creatively adopts a high-pass filter circuit constructed by a small-capacitance capacitor and an adjustable symmetrical pseudo-resistor with a gate bias voltage Vg, as shown in the following figure: Figure 2 The high-pass filter circuit is shown in the figure. By adjusting the width and length of the MOS tube in the adjustable symmetrical pseudo-resistance, or adjusting the gate adjustable bias voltage Vg, the frequency of the high-pass node can be effectively adjusted. Take the XH018 process in X-FAB used in this circuit as an example:

[0113] (1) Take the first capacitor C IN1 , the second capacitor C IN2 Area: 2×28×30um 2 , the corresponding capacitance value is 11.75pF; take the gate adjustable bias voltage Vg as 1.20V, and adjust the first adjustable pseudo resistance M in turn R11 and M R12 , the second adjustable pseudo resistor M R21 and M R22 The width-to-length ratio is 10um / 1um, 20um / 1um, 30um / 1um and up to 100um / 1um, which can be realized in turn. HPF The equivalent input noise of the entire high-speed instrumentation amplifier within the corresponding bandwidth is less than the 20uVrms required by the design index, meeting the low noise requirement.

[0114] (2) Take the first capacitor C IN1 , the second capacitor C IN2 Area: 2×28×30um 2 , the corresponding capacitance value is

[0115] 11.75pF; take the first adjustable pseudo resistor M R11 and M R12 , the second adjustable pseudo resistor M R21 and M R22 The width-to-length ratio is 40um / 1um. By adjusting the gate adjustable bias voltage Vg to 1.25, 1.20, and 1.15V, f can be achieved in turn. HPF The equivalent input noise of the entire high-speed instrumentation amplifier within the corresponding bandwidth is less than the 20uVrms required by the design index, meeting the low noise requirement.

[0116] Optionally, in the specific implementation of the integrated circuit of the high-pass filter circuit, the first capacitor C IN1 With the second capacitor C IN2 , the first adjustable pseudo-resistance M R11 and M R12 With the second adjustable pseudo resistor M R21 and M R22 , should be matched as much as possible to achieve the same electrical performance. When drawing the integrated circuit layout, a series of matching methods are used, including but not limited to two-dimensional common centroid symmetric matching, symmetrically adding a circle of redundant devices around the MOS tube, and symmetrical signal routing with completely equal length and width when connecting the layout, which can improve the matching degree of the high-pass filter circuit and thus improve the actual performance of the circuit.

[0117] It should be noted that in other embodiments of the present application, the high-pass filter circuit described above can be used alone or in combination with other circuits.

[0118] Current Feedback Instrumentation Amplifier Circuit

[0119] In general, the current feedback instrument amplifier circuit (IA) includes a first resistor R1, a second resistor R2, a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a seventh PMOS transistor PM7, an eighth PMOS transistor PM8, a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a third capacitor C3, a sensing amplifier A1, and a high gain amplifier A2, such as Figure 3 shown.

[0120] The gate end of the first PMOS transistor PM1 is used as the non-inverting input end (VIP) of the current feedback instrument amplifier circuit (IA); the drain end of the first PMOS transistor PM1 is connected to the drain end of the first NMOS transistor NM1, and is also connected to the gate end of the first NMOS transistor NM1, and is also connected to the gate end of the second NMOS transistor NM2, and is also connected to the negative input end of the sensing amplifier A1; the source end of the first PMOS transistor PM1 is connected to the left end of the first resistor R1, and is also connected to the drain end of the third PMOS transistor PM3;

[0121] The gate end of the second PMOS transistor PM2 is used as the negative phase input end (VIN) of the current feedback instrument amplifier circuit (IA); the drain end of the second PMOS transistor PM2 is connected to the drain end of the second NMOS transistor NM2 and is also connected to the positive input end of the sensing amplifier A1; the source end of the second PMOS transistor PM2 is connected to the right end of the first resistor R1 and is also connected to the drain end of the fourth PMOS transistor PM4;

[0122] The gate end of the third PMOS transistor PM3 is connected to the negative output end of the sensing amplifier A1 and is also connected to the gate end of the seventh PMOS transistor PM7; the drain end of the third PMOS transistor PM3 is connected to the left end of the first resistor R1 and is also connected to the source end of the first PMOS transistor PM1; the source end of the third PMOS transistor PM3 is connected to the high power signal VDD;

[0123] The gate end of the fourth PMOS transistor PM4 is connected to the positive output end of the sensing amplifier A1 and is also connected to the gate end of the eighth PMOS transistor PM8; the drain end of the fourth PMOS transistor PM4 is connected to the right end of the first resistor R1 and is also connected to the source end of the second PMOS transistor PM2; the source end of the fourth PMOS transistor PM4 is connected to the high power signal VDD;

[0124] The gate end of the first NMOS transistor NM1 is connected to the gate end of the second NMOS transistor NM2, and is also connected to the drain end of the first NMOS transistor NM1, and is also connected to the drain end of the first PMOS transistor PM1, and is also connected to the negative input end of the sensing amplifier A1; the source end of the first NMOS transistor NM1 is connected to the power ground signal GND;

[0125] The gate end of the second NMOS tube NM2 is connected to the gate end of the first NMOS tube NM1, and is also connected to the drain end of the first NMOS tube NM1, and is also connected to the drain end of the first PMOS tube PM1, and is also connected to the negative input end of the sensing amplifier A1; the drain end of the second NMOS tube NM2 is connected to the positive input end of the sensing amplifier A1, and is also connected to the drain end of the second PMOS tube PM2; the source end of the second NMOS tube NM2 is connected to the power ground signal GND;

[0126] The gate end of the fifth PMOS transistor PM5 is connected to the output end of the high-gain amplifier A2, and also serves as the output end (Vout) of the current feedback instrument amplifier circuit (IA); the drain end of the fifth PMOS transistor PM5 is connected to the drain end of the third NMOS transistor NM3, and is also connected to the gate end of the third NMOS transistor NM3, and is also connected to the positive input end of the high-gain amplifier A2; the source end of the fifth PMOS transistor PM5 is connected to the left end of the first resistor R2, and is also connected to the left end of the third capacitor C2, and is also connected to the drain end of the seventh PMOS transistor PM7;

[0127] The gate terminal of the sixth PMOS transistor PM6 is connected to the external output common mode voltage (Vout); the drain terminal of the sixth PMOS transistor PM6 is connected to the drain terminal of the fourth NMOS transistor NM4, and is also connected to the gate terminal of the fourth NMOS transistor NM4, and is also connected to the negative input terminal of the high gain amplifier A2; the source terminal of the sixth PMOS transistor PM6 is connected to the right end of the first resistor R2, and is also connected to the right end of the third capacitor C2, and is also connected to the drain terminal of the eighth PMOS transistor PM8;

[0128] The gate end of the seventh PMOS transistor PM7 is connected to the negative output end of the sensing amplifier A1 and the gate end of the third PMOS transistor PM3; the drain end of the seventh PMOS transistor PM7 is connected to the source end of the fifth PMOS transistor PM5 and the left end of the second resistor R2 and the left end of the third capacitor C3; the source end of the seventh PMOS transistor PM7 is connected to the high power signal VDD;

[0129] The gate end of the eighth PMOS transistor PM8 is connected to the positive output end of the sensing amplifier A1 and the gate end of the fourth PMOS transistor PM4; the drain end of the eighth PMOS transistor PM8 is connected to the source end of the sixth PMOS transistor PM6 and the right end of the second resistor R2 and the right end of the third capacitor C3; the source end of the eighth PMOS transistor PM8 is connected to the high power signal VDD;

[0130] The gate end of the third NMOS transistor NM3 is connected to the drain end of the third NMOS transistor NM3, and is also connected to the drain end of the fifth PMOS transistor PM5, and is also connected to the positive input end of the high gain amplifier A2; the source end of the third NMOS transistor NM3 is connected to the power ground signal GND;

[0131] The gate end of the fourth NMOS transistor NM4 is connected to the drain end of the fourth NMOS transistor NM4, and is also connected to the drain end of the sixth PMOS transistor PM6, and is also connected to the negative input end of the high gain amplifier A2; the source end of the fourth NMOS transistor NM4 is connected to the power ground signal GND;

[0132] In the current feedback instrumentation amplifier circuit (IA), the substrates of all NMOS tubes are connected to the power ground signal GND; the substrates of all PMOS tubes are connected to the high power signal VDD.

[0133] like Figure 3 As shown, the sense amplifier A1 accurately balances the drain current of the first PMOS tube PM1 and the second PMOS tube PM2 by adjusting the complementary current flowing through the third PMOS tube PM3 and the fourth PMOS tube PM4 of the current mirror. The direct result of this is that the input differential voltage is forced to flow through the first resistor R1, so the first PMOS tube PM1 and the second PMOS tube PM2 of the input stage essentially act as a unity gain buffer. Similarly, the high gain amplifier A2 balances the drain current of the fifth PMOS tube PM5 and the sixth PMOS tube PM6 output transconductance stage. Since the seventh PMOS tube PM7 and the eighth PMOS tube PM8 flowing through the current mirror are exact copies of the third PMOS tube PM3 and the fourth PMOS tube PM4 of the current mirror, respectively, the output voltage Vout appears on the second resistor R2. Therefore, the gain of the current feedback instrument amplifier circuit (IA) is given by the ratio R2 / R1. At the same time, the third capacitor C3 is connected in parallel with the second resistor R2 to form a main pole, thereby setting the current feedback instrument amplifier circuit (IA) f LPF Corresponding -3dB bandwidth.

[0134] Optionally, in this embodiment, f LPF It is set between 1MHz and 3MHz, preferably, set at 2MHz. At this time, the common mode rejection ratio of the entire circuit within the bandwidth is higher than 100dB, and the common mode rejection ratio within the effective signal frequency range of 50kHz-500kHz is even higher than 120dB, which well realizes the performance requirements of high common mode rejection ratio.

[0135] Transconductance amplifier circuit

[0136] In general, the transconductance amplifier circuit (OTA) includes: a first transconductance pair of PMOS tubes, a second transconductance pair of PMOS tubes, and a voltage-controlled current source VCVS. The first transconductance pair of PMOS tubes includes: a ninth PMOS tube PM9 and a tenth PMOS tube PM10, wherein the gate of the ninth PMOS tube PM9 is used as a positive phase input terminal, and the drain is connected to a current source, and the gate of the tenth PMOS tube PM10 is used as a negative phase input terminal, and the drain is connected to a current source. The second transconductance pair of PMOS tubes includes: an eleventh PMOS tube PM11 and a twelfth PMOS tube PM12, wherein the gate of the eleventh PMOS tube PM11 is connected to the gate of the twelfth PMOS tube PM12, the drain of the eleventh PMOS tube PM11 is connected to the source of the ninth PMOS tube PM9, and the drain of the twelfth PMOS tube PM12 is used as an output terminal. Two ends of the voltage-controlled current source VCVS are respectively connected to the drains of the ninth PMOS transistor PM9 and the tenth PMOS transistor PM10 of the first transconductance pair, and the drains of the eleventh PMOS transistor PM11 and the twelfth PMOS transistor PM12 of the second transconductance pair.

[0137] More specifically, the transconductance amplifier circuit (OTA) includes a ninth PMOS transistor PM9, a tenth PMOS transistor PM10, an eleventh PMOS transistor PM11, a twelfth PMOS transistor PM12, and a voltage-controlled current source VCVS, such as Figure 4 shown.

[0138] The gate terminal of the ninth PMOS tube PM9 serves as the non-inverting input terminal (Vin+) of the transconductance amplifier circuit (OTA); the drain terminal of the ninth PMOS tube PM9 is connected to one end of the voltage-controlled current source VCVS and is also connected to the drain terminal of the tenth PMOS tube PM10; the source terminal of the ninth PMOS tube PM9 is connected to the drain terminal of the eleventh PMOS tube PM11 and is also connected to the gate terminal of the eleventh PMOS tube PM11 and is also connected to the gate terminal of the twelfth PMOS tube PM12;

[0139] The gate terminal of the tenth PMOS tube PM10 serves as the negative phase input terminal (Vin-) of the transconductance amplifier circuit (OTA); the drain terminal of the tenth PMOS tube PM10 is connected to one end of the voltage-controlled current source VCVS and is also connected to the drain terminal of the ninth PMOS tube PM9; the source terminal of the tenth PMOS tube PM10 is connected to the drain terminal of the twelfth PMOS tube PM12 and also serves as the output terminal (Vo) of the transconductance amplifier circuit (OTA);

[0140] The gate end of the eleventh PMOS transistor PM11 is connected to the gate end of the twelfth PMOS transistor PM12, and is also connected to the drain end of the eleventh PMOS transistor PM11, and is also connected to the source end of the ninth PMOS transistor PM9; the source end of the eleventh PMOS transistor PM11 is connected to the high power signal VDD;

[0141] The gate end of the twelfth PMOS transistor PM12 is connected to the gate end of the eleventh PMOS transistor PM11, and is also connected to the drain end of the eleventh PMOS transistor PM11, and is also connected to the source end of the ninth PMOS transistor PM9; the drain end of the twelfth PMOS transistor PM12 is connected to the source end of the tenth PMOS transistor PM10, and also serves as the output end (Vo) of the transconductance amplifier circuit (OTA); the source end of the twelfth PMOS transistor PM12 is connected to the high power signal VDD;

[0142] One end of the voltage-controlled current source VCVS is connected to the drain end of the ninth PMOS transistor PM9 and the drain end of the tenth PMOS transistor PM10 ; the other end is connected to the power ground signal GND.

[0143] It should be pointed out that according to Figure 4 The connection shown in detail in the figure becomes a transconductance amplifier circuit (OTA) in the form of a unity gain negative feedback buffer. This connection method improves the load capacity of the overall circuit. When the load capacitance is 10pF, its f LPFThe corresponding -3dB bandwidth drops from 2MHz to 1.986MHz, a decrease of less than 1%. When the load capacitance is 20pF, its f LPF The corresponding -3dB bandwidth is still 1.875MHz, which is still much larger than the maximum signal frequency of 500kHz of the electrical impedance tomography (EIT) pulmonary function monitoring system.

[0144] Optionally, the low-noise, high-common-mode rejection ratio high-speed instrumentation amplifier of the present application is used for electrical impedance imaging technology, which includes electrical impedance imaging technology in the medical field and electrical impedance imaging technology in the industrial field.

[0145] Optionally, the electrical impedance imaging technology in the medical field is one of the following or any combination thereof: pulmonary ventilation monitoring, cardiac imaging, bladder filling monitoring, breast cancer monitoring, stroke monitoring, cerebral edema identification, epilepsy imaging, real-time positioning of brain functional activities, and bioimpedance analysis.

[0146] Optionally, the industrial field electrical impedance imaging technology is one of the following or any combination thereof: fluid flow monitoring, liquid level detection, solid particle distribution monitoring, material defect detection, and non-destructive detection.

[0147] Optionally, the high-speed instrument amplifier adopts a three-stage cascade structure to achieve indicators such as wide bandwidth, low noise, and high common-mode rejection ratio, meeting the performance requirements of electrical impedance imaging technology for instrument amplifiers.

[0148] Optionally, the overall bandwidth of the instrument amplifier can reach 2MHz, the common mode rejection ratio can reach 120dB, and the total harmonic distortion is less than 1%, which meets the signal detection accuracy requirements of electrical impedance imaging.

[0149] Optionally, in the application of electrical impedance imaging technology, the use of this high-speed low-noise instrument amplifier can effectively solve the problems of narrow bandwidth and low common-mode rejection ratio of existing amplifiers, and improve imaging quality and detection accuracy.

[0150] Technical Effects

[0151] In the above embodiment, the high-pass filter circuit uses a symmetrical pseudo-resistor with a gate bias voltage Vg and a capacitor with a smaller capacitance value to set a high-pass pole, and the frequency of the high-pass pole can be adjusted by changing the width, length, and Vg size of the MOS tube in the pseudo-resistor. Compared with the traditional high-pass filter circuit, this structure has the characteristics of high speed, and at the same time, the pole of the high-pass filter circuit can be set at a higher frequency under the constraints of smaller circuit noise and layout area. The current-type feedback instrument amplifier circuit provides high input impedance and high common-mode rejection ratio, and it also has the function of low-pass filtering. The current-type feedback instrument amplifier and the high-pass filter circuit jointly construct the passband of the entire high-speed instrument amplifier, which has a strong suppression ability for input DC offset and out-of-band noise. The transconductance amplifier circuit is connected in a unit gain negative feedback form, which improves the load capacity of the overall circuit.

[0152] In summary, unlike the traditional instrumentation amplifier circuit for bioimpedance imaging, the high-speed instrumentation amplifier proposed in this application includes three parts: a high-pass filter circuit, a current feedback instrumentation amplifier circuit (IA), and a transconductance amplifier circuit (OTA), which solves the problem that the traditional instrumentation amplifier cannot have high speed, low noise, high common mode rejection ratio, and DC voltage offset suppression at the same time. As the core module of the voltage acquisition system, the high-speed instrumentation amplifier can operate in a wide frequency band from several kHz to several MHz, providing high-quality voltage signals for the subsequent image reconstruction system.

[0153] like Figure 2 As shown, the high-pass filter circuit can be high-pass node f HPF When set at 10kHz, the corresponding time constant τ is only 16uS, which satisfies the need for high speed. The high-pass node f can be effectively adjusted by adjusting the width and length of the MOS tube in the adjustable symmetrical pseudo-resistance or adjusting the gate adjustable bias voltage Vg. HPF frequency. While suppressing the DC offset voltage, the high-pass filter circuit also contributes less input noise, so that the equivalent input noise of the entire high-speed instrumentation amplifier within the corresponding bandwidth is less than the 20uVrms required by the design index, meeting the low noise requirement. The current feedback instrumentation amplifier circuit (IA) achieves the performance requirements of high common-mode rejection ratio. The common-mode rejection ratio of the entire high-speed instrumentation amplifier within the bandwidth is higher than 100dB, and the common-mode rejection ratio is even higher than 120dB in the frequency range of 50kHz-500kHz of the effective signal. The transconductance amplifier circuit (OTA) is connected as a buffer in the form of unity gain negative feedback, which realizes the function of improving the overall load capacity of the circuit. When the load capacitance is large, the impact on the -3dB bandwidth of the high-pass filter is small.

[0154] It should be noted that in the application documents of this patent, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one" do not exclude the existence of other identical elements in the process, method, article or device including the elements. In the application documents of this patent, if it is mentioned that an action is performed according to an element, it means that the action is performed at least according to the element, which includes two situations: performing the action only according to the element, and performing the action according to the element and other elements. Expressions such as multiple, multiple, and multiple include 2, 2 times, 2 kinds, and more than 2, more than 2 times, and more than 2 kinds.

[0155] All documents mentioned in this application are considered to be included in the disclosure of this application as a whole, so that they can be used as the basis for modification when necessary. In addition, it should be understood that after reading the above disclosure of this application, those skilled in the art can make various changes or modifications to this application, and these equivalent forms also fall within the scope of protection claimed in this application.

Claims

1. A high-pass filter circuit, characterized in that: include: A first capacitor, a second capacitor, a first adjustable pseudo resistor, and a second adjustable pseudo resistor; The first terminal of the first capacitor is used as a non-inverting input terminal, and the second terminal is respectively connected to the non-inverting input terminal of the current feedback instrumentation amplifier circuit and the first node of the first adjustable pseudo-resistance; The first terminal of the second capacitor is used as a negative phase input terminal, and the second terminal is respectively connected to the negative phase input terminal of the current feedback instrument amplifier circuit and the first node of the second adjustable pseudo resistor; The second node of the first adjustable pseudo resistor and the second adjustable pseudo resistor is connected to the common mode signal input terminal; The control terminals of the first adjustable pseudo resistor and the second adjustable pseudo resistor are connected to an adjustable voltage to adjust the value of the pseudo resistor; wherein, The high-pass filter circuit realizes high-pass filtering by connecting a small-capacitance capacitor and an adjustable pseudo-resistance, wherein the small-capacitance capacitor refers to a capacitor with a capacitance value less than 100pF.

2. The high-pass filter circuit according to claim 1, characterized in that: The high-pass filter circuit uses a connection method of a small-capacitance capacitor and an adjustable pseudo resistor to achieve high-pass filtering. The small-capacitance capacitor refers to a capacitor with a capacitance value less than 100pF, which can achieve fully integrated on-chip capacitance.

3. The high-pass filter circuit according to claim 1, characterized in that: The high-pass filter circuit can be used in the front end of an analog circuit such as an instrument amplifier to provide a high-pass filter function.

4. A high-speed instrumentation amplifier with low noise and high common-mode rejection ratio, characterized in that: include: A high-pass filter circuit, used for providing a high-pass filter function; A current feedback instrument amplifier circuit, whose input end is connected to the high-pass filter circuit, is used to provide high input impedance and high common mode rejection ratio, wherein the high input impedance refers to an input impedance greater than 1MΩ; and a transconductance amplifier circuit, whose input end is connected to the output end of the current feedback instrumentation amplifier circuit, for improving the load driving capability; The high-pass filter circuit uses a connection method of a small-capacitance capacitor and an adjustable pseudo-resistance to achieve high-pass filtering. The small-capacitance capacitor refers to a capacitor with a capacitance value less than 100pF to achieve a fully integrated on-chip capacitor.

5. The high-speed instrumentation amplifier according to claim 4, characterized in that: The high-pass filter circuit comprises: A first capacitor, a second capacitor, a first adjustable pseudo resistor, and a second adjustable pseudo resistor; The first terminal of the first capacitor is used as a non-inverting input terminal, and the second terminal is respectively connected to the non-inverting input terminal of the current feedback instrumentation amplifier circuit and the first node of the first adjustable pseudo-resistance; The first terminal of the second capacitor is used as a negative phase input terminal, and the second terminal is respectively connected to the negative phase input terminal of the current feedback instrument amplifier circuit and the first node of the second adjustable pseudo resistor; The second node of the first adjustable pseudo resistor and the second adjustable pseudo resistor is connected to the common mode signal input terminal; Control terminals of the first adjustable pseudo resistor and the second adjustable pseudo resistor are connected to an adjustable voltage to adjust the value of the pseudo resistor.

6. The high-speed instrumentation amplifier according to claim 4, characterized in that: The current feedback instrument amplifier circuit adopts a current feedback structure to provide high input impedance and high common mode rejection ratio.

7. The high-speed instrumentation amplifier according to claim 4, characterized in that: The current feedback instrument amplifier circuit includes: a first resistor R1, a second resistor R2, a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a seventh PMOS transistor PM7, an eighth PMOS transistor PM8, a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a third capacitor C3, a sensor amplifier A1, and a high gain amplifier A2; wherein, The gate end of the first PMOS transistor PM1 is used as the non-inverting input end (VIP) of the current feedback instrument amplifier circuit (IA); the drain end of the first PMOS transistor PM1 is connected to the drain end of the first NMOS transistor NM1, and is also connected to the gate end of the first NMOS transistor NM1, and is also connected to the gate end of the second NMOS transistor NM2, and is also connected to the negative input end of the sensing amplifier A1; the source end of the first PMOS transistor PM1 is connected to the left end of the first resistor R1, and is also connected to the drain end of the third PMOS transistor PM3; The gate end of the second PMOS transistor PM2 is used as the negative input end (VIN) of the current feedback instrument amplifier circuit (IA); the drain end of the second PMOS transistor PM2 is connected to the drain end of the second NMOS transistor NM2 and is also connected to the positive input end of the sensing amplifier A1; the source end of the second PMOS transistor PM2 is connected to the right end of the first resistor R1 and is also connected to the drain end of the fourth PMOS transistor PM4; The gate end of the third PMOS transistor PM3 is connected to the negative output end of the sensing amplifier A1 and is also connected to the gate end of the seventh PMOS transistor PM7; the drain end of the third PMOS transistor PM3 is connected to the left end of the first resistor R1 and is also connected to the source end of the first PMOS transistor PM1; the source end of the third PMOS transistor PM3 is connected to the high power signal VDD; The gate end of the fourth PMOS transistor PM4 is connected to the positive output end of the sensing amplifier A1 and is also connected to the gate end of the eighth PMOS transistor PM8; the drain end of the fourth PMOS transistor PM4 is connected to the right end of the first resistor R1 and is also connected to the source end of the second PMOS transistor PM2; the source end of the fourth PMOS transistor PM4 is connected to the high power signal VDD; The gate end of the first NMOS transistor NM1 is connected to the gate end of the second NMOS transistor NM2, and is also connected to the drain end of the first NMOS transistor NM1, and is also connected to the drain end of the first PMOS transistor PM1, and is also connected to the negative input end of the sensing amplifier A1; the source end of the first NMOS transistor NM1 is connected to the power ground signal GND; The gate end of the second NMOS tube NM2 is connected to the gate end of the first NMOS tube NM1, and is also connected to the drain end of the first NMOS tube NM1, and is also connected to the drain end of the first PMOS tube PM1, and is also connected to the negative input end of the sensing amplifier A1; the drain end of the second NMOS tube NM2 is connected to the positive input end of the sensing amplifier A1, and is also connected to the drain end of the second PMOS tube PM2; the source end of the second NMOS tube NM2 is connected to the power ground signal GND; The gate end of the fifth PMOS transistor PM5 is connected to the output end of the high-gain amplifier A2, and also serves as the output end (Vout) of the current feedback instrument amplifier circuit (IA); the drain end of the fifth PMOS transistor PM5 is connected to the drain end of the third NMOS transistor NM3, and is also connected to the gate end of the third NMOS transistor NM3, and is also connected to the positive input end of the high-gain amplifier A2; the source end of the fifth PMOS transistor PM5 is connected to the left end of the first resistor R2, and is also connected to the left end of the third capacitor C2, and is also connected to the drain end of the seventh PMOS transistor PM7; The gate terminal of the sixth PMOS transistor PM6 is connected to the external output common mode voltage (Vout); the drain terminal of the sixth PMOS transistor PM6 is connected to the drain terminal of the fourth NMOS transistor NM4, and is also connected to the gate terminal of the fourth NMOS transistor NM4, and is also connected to the negative input terminal of the high gain amplifier A2; the source terminal of the sixth PMOS transistor PM6 is connected to the right end of the first resistor R2, and is also connected to the right end of the third capacitor C2, and is also connected to the drain terminal of the eighth PMOS transistor PM8; The gate end of the seventh PMOS transistor PM7 is connected to the negative output end of the sensing amplifier A1 and the gate end of the third PMOS transistor PM3; the drain end of the seventh PMOS transistor PM7 is connected to the source end of the fifth PMOS transistor PM5 and the left end of the second resistor R2 and the left end of the third capacitor C3; the source end of the seventh PMOS transistor PM7 is connected to the high power signal VDD; The gate end of the eighth PMOS transistor PM8 is connected to the positive output end of the sensing amplifier A1 and the gate end of the fourth PMOS transistor PM4; the drain end of the eighth PMOS transistor PM8 is connected to the source end of the sixth PMOS transistor PM6 and the right end of the second resistor R2 and the right end of the third capacitor C3; the source end of the eighth PMOS transistor PM8 is connected to the high power signal VDD; The gate end of the third NMOS tube NM3 is connected to the drain end of the third NMOS tube NM3, and is also connected to the drain end of the fifth PMOS tube PM5, and is also connected to the positive input end of the high gain amplifier A2; the source end of the third NMOS tube NM3 is connected to the power ground signal GND; The gate end of the fourth NMOS transistor NM4 is connected to the drain end of the fourth NMOS transistor NM4, and is also connected to the drain end of the sixth PMOS transistor PM6, and is also connected to the negative input end of the high gain amplifier A2; the source end of the fourth NMOS transistor NM4 is connected to the power ground signal GND; In the current feedback instrument amplifier circuit (IA), the substrates of all NMOS tubes are connected to the power ground signal GND; and the substrates of all PMOS tubes are connected to the high power signal VDD.

8. The high-speed instrumentation amplifier according to claim 4, characterized in that: The transconductance amplifier circuit is connected in a unit gain negative feedback mode to improve the driving capability.

9. The high-speed instrumentation amplifier according to claim 8, characterized in that: The transconductance amplifier circuit comprises: A first transconductance pair of PMOS transistors includes a ninth PMOS transistor PM9 and a tenth PMOS transistor PM10; The second transconductance pair of PMOS transistors includes an eleventh PMOS transistor PM11 and a twelfth PMOS transistor PM12; and a voltage controlled current source VCVS; The gate of the ninth PMOS transistor PM9 is used as a positive phase input terminal, and the gate of the tenth PMOS transistor PM10 is used as a negative phase input terminal; The drain of the first transconductance pair PMOS tube is connected to the voltage-controlled current source VCVS; The gates of the second transconductance pair of PMOS tubes are connected to each other, and the drains of the second transconductance pair of PMOS tubes are connected to the sources of the first transconductance pair of PMOS tubes; The drain of the PMOS tube of the second transconductor pair serves as an output terminal.

10. The high-speed instrumentation amplifier according to claim 4, characterized in that: The high-speed instrumentation amplifier is used for electrical impedance imaging technology, wherein the electrical impedance imaging technology includes medical imaging and industrial imaging, the medical imaging includes one of the following or any combination thereof: lung ventilation monitoring, cardiac imaging, bladder filling monitoring, breast cancer monitoring, stroke monitoring, cerebral edema identification, epilepsy imaging, real-time positioning of brain functional activities, bioimpedance analysis; and / or, the industrial imaging includes one of the following or any combination thereof: fluid flow monitoring, liquid level detection, solid particle distribution monitoring, material defect detection, non-destructive detection.

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