Clock signal generation circuit capable of reducing EMI (Electro-Magnetic Interference) through frequency jittering technology

Abstract

The invention relates to the technical field of integrated circuits, and discloses a clock signal generation circuit capable of reducing EMI (Electro-Magnetic Interference) through a jittering frequency technology, which comprises a reference voltage and jittering frequency module for generating a jittering Vref signal, a frequency regulation module for generating a Vout signal, and an operational amplifier module for comparing the Vout signal with the Vref signal, according to the high-speed clock, the ring oscillator module is used for generating clock signals with jitter frequency characteristics, the enabling control module is used for generating target clock signals, clock signal energy is distributed in a related frequency range instead of a single frequency point, and the frequency spectrum of the high-speed clock is broadened to a wider field.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuits and discloses a clock signal generating circuit for reducing EMI by using a frequency jittering technology. Background Art

[0002] Electromagnetic interference (EMI) is the "natural enemy" of electronic systems. It is a phenomenon in which electronic devices are exposed to electromagnetic waves in space and interfere with their normal functions. EMI interferes with the normal operation of electronic systems, especially in consumer electronics, microprocessors, and data transmission circuits. One of them is "radiated interference", that is, signals interfere with other electronic networks through space. High-speed systems have many sources of radiation interference, such as integrated circuit pins, high-frequency signal lines, and high-speed interfaces. They have antenna characteristics, can generate electromagnetic waves inside themselves, and can radiate electromagnetic waves to the surroundings. Therefore, it can interfere with other adjacent subsystems and even damage other systems.

[0003] The traditional clock signal generating circuit only outputs a clock signal with a constant frequency. When the clock frequency required by the system is higher, the EMI problem in the system will become more prominent, and the traditional design will be difficult to meet the requirements.

[0004] For example, the existing Chinese patent application with publication number CN117914286A discloses a ring oscillator clock signal generating circuit, which includes a resistor module, a first capacitor, a first inverter, a second inverter and a third inverter which are electrically connected in sequence to form a loop; a second capacitor, whose first plate is grounded and whose second plate is electrically connected between the resistor module and the first capacitor; a fourth inverter, whose input end is electrically connected to the input end of the first inverter and whose output end is electrically connected to the clock signal output end of the ring oscillator clock signal generating circuit; an operator, which is electrically connected between the first plate of the first capacitor and the input end of the fourth inverter; the operator is a fifth inverter or a comparator; the ring oscillator clock signal generating circuit composed of the above components forms a stable oscillation loop, realizing continuous flipping and oscillation of the signal; the values ​​of the resistor and the capacitor can be adjusted according to needs to enable the ring oscillator clock signal generating circuit to adapt to different application needs.

[0005] The clock signal output by the above patent has a constant frequency, and the energy is distributed at a single frequency point, which cannot reduce the impact of EMI;

[0006] For example, a Chinese patent application with the existing publication number CN118432587A discloses a clock signal generator with a spread spectrum function. The present invention can reduce electromagnetic interference and is beneficial to prolonging the service life of the chip. Specifically, during the implementation of the present invention, the operating frequency of the ring oscillator module is controlled by its frequency control module, and the magnitude of the spread spectrum frequency is controlled by the spread spectrum module, so that the clock frequency generated by the ring oscillator module can vary around the operating frequency, and the magnitude of the variation is determined by the spread spectrum frequency. The present invention can expand the energy concentrated at a fixed frequency in the prior art to more frequency points, thereby achieving the effect of reducing electromagnetic interference, and has the characteristics of simple structure, strong robustness, excellent performance, low power consumption and small chip area;

[0007] For example, the existing Chinese patent application with publication number CN118677407A discloses a triangular wave generator for reducing electromagnetic interference of a high-frequency oscillator. The present invention provides a triangular wave generator for reducing EMI applied to a high-frequency oscillator, which is used to provide a reference voltage Vref to the high-frequency oscillator, thereby effectively reducing the electromagnetic interference (EMI) of the high-frequency oscillator; the present invention proportionally reduces the reference voltage Vref of the high-frequency oscillator, so that Vref fluctuates within a small range, so that the output carrier of the high-frequency oscillator fluctuates around the center frequency, achieving frequency spreading, thereby significantly reducing the EMI effect; and the triangular wave generator has the advantage of an adjustable output waveform period;

[0008] The clock signal output by the above patent changes in size, that is, the spread spectrum frequency is fixed and cannot be adjusted. The output end of the spread spectrum module lacks common mode, which will cause the output signal to be unstable. Secondly, the amplitude of the output triangular wave signal Vref cannot be adjusted, and the final clock signal jitter frequency cannot be adjusted. Summary of the invention

[0009] In order to solve the above technical problems, the main purpose of the present invention is to provide a clock signal generating circuit for reducing EMI by frequency jittering technology, comprising:

[0010] A reference voltage and frequency jittering module, comprising a reference voltage unit and a frequency jittering unit, wherein the reference voltage unit and the frequency jittering unit cooperate to obtain a jittered Vref signal and transmit it to the operational amplifier module;

[0011] A frequency adjustment module is used to generate a voltage oscillation signal with adjustable frequency and input it into the operational amplifier module;

[0012] An operational amplifier module, used for comparing the output signal of the frequency adjustment module with the Vref signal;

[0013] A ring oscillator module, used to generate a clock signal with frequency jitter characteristics;

[0014] An enable control module is used to generate a target clock signal.

[0015] As a preferred solution of a clock signal generating circuit for reducing EMI by frequency jittering technology of the present invention, wherein:

[0016] The output end of the reference voltage and frequency jittering module is connected to the in-phase input end of the operational amplifier module;

[0017] The output end of the operational amplifier module is connected to the gate of the PMOS tube PM1 after RC filtering;

[0018] The source of the PMOS tube PM1 is connected to the power supply voltage VCC, and the drain is connected to the input end of the ring oscillator module.

[0019] As a preferred solution of a clock signal generating circuit for reducing EMI by frequency jittering technology of the present invention, wherein:

[0020] The output end of the ring oscillator module is connected to the input ends of the frequency adjustment module and the enable control module;

[0021] The output end of the frequency adjustment module is connected to the inverting input end of the operational amplifier module, and the output signal of the output end of the enable control module is a target clock signal;

[0022] The target clock signal is a clock oscillation signal with a frequency jitter characteristic.

[0023] As a preferred solution of a clock signal generating circuit for reducing EMI by frequency jittering technology of the present invention, wherein:

[0024] The reference voltage and frequency jittering module includes a triangle wave generating circuit and a waveform shaping circuit;

[0025] In the triangular wave generating circuit, the resistance ratio of resistors R1, R2, R3, and R4 is 6:1:1:11, and the resistors are connected in series to divide the voltage, thereby outputting a triangular wave signal that fluctuates between two voltage values, one high and one low, and the frequency of the triangular wave signal can be adjusted;

[0026] The waveform shaping circuit reduces the amplitude of the triangular wave signal in proportion through the operational amplifier OPA and the RC voltage divider circuit, outputs a Vref signal that jitters within a small range, and adjusts the amplitude of the triangular wave signal through the waveform shaping circuit.

[0027] As a preferred solution of a clock signal generating circuit for reducing EMI by frequency jittering technology of the present invention, wherein:

[0028] The waveform shaping circuit adjusts the amplitude calculation expression of the triangle wave signal as follows:

[0029]

[0030] Among them, V ref is the triangle wave signal after amplitude adjustment, R8 and R9 are the resistance values ​​of resistors R8 and R9, R is the total resistance value of the adjustable resistor composed of resistors R10 and R11, V B is the voltage at point B, V CC is the power supply voltage.

[0031] As a preferred solution of a clock signal generating circuit for reducing EMI by frequency jittering technology of the present invention, wherein:

[0032] The frequency adjustment module inputs a clock signal Vin to control the on and off of the PMOS tube PM1 and the NMOS tube NM1;

[0033] If Vin is 1, NM1 is turned on and PM1 is turned off, then the voltage at point A is 0;

[0034] If Vin is 0, NM1 is turned off, PM1 is turned on, Vout is first pulled down, C1 is charged, Vout rises, and Vin is 1, then the voltage at point A is pulled down;

[0035] The charging speed of the capacitor C1 is controlled by controlling the resistance of the variable resistor R1, and the oscillation frequency of Vout is further controlled, and finally the average frequency of the output clock signal is controlled.

[0036] As a preferred solution of a clock signal generating circuit for reducing EMI by frequency jittering technology of the present invention, wherein:

[0037] The ring oscillator module includes a basic ring oscillator and a buffer circuit;

[0038] The basic ring oscillator is composed of three inverters I1, I2, and I3. The output of I1 is connected to the input of I2, the output of I2 is connected to the input of I3, and the output of I3 is connected to the input of I1 and the input of the buffer circuit. An odd number of inverters are connected end to end to generate an oscillation signal.

[0039] As a preferred solution of a clock signal generating circuit for reducing EMI by frequency jittering technology of the present invention, wherein:

[0040] The oscillation signal output by the basic ring oscillator is input into the buffer circuit, and the capacitor C1 attenuates the low-frequency signal in the input signal. The higher the frequency of the oscillation signal, the smaller the attenuation, and the low-frequency oscillation signal is further filtered out.

[0041] Beneficial effects of the present invention:

[0042] The present invention generates a Vref signal that varies within a certain range based on a triangle wave generator, so that the frequency of the output clock signal has a frequency jitter characteristic, and the clock signal energy is distributed within a related frequency range rather than at a single frequency point, broadening the spectrum of the high-speed clock to a wider field, thereby reducing the impact of EMI. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor. Among them:

[0044] Figure 1 This is a system composition diagram of a clock signal generating circuit for reducing EMI through frequency jittering technology according to the present invention;

[0045] Figure 2 This is a circuit schematic diagram of a reference voltage and frequency jittering module of a clock signal generating circuit that reduces EMI through frequency jittering technology in the present invention;

[0046] Figure 3 A schematic diagram of the working waveforms of the reference voltage of a clock signal generating circuit and the key nodes of the frequency jittering module for reducing EMI through the frequency jittering technology of the present invention;

[0047] Figure 4 It is a schematic diagram of the principle of a ring oscillator module of a clock signal generating circuit for reducing EMI by frequency jittering technology according to the present invention;

[0048] Figure 5 This is a schematic diagram of the principle of a frequency adjustment module of a clock signal generating circuit for reducing EMI through frequency jittering technology in the present invention;

[0049] Figure 6 It is a schematic diagram of the principle of a comparator COMP of a clock signal generating circuit for reducing EMI by frequency jittering technology of the present invention;

[0050] Figure 7 The schematic diagram is a principle diagram of an operational amplifier OPA of a clock signal generating circuit for reducing EMI by frequency jittering technology according to the present invention.

[0051] Figure 8 This is a simulation result diagram obtained by simulating a clock signal generating circuit that reduces EMI through frequency jittering technology in the present invention.

[0052] Fig. 9 The following is a comparison chart of the frequency spectrum of the output clock before and after using the frequency jittering technology. DETAILED DESCRIPTION

[0053] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are described in detail below in conjunction with the accompanying drawings.

[0054] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0055] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The term "in one embodiment" that appears in different places in this specification does not necessarily refer to the same embodiment, nor does it refer to a separate or selective embodiment that is mutually exclusive with other embodiments.

[0056] Example 1

[0057] like Figure 1 As shown, a clock signal generating circuit for reducing EMI by frequency jittering technology includes:

[0058] The reference voltage and frequency jittering module generates a Vref signal that jitters within a small range and transmits it to the operational amplifier module;

[0059] The operational amplifier module compares the output signal of the frequency adjustment module with the Vref signal, and the output end is connected to the gate of the PMOS tube, so as to output an oscillating current signal at the drain of the PMOS tube and transmit it to the ring oscillator module;

[0060] The ring oscillator module generates a clock signal with a frequency jitter characteristic through the oscillation current signal, and transmits the clock signal to the frequency adjustment module and the enable control module;

[0061] The frequency adjustment module controls the charging and discharging speed of the capacitor through an adjustable resistor, thereby generating a frequency-adjustable voltage oscillation signal which is transmitted to the operational amplifier module to control the average frequency of the final output clock signal;

[0062] The enable control module can output a clock signal only when the input enable signal is at a high level through a NAND gate.

[0063] Furthermore, the reference voltage and frequency jittering module includes a triangular wave generating circuit and a waveform shaping circuit. The triangular wave generating circuit forms a triangular wave by charging and discharging a capacitor. After input into the waveform shaping circuit, the signal amplitude is proportionally reduced, and a Vref signal jittering within a small range is output.

[0064] Further, the ring oscillator module includes a basic ring oscillator and a buffer circuit, wherein the basic ring oscillator is composed of three inverters, and uses the oscillation signal output by the drain of the PMOS tube as a power source, and the three inverters are connected end to end to generate an oscillation signal;

[0065] Specifically, the frequency-jittering clock signal generating circuit includes a reference voltage and frequency-jittering module, an operational amplifier module, a ring oscillator module, a frequency adjustment module and an enable control module. The output end of the reference voltage and frequency-jittering module is connected to the in-phase input end of the operational amplifier module, the output end of the operational amplifier module is connected to the gate of the PMOS tube PM1 after RC filtering, the source of the PMOS tube PM1 is connected to the power supply voltage VCC, and the drain is connected to the input end of the ring oscillator module, the output end of the ring oscillator module is connected to the input end of the frequency adjustment module and the enable control module, the output end of the frequency adjustment module is connected to the inverting input end of the operational amplifier module, and the output signal of the output end of the enable control module is the final output clock oscillation signal with frequency-jittering characteristics.

[0066] Example 2

[0067] A clock signal generating circuit for reducing EMI by frequency jittering technology also includes a reference voltage and a frequency jittering module

[0068] like Figure 2 As shown,

[0069] The reference voltage and frequency jitter module includes a triangular wave generation circuit and a waveform shaping circuit. In the triangular wave generation circuit, the resistance ratio of resistors R1, R2, R3, and R4 is 6:1:1:11, and the resistors are connected in series to divide the voltage, thereby outputting two voltage values, one high and one low. Figure 3 As shown, T is the period, and the vertical coordinates are VP, VN, V A 、V refThe working waveforms of the nodes; that is, the input transmission gate TG1 with 0.684VCC and the input transmission gate TG2 with 0.579VCC. The outputs of the comparator COMP and the inverter I1 control the switches of TG1 and TG2, and the switch states of TG1 and TG2 are opposite, that is, only one of the two voltage values, one high and one low, can be input to COMP at the same time. At the beginning, the input voltage VN of COMP is 0, VP > VN, the output at point A of COMP is high level, TG1 is turned on and TG2 is turned off, VP = 0.684VCC, and the capacitor C1 starts to charge. The voltage value of VN rises linearly. When VN is charged to be greater than 0.684VCC, VP < VN, the potential at point A of the COMP output flips to 0, TG1 is turned off and TG2 is turned on, VP = 0.579VCC, and the capacitor C1 starts to discharge. The voltage value of VN drops linearly. When VN discharges to be less than 0.579VCC, the output at point A of COMP flips back to high level, and the above process is repeated. Thus, a triangular wave signal with an amplitude between 0.684VCC and 0.579VCC is generated and input to the waveform shaping circuit. The frequency of the triangular wave can control whether the resistors R5 and R6 are connected to the circuit through the signals ADJ0 and ADJ1, so as to control the charging speed of the capacitor C1, thereby adjusting the frequency of the triangular wave, and further controlling the jitter frequency of the finally output clock signal. The waveform shaping circuit uses an operational amplifier OPA and an RC voltage dividing circuit to reduce the amplitude of the triangular wave signal in proportion and output a Vref signal that jitters within a small range. The signal ADJ is connected to the gates of the PMOS transistors PM1, PM2, and PM3, which can control whether PM1, PM2, and PM3 are turned on or off, so as to control whether the resistor R10 and the capacitor C2 are connected to the RC voltage dividing circuit, thereby adjusting the amplitude of the triangular wave signal Vref. The following is the derivation of the amplitude formula:

[0070]

[0071] The calculation expression for the waveform shaping circuit to adjust the amplitude of the triangular wave signal is as follows:

[0072]

[0073] where, V ref is the triangular wave signal after amplitude adjustment, R8 and R9 are the resistance values of the resistors R8 and R9, R is the total resistance of the adjustable resistor composed of the resistors R10 and R11, V B is the voltage at point B, and V CC is the power supply voltage.

[0074] As Figure 6 shown, it is the circuit schematic diagram of the comparator COMP, including a positive input channel, a negative input channel, an output filter and a hysteresis unit, an output polarity and direction unit, etc.

[0075] As Figure 7 As shown in the figure, it is the schematic diagram of the operational amplifier OPA circuit, which adopts a two-stage operational amplifier with a five-tube OTA in the first stage and a common source stage in the second stage. The bias circuit is on the far left, the first stage amplifier is in the middle, which provides high gain, and the second stage is a common source stage, which provides a large output swing.

[0076] Example 3

[0077] A clock signal generating circuit for reducing EMI by frequency jittering technology also includes a ring oscillator module,

[0078] like Figure 4 As shown, the ring oscillator module includes a basic ring oscillator and a buffer circuit, wherein the basic ring oscillator is composed of three inverters I1, I2, and I3, the output of I1 is connected to the input of I2, the output of I2 is connected to the input of I3, the output of I3 is connected to the input of I1 and the input of the buffer circuit, and an odd number of inverters are connected end to end to generate an oscillation signal. The input end of the ring oscillator module is the power supply of the inverters I1, I2, and I3, so that the input oscillation current signal can control the oscillation frequency of the output signal of the ring oscillator. The oscillation signal output by the basic ring oscillator is input into the buffer circuit, and the capacitor C1 can cause the low-frequency signal in the input signal to be severely attenuated. The higher the frequency, the smaller the attenuation, so as to achieve the purpose of filtering out the low-frequency signal, but at this time, the signal at point A will definitely be attenuated, and it may not even be enough to drive the buffer I4 behind, resulting in the output OUT being always 0, so the inverter I5 and the resistor R1 are added to provide a common mode, so that the signal at point A is amplified, and then input into the buffer I4 to be further amplified and output. Compared with a buffer circuit with only a buffer and no capacitor, this design can filter out low-frequency signals and output a clock signal with a cleaner frequency.

[0079] Example 4

[0080] A clock signal generating circuit for reducing EMI by frequency jittering technology, including a frequency adjustment module

[0081] Specifically, Figure 5 As shown, the frequency adjustment module inputs the clock signal Vin to control the on and off of the PMOS tube PM1 and the NMOS tube NM1. When Vin is 1, NM1 is turned on, PM1 is turned off, and the voltage at point A is 0. When Vin is 0, NM1 is turned off, PM1 is turned on, Vout is first pulled down, and then C1 starts to be charged, Vout rises, and then Vin is 1 again, and the voltage at point A is pulled down, and so on, so that Vout oscillates. By controlling the resistance value of the variable resistor R1, the speed of charging the capacitor C1 can be controlled, so that the oscillation frequency of Vout can be controlled, and finally the average frequency of the output clock signal can be controlled.

[0082] Example 5

[0083] like Figure 8 As shown, it is a simulation diagram of clock signal parameters, where Figure 8 It is divided into an upper part and a lower part, of which Figure 8 The upper part is a partial enlarged view of the clock signal, with the horizontal axis representing time and the vertical axis representing the voltage value of the clock signal;

[0084] Figure 8 The lower part is the overall simulation diagram of the generated clock signal, including the overall clock signal and the clock signal frequency. The horizontal axis represents time, and dy between M3 and M4 is the maximum jitter frequency amplitude.

[0085] Fig. 9 This is a spectrum comparison diagram of the output clock before and after using the frequency jittering technology. The vertical axis Spectrum amplitude is the spectrum amplitude and the horizontal axis is the frequency.

[0086] Furthermore, Fig. 9 The dotted line part represents the output waveform spectrum of the signal without frequency jittering technology, and the solid line part represents the output waveform spectrum after frequency jittering technology. The spectrum is broadened to a wider range, thereby reducing the impact of EMI.

[0087] Since the simulation diagram is generated by simulation software fitting, the output image is annotated in English.

[0088] Importantly, it should be noted that the construction and arrangement of the present application shown in a plurality of different exemplary embodiments are only exemplary. Although only four embodiments are described in detail in this disclosure, it should be readily understood by those who refer to this disclosure that many modifications are possible, for example, the size, scale, structure, shape and ratio of various elements, and parameter values ​​(e.g., temperature, pressure, etc.), installation arrangement, use of materials, color, directional changes, etc., without substantially departing from the novel teachings and advantages of the subject matter described in the application. For example, the element shown as integrally formed can be composed of multiple parts or elements, the position of the element can be inverted or otherwise changed, and the nature or number or position of the discrete element can be changed or changed. Therefore, all such modifications are intended to be included in the scope of the present invention. The order or sequence of any process or method step can be changed or reordered according to an alternative embodiment. Any "device plus function" clause is intended to cover the structure of the execution function described in this article, and is not only structurally equivalent but also equivalent structure. Without departing from the scope of the present invention, other replacements, modifications, changes and omissions can be made in the design, operating conditions and arrangement of the exemplary embodiment. Therefore, the invention is not limited to a specific embodiment, but extends to numerous modifications still falling within the scope of the appended claims.

[0089] The above description of the embodiments is to facilitate those skilled in the art to understand and apply the present invention. It is obvious that those skilled in the art can easily make various modifications to the above embodiments and apply the general principles described herein to other embodiments without creative work. Therefore, the present invention is not limited to the above embodiments.

[0090] Additionally, in order to provide a concise description of exemplary embodiments, all features of an actual embodiment (ie, those features that are not relevant to the best mode presently contemplated for carrying out the invention or those that are not relevant to implementing the invention) may not be described.

[0091] It should be understood that in the development of any actual implementation, as in any engineering or design project, numerous implementation-specific decisions may be made. Such a development effort may be complex and time-consuming, but for those of ordinary skill having the benefit of this disclosure, the development effort will be a routine task of design, fabrication, and production without undue experimentation.

[0092] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. A clock signal generating circuit for reducing EMI by frequency jittering technology, characterized in that: include: A reference voltage and frequency jittering module, comprising a reference voltage unit and a frequency jittering unit, wherein the reference voltage unit and the frequency jittering unit cooperate to obtain a jittered Vref signal and transmit it to the operational amplifier module; A frequency adjustment module is used to generate a voltage oscillation signal with adjustable frequency and input it into the operational amplifier module; An operational amplifier module, used for comparing the output signal of the frequency adjustment module with the Vref signal; A ring oscillator module, used to generate a clock signal with frequency jitter characteristics; An enable control module is used to generate a target clock signal.

2. The clock signal generating circuit for reducing EMI by frequency jittering technology according to claim 1, characterized in that: The output end of the reference voltage and frequency jittering module is connected to the in-phase input end of the operational amplifier module; The output end of the operational amplifier module is connected to the gate of the PMOS tube PM1 after RC filtering; The source of the PMOS tube PM1 is connected to the power supply voltage VCC, and the drain is connected to the input end of the ring oscillator module.

3. The clock signal generating circuit for reducing EMI by frequency jittering technology according to claim 2, characterized in that: The output end of the ring oscillator module is connected to the input ends of the frequency adjustment module and the enable control module; The output end of the frequency adjustment module is connected to the inverting input end of the operational amplifier module, and the output signal of the output end of the enable control module is a target clock signal; The target clock signal is a clock oscillation signal with a frequency jitter characteristic.

4. The clock signal generating circuit for reducing EMI by frequency jittering technology according to claim 3, characterized in that: The reference voltage and frequency jittering module includes a triangle wave generating circuit and a waveform shaping circuit; In the triangular wave generating circuit, the resistance ratio of resistors R1, R2, R3, and R4 is 6:1:1:11, and the resistors are connected in series to divide the voltage, thereby outputting a triangular wave signal that fluctuates between two voltage values, one high and one low, and the frequency of the triangular wave signal can be adjusted; The waveform shaping circuit reduces the amplitude of the triangular wave signal in proportion through the operational amplifier OPA and the RC voltage divider circuit, outputs a Vref signal that jitters within a small range, and adjusts the amplitude of the triangular wave signal through the waveform shaping circuit.

5. The clock signal generating circuit for reducing EMI by frequency jittering technology according to claim 4, characterized in that: The waveform shaping circuit adjusts the amplitude calculation expression of the triangle wave signal as follows: Among them, V ref is the triangle wave signal after amplitude adjustment, R8 and R9 are the resistance values ​​of resistors R8 and R9, R is the total resistance value of the adjustable resistor composed of resistors R10 and R11, V B is the voltage at point B, V CC is the power supply voltage.

6. The clock signal generating circuit for reducing EMI by frequency jittering technology according to claim 5, characterized in that: The frequency adjustment module inputs a clock signal Vin to control the on and off of the PMOS tube PM1 and the NMOS tube NM1; If Vin is 1, NM1 is turned on and PM1 is turned off, then the voltage at point A is 0; If Vin is 0, NM1 is turned off, PM1 is turned on, Vout is first pulled down, C1 is charged, Vout rises, and Vin is 1, then the voltage at point A is pulled down; The charging speed of the capacitor C1 is controlled by controlling the resistance of the variable resistor R1, and the oscillation frequency of Vout is further controlled, and finally the average frequency of the output clock signal is controlled.

7. The clock signal generating circuit for reducing EMI by frequency jittering technology according to claim 6, characterized in that: The ring oscillator module includes a basic ring oscillator and a buffer circuit; The basic ring oscillator is composed of three inverters I1, I2, and I3. The output of I1 is connected to the input of I2, the output of I2 is connected to the input of I3, and the output of I3 is connected to the input of I1 and the input of the buffer circuit. An odd number of inverters are connected end to end to generate an oscillation signal.

8. The clock signal generating circuit for reducing EMI by frequency jittering technology according to claim 7, characterized in that: The oscillation signal output by the basic ring oscillator is input into the buffer circuit, and the capacitor C1 attenuates the low-frequency signal in the input signal. The higher the frequency of the oscillation signal, the smaller the attenuation, and the low-frequency oscillation signal is further filtered out.

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