Anti-backflow protection substrate potential generation circuit

Abstract

The embodiment of the invention provides an anti-backflow protection substrate potential generation circuit, which comprises a substrate pull-up control network and a substrate pull-down control network, the substrate pull-up control network is used for forming a pull-up conduction path from the substrate pull-up control network to a power supply, and the substrate pull-down control network is used for detecting a driving-stage voltage of a power supply circuit and generating an anti-backflow protection voltage according to the driving-stage voltage of the power supply circuit. If the driving stage voltage is a high level, a pull-down conduction path from the substrate pull-down control network to the ground is turned off, and the anti-backflow protection substrate potential generation circuit provided by the embodiment of the invention can be applied to a scene where the requirement for the output differential voltage or the absolute value of the output high level is not high; according to the power supply circuit, the sink current of the output port to the power supply can be prevented, the overshoot of the rising edge can be reduced, the occupied area of the power supply circuit is small, and the influence on propagation delay is small.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of circuit protection devices, and in particular to a circuit for generating a potential for a backflow protection substrate. Background Art

[0002] In the relevant technology of power supply circuit, the method of preventing the output port from injecting current into the power supply when the potential is fixed to be higher than the power supply voltage, that is, the scheme of isolating the output port from the power supply is mainly: adopting a standard push-pull output structure, the pull-up tube is a PMOS tube, and the pull-down tube is an NMOS tube, and the substrate voltage of the pull-up tube is set to the higher level of the power supply voltage and the output voltage, so as to ensure that the output stage pull-up tube will not leak to the power supply through the PN junction (the P terminal is connected to the output port, and the N-type substrate is connected to the power supply), and at the same time, it is necessary to ensure that the power supply voltage of the previous stage of the output stage (here referred to as the driver stage) is also a high voltage, so as to ensure that when the output of the driver stage is at a high level, the pull-up tube of the output stage is completely turned off, and the pull-up tube will not be turned on because the high level fixed at the drain end (drain) is higher than the power supply voltage, that is, the gate end (gate) voltage, thereby forming a path to the power supply. The key to this solution is the high-level selection circuit, which can select the higher one between the power supply voltage and the output port voltage. This voltage is named Vmax. This Vmax is used as both the substrate potential of the output pull-up tube and the power supply of the driver stage. Because the driver stage is large in size to drive the large-sized output tube, the through current is large when the circuit state is switched, which may lower the potential of Vmax, causing other leakage and slower signal transmission speed problems. Therefore, a larger switch tube is needed between the power supply voltage and Vmax to ensure the current capacity, and a larger capacitor is needed as a supplementary power supply when extracting charge. Both methods require a larger area and will also affect the chip's electrostatic protection capability. While increasing the size of the switch tube and capacitor, the size of the ESD protection circuit also needs to be increased, reducing the problems caused by this isolation solution at the cost of a larger area. Summary of the invention

[0003] The main purpose of the embodiments of the present application is to provide a backflow protection substrate potential generating circuit to solve the problem in the related art that the backflow protection circuit needs to increase the size of the device and increase the chip area.

[0004] According to one aspect of an embodiment of the present application, there is provided an anti-backflow protection substrate potential generating circuit, which is applied to a power supply circuit, and includes: a substrate pull-up control network, which is connected to the output stage of the power supply circuit, and forms a pull-up conduction path from the substrate pull-up control network to the power supply when the output stage voltage is at a high level, and the output end of the substrate pull-up control network is connected to the substrate end of the output pull-up tube of the power supply circuit, and the output stage voltage is the voltage between the output pull-up tube and the output pull-down tube; a substrate pull-down control network, which shuts off the pull-down conduction path from the substrate pull-down control network to ground when the driving stage voltage is at a high level, and the driving stage voltage is the gate voltage of the output pull-up tube; the substrate potential is the potential between the substrate pull-up tube of the substrate pull-up control network and the substrate pull-down tube of the substrate pull-down control network.

[0005] According to at least one specific implementation of the embodiments of the present application, the output pull-up tube is an NMOS tube with a deep N-well, the substrate end of the output pull-up tube is connected to the output end of the anti-backflow protection substrate potential generating circuit, and the substrate potential is located at the output end of the anti-backflow protection substrate potential generating circuit.

[0006] According to at least one specific implementation of the embodiments of the present application, the substrate pull-up control network includes a substrate pull-up tube and a high-resistance detection switch, the substrate pull-up tube is used to receive the output signal of the output pull-up tube, and provide a pull-up conduction path for the output pull-up tube when the signal of the output pull-up tube is at a high level, and the high-resistance detection switch is used to shut off the pull-up conduction path when the output pull-up tube is in a high-resistance output state.

[0007] According to at least one specific implementation of the embodiments of the present application, the gate of the output pull-up tube is used to input the driving stage voltage, the drain of the output pull-up tube is connected to the power supply, the source of the output pull-up tube is connected to the drain of the output pull-down tube, the output stage voltage is between the output pull-up tube and the output pull-down tube, and the output stage voltage is connected to the gate of the substrate pull-up tube.

[0008] According to at least one specific implementation of the embodiments of the present application, the drain of the high-resistance detection switch is connected to the power supply, the substrate end of the high-resistance detection switch is connected to the substrate end of the output pull-up tube, and the source of the high-resistance detection switch is connected to the drain of the substrate pull-up tube.

[0009] According to at least one specific implementation of the embodiments of the present application, the substrate pull-down control network includes an inverter, a substrate pull-down tube and a voltage-controlled current source, the inverter is used to obtain the driving stage voltage and output a driving stage voltage inversion signal, the substrate pull-down tube is used to detect whether the driving stage voltage inversion signal is a high level, and the voltage-controlled current source is used to provide a leakage path for the substrate potential.

[0010] According to at least one specific implementation of the embodiments of the present application, the substrate pull-down tube and the voltage-controlled current source are both MOS tubes, the input end of the inverter is connected to the gate of the output pull-up tube for inputting the driving stage voltage, and the output end of the inverter is connected to the gate of the substrate pull-down tube.

[0011] According to at least one specific implementation of the embodiments of the present application, the drain of the substrate pull-down tube is connected to the source of the substrate pull-up tube, the source of the substrate pull-down tube is connected to the substrate end of the substrate pull-up tube, the drain of the voltage-controlled current source is connected to the source of the substrate pull-up tube, and the source of the voltage-controlled current source is grounded.

[0012] According to at least one specific implementation of the embodiment of the present application, the source of the output pull-down tube is grounded, and the substrate end of the output pull-down tube is connected to the source.

[0013] According to at least one specific implementation of the embodiments of the present application, the gate and substrate end of the voltage-controlled current source are respectively connected to the source, the drain of the voltage-controlled current source is connected between the substrate pull-up tube and the substrate pull-down tube, and the source of the voltage-controlled current source is grounded.

[0014] The beneficial technical effects of the embodiments of the present application are:

[0015] The substrate potential generating circuit provided in the embodiment of the present application processes the substrate potential of the output pull-up tube in the power supply circuit, so that the power supply circuit can realize the anti-backflow function while occupying a smaller area, and prevent the power supply from backflowing when the output terminal of the power supply circuit is connected to a high level. The substrate potential generating circuit has a substrate pull-up control network and a substrate pull-down control network. A reasonable substrate potential is generated by the substrate pull-up network and the substrate pull-down control network in the substrate potential generating circuit, and a PN junction conduction path from the output to the power supply formed by directly connecting the substrate to the power supply is avoided, thereby providing anti-backflow capability for the power supply circuit.

[0016] The anti-backflow protection substrate potential generating circuit provided in the embodiment of the present application can be applied to the scenario of outputting differential voltage or the scenario where the absolute value of the output high level is not required to be high. It can not only prevent the output port from injecting current into the power supply, but also reduce the overshoot of the rising edge, so that the power supply circuit occupies a smaller area and has less impact on the propagation delay. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the specific implementation methods of the embodiments of the present application or the technical solutions in the related technologies, the drawings required for use in the specific implementation methods or the related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some implementation methods of the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 It is an application scenario diagram of an embodiment of the present application.

[0019] Figure 2 It is a principle block diagram of an embodiment of the present application.

[0020] Figure 3 It is a circuit schematic diagram of an embodiment of the present application. DETAILED DESCRIPTION

[0021] In order to enable those skilled in the art to better understand the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only implementation methods of a part of the embodiments of the present application, rather than all implementation methods. Based on the embodiments in the embodiments of the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the embodiments of the present application.

[0022] It should be noted that the terms "first", "second", etc. in the specification and claims of the embodiments of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0023] In addition, the terms "installed", "set", "provided with", "connected", "connected", and "socketed" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be an internal connection between two devices, elements, or components. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0024] It should be noted that, in the absence of conflict, the implementation methods and features in the embodiments of the present application can be combined with each other. The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0025] like Figure 1 and Figure 2 As shown, the above specification has mentioned that in order to prevent the output port from being fixed to a potential higher than the power supply voltage and causing the current to flow to the power supply, the usual practice is to adopt a standard push-pull output circuit structure. In the push-pull output circuit, the output pull-up tube is a PMOS tube, and the output pull-down tube is an NMOS tube. The output pull-up and pull-down tubes can be turned on respectively under different input signals to ensure the stability of the output signal. The substrate voltage of the pull-up PMOS tube is set to the higher voltage Vmax of the power supply voltage and the output voltage to prevent the PN junction from leaking to the power supply. The related technology usually uses a high-level selection circuit to select the higher voltage Vmax of the power supply voltage and the output port voltage. Vmax is used as both the substrate potential of the output pull-up tube and the power supply of the driver stage. Since the current through the driver stage is large when the circuit state is switched, the potential of Vmax may be lowered, so a larger switch tube is required to ensure the current capacity, and a larger capacitor is required as a supplementary power supply when extracting charge, which will cause the driver stage to occupy a larger area, increase the size of the ESD protection circuit, and may affect the electrostatic protection capability of the chip.

[0026] In view of the above situation, an anti-backflow protection substrate potential generating circuit is provided in the embodiment of the present application, which is mainly applied to a power supply circuit C. A power supply VDD, an output pull-up tube Q1, and an output pull-down tube Q2 are provided in the power supply circuit C. The anti-backflow protection substrate potential generating circuit includes:

[0027] The substrate pull-up control network A is connected to the output stage OUT of the power circuit C. If the output stage voltage OUT is detected to be at a high level, a pull-up conduction path is formed from the substrate pull-up control network A to the power supply VDD, and the output end of the substrate pull-up control network A is connected to the substrate end of the output pull-up tube Q1 of the power circuit C;

[0028] The substrate pull-down control network B detects the driving stage voltage of the power circuit C. If the driving stage voltage is at a high level, the pull-down conduction path from the substrate pull-down control network B to the ground is turned off. The driving stage voltage is the gate voltage of the output pull-up tube Q1.

[0029] The output stage voltage is the voltage between the output pull-up tube Q1 and the output pull-down tube Q2 of the power circuit C. The substrate potential is located at the output end of the substrate potential generation circuit. The output pull-up tube Q1 is an NMOS tube with a deep N well DNW. The deep N well (DNW) is an independent area isolated on the P-type substrate (P-sub). The substrate end Bulk of the output pull-up tube Q1 is connected to the output end of the substrate potential generation circuit, and the substrate end of the output pull-down tube Q2 is connected to its own source. The substrate potential is the potential between the substrate pull-up tube in the substrate pull-up control network A and the substrate pull-down tube in the substrate pull-down control network B.

[0030] By setting a substrate pull-up control network A and a substrate pull-down control network B in the substrate potential generation circuit, the substrate potential is dynamically adjusted according to the state of the output stage voltage and the driving stage voltage, so that the substrate potential can adapt to different working conditions. When the output stage voltage is at a high level, a pull-up conduction path is formed through the substrate pull-up control network A, so that the substrate potential is close to a high level, thereby reducing the voltage difference between the substrate and the source end of the output pull-up tube, reducing the influence of the substrate bias effect, and finally making the output high level higher than the case where the substrate is directly grounded, reducing the disadvantage of the output high level not being high enough introduced by the NMOS tube pull-up, and ensuring VOH. The substrate pull-down control network B detects the driving stage voltage and turns off the pull-down conduction path when the driving stage voltage is at a high level, so that the substrate voltage can be stabilized at a high level without a through current.

[0031] exist Figure 1 and Figure 2 In the application scenario and principle block diagram, the technical solution provided by the embodiment of the present application can dynamically control the substrate potential of the pull-up tube, effectively preventing the problem of the output pull-up tube injecting current into the power supply in a high-level state. In addition, the technical solution provided by the embodiment of the present application can also significantly reduce the overshoot phenomenon during the rising edge of the output signal, so it is particularly suitable for those scenarios that do not require high absolute values ​​of the output high level, but pay more attention to the differential voltage performance of the output end. The technical solution provided by the embodiment of the present application can optimize the chip space utilization without sacrificing circuit performance, and by reasonably controlling the substrate potential, it can avoid leakage current from being injected into the power supply when the output pull-up tube is at a high level, thereby improving the stability of the power supply circuit C. At the same time, by adjusting the substrate potential, the overshoot of the output signal at the rising edge is effectively suppressed, further improving the reliability of the circuit.

[0032] like Figure 3As shown, the substrate pull-up control network includes a substrate pull-up tube Q4 and a high-resistance detection switch Q3. The substrate pull-up tube Q4 is used to receive the output signal of the output pull-up tube Q1, and provides a pull-up conduction path for the output pull-up tube Q1 when the signal of the output pull-up tube Q1 is high. The substrate pull-up tube in the substrate pull-up control network is a native type device, and the substrate potential output by the native type device is close to the output high level under normal working conditions. "Native type device" refers to a MOS tube with a threshold voltage close to zero, also known as a depletion type MOS tube. The characteristic of the native type device is that the threshold voltage is very low, sometimes even negative, which means that the native type device can be turned on without an external voltage. The above characteristics of the native type device make the native MOS tube different from the traditional enhancement MOS tube (whose threshold voltage is positive). The enhancement MOS tube requires a gate voltage higher than the threshold voltage to be turned on, while the native MOS tube has a very low threshold voltage because of its low channel doping level or no doping.

[0033] The gate of the output pull-down tube Q2 is used to input the driving stage voltage, the drain of the output pull-down tube Q2 is connected to the power supply VDD, the source of the output pull-up tube Q1 is connected to the drain of the output pull-down tube Q2, the output stage voltage OUT is between the output pull-up tube Q1 and the output pull-down tube Q2, and the output stage voltage OUT is connected to the gate of the substrate pull-up tube Q4.

[0034] The high-resistance detection switch Q3 is used to shut off the pull-up conduction path when the output pull-up tube Q1 is in a high-resistance output state. The drain of the high-resistance detection switch Q3 is connected to the power supply VDD, the substrate end of the high-resistance detection switch Q3 is connected to the substrate end Bulk of the output pull-up tube Q1, and the source of the high-resistance detection switch Q3 is connected to the drain of the substrate pull-up tube Q4. The function of the high-resistance detection switch Q3 is to cut off the pull-up conduction path when the output pull-up tube Q1 outputs a high-resistance state, avoid leakage that may exist in the pull-up conduction path, and prevent the high-resistance state of the output pull-up tube Q1 from being damaged.

[0035] The high-resistance detection switch Q3 itself is also a MOS tube. There are many ways to detect whether the output pull-up tube Q1 is in a high-resistance state through the high-resistance detection switch Q3. In the embodiment of the present application, the output pull-up tube Q1 is an NMOS tube with DNW. For example, the gate of the high-resistance detection switch Q3 can be directly connected through the signal of the external enable control pin. If the chip is in a disabled state (that is, a high-resistance state), the gate of Q3 is low and non-conductive, the high-resistance detection switch is turned off, the pull-up network is not conductive, and the substrate can maintain the correct low level; or a suitable signal is selected nearby as the gate voltage of Q3, such as using the gates of the output pull-up tube and the output pull-down tube for logical operations.

[0036] The substrate pull-down control network B includes an inverter N, a substrate pull-down tube Q5 and a voltage-controlled current source Q6. The inverter N is used to obtain the driving stage voltage and output the driving stage voltage inversion signal. The substrate pull-down tube Q5 is used to detect whether the driving stage voltage inversion signal is a high level. The voltage-controlled current source Q6 is used to provide a leakage path for the substrate potential.

[0037] The substrate pull-down tube Q5 and the voltage-controlled current source Q6 are both MOS tubes. The input end of the inverter N is connected to the gate of the output pull-down tube Q2 for inputting the driving level voltage. The output end of the inverter N is connected to the gate of the substrate pull-down tube Q5. The drain of the substrate pull-down tube Q5 is connected to the source of the substrate pull-up tube Q4. The source of the substrate pull-down tube Q5 is connected to the substrate end of the substrate pull-up tube Q4. The drain of the voltage-controlled current source Q6 is connected to the source of the substrate pull-up tube Q4. The source of the voltage-controlled current source Q6 is grounded. The gate of the substrate pull-down tube Q5 is connected to the output end of the inverter N. When receiving a high-level signal, the pull-down conduction path of the substrate pull-down control network B is turned off, and a path from the drain to the source of the voltage-controlled current source Q6 is formed to fine-tune the substrate voltage by increasing the leakage current. The substrate pull-down tube Q5 obtains the driving stage voltage as the input signal through the inverter, rather than directly using the output terminal OUT as the control signal, which can prevent the output terminal OUT from signal backflow due to the connection with the outside, avoid causing the pull-down conduction path to be falsely triggered, and avoid further adding load to the output terminal OUT.

[0038] The idea of ​​making the MOS tube equivalent to a voltage-controlled current source can be realized through a basic voltage-controlled current source circuit. The gate voltage (Vgs) of the MOS tube is used to control the drain current (I d). By changing Vgs, the size of the drain current can be controlled, thereby realizing the function of the voltage-controlled current source.

[0039] The source of the substrate pull-down tube Q5 is grounded, the substrate end of the substrate pull-down tube Q5 is connected to the source, the gate and substrate end of the voltage-controlled current source Q6 are respectively connected to the source, and the drain of the voltage-controlled current source Q6 is connected between the substrate pull-up tube Q4 and the substrate pull-down tube Q5. The voltage-controlled current source Q6 uses a native tube, and the control principle is different from the above idea. In this structure, the pull-down current is controlled by Vds, thereby providing a supplementary adjustment method for the substrate voltage: when the output voltage OUT is high and the substrate potential is also high, a certain leakage current is generated to avoid the situation where the Vgs of the substrate pull-up tube Q4 is less than zero, resulting in the substrate potential being higher than the output voltage, thereby avoiding possible substrate current; it can also make the substrate low through the pull-down leakage current when the high-resistance detection switch is turned off, that is, when there is no pull-up conduction path, to ensure that the substrate potential is not in a high-resistance state and avoid possible errors.

[0040] The substrate pull-down control network B composed of the inverter N, the substrate pull-down tube Q5 and the voltage-controlled current source Q6 can avoid the pull-down false triggering caused by the return groove of the output signal, dynamically control the substrate potential, ensure the stability of the output terminal OUT and the safe operation of the circuit, and can improve the high level (voh) under load that can be achieved by using the NMOS pull-up tube. The driver level voltage is obtained as the input signal through the inverter N, which avoids the false triggering of the pull-down conduction path and improves the reliability of the circuit. The substrate pull-down tube Q5 obtains the signal from the driver level voltage, avoids adding additional load to the output terminal OUT, and ensures the operation efficiency of the circuit. The voltage-controlled current source Q6 controls the pull-down current through Vds (drain-source voltage), dynamically adjusts the substrate potential, and prevents the substrate potential from being too high or in a high-resistance state. When the output terminal OUT is a high voltage and the substrate potential is also a high voltage, the voltage-controlled current source Q6 will generate a certain leakage current to maintain the stability of the substrate potential and avoid the Vgs (gate-source voltage) of the substrate pull-up tube Q4 from being less than zero.

[0041] The substrate pull-down control network B reduces the circuit performance degradation caused by external interference and improves the anti-interference ability of the circuit by controlling the substrate potential. By finely controlling the substrate potential and dynamically adjusting the pull-down current, stable control of the substrate potential is achieved, thereby improving the stability and reliability of the circuit.

[0042] It can be seen from the above implementation that the substrate potential generating circuit composed of the substrate pull-up control network A and the substrate pull-down control network B does not require the size of the pull-up tube to be too large. A pull-up tube with too large a size will increase the load capacitance, and will also require a larger voltage-controlled current source to provide a larger current to ensure that the vgs of the pull-up tube is greater than zero, that is, the substrate voltage is lower than the source voltage of the output pull-up tube. In the process of the output voltage changing from low to high under normal operation, the substrate voltage does not need to follow the output voltage quickly all the time. The pull-down current of the voltage-controlled current source increases with the increase of the substrate voltage, so that the speed of the substrate voltage rising gradually slows down, which can achieve the effect of reducing the output overshoot, that is: at the moment when the output overshoot occurs, the substrate potential does not reach the high level in the stable state, which affects the ability of the output pull-up tube and suppresses the generation of overshoot. When the output level tends to be stable, it is ensured that the substrate voltage is also stable, thereby avoiding the influence of the substrate voltage on the transient output waveform at this moment. It can be seen that the rise of the substrate voltage is controlled so that its speed is not too fast, that is, a smaller pull-up control network size can achieve the function of reducing the output rising edge overshoot.

[0043] The substrate voltage generating circuit provided in the embodiment of the present application does not need to consider the speed, but only needs to ensure the logic function. It can be implemented with a smaller area. Compared with the anti-backflow circuit structure implemented with a larger area in the related technology, it has less impact on the ESD (electrostatic discharge) level. While ensuring voh (output high-level voltage), it can also reduce overshoot. Since the impact on the output waveform mainly occurs in the second half of the rising edge, the impact on tpd (propagation delay) is much smaller than the impact on tr (rise time), which is equivalent to a smaller increase in tpd (propagation delay) and a significant improvement in overshoot.

[0044] In summary, the anti-backflow protection substrate potential generating circuit provided in the embodiment of the present application reduces the overshoot phenomenon of the output signal, protects the back-end equipment from damage caused by overshoot, and improves the signal integrity. It does not require complex high-speed circuit design, so it can be implemented in a smaller IC area. Compared with the anti-backflow structure that requires a larger area, it saves chip space, realizes the control of substrate voltage without sacrificing ESD protection, has less impact on the propagation delay tpd, and has a greater impact on the rise time tr, thereby significantly improving the overshoot phenomenon without significantly increasing the propagation delay. While reducing the overshoot, the scheme can also guarantee Voh (output high level voltage), ensure the accuracy of the logic function and the reliability of the circuit, and optimize the output waveform.

[0045] Those skilled in the art will appreciate that, unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as the general understanding of those skilled in the art in the field to which the embodiments of the present application belong. It should also be understood that terms such as those defined in general dictionaries should be understood to have meanings consistent with those in the context of the relevant technology, and will not be interpreted with idealized or overly formal meanings unless specifically defined.

[0046] It should be noted that certain words are used in the description and claims of the embodiments of the present application to refer to specific components. Those skilled in the art should understand that different manufacturers and manufacturers may use different terms to refer to the same component. The description and claims of the embodiments of the present application do not use the difference in terms as a way to distinguish components, but use the difference in the functions of the components as the criterion for distinction.

[0047] In the description of the specification of the embodiments of the present application, the description with reference to the terms "one embodiment", "example", "specific example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0048] In addition, the technical solutions between the various implementation methods of the embodiments of the present application can be combined with each other, but it must be based on the fact that ordinary technicians in the field can implement it. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0049] All features disclosed in the embodiments of the present application, or steps in all disclosed methods or processes, except mutually exclusive features and / or steps, can be combined in any way. Any feature disclosed in the specification of the embodiments of the present application, unless otherwise described, can be replaced by other alternative features that are equivalent or have similar purposes. That is, unless otherwise described, each feature is just an example in a series of equivalent or similar features. Throughout the specification, the same reference numerals indicate the same elements.

[0050] Those skilled in the art will appreciate that the modules in the device in the embodiment can be adaptively changed and arranged in one or more devices different from the embodiment. The modules or units or components in the embodiment can be combined into one module or unit or component, and in addition they can be divided into multiple submodules or subunits or subcomponents. Except that at least some of such features and / or processes or units are mutually exclusive, all features disclosed in the specification of the embodiment of the application (including corresponding claims, abstracts and drawings) and all processes or units of any method or device disclosed in this way can be combined in any combination. Unless otherwise clearly stated, each feature disclosed in the specification of the embodiment of the application (including corresponding claims, abstracts and drawings) can be replaced by alternative features providing the same, equivalent or similar purpose.

[0051] Although the implementation methods of the embodiments of the present application are described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the embodiments of the present application, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A backflow protection substrate potential generating circuit, applied to a power supply circuit, characterized in that: include: A substrate pull-up control network is connected to the output stage of the power supply circuit, and a pull-up conduction path is formed from the substrate pull-up control network to the power supply when the output stage voltage is at a high level. The output end of the substrate pull-up control network is connected to the substrate end of the output pull-up tube of the power supply circuit, and the output stage voltage is the voltage between the output pull-up tube and the output pull-down tube; A substrate pull-down control network, which turns off the pull-down conduction path from the substrate pull-down control network to ground when the driving stage voltage is at a high level, and the driving stage voltage is the gate voltage of the output pull-up tube; The substrate potential is the potential between the substrate pull-up tube of the substrate pull-up control network and the substrate pull-down tube of the substrate pull-down control network.

2. The anti-backflow protection substrate potential generating circuit according to claim 1, characterized in that: The output pull-up tube is an NMOS tube with a deep N well. The substrate end of the output pull-up tube is connected to the output end of the anti-backflow protection substrate potential generating circuit. The substrate potential is located at the output end of the anti-backflow protection substrate potential generating circuit.

3. The anti-backflow protection substrate potential generating circuit according to claim 1, characterized in that: The substrate pull-up control network includes a substrate pull-up tube and a high-resistance detection switch. The substrate pull-up tube is used to receive the output signal of the output pull-up tube and provide a pull-up conduction path for the output pull-up tube when the signal of the output pull-up tube is at a high level. The high-resistance detection switch is used to shut off the pull-up conduction path when the output pull-up tube is in a high-resistance output state.

4. The anti-backflow protection substrate potential generating circuit according to claim 3, characterized in that: The gate of the output pull-up tube is used to input the driving stage voltage, the drain of the output pull-up tube is connected to the power supply, the source of the output pull-up tube is connected to the drain of the output pull-down tube, the output stage voltage is between the output pull-up tube and the output pull-down tube, and the output stage voltage is connected to the gate of the substrate pull-up tube.

5. The circuit for generating a potential for backflow protection substrate according to claim 4, characterized in that: The drain of the high-resistance detection switch is connected to the power supply, the substrate end of the high-resistance detection switch is connected to the substrate end of the output pull-up tube, and the source of the high-resistance detection switch is connected to the drain of the substrate pull-up tube.

6. The anti-backflow protection substrate potential generating circuit according to claim 1, characterized in that: The substrate pull-down control network includes an inverter, a substrate pull-down tube and a voltage-controlled current source. The inverter is used to obtain the driving stage voltage and output a driving stage voltage inversion signal. The substrate pull-down tube is used to detect whether the driving stage voltage inversion signal is a high level. The voltage-controlled current source is used to provide a leakage path for the substrate potential.

7. The circuit for generating a potential for backflow protection substrate according to claim 6, characterized in that: The substrate pull-down tube and the voltage-controlled current source are both MOS tubes. The input end of the inverter is connected to the gate of the output pull-up tube for inputting the driving stage voltage. The output end of the inverter is connected to the gate of the substrate pull-down tube.

8. The circuit for generating a potential for backflow protection substrate according to claim 6, characterized in that: The drain of the substrate pull-down tube is connected to the source of the substrate pull-up tube, the source of the substrate pull-down tube is connected to the substrate end of the substrate pull-up tube, the drain of the voltage-controlled current source is connected to the source of the substrate pull-up tube, and the source of the voltage-controlled current source is grounded.

9. The circuit for generating a potential for backflow protection substrate according to claim 6, characterized in that: The source of the output pull-down tube is grounded, and the substrate end of the output pull-down tube is connected to the source.

10. The circuit for generating a potential for backflow protection substrate according to claim 9, characterized in that: The gate and substrate end of the voltage-controlled current source are respectively connected to the source, the drain of the voltage-controlled current source is connected between the substrate pull-up tube and the substrate pull-down tube, and the source of the voltage-controlled current source is grounded.

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