Optical isolation solid relay
By designing the input delay circuit, input leakage circuit, isolation module, output delay circuit and output anti-interference circuit of the optically isolated solid relay, the problem of slow capacitor discharge and semiconductor burning when the delay time is required for a long time is solved, the stability and reliability of the system are improved, and the anti-interference ability is enhanced.
Patent Information
- Application Number
- CN202411843690.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-14
- Publication Date
- 2025-05-02
AI Technical Summary
In the case of long delay time requirements for existing solid relays, the time constant of the RC network is large, resulting in slow capacitor leakage and slow field effect tubes pose a risk of semiconductor burning, and due to misdirection, slow capacitor leakage, output shock and peak voltage damage, resulting in poor reliability and stability.
An optically isolated solid relay is designed, including an input delay circuit, an input leakage circuit, an isolation module, an output delay circuit and an output anti-interference circuit. Through these circuits, the delay processing, rapid discharge, slow-on processing and anti-interference ability of the input signal is achieved.
It effectively prevents misdirection caused by input interference signals, avoids the risk of field effect tube semiconductor burning caused by slow capacitor leakage, improves the stability and reliability of the system, extends the service life of the relay, and enhances the anti-interference ability.
Smart Images
Figure CN119921745A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of solid-state relays, and in particular to an optically isolated solid-state relay. Background Art
[0002] Solid-state relays have the advantages of small size, high reliability and long life. They are gradually replacing traditional electromagnetic contact relays and are widely used in high-reliability fields, especially in some control systems with relatively high requirements. The use of solid-state relays can also prevent the sparks that may be caused by the contacts of contact relays. In recent years, magnetic isolation solid-state relays have performed poorly in electromagnetic compatibility experiments and may misfire in certain frequency bands.
[0003] In some systems with high reliability requirements (such as ignition systems), in order to prevent the input interference signal from causing the solid-state relay to be misconnected, it is usually required to add a delay function of several ms, which is generally achieved by using an RC network. However, when the delay time is required to be longer, the time constant of the RC network is large. When it is turned off, the capacitor discharges slowly, and the field effect tube may be half-conducted and burned, resulting in poor reliability and stability of the solid-state relay in the related art. Therefore, providing a solid-state relay with a delayed connection and fast input discharge has become a technical problem to be solved in this field. Summary of the invention
[0004] In order to solve the above problems, the present application provides an optically isolated solid-state relay.
[0005] In a first aspect, the present application provides an optically isolated solid-state relay, comprising: an input delay circuit, an input discharge circuit, an isolation module, an output delay circuit, an output anti-interference circuit and a MOS tube, wherein the input delay circuit is connected between the input end of the optically isolated solid-state relay and the input end of the isolation module, and the input delay circuit is used to delay the input signal; the input discharge circuit is connected to the input delay circuit, and the input discharge circuit is configured to provide a discharge circuit for the input capacitor when the input is turned off, wherein the input delay circuit includes an input capacitor; the input end of the output delay circuit is connected to the output end of the isolation module, and the output end of the output delay circuit is connected to the gate and source of the MOS tube, the drain and source of the MOS tube serve as the positive output end and the negative output end of the optically isolated solid-state relay respectively, and the output delay circuit is used to perform slow-on processing on the MOS tube; the output anti-interference circuit is connected between the output delay circuit and the MOS tube, and the output anti-interference circuit is configured to provide a discharge path for the gate-source voltage of the MOS tube when a peak voltage is generated at the output end of the MOS tube.
[0006] By adopting the above technical solution, the optically isolated solid-state relay realizes the delayed processing of the input signal, effectively preventing the mis-conduction phenomenon caused by the input interference signal. At the same time, the input discharge circuit provides a fast discharge path for the input capacitor when the input is turned off, avoiding the risk of the field effect tube being half-conducted and burned due to the slow discharge of the capacitor. The output delay circuit performs a slow turn-on process on the MOS tube, further improving the stability and reliability of the system. When the output anti-interference circuit generates a spike voltage at the output end of the MOS tube, it provides a discharge path for its gate-source voltage, enhancing the anti-interference ability of the equipment. This technical solution solves the problems of mis-conduction, slow capacitor discharge, output shock and spike voltage damage, improves the reliability and stability of the optically isolated solid-state relay, and extends the service life of the optically isolated solid-state relay by reducing faults caused by mis-conduction, half-conduction burning and spike voltage damage.
[0007] Optionally, the input delay circuit includes: a first resistor, a first capacitor, a first diode and a first voltage-stabilizing diode, wherein the first end of the first resistor is electrically connected to the positive input terminal of the optically isolated solid-state relay, the second end of the first resistor is electrically connected to the positive electrode of the first diode, the negative electrode of the first diode is electrically connected to the negative electrode of the first voltage-stabilizing diode, the positive electrode of the first voltage-stabilizing diode is electrically connected to the positive input terminal of the isolation module, the negative input terminal of the isolation module is electrically connected to the negative input terminal of the optically isolated solid-state relay, and the first capacitor is connected between the negative electrode of the first voltage-stabilizing diode and the negative input terminal of the optically isolated solid-state relay, wherein the first capacitor is an input capacitor.
[0008] By adopting the above technical solution, the delay processing of the input signal is realized, and the mis-conduction phenomenon caused by the input interference signal is effectively prevented. Specifically, the input delay circuit composed of the first resistor, the first capacitor, the first diode and the first voltage-stabilizing diode ensures that the input signal triggers the subsequent circuit action only after reaching the predetermined delay time through the delay processing of the input signal, thereby improving the stability and reliability of the system. At the same time, the design can also adapt to the delay requirements in different application scenarios, enhancing the flexibility and scope of application of the product.
[0009] Optionally, the input discharge circuit includes: a first transistor, a second transistor, a second resistor and a third resistor, wherein the first transistor is a PNP transistor, the emitter of the first transistor is electrically connected to the negative electrode of the first voltage-stabilizing diode, the base of the first transistor is electrically connected to the positive electrode of the first diode, and the collector of the first transistor is electrically connected to the negative input terminal of the optical isolation solid relay through the second resistor; the second transistor is an NPN transistor, the collector of the second transistor is electrically connected to the base of the first transistor, the base of the second transistor is electrically connected to the collector of the first transistor, and the emitter of the second transistor is electrically connected to the negative input terminal of the optical isolation solid relay, wherein when the input is turned off, the voltage across the first capacitor is quickly discharged through the second resistor; the third resistor is connected between the base of the first transistor and the negative input terminal of the optical isolation solid relay.
[0010] By adopting the above technical solution, when the input of the optical isolation solid state relay is turned off, the voltage across the first capacitor can be quickly discharged through the second resistor, thereby avoiding the problem of the field effect tube being half-conducted or even burned due to the slow discharge of the capacitor when the RC network in the related art is turned off. Specifically, the discharge circuit composed of the first transistor and the second transistor can be quickly turned on when the input is turned off, so that the voltage across the first capacitor is quickly released through the second resistor, improving the reliability and safety of the system.
[0011] Optionally, the isolation module includes a light-emitting diode chip and a photocell chip, the positive electrode of the light-emitting diode chip is electrically connected to the positive electrode of the first voltage-stabilizing diode, the negative electrode of the light-emitting diode chip is electrically connected to the negative input terminal of the optical isolation solid-state relay, the positive electrode of the photocell chip is electrically connected to the gate of the MOS tube through the output delay circuit, and the negative electrode of the photocell chip is electrically connected to the negative output terminal of the optical isolation solid-state relay, wherein the isolation module is used to achieve optical isolation between the input and output of the optical isolation solid-state relay.
[0012] By adopting the above technical solution, the optical isolation solid-state relay realizes effective optical isolation between input and output, ensuring the safety and stability of the relay in a high-voltage environment. Specifically, the combined use of the light-emitting diode chip and the photovoltaic cell chip enables the input signal to be transmitted to the output end through an optical signal, avoiding the electromagnetic interference problem existing in the traditional electrical isolation method and improving the anti-interference ability of the system. At the same time, this optical isolation design can also effectively prevent the interference signal at the input end from directly affecting the output end, further enhancing the reliability and safety of the relay.
[0013] Optionally, the capacitance value of the first capacitor is allowed to be adjusted to meet the delay time requirement of the input delay circuit.
[0014] By adopting the above technical solution, the delay time of the input delay circuit can be flexibly adjusted to meet the needs of different application scenarios. Specifically, the capacitance value of the first capacitor can be adjusted according to actual needs, thereby accurately controlling the delay time of the input signal, ensuring that false triggering can be effectively prevented under various working conditions, and improving the reliability and stability of the system.
[0015] Optionally, the output delay circuit includes: a fourth resistor, a second capacitor and a fifth resistor, wherein the first end of the fourth resistor is electrically connected to the positive output terminal of the isolation module, the second end of the fourth resistor is electrically connected to the gate of the MOS tube through the fifth resistor, the second capacitor is connected between the second end of the fourth resistor and the negative output terminal of the isolation module, and the negative output terminal of the isolation module is electrically connected to the negative output terminal of the optical isolation solid state relay.
[0016] By adopting the above technical solution, the slow connection processing of the output signal is realized, which effectively avoids the current shock caused by the rapid opening of the MOS tube and improves the stability and reliability of the system. At the same time, the delay time is controlled by the RC network, so that the output delay is adjustable to meet the needs of different application scenarios.
[0017] Optionally, the output anti-interference circuit includes a third transistor, which is a PNP transistor, the emitter of the third transistor is electrically connected to the gate of the MOS tube, the base of the third transistor is electrically connected to the second end of the fourth resistor, and the collector of the third transistor is electrically connected to the source of the MOS tube, wherein when a peak voltage is generated at the output end of the MOS tube, the gate-source voltage of the MOS tube is discharged through the third transistor.
[0018] By adopting the above technical solution, when a peak voltage is generated at the output end of the MOS tube, the third transistor is quickly turned on to discharge the gate-source voltage of the MOS tube, thereby effectively avoiding the risk of damage to the MOS tube due to overvoltage and improving the stability and reliability of the optical isolation solid-state relay.
[0019] Optionally, the output anti-interference circuit further includes a sixth resistor, wherein the sixth resistor is connected in parallel with the second capacitor.
[0020] By adopting the above technical solution, when a peak voltage is generated at the output end of the MOS tube, the gate-source voltage of the MOS tube can be quickly discharged through the third triode, effectively protecting the MOS tube from damage. At the same time, the sixth resistor is connected in parallel with the second capacitor, which further speeds up the charging and discharging speed of the second capacitor and improves the response speed and stability of the system.
[0021] Optionally, the optically isolated solid-state relay further includes: a second voltage regulator diode, wherein the cathode of the second voltage regulator diode is electrically connected to the gate of the MOS tube, and the anode of the second voltage regulator diode is electrically connected to the source of the MOS tube.
[0022] By adopting the above technical solution, the second voltage stabilizing diode can play a voltage stabilizing role when the gate-source voltage of the MOS tube exceeds a certain threshold, effectively protecting the MOS tube from overvoltage shock, improving the voltage resistance of the MOS tube, and thus enhancing the reliability and stability of the entire optical isolation solid-state relay.
[0023] Optionally, the MOS tube is an NMOS tube.
[0024] By adopting the above technical solution and selecting NMOS tube as the output control element, it performs well in low power consumption and high efficiency, while improving the overall performance of the system.
[0025] In summary, one or more technical solutions provided in this application have at least the following technical effects or advantages: 1. It solves the problems of mis-conduction, slow capacitor discharge, output impact and spike voltage damage, improves the reliability and stability of the optical isolation solid state relay, and extends the service life of the optical isolation solid state relay by reducing the failures caused by mis-conduction, semi-conduction burning and spike voltage damage; 2. The discharge circuit composed of the first transistor and the second transistor can be turned on quickly when the input is turned off, so that the voltage across the first capacitor is quickly released through the second resistor, thereby improving the reliability and safety of the system and avoiding the problem of the field effect tube being half-conducted or even burned due to the slow discharge of the capacitor when the RC network in the related art is turned off; 3. The output anti-interference circuit can effectively reduce the impact of spike voltage on the circuit, help absorb and discharge spike voltage, and enhance the anti-interference ability of the entire optical isolation solid state relay. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figure 1 This is a structural block diagram of an optically isolated solid-state relay provided in an embodiment of the present application; Figure 2 This is a schematic diagram of an input circuit of an optically isolated solid-state relay provided in an embodiment of the present application; Figure 3 This is a schematic diagram of an output circuit of an optically isolated solid-state relay provided in an embodiment of the present application; Figure 4 This is a circuit diagram of a delayed and anti-interference optically isolated solid-state relay provided in an embodiment of the present application.
[0027] Description of reference numerals: R1-first resistor, R2-second resistor, R3-third resistor, R4-fourth resistor, R5-fifth resistor, R6-sixth resistor, C1-first capacitor, C2-second capacitor, D1-first diode, ZD1-first voltage-stabilizing diode, ZD2-second voltage-stabilizing diode, V1-first transistor, V2-second transistor, V3-third transistor, V4-light-emitting diode chip, V5-photocell chip, Q1-NMOS tube, IM1-isolation module. DETAILED DESCRIPTION
[0028] In order to enable technicians in this field to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below in conjunction with the drawings in the embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments.
[0029] In the description of the embodiments of the present application, words such as "for example" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "for example" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "for example" or "for example" is intended to present related concepts in a specific way.
[0030] In the description of the embodiments of the present application, the term "plurality" means two or more. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. The terms "include", "comprise", "have" and their variations all mean "including but not limited to", unless otherwise specifically emphasized.
[0031] The following is combined with Figure 1-Figure 4 The embodiments of the present application are described.
[0032] The present application provides an optically isolated solid-state relay, such as Figure 1 As shown, Figure 1 : is a structural block diagram of an optically isolated solid-state relay provided in an embodiment of the present application, including: an input delay circuit, an input discharge circuit, an isolation module, an output delay circuit, an output anti-interference circuit and a MOS tube, wherein: The input delay circuit is connected between the input end of the optical isolation solid state relay and the input end of the isolation module, and the input delay circuit is used to delay the input signal; The input discharge circuit is connected to the input delay circuit, and the input discharge circuit is configured to provide a discharge circuit for the input capacitor when the input is turned off, wherein the input delay circuit includes the input capacitor; The input end of the output delay circuit is connected to the output end of the isolation module, the output end of the output delay circuit is connected to the gate and source of the MOS tube, the drain and source of the MOS tube serve as the positive output end and the negative output end of the optical isolation solid state relay respectively, and the output delay circuit is used to perform a slow-on process on the MOS tube; The output anti-interference circuit is connected between the output delay circuit and the MOS tube. The output anti-interference circuit is configured to provide a discharge path for the gate-source voltage of the MOS tube when a peak voltage is generated at the output end of the MOS tube.
[0033] In the above embodiment, the optically isolated solid-state relay realizes the delayed processing of the input signal, effectively preventing the mis-conduction phenomenon caused by the input interference signal. At the same time, the input discharge circuit provides a fast discharge path for the input capacitor when the input is turned off, avoiding the risk of the field effect tube being half-conducted and burned due to the slow discharge of the capacitor. The output delay circuit performs a slow connection process on the MOS tube, further improving the stability and reliability of the system. When the output anti-interference circuit generates a spike voltage at the output end of the MOS tube, it provides a discharge path for its gate-source voltage, enhancing the anti-interference ability of the equipment. This technical solution solves the problems of mis-conduction, slow capacitor discharge, output impact and spike voltage damage, improves the reliability and stability of the optically isolated solid-state relay, and extends the service life of the optically isolated solid-state relay by reducing faults caused by mis-conduction, half-conduction burning and spike voltage damage.
[0034] The optically isolated solid relay structure of this embodiment includes an input delay circuit, an input discharge circuit, an isolation module, an output delay circuit, an output anti-interference circuit and a MOS tube. The input delay circuit performs delay processing on the input signal, which helps to prevent mis-conduction caused by input interference signals. The input delay circuit can effectively perform delay processing on the input signal to ensure that it starts working only after receiving a valid signal that lasts for a period of time, thereby avoiding misoperation caused by short-term interference; the input discharge circuit is connected to the input delay circuit to provide a fast discharge path for the input capacitor, thereby solving the problem of slow capacitor discharge and possible semi-conduction burning of the field effect tube; the isolation module realizes electrical isolation between the input and the output, thereby improving the safety and reliability of the relay; the output delay circuit performs slow connection processing on the MOS tube, thereby helping to reduce the impact and instability of the output end; the output anti-interference circuit provides a discharge path for the gate-source voltage of the MOS tube, thereby preventing the peak voltage from damaging the MOS tube; the MOS tube serves as the output switch of the relay, and its drain and source serve as the positive output terminal and the negative output terminal of the optically isolated solid relay, respectively. Through the input delay circuit, the response time of the input signal can be extended to prevent false conduction caused by input interference signals; through the input discharge circuit, the charge in the input capacitor can be quickly discharged to avoid the risk of burning the field effect tube when it is half-conducted; through the output delay circuit, the connection speed of the output end can be slowed down to reduce output shock and instability; through the output anti-interference circuit, a discharge path can be provided for the gate-source voltage of the MOS tube to prevent the spike voltage from damaging the MOS tube. In summary, the circuit structure of the optical isolation solid-state relay of this embodiment significantly improves the performance of the solid-state relay, making it more suitable for high-reliability application scenarios.
[0035] In an optional embodiment, if Figure 2 As shown, the input delay circuit includes: a first resistor R1, a first capacitor C1, a first diode D1 and a first voltage-stabilizing diode ZD1, wherein the first end of the first resistor R1 is electrically connected to the positive input end of the optical isolation solid state relay, the second end of the first resistor R1 is electrically connected to the positive electrode of the first diode D1, the negative electrode of the first diode D1 is electrically connected to the negative electrode of the first voltage-stabilizing diode ZD1, the positive electrode of the first voltage-stabilizing diode ZD1 is electrically connected to the positive input end of the isolation module IM1, the negative input end of the isolation module IM1 is electrically connected to the negative input end of the optical isolation solid state relay, the first capacitor C1 is connected between the negative electrode of the first voltage-stabilizing diode ZD1 and the negative input end of the optical isolation solid state relay, wherein the first capacitor C1 is an input capacitor.
[0036] In the above embodiment, the delayed processing of the input signal is realized, and the misleading conduction phenomenon caused by the input interference signal is effectively prevented. Figure 2As shown, the input circuit of the optical isolation solid state relay includes an input delay circuit and an input discharge circuit. Specifically, the input delay circuit composed of the first resistor R1, the first capacitor C1, the first diode D1 and the first voltage stabilizing diode ZD1 ensures that the input signal triggers the subsequent circuit action only after reaching the predetermined delay time through delay processing of the input signal, thereby improving the stability and reliability of the system. At the same time, the design can also adapt to the delay requirements in different application scenarios, enhancing the flexibility and scope of application of the product.
[0037] The first resistor R1 and the first capacitor C1 together form an RC delay circuit, which can adjust the delay time in combination with the first voltage stabilizing diode ZD1 and the conduction voltage drop of the light emitting diode chip V4 in the input end of the isolation module IM1. The delay time is the time when the voltage across the first capacitor C1 rises to the sum of the voltage stabilizing value of the first voltage stabilizing diode ZD1 and the conduction voltage drop of the light emitting diode chip V4 in the isolation module IM1. In this embodiment, the delay of the input signal can be accurately controlled by the combination of the first resistor R1, the first capacitor C1, the first diode D1 and the first voltage stabilizing diode ZD1 to meet the requirements of time control for specific applications. The function of the first voltage stabilizing diode ZD1 is to stabilize the voltage, ensure that the voltage of the input signal is at a safe and stable level, and avoid the influence of voltage fluctuations on the operation of the relay.
[0038] In an optional embodiment, if Figure 2 As shown, the input discharge circuit includes: a first transistor V1, a second transistor V2, a second resistor R2 and a third resistor R3, wherein the first transistor V1 is a PNP transistor, the emitter of the first transistor V1 is electrically connected to the cathode of the first voltage stabilizing diode ZD1, the base of the first transistor V1 is electrically connected to the anode of the first diode D1, and the collector of the first transistor V1 is electrically connected to the cathode input terminal of the optical isolation solid state relay through the second resistor R2; the second transistor V2 It is an NPN transistor, the collector of the second transistor V2 is electrically connected to the base of the first transistor V1, the base of the second transistor V2 is electrically connected to the collector of the first transistor V1, and the emitter of the second transistor V3 is electrically connected to the negative input terminal of the optical isolation solid state relay, wherein when the input is turned off, the voltage across the first capacitor C1 is quickly discharged through the second resistor R2; the third resistor R3 is connected between the base of the first transistor V1 and the negative input terminal of the optical isolation solid state relay.
[0039] In the above embodiment, when the input of the optical isolation solid state relay is turned off, the voltage across the first capacitor C1 can be quickly discharged through the second resistor R2, thereby avoiding the problem of the field effect tube being half-conducted or even burned due to the slow capacitor discharge of the RC network in the related art when it is turned off. Specifically, the discharge circuit composed of the first transistor V1 and the second transistor V2 can be quickly turned on when the input is turned off, so that the voltage across the first capacitor C1 is quickly released through the second resistor R2, thereby improving the reliability and safety of the system.
[0040] In the prior art, when the input signal is turned off, the charge discharge speed in the input capacitor may be slow, causing the field effect tube and other components to be in a semi-conducting state, which may cause burnout and other faults over a long period of time. The input discharge circuit realizes the rapid discharge of the charge in the input capacitor (first capacitor C1) through a carefully designed combination of transistors (first transistor V1 and second transistor V2) and resistors (second resistor R2 and third resistor R3). When the input signal is turned off, the first transistor V1 and the second transistor V2 form a discharge path, so that the voltage across the first capacitor C1 can be quickly reduced, thereby avoiding the failure of the field effect tube and other components caused by being in a semi-conducting state for a long time. Rapid discharge of capacitor charge not only protects the field effect tube and other components from damage, but also improves the stability and reliability of the entire circuit, which helps to extend the service life of the relay and reduce the downtime caused by faults. The two-stage amplification composed of the first transistor V1 and the second transistor V2 can achieve the effect of rapid discharge.
[0041] In an optional embodiment, the isolation module IM1 includes a light-emitting diode chip V4 and a photocell chip V5, the positive electrode of the light-emitting diode chip V4 is electrically connected to the positive electrode of the first voltage-stabilizing diode ZD1, the negative electrode of the light-emitting diode chip V4 is electrically connected to the negative electrode input terminal of the optical isolation solid-state relay, the positive electrode of the photocell chip V5 is electrically connected to the gate of the MOS tube through the output delay circuit, and the negative electrode of the photocell chip V5 is electrically connected to the negative electrode output terminal of the optical isolation solid-state relay, wherein the isolation module IM1 is used to realize optical isolation between the input and output of the optical isolation solid-state relay.
[0042] In the above embodiment, the optical isolation solid-state relay realizes effective optical isolation between input and output, ensuring the safety and stability of the relay under high voltage environment. Specifically, the combined use of the light-emitting diode chip V4 and the photocell chip V5 enables the input signal to be transmitted to the output end through the optical signal, avoiding the electromagnetic interference problem existing in the traditional electrical isolation method and improving the anti-interference ability of the system. At the same time, this optical isolation design can also effectively prevent the interference signal at the input end from directly affecting the output end, further enhancing the reliability and safety of the relay.
[0043] The isolation module IM1 (also referred to as an optical isolation module) of this embodiment uses a light emitting diode chip V4 and a photocell chip V5 to achieve optical isolation. Figure 2-Figure 4 As shown, the influence of electromagnetic interference is eliminated, and the optical signal transmission is not affected by the electromagnetic field, ensuring the reliability and stability of the signal; the LED chip V4 converts the input signal into an optical signal, which is received and converted back into an electrical signal through the photocell chip V5, realizing complete electrical isolation between the input and the output. The isolation module adopts a combination of the LED chip V4 and the photocell chip V5 to achieve complete electrical isolation between the input and the output. This can effectively prevent electrical noise, interference and electric shock hazards, and improve the safety and reliability of the relay; the LED chip V4 and the photocell chip V5 are optical coupling components, which have fast response speed and small transmission delay. At the same time, since the optical signal transmission is not affected by electrical characteristics, it can greatly reduce signal distortion and improve the performance of the relay; the LED chip V4 and the photocell chip V5 are solid-state components with high reliability and stability. They are not easily affected by environmental factors such as temperature and humidity, so they can maintain a stable isolation effect for a long time.
[0044] In an optional embodiment, the capacitance value of the first capacitor C1 is allowed to be adjusted to meet the delay time requirement of the input delay circuit.
[0045] In the above embodiment, the delay time of the input delay circuit can be flexibly adjusted to meet the needs of different application scenarios. Specifically, the capacitance value of the first capacitor C1 can be adjusted according to actual needs, thereby accurately controlling the delay time of the input signal, ensuring that false triggering can be effectively prevented under various working conditions, and improving the reliability and stability of the system.
[0046] This embodiment can meet the requirements of different delay times by allowing the capacitance value of the first capacitor C1 to be adjusted. This increases the flexibility and applicability of the optical isolation solid-state relay, enabling it to be applied to a wider range of scenarios; there is no need to design and produce different relays for each delay time requirement, and the required delay time can be achieved by simply adjusting the capacitance value, which reduces design and production costs and improves production efficiency; when the delay time needs to be adjusted, only the capacitor needs to be replaced or adjusted, without large-scale modifications to the entire circuit. This simplifies the maintenance and upgrade process and reduces maintenance costs.
[0047] In an optional embodiment, if Figure 3As shown, the output delay circuit includes: a fourth resistor R4, a second capacitor C2 and a fifth resistor R5, wherein the first end of the fourth resistor R4 is electrically connected to the positive output end of the isolation module IM1, the second end of the fourth resistor R4 is electrically connected to the gate of the MOS tube through the fifth resistor R5, the second capacitor C2 is connected between the second end of the fourth resistor R4 and the negative output end of the isolation module IM1, and the negative output end of the isolation module IM1 is electrically connected to the negative output end of the optical isolation solid state relay.
[0048] In the above embodiment, the slow-on processing of the output signal is realized, which effectively avoids the current shock caused by the rapid opening of the MOS tube and improves the stability and reliability of the system; at the same time, the delay time is controlled by the RC network, so that the output delay is adjustable to meet the needs of different application scenarios.
[0049] like Figure 3 As shown, the output circuit of the optical isolation solid-state relay includes an output delay circuit, an output anti-interference circuit and a MOS tube. The output delay circuit of this embodiment realizes the control of the output response time through the combination of the fourth resistor R4, the second capacitor C2 and the fifth resistor R5. When the input signal changes, the output will not respond immediately, but will change after a delay, thereby realizing the slow rise control of the gate voltage of the MOS tube, effectively avoiding the current shock caused by rapid conduction, which helps to reduce electrical shock and interference and improve the stability of the circuit. By adjusting the resistance values of the fourth resistor R4, the second capacitor C2 and the fifth resistor R5, the output delay time can be flexibly adjusted to meet the needs of different application scenarios. This increases the flexibility and applicability of the relay; the output delay function can provide a smooth transition when the relay switches states, reducing the impact and damage to the load equipment caused by instantaneous voltage or current changes; the output delay circuit can effectively filter out instantaneous interference in the input signal, ensuring that the output signal will only change after the input signal continues for a period of time, avoiding malfunction of the load equipment; the charging and discharging process of the second capacitor C2 ensures a smooth transition of the output signal when it is turned on and off, reducing the impact on the load equipment and improving the reliability and life of the system.
[0050] In an optional embodiment, if Figure 3 As shown, the output anti-interference circuit includes a third triode V3, which is a PNP triode. The emitter of the third triode V3 is electrically connected to the gate of the MOS tube, the base of the third triode V3 is electrically connected to the second end of the fourth resistor R4, and the collector of the third triode V3 is electrically connected to the source of the MOS tube. When a peak voltage is generated at the output end of the MOS tube, the gate-source voltage of the MOS tube is discharged through the third triode V3.
[0051] In the above embodiment, when a peak voltage is generated at the output end of the MOS tube, the third transistor V3 is quickly turned on to discharge the gate-source voltage of the MOS tube, thereby effectively avoiding the risk of damage to the MOS tube due to overvoltage and improving the stability and reliability of the optical isolation solid state relay.
[0052] During the switching process of the MOS tube, due to the parasitic parameters and rapid voltage changes in the circuit, spike voltages are easily generated, which may cause device damage or affect the stability of the circuit. In the absence of effective spike voltage suppression measures, the spike voltage generated by the MOS tube during switching may damage the circuit, especially in high-frequency switching applications. In this embodiment, through the setting of the third transistor V3, when a spike voltage is generated at the output end of the MOS tube, the gate-source voltage of the MOS tube can be discharged through the third transistor V3, effectively reducing the impact of the spike voltage on the circuit; the addition of the third transistor V3 provides an additional anti-interference path, which helps to absorb and discharge the spike voltage, and enhances the anti-interference ability of the entire optical isolation solid-state relay; the discharge of the spike voltage can protect the MOS tube from the influence of voltage spikes, extend the service life of the MOS tube, and improve the reliability of the entire relay; by discharging the spike voltage, the system can better cope with various interferences, and improve the anti-interference ability and stability. The output circuit of the solid-state relay in the related art does not provide an effective output anti-interference circuit. Therefore, when the output voltage rises at a fast rate, part of the output voltage will be coupled to the gate through the parasitic capacitance between the drain and gate of the MOS tube, and charge the second capacitor C2; due to the lack of a fast discharge circuit in the loop, the coupled voltage cannot be discharged quickly. When the accumulated charge exceeds the threshold voltage of the power MOS tube, it will cause the power MOS tube to be misconnected. The output anti-interference circuit provided in this embodiment can solve this problem.
[0053] In an optional embodiment, if Figure 3 As shown, the output anti-interference circuit further includes a sixth resistor R6, wherein the sixth resistor R6 is connected in parallel with the second capacitor C2.
[0054] In the above embodiment, when a peak voltage is generated at the output end of the MOS tube, the gate-source voltage of the MOS tube can be quickly discharged through the third triode V3, effectively protecting the MOS tube from damage. At the same time, the sixth resistor R6 is connected in parallel with the second capacitor C2, which further speeds up the charging and discharging speed of the second capacitor C2 and improves the response speed and stability of the system.
[0055] When the photocell chip does not provide a fast discharge path, the sixth resistor can be used for fast discharge. After the sixth resistor R6 in this embodiment is connected in parallel with the second capacitor C2, an RC discharge loop can be formed. When the gate-source voltage needs to be discharged, the sixth resistor R6 can provide an additional discharge path to accelerate the discharge process of the capacitor, thereby more effectively suppressing the spike voltage; by accelerating the discharge speed of the second capacitor C2, the MOS tube can enter the fully turned-off state faster when it is turned off, reducing the time of partial conduction and reducing the risk of burning; the combination of the sixth resistor R6 and the third triode V3 provides a dual protection mechanism. The third triode V3 is responsible for quickly discharging the gate-source voltage when the spike voltage is generated, while the sixth resistor R6 accelerates the discharge process of the second capacitor C2, further reducing the duration of the spike voltage. By accelerating the capacitor discharge speed and enhancing the discharge effect of the spike voltage, the system can better cope with various interferences and abnormal situations, reduce the failure rate of the MOS tube, and improve the stability and reliability of the system.
[0056] In an optional embodiment, the optically isolated solid-state relay further includes: a second zener diode ZD2, wherein the cathode of the second zener diode ZD2 is electrically connected to the gate of the MOS tube, and the anode of the second zener diode ZD2 is electrically connected to the source of the MOS tube.
[0057] In the above embodiment, the second voltage stabilizing diode ZD2 can play a voltage stabilizing role when the gate-source voltage of the MOS tube exceeds a certain threshold, effectively protecting the MOS tube from overvoltage shock, improving the voltage resistance of the MOS tube, and thus enhancing the reliability and stability of the entire optical isolation solid state relay.
[0058] like Figure 3-Figure 4 As shown, a second voltage stabilizing diode ZD2 is further provided in the output circuit. By providing the second voltage stabilizing diode ZD2, the maximum voltage of the gate of the MOS tube can be limited to prevent the excessive voltage from damaging the MOS tube, thereby protecting the MOS tube; the addition of the second voltage stabilizing diode ZD2 helps to stabilize the gate voltage of the MOS tube, reduce the influence of voltage fluctuation on the working state of the MOS tube, and improve the stability of the circuit; the second voltage stabilizing diode ZD2 can absorb and limit the voltage spike caused by external interference or internal changes of the circuit, and enhance the anti-interference ability of the entire optical isolation solid state relay.
[0059] In an optional embodiment, the MOS transistor is an NMOS transistor Q1.
[0060] In the above embodiment, the NMOS transistor Q1 is selected as the output control element, so that it performs well in terms of low power consumption and high efficiency, while improving the overall performance of the system.
[0061] NMOS tube Q1 can reduce power loss and improve circuit efficiency due to its low on-resistance; NMOS tube Q1 can improve the response speed of the circuit due to its fast switching characteristics, which is particularly important for application scenarios that require fast switching; NMOS tube Q1 performs well in high-frequency and high-power applications and has high reliability and stability. This enables the relay to operate stably for a long time in these applications and reduces the failure rate. NMOS tube Q1 has relatively stable performance in high-temperature environments and can adapt to various harsh working conditions, improving the environmental adaptability and reliability of the system.
[0062] It should be noted that the above-described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application will be described in detail below in conjunction with specific embodiments.
[0063] The embodiment of the present application provides a time-delay anti-interference optical isolation solid-state relay, Figure 4 The circuit diagram of a time-delay anti-interference optical isolation solid-state relay provided in the embodiment of the present application includes an input part (or called input circuit) and an output part (or called output circuit). An isolation module is connected between the input circuit and the output circuit to achieve electrical isolation between the input and the output. The isolation module includes a light-emitting diode chip V4 and a photocell chip V5. Among them, the input circuit is as follows Figure 2 As shown, the output circuit is as Figure 3 shown.
[0064] The working principles of the input circuit and the output circuit are described below.
[0065] (1) Input circuit The input circuit structure of the solid state relay of the present application embodiment is shown in Figure 2 The delay function is realized by the first capacitor C1, the first resistor R1, the first voltage zener diode ZD1, and the light emitting diode chip V4. The first capacitor C1 and the first resistor R1 form an RC delay network, which can adjust the delay time in combination with the first voltage zener diode ZD1 and the light emitting diode chip V4. The time it takes for the voltage across the first capacitor C1 to rise to the sum of the voltage stabilization value of the first voltage zener diode ZD1 and the conduction voltage of the light emitting diode chip V4 is the delay time.
[0066] Figure 2 The circuit shown also has an anti-temperature drift function. Through the temperature drift characteristics of the first voltage zener diode ZD1 (voltage stabilization value is greater than 6.2V) and the light emitting diode chip V4 (at low temperatures, the on-state voltage of the light emitting diode chip V4 increases, the voltage stabilization value of the first voltage zener diode ZD1 decreases, and the influence of temperature changes is offset. At high temperatures, the two change in the opposite way, and the influence of temperature changes can be offset by the same logic), the shortcoming of the delay circuit having large delay temperature drift in the full temperature range is improved.
[0067] In addition, in the related art, there is a solution of using a combination of multiple resistors to achieve delay, which leads to a large restriction on the resistance value of the resistor, and at high frequency of switching, the delay time may be shortened. Figure 2 The delay function in the circuit is only affected by the first capacitor C1, the first resistor R1, the first voltage regulator diode ZD1, and the light-emitting diode chip V4. Under the rated voltage, the light-emitting diode drive current I C ≥10mA, the resistance value of the first resistor R1 can be determined, and then the required delay time can be adjusted by adjusting the capacitance of the first capacitor C1. Figure 2 The effect of the first diode D1 on input delay can be ignored. The main function of the first diode D1 is to discharge the voltage across the first capacitor C1 through the first transistor V1 when the input is turned off, rather than directly through the third resistor R3, so as to achieve the purpose of fast discharge.
[0068] for Figure 2 In the input delay circuit shown, when the product is turned on, the voltage relationship across the RC series circuit is: U=U0e -t / τ Where: Uo is the voltage at the relay input, unit is V; t is the time; τ is the time constant of the RC circuit.
[0069] From the above formula, the input on time of the product can be obtained as: T≈-τln[1-(U2+U E1 ) / (U0-U1)], U1 represents the conduction voltage drop of the first diode, U2 represents the voltage value of the first voltage regulator diode, and U E1 It represents the conduction voltage drop of the light emitting diode chip V4 in the isolation module IM1.
[0070] In this circuit, the first resistor R1 and the first capacitor C1 form an RC delay network, which is combined with the first voltage zener diode ZD1 and the light emitting diode chip V4 to adjust the delay time. The delay time is the time it takes for the voltage across the first capacitor C1 to rise to the sum of the voltage stabilization value of the first voltage zener diode ZD1 and the conduction voltage of the light emitting diode chip V4. At the same time, the circuit also has an anti-temperature drift function, which is achieved through the opposite temperature drift characteristics of the first voltage zener diode ZD1 and the light emitting diode chip V4.
[0071] The key to the input circuit of the embodiment of the present application is that the relay product forms an input fast discharge circuit through the first diode D1, the first transistor V1, the second transistor V2, and the second resistor R2, which improves the disadvantage of slow input discharge in the input circuit in the related art. When the input is turned off, due to the presence of the first diode D1, when the voltage across the first capacitor C1 is higher than 0.7V than the base of the first transistor V1, the first transistor V1 will be turned on, and the voltage across the first capacitor C1 will be discharged through the second resistor R2. And because the second resistor R2 is independent of the delayed connection system, its resistance value is not limited by the parameters of other devices in the circuit, and its discharge rate is greatly improved compared with the circuit in the related art.
[0072] (2) Output circuit The output circuit structure of the solid state relay in the present embodiment is shown in FIG. Figure 3 .
[0073] For the output slow-on circuit, Figure 3 The slow-on principle of the middle circuit is: the fourth resistor R4 and the second capacitor C2 form an RC delay network. In addition, the parasitic capacitance between the fifth resistor R5 and the drain gate of the NMOS tube Q1 also forms a delay network, which plays a role in slow-on and has the function of resisting input interference. When there is a strong interference voltage at the input, the voltage coupled to the secondary will be filtered and absorbed by the RC circuit (such as R4C2), and has a good ability to resist input interference. On this basis, the output circuit of this embodiment reduces the risk of mis-conduction of the product due to the output spike voltage by adding the third transistor V3. When a spike voltage is suddenly added to the output, the coupled gate-source voltage V GS The capacitor C2 is charged through the BE junction of the third transistor V3. During the charging process, the third transistor V3 will be turned on, and the gate-source voltage will be discharged through the third transistor V3, so that the coupled gate voltage is limited to the transistor BE junction conduction voltage drop, thereby relaxing the requirement on the field effect transistor threshold voltage. Even if the field effect transistor threshold voltage is low, there will be no mis-conduction when a spike voltage is suddenly added to the output.
[0074] However, the output circuit of the solid-state relay in the related art does not adopt the Figure 3The third triode V3 shown has poor output spike interference resistance, because the electrodes inside the power MOSFET are not physically isolated, and there is parasitic capacitance between the electrodes. When the output voltage rises faster, part of the output voltage will be coupled to the gate through parasitic capacitance (such as the parasitic capacitance between the drain and gate of the NMOS tube) to charge the second capacitor C2. Due to the lack of a fast discharge circuit in the loop, the coupled voltage cannot be discharged quickly. When the accumulated charge exceeds the power MOSFET threshold voltage, the power MOSFET will be mis-conducted. It can be seen that the output circuit of the solid relay in the related art has poor performance. The output circuit of the embodiment of the present application effectively improves the output spike interference resistance.
[0075] In summary, the embodiments of the present application provide a solid-state relay circuit that has delayed connection, fast input discharge, and anti-interference functions.
[0076] It should be noted that: when the device provided in the above embodiment realizes its function, only the division of the above functional modules is used as an example. In actual application, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the device and method embodiments provided in the above embodiment belong to the same concept, and the specific implementation process is detailed in the method embodiment, which will not be repeated here.
[0077] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.
[0078] The above is only an exemplary embodiment of the present disclosure and cannot be used to limit the scope of the present disclosure. That is, any equivalent changes and modifications made according to the teachings of the present disclosure are still within the scope of the present disclosure. After considering the disclosure of the specification, those skilled in the art will easily think of other embodiments of the present disclosure.
[0079] This application is intended to cover any modifications, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary technical means in the technical field not recorded in the present disclosure.
Claims
1. An optically isolated solid-state relay, characterized in that: include: Input delay circuit, input discharge circuit, isolation module, output delay circuit, output anti-interference circuit and MOS tube, among which, The input delay circuit is connected between the input end of the optical isolation solid state relay and the input end of the isolation module, and the input delay circuit is used to delay the input signal; The input discharge circuit is connected to the input delay circuit, and the input discharge circuit is configured to provide a discharge circuit for the input capacitor when the input is turned off, wherein the input delay circuit includes the input capacitor; The input end of the output delay circuit is connected to the output end of the isolation module, the output end of the output delay circuit is connected to the gate and source of the MOS tube, the drain and source of the MOS tube serve as the positive output end and the negative output end of the optical isolation solid state relay respectively, and the output delay circuit is used to perform a slow-on process on the MOS tube; The output anti-interference circuit is connected between the output delay circuit and the MOS tube, and the output anti-interference circuit is configured to provide a discharge path for the gate-source voltage of the MOS tube when a peak voltage is generated at the output end of the MOS tube.
2. The optical isolation solid state relay according to claim 1, characterized in that: The input delay circuit includes: a first resistor, a first capacitor, a first diode and a first voltage regulator diode, wherein: The first end of the first resistor is electrically connected to the positive input terminal of the optical isolation solid state relay, the second end of the first resistor is electrically connected to the positive electrode of the first diode, the negative electrode of the first diode is electrically connected to the negative electrode of the first voltage regulator diode, the positive electrode of the first voltage regulator diode is electrically connected to the positive input terminal of the isolation module, the negative input terminal of the isolation module is electrically connected to the negative input terminal of the optical isolation solid state relay, and the first capacitor is connected between the negative electrode of the first voltage regulator diode and the negative input terminal of the optical isolation solid state relay, wherein the first capacitor is the input capacitor.
3. The optical isolation solid state relay according to claim 2, characterized in that: The input discharge circuit includes: a first transistor, a second transistor, a second resistor and a third resistor, wherein: The first transistor is a PNP transistor, the emitter of the first transistor is electrically connected to the cathode of the first voltage stabilizing diode, the base of the first transistor is electrically connected to the anode of the first diode, and the collector of the first transistor is electrically connected to the cathode input terminal of the optical isolation solid state relay through the second resistor; The second transistor is an NPN transistor, the collector of the second transistor is electrically connected to the base of the first transistor, the base of the second transistor is electrically connected to the collector of the first transistor, and the emitter of the second transistor is electrically connected to the negative input terminal of the optical isolation solid state relay, wherein when the input is turned off, the voltage across the first capacitor is quickly discharged through the second resistor; The third resistor is connected between the base of the first transistor and the negative input terminal of the optical isolation solid state relay.
4. The optical isolation solid state relay according to claim 2, characterized in that: The isolation module includes a light-emitting diode chip and a photocell chip, wherein the positive electrode of the light-emitting diode chip is electrically connected to the positive electrode of the first voltage-stabilizing diode, the negative electrode of the light-emitting diode chip is electrically connected to the negative electrode input terminal of the optically isolated solid-state relay, the positive electrode of the photocell chip is electrically connected to the gate of the MOS tube through the output delay circuit, and the negative electrode of the photocell chip is electrically connected to the negative electrode output terminal of the optically isolated solid-state relay, wherein the isolation module is used to realize optical isolation between the input and output of the optically isolated solid-state relay.
5. The optical isolation solid state relay according to claim 2, characterized in that: The capacitance value of the first capacitor is allowed to be adjusted to meet the delay time requirement of the input delay circuit.
6. The optical isolation solid state relay according to claim 1, characterized in that: The output delay circuit includes: a fourth resistor, a second capacitor and a fifth resistor, wherein: The first end of the fourth resistor is electrically connected to the positive output end of the isolation module, the second end of the fourth resistor is electrically connected to the gate of the MOS tube through the fifth resistor, the second capacitor is connected between the second end of the fourth resistor and the negative output end of the isolation module, and the negative output end of the isolation module is electrically connected to the negative output end of the optical isolation solid state relay.
7. The optical isolation solid state relay according to claim 6, characterized in that: The output anti-interference circuit includes a third triode, which is a PNP triode, an emitter of the third triode is electrically connected to the gate of the MOS tube, a base of the third triode is electrically connected to the second end of the fourth resistor, and a collector of the third triode is electrically connected to the source of the MOS tube, wherein when a peak voltage is generated at the output end of the MOS tube, the gate-source voltage of the MOS tube is discharged through the third triode.
8. The optical isolation solid state relay according to claim 7, characterized in that: The output anti-interference circuit further includes a sixth resistor, wherein the sixth resistor is connected in parallel with the second capacitor.
9. The optical isolation solid state relay according to claim 1, characterized in that: The optical isolation solid state relay further includes: a second voltage stabilizing diode, wherein the cathode of the second voltage stabilizing diode is electrically connected to the gate of the MOS tube, and the anode of the second voltage stabilizing diode is electrically connected to the source of the MOS tube.
10. The optical isolation solid state relay according to claim 9, characterized in that: The MOS tube is an NMOS tube.