Simple high-reliability ESD (Electro-Static Discharge) design architecture capable of being widely applied to analog switch
By adopting a simple and highly reliable ESD design architecture including ESD protection diodes and MOS switching circuits in the analog switch chip, the problems of weak ESD protection capabilities and excessive layout area in the prior art are solved, and high-reliability ESD protection and the effect of reducing chip costs are achieved.
Patent Information
- Application Number
- CN202411978353.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2025-05-02
AI Technical Summary
The ESD protection architecture of the existing analog switch chips has a back-to-back ESD protection diode, which leads to an over-the-top layout area and a weak ESD protection capability, which cannot effectively solve the problem of the special power-on timing of ordinary analog switch chips and the problem of the inability to overvoltage of analog ports.
Using a simple and highly reliable ESD design architecture including ESD protection diodes and MOS switching circuits, it provides high-reliable ESD protection capabilities while reducing chip area by connecting the S and D ports of the diodes D22-D32 and the MOS switching circuits.
It realizes high-reliable ESD protection for analog switch chips, solves the problem of special power-on timing and the problem of analog ports not being overvoltage, and at the same time reduces the chip area and cost, and improves the ESD protection capability.
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Figure CN119921751A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of vehicle collaborative task offloading, and in particular relates to a simple and high-reliability ESD design architecture that can be widely used in analog switches. Background Art
[0002] Analog switch chips are core components widely used in signal selection and transmission in signal systems. They can be divided into two categories: ordinary analog switches and special analog switches. In order to improve the reliability of analog switch chips, ESD protection design of the chips is essential.
[0003] The ESD protection architecture of common analog switch chips is as follows: Figure 1 As shown in the figure, this architecture requires that the chip port power-on timing be specially set when using this type of analog switch chip, that is, the S / D port signal of the analog switch chip must be powered on later than the positive and negative power supplies; at the same time, the S / D port signal cannot exceed the positive and negative power supply voltage when the chip is working normally. Otherwise, the signal of the S / D port will be connected to the positive and negative power supply terminals of the chip through D4 / D5 / D6 / D7, which may cause the system to work abnormally at best, or even cause the chip to burn out, resulting in system function failure.
[0004] Special analog switches usually have functions such as overvoltage protection, power-off isolation, and cold backup. The chip ESD protection architecture is as follows: Figure 2 As shown, this architecture can ensure that the analog switch has no port power-on sequence requirements during use; at the same time, in special use cases such as when the S / D signal of the chip analog signal port exceeds the positive and negative power supply voltage, the chip is powered off, or the chip is used as a cold backup, the S / D port signal will not be connected to the positive and negative power supply ports through the ESD protection device, avoiding system abnormalities or even system damage. However, this architecture has back-to-back ESD protection diodes between the S / D port and the positive and negative power supply ports, which will result in: first, the chip ESD protection device layout area is too large; second, during the ESD protection process, such as when the S to D port tests a positive ESD pulse, Figure 4 In the ESD architecture shown, there are at least two reverse ESD protection diodes D13 and D18 or D16 and D19 connected in series between the S and D ports. However, due to the breakdown weakness of a reverse diode D34 or D35 in the MOS switch circuit equivalent diode model between the S and D ports, the ESD protection capability of this ESD protection architecture is relatively weak. Therefore, we propose a simple and high-reliability ESD design architecture that can be widely used in analog switches. Summary of the invention
[0005] In order to solve the above technical problems, the present invention provides a simple and high-reliability ESD design architecture that can be widely used in analog switches, including ESD protection diodes and MOS switch circuits, wherein the ESD protection diodes include diodes D22, D23, D24, D25, D26, D27, D28, D29, D30, D31 and D32, the EN pin is connected to the cathode of diode D22, the anodes of diodes D23 and D24 are connected and grounded, the anode of diode D22 is grounded, and the cathode of diode D23 is connected to the positive power supply V DD, and the anode of the diode D24 is connected to the negative power supply VSS, the anode of the diode D27 is connected to the positive power supply VDD, the cathode of the diode D27 is connected to the cathodes of the diodes D25, D29 and D31, the anodes of the diodes D25 and D29 are connected to the cathodes of the diodes D26 and D30 respectively, the anodes of the diodes D26 and D30 are both connected to the anode of the diode D28, the cathode of the diode D28 is connected to the negative power supply VSS, the anode of the diode D31 is connected to the anodes of the diodes D28 and D30, and the positive and negative electrodes of the diode D32 are connected to the positive power supply VDD and the negative power supply VSS respectively;
[0006] The MOS switch circuit is specifically a universal MOS switch architecture, and the S port and the D port of the MOS switch circuit are respectively connected to the conductors between the diodes D25 and D26 and the diodes D29 and D30.
[0007] Preferably, the MOS switch circuit includes a diode D33, a diode D34, a diode D35 and a diode D36, wherein the cathodes of the diode D33 and the diode D34 are adjacent, the anode of the diode D33 is connected to the diode D35 and the S port, the anodes of the diode D35 and the diode D36 are connected, and the cathode of the diode D36 is connected to the anode of the diode D34 and the D port.
[0008] Preferably, the cathode of the diode D29 and the anode of the diode D30 are also connected to the chip internal wire networks VDD_1 and VSS_1 respectively.
[0009] Beneficial effects of the present invention:
[0010] The present invention provides a simple and highly reliable ESD design architecture that can be widely used for analog switches. It can not only solve the problems of special power-on timing of ordinary analog switch chips and the inability of analog ports to be over-voltaged, but also can provide highly reliable ESD protection capabilities for special types of analog switch chips, such as analog switch chips with power-off isolation, overvoltage protection, cold backup, etc., while reducing the chip area and thus reducing the chip cost. BRIEF DESCRIPTION OF THE DRAWINGS
[0011] Figure 1 is the overall circuit diagram of the present invention;
[0012] Figure 2 is a circuit diagram of a MOS switch circuit of the present invention;
[0013] Figure 3 The TLP test diagram of the S and D ports of the MOS switch circuit designed for the ESD architecture of the present invention;
[0014] Figure 4 It is a common overall circuit diagram in the present invention. DETAILED DESCRIPTION
[0015] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0016] Various embodiments of the present invention may be presented in the form of a range. It should be understood that the description in the form of a range is only for convenience and simplicity and should not be understood as a rigid limitation on the scope of the present invention; therefore, it should be considered that the range description has specifically disclosed all possible sub-ranges and single values within the range. For example, it should be considered that the range description from 1 to 6 has specifically disclosed sub-ranges, such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., as well as single numbers within the range, such as 1, 2, 3, 4, 5 and 6, regardless of the range. In addition, whenever a numerical range is indicated in the present invention, it is intended to include any quoted numbers (fractions or integers) within the indicated range. Unless otherwise specified, the various raw materials, reagents, instruments and equipment used in the present invention can be purchased from the market or can be prepared by existing equipment.
[0017] In the present invention, in the absence of any contrary description, the directional words used, such as "upper" and "lower", are specifically the directions of the drawings in the accompanying drawings. In addition, in the present invention, the terms "include", "comprise", etc. refer to "including but not limited to". In the present invention, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. In the present invention, "and / or" describes the association relationship of associated objects, indicating that three relationships may exist, for example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. Wherein A and B can be singular or plural. In the present invention, "at least one" refers to one or more, and "plural" refers to two or more. "At least one", "at least one of the following" or similar expressions refer to any combination of these items, including any combination of singular items or plural items. For example, "at least one of a, b, or c" or "at least one of a, b and c" can both mean: a, b, c, ab, i.e. a and b, ac, bc or abc, where a, b, c can be single or plural, respectively.
[0018] like Figure 1-Figure 4 As shown, an embodiment of the present invention provides a simple and high-reliability ESD design architecture that can be widely used in analog switches, characterized in that it includes an ESD protection diode and a MOS switch circuit, the ESD protection diode includes a diode D22, a diode D23, a diode D24, a diode D25, a diode D26, a diode D27, a diode D28, a diode D29, a diode D30, a diode D31 and a diode D32, the EN pin is connected to the cathode of the diode D22, the anodes of the diodes D23 and D24 are connected and grounded, the anode of the diode D22 is grounded, and the cathode of the diode D23 is connected to the positive power supply V DD, and the anode of the diode D24 is connected to the negative power supply VSS, the anode of the diode D27 is connected to the positive power supply VDD, the cathode of the diode D27 is connected to the cathodes of the diodes D25, D29 and D31, the anodes of the diodes D25 and D29 are connected to the cathodes of the diodes D26 and D30 respectively, the anodes of the diodes D26 and D30 are both connected to the anode of the diode D28, the cathode of the diode D28 is connected to the ground voltage VSS, the anode of the diode D31 is connected to the anodes of the diodes D28 and D30, and the positive and negative electrodes of the diode D32 are connected to the positive power supply VDD and the negative power supply VSS respectively;
[0019] The MOS switch circuit is specifically a universal MOS switch architecture, and the S port and the D port of the MOS switch circuit are respectively connected to the conductors between the diodes D25 and D26 and the diodes D29 and D30;
[0020] The MOS switch circuit includes a diode D33, a diode D34, a diode D35 and a diode D36, wherein the cathodes of the diodes D33 and D34 are adjacent, the anode of the diode D33 is connected to the diode D35 and the S port, the anodes of the diodes D35 and D36 are connected, and the cathode of the diode D36 is connected to the anode of the diode D34 and the D port.
[0021] The cathode of the diode D29 and the anode of the diode D30 are also connected to the chip internal wire networks VDD_1 and VSS_1 respectively.
[0022] Specifically: 1. There is no special requirement for the port power-on timing for the use of the analog switch chip, that is, the analog signal port S and port D can be powered on before the power supply VDD and the ground voltage VSS. When the port S and port D are powered on first, because there is a reverse-biased diode D27 between the port S and port D and the positive power supply VDD and a reverse-biased diode D28 between the negative power supply VSS, the signals of the port S and port D will not be connected to the positive power supply VDD and the negative power supply VSS, and any timing power-on can be achieved.
[0023] 2. During the use of the analog switch chip, the signal voltages of port S and port D are allowed to exceed the positive and negative power supply voltages. For example, when the signals of port S and port D are higher than the positive power supply VDD or lower than the negative power supply VSS, there is a reverse-biased diode D27 between port S and port D and the positive power supply VDD and a reverse-biased diode D28 between the negative power supply VSS. Therefore, the signals of port S and port D will not be connected to the positive power supply VDD and the negative power supply VSS, thereby achieving the use of port S and port D signals that can exceed the positive and negative power supply voltages.
[0024] 3. This structure can effectively save the layout area of the ESD protection diode. Figure 1 and Figure 2 The comparison of port D layouts of different ESD architectures is shown in Figure 4. The layout areas of diodes D25, D26, D29, and D30 only need half of the original layout area to achieve the original ESD protection capability. For multi-channel analog switches, it can greatly reduce the chip area, thereby reducing chip costs.
[0025] Fourth, this ESD protection architecture provides common discharge paths VDD_1 and VSS_1, and there are no two reverse-biased diodes in series between port S and port D, thus greatly improving the ESD protection capability of the ESD device between port S and port D. Figure 3 The figure shows the TLP test results between the S and D ports of a typical product that uses this ESD protection architecture. It can be seen that its ESD protection capability has been greatly improved.
[0026] The above description is only a specific embodiment of the present invention, so that those skilled in the art can understand or implement the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined in the present invention can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown in the present invention, but should conform to the widest range consistent with the principles and novel features of the present invention.
Claims
1. A simple and high-reliability ESD design architecture that can be widely used in analog switches, characterized in that: It includes an ESD protection diode and a MOS switch circuit, wherein the ESD protection diode includes a diode D22, a diode D23, a diode D24, a diode D25, a diode D26, a diode D27, a diode D28, a diode D29, a diode D30, a diode D31 and a diode D32, the EN pin is connected to the cathode of the diode D22, the anodes of the diodes D23 and D24 are connected and grounded, the anode of the diode D22 is grounded, the cathode of the diode D23 is connected to a positive power supply VDD, and the anode of the diode D24 is connected to a negative power supply VSS, The anode of the diode D27 is connected to the positive power supply VDD, the cathode of the diode D27 is connected to the cathodes of the diodes D25, D29 and D31, the anodes of the diodes D25 and D29 are connected to the cathodes of the diodes D26 and D30 respectively, the anodes of the diodes D26 and D30 are connected to the anode of the diode D28, the cathode of the diode D28 is connected to the negative power supply VSS, the anode of the diode D31 is connected to the anodes of the diodes D28 and D30, and the positive and negative electrodes of the diode D32 are connected to the positive power supply VDD and the negative power supply VSS respectively; The MOS switch circuit is specifically a universal MOS switch architecture, and the S port and the D port of the MOS switch circuit are respectively connected to the conductors between the diodes D25 and D26 and the diodes D29 and D30.
2. A simple and high-reliability ESD design architecture that can be widely used in analog switches according to claim 1, characterized in that: The MOS switch circuit includes a diode D33, a diode D34, a diode D35 and a diode D36, wherein the cathodes of the diodes D33 and D34 are adjacent, the anode of the diode D33 is connected to the diode D35 and the S port, the anodes of the diodes D35 and D36 are connected, and the cathode of the diode D36 is connected to the anode of the diode D34 and the D port.
3. A simple and high-reliability ESD design architecture that can be widely used in analog switches according to claim 1, characterized in that: The cathode of the diode D29 and the anode of the diode D30 are also connected to the chip internal wire networks VDD_1 and VSS_1 respectively.