Bidirectional level shifter suitable for open-drain and push-pull applications

Abstract

The invention discloses a bidirectional level shifter suitable for open-drain and push-pull applications, and belongs to the technical field of integrated circuits. The converter comprises an NMOS transmission tube, a gate driving module, a first NAND gate, a second NAND gate, a first level conversion module, a second level conversion module, a first feedback control monostable module, a second feedback control monostable module, a first pull-up output module and a second pull-up output module. The gate driving module automatically selects the lower voltage in the first power supply voltage and the second power supply voltage to control the conduction of the NMOS transmission tube, so that bidirectional signal transmission is realized; the feedback control monostable module triggers a forward pulse at a rising edge of an input signal to drive a large-size PMOS tube to quickly pull up an output level, so that the problem of low switching speed caused by large resistance of a pull-up resistor in traditional open-drain output is solved; the pull-up output module controls the disconnection of the output end and the power supply through the substrate voltage when the power supply is powered off, and keeps a high resistance state. The circuit does not need a direction control signal, is compatible with open-drain and push-pull modes, and has high driving capability and power-off protection characteristics.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, more specifically to a method for transmitting signals between two devices with different power supply voltages, and more particularly to a bidirectional level converter suitable for open-drain and push-pull applications. Background Art

[0002] In integrated circuits, an NMOS tube is often used to achieve bidirectional signal transmission. However, since the NMOS tube cannot directly output a high level, a pull-up resistor needs to be connected to the power supply to achieve bidirectional level conversion. This output drive mode is called open-drain output. Open-drain output can achieve "line and", that is, multiple signal output ports are directly connected together. Only when all output ports are high level, it is high level; as long as any output port is low level, it is low level. This feature makes open-drain output widely used in bus interfaces such as I2C and SMBus.

[0003] Usually, in order to reduce static power consumption, the pull-up resistor of the open-drain output has a large resistance value, which makes the pull-up switching speed of the open-drain output slow and difficult to drive a large load. The push-pull output is that the NMOS and PMOS tubes work alternately. One of the two MOS tubes is cut off and the other is turned on. It can directly output high and low levels and has a strong driving ability, especially when outputting high levels. However, if multiple push-pull output ports are directly connected, the circuit is prone to short circuit. For example, if one push-pull output is high and the other push-pull output is low, a large current will flow directly from the high-level power supply to the low-level ground, causing circuit damage. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a bidirectional level converter suitable for open-drain and push-pull applications, which can automatically perform bidirectional level conversion without a direction control signal, realize a "wired AND" function, a strong driving capability, and keep the port in a high impedance state when power is off.

[0005] The present invention adopts the following technical solutions to solve the above technical problems: The present invention provides a bidirectional level converter suitable for open-drain and push-pull applications, comprising: An NMOS transmission tube, whose drain and source are connected to the first and second signal terminals respectively, and whose gate is connected to the gate driving module, for realizing bidirectional signal transmission between the first and second signal terminals; A gate driving module, used for controlling the conduction state of the NMOS transmission tube according to the lower voltage of the power supply voltage input from the first and second signal terminals; First and second NAND gates, wherein the first input end of the first NAND gate is connected to the first signal end, and the second input end thereof is connected to the output end of the second level conversion module; the first input end of the second NAND gate is connected to the second signal end, and the second input end thereof is connected to the output end of the first level conversion module; the output ends of the first and second NAND gates are connected to the input ends of the first and second level conversion modules respectively; The first and second level conversion modules, whose output ends are respectively connected to the input ends of the first and second feedback control monostable modules, are used to convert the input signal level into the voltage of the corresponding power domain; The first and second feedback control monostable modules, whose output ends are respectively connected to the input ends of the first and second pull-up output modules, are used to trigger a positive pulse at the rising edge of the input signal to drive the output; The first and second pull-up output modules have output terminals connected to the first and second signal terminals respectively, and are used to quickly pull up the output level when receiving a positive pulse, and disconnect from the power supply to maintain a high impedance state when the power supply is cut off.

[0006] Furthermore, the bidirectional level converter proposed in the present invention, the gate driving module includes: The first and second NMOS transistors have drains connected to the first power supply voltage and the second power supply voltage, respectively, and gates connected to the second power supply voltage and the first power supply voltage, respectively, through a first resistor and a second resistor; The sources of the first and second NMOS transistors are commonly connected to the gate of the NMOS transmission transistor for outputting a lower voltage between the first power supply voltage and the second power supply voltage.

[0007] Furthermore, the feedback control monostable module of the bidirectional level converter proposed in the present invention comprises: first to ninth PMOS tubes and third to tenth NMOS tubes, and a delay resistor; wherein The gates of the first PMOS tube and the third NMOS tube are respectively connected to the signal input terminal of the feedback control monostable module, and the drains of the ninth PMOS tube and the tenth NMOS tube are respectively connected to the signal output terminal of the feedback control monostable module; The sources of the first to third PMOS tubes and the fifth to ninth PMOS tubes are respectively connected to the power input terminal; The drain of the first PMOS tube, the drain of the third NMOS tube, the gate of the second PMOS tube, the gate of the fourth NMOS tube, the gate of the eighth PMOS tube, and the gate of the eighth NMOS tube are connected; The sources of the third to seventh NMOS tubes and the sources of the ninth to tenth NMOS tubes are connected and then grounded; The drain of the second PMOS tube is connected to the drain of the fourth NMOS tube, the gate of the fifth PMOS tube, and the gate of the sixth NMOS tube respectively; The enable signal EN is input to the gate of the third PMOS tube and the gate of the fifth NMOS tube respectively; the drain of the third PMOS tube is connected to the drain of the fifth NMOS tube and the gate of the fourth PMOS tube; The source of the fourth PMOS tube is respectively connected to the drain of the fifth PMOS tube and one end of the delay resistor, the drain of the fourth PMOS tube is respectively connected to the other end of the delay resistor, the drain of the sixth NMOS tube, the gate of the sixth PMOS tube, and the gate of the seventh NMOS tube are connected; The drain of the sixth PMOS tube is respectively connected to the drain of the seventh NMOS tube, the gate of the seventh PMOS tube, and the gate of the ninth NMOS tube; The drain of the seventh PMOS tube is respectively connected to the drain of the eighth PMOS tube, the drain of the eighth NMOS tube, the gate of the ninth PMOS tube, and the gate of the tenth NMOS tube; the source of the eighth NMOS tube is connected to the drain of the ninth NMOS tube.

[0008] Furthermore, the pull-up output module of the bidirectional level converter proposed in the present invention includes: tenth to eighteenth PMOS tubes, eleventh to twelfth NMOS tubes, and a fourth resistor; Among them, the tenth to fourteenth PMOS tubes form a substrate voltage control network, the gate and drain of the tenth PMOS tube are connected to the substrate potential, and the source is connected to the power supply; the gate of the eleventh PMOS tube is connected to the gate of the seventeenth PMOS tube, the source is connected to the power supply, and the drain is connected to the substrate potential; the gate of the twelfth PMOS tube is connected to the power supply, the source is connected to the substrate potential, and the drain is connected to the gate of the seventeenth PMOS tube; the gate of the thirteenth PMOS tube is connected to the gate of the seventeenth PMOS tube, the source is connected to the power supply, and the drain is connected to the source of the fourteenth PMOS tube; the gate of the fourteenth PMOS tube is connected to the output of the monostable module, and the drain is connected to the gate of the fifteenth PMOS tube; the fifteenth PMOS tube serves as a large-size pull-up drive tube, and its gate is connected to the output signal of the feedback control monostable module, the source is connected to the power supply, and the drain is directly connected to the output end; The sixteenth to eighteenth PMOS tubes form a power-off protection network, wherein the gate of the sixteenth PMOS tube is connected to the power supply, the source is connected to the gate of the fifteenth PMOS tube, and the drain is connected to the output terminal; the gate of the seventeenth PMOS tube is connected to the source of the eighteenth PMOS tube, the source is connected to the power supply, and the drain is connected to the output terminal through the fourth resistor; the gate of the eighteenth PMOS tube is connected to the power supply, the source is connected to the gate of the seventeenth PMOS tube, and the drain is connected to the output terminal; The eleventh and twelfth NMOS tubes form a normal conduction control, wherein the gate of the eleventh NMOS tube is connected to the power supply, the source is grounded, and the drain is connected to the gate of the seventeenth PMOS tube; the gate of the twelfth NMOS tube is connected to the output of the monostable module, the source is grounded, and the drain is connected to the gate of the fifteenth PMOS tube; One end of the fourth resistor is connected to the drain of the seventeenth PMOS tube, and the other end is connected to the output end.

[0009] Furthermore, in the bidirectional level converter proposed in the present invention, when the power supply voltage at any signal end is powered off, the gate drive module outputs zero voltage to turn off the NMOS transmission tube, and at the same time the pull-up output module is completely disconnected from the power supply, so that the input and output ports are in a high-impedance state.

[0010] Furthermore, in the bidirectional level converter proposed in the present invention, the first level conversion module and the second level conversion module adopt conventional level conversion circuits to convert the level of the input signal into the voltage of the corresponding power domain.

[0011] Furthermore, in the bidirectional level converter provided in the present invention, the NMOS transmission tube is a large-size NMOS tube to enhance the driving capability when it is turned on.

[0012] Furthermore, in the bidirectional level converter proposed by the present invention, the resistance value of the delay resistor is set to make the pulse width of the feedback control monostable module meet the stable switching requirement of the output level.

[0013] Furthermore, in the bidirectional level converter proposed in the present invention, the first signal end and the second signal end are respectively connected to the second feedback-controlled monostable module and the first feedback-controlled monostable module. When the first signal end or the second signal end outputs a high level, the signal is returned to the second and first feedback-controlled monostable circuits respectively to turn off the forward pulse.

[0014] Furthermore, in the bidirectional level converter proposed in the present invention, the pull-up output module disconnects the signal terminal from the power supply by controlling the substrate voltage when the power supply is turned off. Compared with the prior art, the present invention adopts the above technical solution and has the following technical effects: By adopting the bidirectional level converter proposed in the present invention, the low level can be directly transmitted bidirectionally through the NMOS transmission tube; a high level is input on one side and a high level is driven to be output on the other side, and at the same time, the pull-up output module on the input side is controlled not to be turned on, so no direction control signal is required, and bidirectional level conversion can be automatically realized; at the same time, since the NMOS transmission tube is an open-drain output, a "line and" function can be realized in combination with a pull-up resistor.

[0015] On the other hand, the present invention adopts a large-size NMOS transmission tube and a large-size PMOS tube in the pull-up output module, which has a strong driving capability. When the power is off, the pull-up output module is turned off, the NMOS transmission tube is not turned on, and the port remains in a high-impedance state when the power is off, which is suitable for open-drain and push-pull applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is the overall circuit diagram of the bidirectional level converter of the present invention; in the figure: A1, AB1, AB2, B1, BA1, BA2 are the input and output signals of each module, the level conversion module adopts a conventional level conversion circuit, and the MOS tube adopts a large-size NMOS tube.

[0017] Figure 2 yes Figure 1 Timing waveform of the signal in .

[0018] Figure 3 : is a gate drive circuit diagram; in the figure: NM1, NM2 are the first and second NMOS tubes, respectively, and R1, R2 are the first and second resistors, respectively.

[0019] Figure 4 It is a feedback control monostable circuit diagram; in the figure: PM1~PM9 are the first to ninth PMOS tubes, NM3~NM10 are the third to tenth NMOS tubes, and R3 is a delay resistor.

[0020] Figure 5 This is a pull-up output circuit diagram, in which: PM10~PM18 are the tenth to eighteenth PMOS tubes respectively, and the substrates of all PMOS tubes in the figure are connected to internal signals; NM11 and NM12 are the eleventh and twelfth NMOS tubes respectively, and the substrates of all NMOS tubes are grounded; R4 is the fourth resistor. DETAILED DESCRIPTION

[0021] The technical solution of the present invention is further described in detail below in conjunction with the accompanying drawings: It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as generally understood by those skilled in the art in the art to which the present invention belongs. It should also be understood that terms such as those defined in common dictionaries should be understood to have meanings consistent with the meanings in the context of the prior art, and will not be interpreted with idealized or overly formal meanings unless defined as herein.

[0022] like Figure 1As shown, it is a circuit diagram of a bidirectional level converter suitable for open-drain and push-pull applications proposed by the present invention, which includes: two signal terminals A and B, an NMOS transmission tube, a gate drive module, a first to second NAND gate, a first to second level conversion module, a first to second feedback control monostable module, and a first to second pull-up output module. The circuit and signal of bidirectional transmission are similar, taking the input of terminal A and the output of terminal B as an example. When the power supply VCCA of terminal A and the power supply VCCB of terminal B are powered on, the gate drive module outputs the lower voltage of VCCA and VCCB to the gate of the NMOS transmission tube, so that the NMOS transmission tube is turned on and can transmit a low level. In the initial state, the input of terminal A is low level, and the output of terminal B is low level. At this time, the output signal A1 of the first NAND gate NAND1, the output signal AB1 of the first level conversion module, the output signal B1 of the second NAND gate NAND2, and the output signal BA1 of the second level conversion module are high level, and the output signal AB2 of the first feedback control monostable circuit and the output signal BA2 of the second feedback control monostable circuit are low level.

[0023] When the input of the A terminal switches from low level to high level, the output signal A1 of the first NAND gate NAND1 switches from high level to low level, and the signal AB1 output by the first level conversion module switches from high level to low level in the VCCB voltage domain, starts the first feedback control monostable circuit, outputs a positive pulse, turns on the pull-up PMOS tube in the first pull-up output module, quickly pulls up and outputs a high level signal to the B terminal, and the B terminal returns the signal to the first feedback control monostable circuit after outputting a high level, turning off the positive pulse. The AB1 signal is opposite to the output signal of the B terminal, and the output signal B1 of the second NAND gate NAND2 remains at a high level, and then the output signal BA1 of the second level conversion module and the output signal BA2 of the second feedback control monostable remain at a low level, and the second pull-up output module remains closed. When one of the power supply voltages in VCCA or VCCB is 0, that is, it is in a power-off state, the gate drive module outputs 0, the NMOS transmission tube is turned off, and the pull-up output module remains turned off, and the input and output ports are in a high impedance state.

[0024] Figure 2 is a signal timing waveform diagram of the bidirectional level converter of the present invention, such as Figure 2 Combination Figure 1 As shown, the level conversion process between the input signal A and the output signal B and the coordinated relationship between the control signals are specifically shown. Among them: 1. Initial state (t0-t1): The input of A terminal is low level (VCCA voltage domain), and the output of B terminal is low level (VCCB voltage domain); The first NAND gate outputs a signal A1 at a high level, and the signal AB1 output by the first level conversion module is at a high level in the VCCB voltage domain; The feedback control monostable module is not triggered, the pull-up output module is turned off, and the B terminal maintains a low level through the NMOS transmission tube.

[0025] 2. Rising edge trigger at the A terminal (t1 - t2): The input at the A terminal switches from low level to high level (in the VCCA voltage domain), causing the A1 signal to jump from high level to low level; After passing through the first level conversion module, the AB1 signal switches from high level in the VCCB voltage domain to low level, triggering the first feedback control monostable module to generate a positive pulse; The positive pulse drives the large-sized PMOS transistor PM15 in the pull-up output module to conduct, quickly pulling up the output at the B terminal to high level in the VCCB voltage domain.

[0026] 3. Steady state maintenance (t2 - t3): After the B terminal outputs a high level, the feedback signal turns off the positive pulse of the first feedback control monostable module; The AB1 signal is inverted with respect to the output signal at the B terminal, the output signal B1 of the second NAND gate remains high level, the signals BA1 output by the second level conversion module and the output signal BA2 of the second feedback control monostable module maintain low level, and the pull-up output module at the A terminal remains turned off.

[0027] When either the VCCA or VCCB power supply is cut off, the gate drive module outputs zero voltage and the NMOS transmission tube is turned off; The pull-up output module is completely disconnected from the power supply through substrate voltage control, and the input and output ports present a high impedance state.

[0028] Figure 3 It is the structural diagram of the gate drive circuit, specifically including the first to second NMOS transistors NM1, NM2, the first to second resistors R1, R2, and the output terminal OUT. The drains of the first to second NMOS transistors NM1, NM2 are respectively connected to the first power supply voltage VCCA and the second power supply voltage VCCB; one ends of the first to second resistors R1, R2 are respectively connected to the gates of NM1 and NM2, and the other ends are respectively connected to the second power supply voltage VCCB and the first power supply voltage VCCA; the source electrodes of the output terminal OUT, NM1, and NM2 are commonly connected to the gate of the NMOS transmission tube.

[0029] Its working principle is as follows: When VCCA < VCCB, the gate voltage VCCA of NM1 is lower than the gate voltage VCCB of NM2, NM1 conducts, NM2 is cut off, and the output OUT is at the VCCA voltage; the resistors R1, R2 are used to limit the gate current and protect the NMOS transistors from damage caused by voltage mutations.

[0030] When VCCB < VCCA, NM2 conducts, NM1 cuts off, and the output OUT is at the VCCB voltage.

[0031] Figure 4 It is a feedback control monostable circuit, and its circuit components include the following: the first to ninth PMOS transistors PM1 - PM9: constituting the core switches and level controls for monostable trigger logic; the third to tenth NMOS transistors NM3 - NM10: collaborating with the PMOS transistors to complete signal path switching and delay control; the delay resistor R3: introducing signal delay to control the monostable pulse width; the enable signal EN: used to globally enable or disable the monostable circuit function; the input signal IN: the original signal triggering the monostable pulse; the output signal OUT: the generated positive pulse with a fixed width.

[0032] The feedback control monostable circuit can be divided into the following parts in terms of its composition: 1. The input - to - output path part, including PM1, NM3, PM8, NM8, PM9, NM10; 2. The monostable trigger part (including the delay part), including PM2, NM4, PM3, PM5, R3, NM6, PM6, NM7, PM7, NM9; 3. The feedback control part, including PM3, NM5, PM4.

[0033] Among them: the gates of PM1 and NM3 are respectively connected to the signal input terminal of the feedback control monostable module, and the drains of PM9 and NM10 are respectively connected to the signal output terminal of the feedback control monostable module; the sources of PM1 - PM3, PM5 - PM9 are respectively connected to the power input terminal VCC; the drain of PM1, the drain of NM3, the gates of PM2, NM4, the gates of PM8, NM8 are connected to each other. The sources of NM3 - NM7, the sources of NM9 - NM10 are connected to each other and then grounded. The drain of PM2 is respectively connected to the drains of NM4, the gate of PM5, the gate of NM6.

[0034] The enable signal EN is respectively input to the gates of PM3 and NM5; the drain of PM2 is connected to the drain of NM5 and the gate of PM4; the source of PM4 is respectively connected to the drain of PM5 and one end of the delay resistor R3, the drain of PM4 is respectively connected to the other end of the delay resistor R3, the drain of NM6, the gate of PM6, the gate of NM7 are connected; The drain of PM6 is respectively connected to the drains of NM7, the gate of PM7, the gate of NM9; The drain of PM7 is respectively connected to the drains of PM8, NM8, the gate of PM9, the gate of NM10; the source of NM8 is connected to the drain of NM9.

[0035] Furthermore, the feedback control monostable circuit works as follows: 1. The enable signal is invalid (EN = low level), that is, the circuit has a normal monostable trigger function.

[0036] The monostable is triggered by the input signal: when the input signal switches from high level to low level, NM8 changes from off to on, and the delay resistor R3 makes NM9 temporarily remain on, and the output end is briefly pulled high; when the delay ends, NM9 is turned off, and the output end returns to a low level, thereby outputting a monostable pulse.

[0037] 2. The enable signal is valid (EN = high level), that is, the monostable pulse width of the circuit is controlled by EN.

[0038] When the circuit is in a monostable state triggered by an input signal, if EN changes from a low level to a high level, PM4 is turned on, short-circuiting resistor R3, immediately ending the delay and forcing the output end to return to a low level.

[0039] refer to Figure 5 The figure shows the structure of the pull-up output circuit, which includes the following components: The tenth to eighteenth PMOS tubes PM10-PM18 are used for output level driving, substrate voltage control and power-off protection; The eleventh to twelfth NMOS transistors NM11-NM12 cooperate with the PMOS to control the connection state between the output terminal and the power supply; The fourth resistor R4 provides a weak pull-up path to limit the static current.

[0040] Among them, PM10-PM14 form a substrate voltage control network, in which the gate and drain of PM10 are connected to the substrate potential, and the source is connected to the power supply VCC. The gate of PM11 is connected to the gate of PM17, the source is connected to the power supply VCC, and the drain is connected to the substrate potential. The gate of PM12 is connected to the power supply VCC, the source is connected to the substrate potential, and the drain is connected to the gate of PM17. The gate of PM13 is connected to the gate of PM17, the source is connected to the power supply VCC, and the drain is connected to the source of PM14. The gate of PM14 is connected to the output of the monostable module, and the drain is connected to the gate of PM15. PM15 is a large-size pull-up driver tube, with its gate connected to the output signal (positive pulse) of the feedback control monostable module, the source is connected to VCC, and the drain is directly connected to the output terminal.

[0041] PM16-PM18 form a power-off protection network, in which the gate of PM16 is connected to the power supply VCC, the source is connected to the gate of PM15, and the drain is connected to the output terminal. The gate of PM17 is connected to the source of PM18, the source is connected to VCC, and the drain is connected to the output terminal through resistor R4. The gate of PM18 is connected to the power supply VCC, the source is connected to the gate of PM17, and the drain is connected to the output terminal.

[0042] NM11-NM12 form a normally on control, where the gate of NM11 is connected to VCC, the source is grounded, and the drain is connected to the gate of PM17. The gate of NM12 is connected to the output of the monostable module, the source is grounded, and the drain is connected to the gate of PM15.

[0043] One end of the fourth resistor R4 is connected to the drain of PM17, and the other end is connected to the output terminal, providing a weak pull-up path under normal conditions.

[0044] The working principle of the pull-up output circuit is as follows: when the power supply is powered on normally, NM11 is turned on, PM17 is turned on, and the output port is connected to the power supply through the large resistor R4; PM10 and PM11 are turned on, and the substrates of all PMOS tubes are connected to the power supply. When the pulse generated by the input monostable circuit is input, PM15 is briefly turned on. PM15 is a large-size MOS tube with strong output capability and can quickly pull up the output. When the power supply voltage is 0, PM18 is turned on, and the higher voltage of the output port is transmitted to the gate of PM17, and transmitted to the substrate of the PMOS tube through the turned-on PM12, so that PM17 is turned off; at the same time, PM16 is turned on, and the higher voltage of the output end is transmitted to the gate of PM15, and PM15 is turned off, and the output port is disconnected from the power supply.

[0045] From a functional perspective, the pull-up output circuit includes a normal power-on state and a power-off protection state, as follows: 1. Normal power-on state (VCCA and VCCB are powered normally) Substrate voltage control: PM10-PM11 is turned on, fixing the substrate potential to VCC to eliminate the influence of body effect.

[0046] Output drive: When the monostable module outputs a positive pulse, the PM15 gate voltage is pulled low, PM15 is turned on, and the large size design enables it to quickly pull the output end to a high level.

[0047] Weak pull-up maintenance: PM17 is turned on when NM11 is turned on (gate connected to high level), and the output end is weakly pulled up to VCC through R4 to maintain a low-power static level.

[0048] 2. Power failure protection (VCCB power failure or VCCA power failure) PMOS shutdown: When VCC is powered off, the gate voltage of PM18 disappears, PM18 turns on, and transmits the residual voltage at the output end to the gate of PM17, forcing PM17 to turn off and cut off the pull-up path of R4. PM16 turns on due to the reduction of the output voltage, and pulls the gate voltage of PM15 up to the output voltage, ensuring that PM15 is completely turned off.

[0049] Substrate isolation: PM10-PM11 is turned off due to VCCB power failure, PM12-PM14 is turned on, and the substrate potential is equal to the output potential to prevent leakage current.

[0050] High impedance state realization: The output end is disconnected from both VCC and ground, and only the residual potential is maintained by parasitic capacitance to achieve a high impedance state.

[0051] The above descriptions are only some embodiments of the present invention. It should be pointed out that, for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A bidirectional level converter suitable for open-drain and push-pull applications, characterized in that include: An NMOS transmission tube, whose drain and source are respectively connected to the first and second signal terminals, and whose gate is connected to the gate driving module, is used to realize bidirectional signal transmission between the first and second signal terminals; A gate driving module, used for controlling the conduction state of the NMOS transmission tube according to the lower voltage of the power supply voltage input from the first and second signal terminals; First and second NAND gates, wherein a first input end of the first NAND gate is connected to the first signal end, and a second input end of the first NAND gate is connected to the output end of the second level conversion module; A first input end of the second NAND gate is connected to the second signal end, and a second input end thereof is connected to the output end of the first level conversion module; The output ends of the first and second NAND gates are connected to the input ends of the first and second level conversion modules respectively; The first and second level conversion modules, whose output ends are respectively connected to the input ends of the first and second feedback control monostable modules, are used to convert the input signal level into the voltage of the corresponding power domain; The first and second feedback control monostable modules, whose output ends are respectively connected to the input ends of the first and second pull-up output modules, are used to trigger a positive pulse at the rising edge of the input signal to drive the output; The first and second pull-up output modules have output ends connected to the second and first signal ends respectively, and are used to quickly pull up the output level when receiving a positive pulse, and disconnect from the power supply to maintain a high impedance state when the power supply is cut off.

2. The bidirectional level converter according to claim 1, wherein: The gate driving module comprises: A first NMOS transistor and a second NMOS transistor, whose drains are connected to a first power supply voltage and a second power supply voltage respectively, and whose gates are connected to the second power supply voltage and the first power supply voltage respectively through a first resistor and a second resistor; The sources of the first NMOS transistor and the second NMOS transistor are commonly connected to the gate of the NMOS transmission transistor for outputting a lower voltage between the first power supply voltage and the second power supply voltage.

3. The bidirectional level converter according to claim 1, wherein: The feedback control monostable module includes: first to ninth PMOS tubes and third to tenth NMOS tubes, and a delay resistor; wherein The gates of the first PMOS tube and the third NMOS tube are respectively connected to the signal input terminal of the feedback control monostable module, and the drains of the ninth PMOS tube and the tenth NMOS tube are respectively connected to the signal output terminal of the feedback control monostable module; The sources of the first to third PMOS tubes and the fifth to ninth PMOS tubes are respectively connected to the power input terminal; The drain of the first PMOS tube, the drain of the third NMOS tube, the gate of the second PMOS tube, the gate of the fourth NMOS tube, the gate of the eighth PMOS tube, and the gate of the eighth NMOS tube are connected; The sources of the third to seventh NMOS tubes and the sources of the ninth to tenth NMOS tubes are connected and then grounded; The drain of the second PMOS tube is connected to the drain of the fourth NMOS tube, the gate of the fifth PMOS tube, and the gate of the sixth NMOS tube respectively; The enable signal is input to the gate of the third PMOS tube and the gate of the fifth NMOS tube respectively; the drain of the third PMOS tube is connected to the drain of the fifth NMOS tube and the gate of the fourth PMOS tube; The source of the fourth PMOS tube is respectively connected to the drain of the fifth PMOS tube and one end of the delay resistor, the drain of the fourth PMOS tube is respectively connected to the other end of the delay resistor, the drain of the sixth NMOS tube, the gate of the sixth PMOS tube, and the gate of the seventh NMOS tube are connected; The drain of the sixth PMOS tube is respectively connected to the drain of the seventh NMOS tube, the gate of the seventh PMOS tube, and the gate of the ninth NMOS tube; The drain of the seventh PMOS tube is respectively connected to the drain of the eighth PMOS tube, the drain of the eighth NMOS tube, the gate of the ninth PMOS tube, and the gate of the tenth NMOS tube; the source of the eighth NMOS tube is connected to the drain of the ninth NMOS tube.

4. The bidirectional level converter according to claim 1, wherein: The pull-up output module includes: tenth to eighteenth PMOS tubes, eleventh to twelfth NMOS tubes, and a fourth resistor; Among them, the tenth to fourteenth PMOS tubes form a substrate voltage control network, the gate and drain of the tenth PMOS tube are connected to the substrate potential, and the source is connected to the power supply; the gate of the eleventh PMOS tube is connected to the gate of the seventeenth PMOS tube, the source is connected to the power supply, and the drain is connected to the substrate potential; the gate of the twelfth PMOS tube is connected to the power supply VCC, the source is connected to the substrate potential, and the drain is connected to the gate of the seventeenth PMOS tube; the gate of the thirteenth PMOS tube is connected to the gate of the seventeenth PMOS tube, the source is connected to the power supply, and the drain is connected to the source of the fourteenth PMOS tube; the gate of the fourteenth PMOS tube is connected to the output of the monostable module, and the drain is connected to the gate of the fifteenth PMOS tube; the fifteenth PMOS tube serves as a large-size pull-up drive tube, and its gate is connected to the output signal of the feedback control monostable module, the source is connected to the power supply, and the drain is directly connected to the output end; The sixteenth to eighteenth PMOS tubes form a power-off protection network, wherein the gate of the sixteenth PMOS tube is connected to the power supply, the source is connected to the gate of the fifteenth PMOS tube, and the drain is connected to the output terminal; the gate of the seventeenth PMOS tube is connected to the source of the eighteenth PMOS tube, the source is connected to the power supply, and the drain is connected to the output terminal through the fourth resistor; the gate of the eighteenth PMOS tube is connected to the power supply, the source is connected to the gate of the seventeenth PMOS tube, and the drain is connected to the output terminal; The eleventh and twelfth NMOS tubes form a normal conduction control, wherein the gate of the eleventh NMOS tube is connected to the power supply, the source is grounded, and the drain is connected to the gate of the seventeenth PMOS tube; the gate of the twelfth NMOS tube is connected to the output of the monostable module, the source is grounded, and the drain is connected to the gate of the fifteenth PMOS tube; One end of the fourth resistor is connected to the drain of the seventeenth PMOS tube, and the other end is connected to the output end.

5. The bidirectional level converter according to claim 1, wherein: When the power supply voltage of any signal terminal is powered off, the gate drive module outputs zero voltage to turn off the NMOS transmission tube, and the pull-up output module is completely disconnected from the power supply, so that the input and output ports are in a high impedance state.

6. The bidirectional level converter according to claim 1, wherein: The first level conversion module and the second level conversion module adopt a standard level conversion circuit, which is used to convert the level of the input signal into the voltage of the corresponding power domain.

7. The bidirectional level converter according to claim 1, wherein: The NMOS transmission tube is a large-size NMOS tube, which is used to enhance the driving capability when it is turned on.

8. The bidirectional level converter according to claim 3, characterized in that: The resistance value of the delay resistor is set to make the pulse width of the feedback control monostable module meet the stable switching requirement of the output level.

9. The bidirectional level converter according to claim 1, wherein: The first signal end and the second signal end are connected to the second feedback control monostable module and the first feedback control monostable module respectively. When the first signal end or the second signal end outputs a high level, the signal is returned to the second and first feedback control monostable circuits respectively to turn off the forward pulse.

10. The bidirectional level converter according to claim 4, characterized in that: The pull-up output module disconnects the signal terminal from the power supply through substrate voltage control when the power supply is turned off.

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