A bidirectional level translator for open-drain and push-pull applications

Abstract

The present invention discloses a bidirectional level converter suitable for open-drain and push-pull applications, belonging to the field of integrated circuit technology. The converter includes an NMOS transmission tube, a gate drive module, first and second NAND gates, first and second level conversion modules, first and second feedback-controlled monostable modules, and first and second pull-up output modules. The gate drive module automatically selects the lower of the first and second power supply voltages to control the conduction of the NMOS transmission tube, thereby achieving bidirectional signal transmission. The feedback-controlled monostable module triggers a positive pulse on the rising edge of the input signal, driving a large-sized PMOS tube to quickly raise the output level, thus solving the problem of slow switching speed caused by the large pull-up resistor value in traditional open-drain output. The pull-up output module disconnects the output terminal from the power supply through substrate voltage control when the power is off, maintaining a high-impedance state. The present invention does not require a direction control signal, is compatible with open-drain and push-pull modes, and has high drive capability and power-off protection characteristics.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and more particularly to a method for transmitting signals between two devices with different power supply voltages, and more particularly to a bidirectional level converter suitable for open-drain and push-pull applications. Background Art

[0002] In integrated circuits, an NMOS transistor is often used to achieve bidirectional signal transmission. However, since NMOS transistors cannot directly output a high level, a pull-up resistor must be connected to the power supply to achieve bidirectional level conversion. This output drive method is called open-drain output. Open-drain output can implement "wired-AND" operation, that is, multiple signal output ports are directly connected together. The signal is high only when all output ports are high; if any output port is low, the signal is low. This characteristic makes open-drain output widely applicable to bus interfaces such as I2C and SMBus.

[0003] To reduce static power consumption, the pull-up resistors for open-drain outputs are typically large. This results in slow pull-up switching speeds and makes it difficult to drive large loads. Push-pull outputs, on the other hand, alternate between NMOS and PMOS transistors, with one transistor turned off and the other turned on. This allows for direct output of both high and low levels, and offers strong drive capability, especially when outputting high levels. However, if multiple push-pull outputs are directly connected, the circuit is susceptible to short circuits. For example, if one push-pull output is high and another is low, a large current can flow directly from the high-level power supply to the low-level ground, damaging the circuit. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a bidirectional level converter suitable for open-drain and push-pull applications, which can automatically perform bidirectional level conversion without a direction control signal, realize "wired-AND" function, strong driving capability, and keep the port in a high-impedance state when power is off.

[0005] The present invention adopts the following technical solutions to solve the above technical problems:

[0006] The present invention provides a bidirectional level converter suitable for open-drain and push-pull applications, comprising:

[0007] An NMOS transmission tube, whose drain and source are connected to the first and second signal terminals respectively, and whose gate is connected to the gate driving module, is used to realize bidirectional signal transmission between the first and second signal terminals;

[0008] A gate driving module, configured to control the conduction state of the NMOS transmission tube according to the lower voltage of the power supply voltage inputted from the first and second signal terminals;

[0009] First and second NAND gates, wherein the first input end of the first NAND gate is connected to the first signal end, and the second input end thereof is connected to the output end of the second level conversion module; the first input end of the second NAND gate is connected to the second signal end, and the second input end thereof is connected to the output end of the first level conversion module; the output ends of the first and second NAND gates are connected to the input ends of the first and second level conversion modules, respectively;

[0010] The first and second level conversion modules, whose output terminals are connected to the input terminals of the first and second feedback-controlled monostable modules respectively, are used to convert the input signal level into the voltage of the corresponding power domain;

[0011] The first and second feedback-controlled monostable modules have output terminals connected to the input terminals of the first and second pull-up output modules, respectively, for triggering a positive pulse on the rising edge of the input signal to drive the output;

[0012] The first and second pull-up output modules have output terminals connected to the first and second signal terminals respectively, and are used to quickly pull up the output level when receiving a positive pulse, and disconnect from the power supply to maintain a high impedance state when the power is cut off.

[0013] Furthermore, the bidirectional level converter proposed in the present invention includes a gate drive module comprising:

[0014] The drains of the first and second NMOS transistors are connected to the first power supply voltage and the second power supply voltage respectively, and the gates are connected to the second power supply voltage and the first power supply voltage respectively through the first resistor and the second resistor;

[0015] The sources of the first and second NMOS transistors are commonly connected to the gate of the NMOS transmission transistor for outputting a lower voltage between the first power supply voltage and the second power supply voltage.

[0016] Furthermore, the feedback control monostable module of the bidirectional level converter proposed in the present invention includes: first to ninth PMOS transistors and third to tenth NMOS transistors, and a delay resistor; wherein

[0017] The gates of the first PMOS transistor and the third NMOS transistor are respectively connected to the signal input terminal of the feedback control monostable module, and the drains of the ninth PMOS transistor and the tenth NMOS transistor are respectively connected to the signal output terminal of the feedback control monostable module;

[0018] The sources of the first to third PMOS transistors and the fifth to ninth PMOS transistors are respectively connected to the power input terminal;

[0019] The drain of the first PMOS transistor, the drain of the third NMOS transistor, the gate of the second PMOS transistor, the gate of the fourth NMOS transistor, the gate of the eighth PMOS transistor, and the gate of the eighth NMOS transistor are connected;

[0020] The sources of the third to seventh NMOS transistors and the sources of the ninth to tenth NMOS transistors are connected and then grounded;

[0021] The drain of the second PMOS transistor is connected to the drain of the fourth NMOS transistor, the gate of the fifth PMOS transistor, and the gate of the sixth NMOS transistor respectively;

[0022] The enable signal EN is input to the gate of the third PMOS transistor and the gate of the fifth NMOS transistor respectively; the drain of the third PMOS transistor is connected to the drain of the fifth NMOS transistor and the gate of the fourth PMOS transistor;

[0023] The source of the fourth PMOS transistor is connected to the drain of the fifth PMOS transistor and one end of the delay resistor respectively; the drain of the fourth PMOS transistor is connected to the other end of the delay resistor respectively; the drain of the sixth NMOS transistor, the gate of the sixth PMOS transistor, and the gate of the seventh NMOS transistor are connected;

[0024] The drain of the sixth PMOS transistor is connected to the drain of the seventh NMOS transistor, the gate of the seventh PMOS transistor, and the gate of the ninth NMOS transistor respectively;

[0025] The drain of the seventh PMOS tube is respectively connected to the drain of the eighth PMOS tube, the drain of the eighth NMOS tube, the gate of the ninth PMOS tube, and the gate of the tenth NMOS tube; the source of the eighth NMOS tube is connected to the drain of the ninth NMOS tube.

[0026] Furthermore, the bidirectional level converter proposed in the present invention has a pull-up output module comprising: tenth to eighteenth PMOS transistors, eleventh to twelfth NMOS transistors, and a fourth resistor;

[0027] Among them, the tenth to fourteenth PMOS transistors form a substrate voltage control network, the gate and drain of the tenth PMOS transistor are connected to the substrate potential, and the source is connected to the power supply; the gate of the eleventh PMOS transistor is connected to the gate of the seventeenth PMOS transistor, the source is connected to the power supply, and the drain is connected to the substrate potential; the gate of the twelfth PMOS transistor is connected to the power supply, the source is connected to the substrate potential, and the drain is connected to the gate of the seventeenth PMOS transistor; the gate of the thirteenth PMOS transistor is connected to the gate of the seventeenth PMOS transistor, the source is connected to the power supply, and the drain is connected to the source of the fourteenth PMOS transistor; the gate of the fourteenth PMOS transistor is connected to the output of the monostable module, and the drain is connected to the gate of the fifteenth PMOS transistor; the fifteenth PMOS transistor serves as a large-size pull-up driver transistor, its gate is connected to the output signal of the feedback control monostable module, its source is connected to the power supply, and its drain is directly connected to the output end;

[0028] The sixteenth to eighteenth PMOS transistors form a power-off protection network, wherein the gate of the sixteenth PMOS transistor is connected to the power supply, the source is connected to the gate of the fifteenth PMOS transistor, and the drain is connected to the output terminal; the gate of the seventeenth PMOS transistor is connected to the source of the eighteenth PMOS transistor, the source is connected to the power supply, and the drain is connected to the output terminal through a fourth resistor; the gate of the eighteenth PMOS transistor is connected to the power supply, the source is connected to the gate of the seventeenth PMOS transistor, and the drain is connected to the output terminal;

[0029] The eleventh and twelfth NMOS transistors form a normally-on control, wherein the gate of the eleventh NMOS transistor is connected to the power supply, the source is grounded, and the drain is connected to the gate of the seventeenth PMOS transistor; the gate of the twelfth NMOS transistor is connected to the output of the monostable module, the source is grounded, and the drain is connected to the gate of the fifteenth PMOS transistor;

[0030] One end of the fourth resistor is connected to the drain of the seventeenth PMOS transistor, and the other end is connected to the output end.

[0031] Furthermore, in the bidirectional level converter proposed in the present invention, when the power supply voltage at any signal end is cut off, the gate drive module outputs zero voltage to turn off the NMOS transmission tube, and at the same time the pull-up output module is completely disconnected from the power supply, so that the input and output ports are in a high-impedance state.

[0032] Furthermore, in the bidirectional level converter proposed in the present invention, the first level conversion module and the second level conversion module adopt conventional level conversion circuits for converting the level of the input signal into the voltage of the corresponding power domain.

[0033] Furthermore, in the bidirectional level converter proposed in the present invention, the NMOS transmission tube is a large-sized NMOS tube to enhance the driving capability when it is turned on.

[0034] Furthermore, in the bidirectional level converter proposed by the present invention, the resistance value of the delay resistor is set so that the pulse width of the feedback control monostable module meets the stable switching requirement of the output level.

[0035] Furthermore, in the bidirectional level converter proposed in the present invention, the first signal end and the second signal end are respectively connected to the second feedback-controlled monostable module and the first feedback-controlled monostable module. When the first signal end or the second signal end outputs a high level, the signal is returned to the second and first feedback-controlled monostable circuits, respectively, to turn off the forward pulse.

[0036] Furthermore, the bidirectional level converter proposed in the present invention has a pull-up output module that disconnects the signal terminal from the power supply by controlling the substrate voltage when the power is off. Compared with the prior art, the present invention adopts the above technical solution and has the following technical effects:

[0037] With the bidirectional level converter proposed in the present invention, a low level can be directly transmitted bidirectionally through the NMOS transmission tube; a high level is input on one side, and the other side drives the output high level, while the pull-up output module on the input side is controlled not to be turned on. Therefore, no direction control signal is required, and bidirectional level conversion can be automatically achieved. At the same time, because the NMOS transmission tube has an open-drain output, it can realize a "wired-AND" function in combination with a pull-up resistor.

[0038] On the other hand, the present invention uses a large-size NMOS transmission tube and a large-size PMOS tube in the pull-up output module, which has a strong driving capability. When the power is off, the pull-up output module is turned off and the NMOS transmission tube is not turned on. When the power is off, the port remains in a high-impedance state, which is suitable for open-drain and push-pull applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 This is the overall circuit diagram of the bidirectional level converter of the present invention; in the figure: A1, AB1, AB2, B1, BA1, BA2 are the input and output signals of each module, the level conversion module adopts a conventional level conversion circuit, and the MOS tube adopts a large-size NMOS tube.

[0040] Figure 2 yes Figure 1 The timing waveform of the signal in .

[0041] Figure 3 This is a gate drive circuit diagram; in the figure: NM1 and NM2 are the first and second NMOS tubes respectively, and R1 and R2 are the first and second resistors respectively.

[0042] Figure 4 This is a feedback control monostable circuit diagram; in the figure: PM1~PM9 are the first to ninth PMOS transistors, NM3~NM10 are the third to tenth NMOS transistors, and R3 is a delay resistor.

[0043] Figure 5 This is a pull-up output circuit diagram. In the figure: PM10~PM18 are the tenth to eighteenth PMOS tubes respectively, and the substrates of all PMOS tubes in the figure are connected to internal signals; NM11 and NM12 are the eleventh and twelfth NMOS tubes respectively, and the substrates of all NMOS tubes are grounded; R4 is the fourth resistor. DETAILED DESCRIPTION

[0044] The technical solution of the present invention is further described in detail below with reference to the accompanying drawings:

[0045] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art in the art to which this invention belongs. It should also be understood that terms such as those defined in common dictionaries should be understood to have meanings consistent with their meanings in the context of the prior art and, unless defined as such, will not be interpreted in an idealized or overly formal sense.

[0046] like Figure 1 The figure shows a circuit diagram of a bidirectional level converter suitable for open-drain and push-pull applications, according to the present invention. The circuit includes two signal terminals, A and B, an NMOS transistor, a gate driver module, a first-to-second NAND gate, a first-to-second level conversion module, a first-to-second feedback-controlled monostable module, and a first-to-second pull-up output module. The circuit and signal for bidirectional transmission are similar, taking the example of input at terminal A and output at terminal B. When the power supply VCCA at terminal A and the power supply VCCB at terminal B are powered on, the gate driver module outputs the lower voltage of VCCA or VCCB to the gate of the NMOS transistor, turning it on and enabling it to transmit a low level. Initially, the input to terminal A is low, and the output from terminal B is low. At this point, the output signal A1 of the first NAND gate NAND1, the output signal AB1 of the first level conversion module, the output signal B1 of the second NAND gate NAND2, and the output signal BA1 of the second level conversion module are all high, while the output signals AB2 of the first feedback-controlled monostable circuit and BA2 of the second feedback-controlled monostable circuit are all low.

[0047] When the input at terminal A switches from low to high, the output signal A1 of the first NAND gate NAND1 switches from high to low. The signal AB1 output by the first level shifter module switches from high to low in the VCCB voltage domain, activating the first feedback-controlled monostable circuit and outputting a positive pulse. This turns on the pull-up PMOS transistor in the first pull-up output module, rapidly pulling up and outputting a high-level signal to terminal B. After terminal B outputs a high level, the signal returns to the first feedback-controlled monostable circuit, shutting off the positive pulse. The AB1 signal is the opposite of the output signal at terminal B. The output signal B1 of the second NAND gate NAND2 remains high, and the output signal BA1 of the second level shifter module and the output signal BA2 of the second feedback-controlled monostable remain low, keeping the second pull-up output module disabled. When either the VCCA or VCCB supply voltage is 0, i.e., in a power-off state, the gate driver module outputs 0, the NMOS transistor turns off, and the pull-up output module remains off, with the input and output ports in a high-impedance state.

[0048] Figure 2 The signal timing waveform diagram of the bidirectional level converter of the present invention is as follows: Figure 2 Combine Figure 1As shown in the figure, the level conversion process between the input signal A and the output signal B and the coordinated relationship between the control signals are specifically shown.

[0049] 1. Initial state (t0-t1):

[0050] The input of terminal A is low level (VCCA voltage domain), and the output of terminal B is low level (VCCB voltage domain);

[0051] The output signal A1 of the first NAND gate is high level, and the signal AB1 output by the first level conversion module is high level in the VCCB voltage domain;

[0052] The feedback control monostable module is not triggered, the pull-up output module is turned off, and the B terminal maintains a low level through the NMOS transmission tube.

[0053] 2. A-terminal input rising edge trigger (t1-t2):

[0054] The input of terminal A switches from low level to high level (VCCA voltage domain), causing the A1 signal to jump from high level to low level;

[0055] After passing through the first level conversion module, the AB1 signal switches from a high level in the VCCB voltage domain to a low level, triggering the first feedback control monostable module to generate a positive pulse;

[0056] The positive pulse drives the large-size PMOS tube PM15 in the pull-up output module to turn on, quickly pulling the B-end output up to the high level of the VCCB voltage domain.

[0057] 3. Steady state maintenance (t2-t3):

[0058] After the B terminal outputs a high level, the feedback signal turns off the forward pulse of the first feedback control monostable module;

[0059] The AB1 signal is opposite to the output signal of the B terminal, the second NAND gate output signal B1 remains high, the signal BA1 output by the second level conversion module and the output signal BA2 of the second feedback control monostable module remain low, and the pull-up output module of the A terminal remains closed.

[0060] When either VCCA or VCCB is powered off, the gate drive module outputs zero voltage and the NMOS transmission tube is turned off;

[0061] The pull-up output module is completely disconnected from the power supply through substrate voltage control, and the input and output ports are in a high-impedance state.

[0062] Figure 3It is the structural diagram of a gate drive circuit, specifically including the first to second NMOS transistors NM1 and NM2, the first to second resistors R1 and R2, and the output terminal OUT. The drains of the first to second NMOS transistors NM1 and NM2 are respectively connected to the first power supply voltage VCCA and the second power supply voltage VCCB; one ends of the first to second resistors R1 and R2 are respectively connected to the gates of NM1 and NM2, and the other ends are respectively connected to the second power supply voltage VCCB and the first power supply voltage VCCA; the source electrodes of the output terminal OUT, NM1, and NM2 are commonly connected to the gate of the NMOS transmission transistor.

[0063] Its working principle is as follows:

[0064] When VCCA < VCCB, the gate voltage VCCA of NM1 is lower than the gate voltage VCCB of NM2, NM1 conducts, NM2 cuts off, and the output OUT is the VCCA voltage; the resistors R1 and R2 are used to limit the gate current and protect the NMOS transistors from damage caused by voltage mutations.

[0065] When VCCB < VCCA, NM2 conducts, NM1 cuts off, and the output OUT is the VCCB voltage.

[0066] Figure 4 It is a feedback control monostable circuit, and the circuit components include the following: the first to ninth PMOS transistors PM1 - PM9: constituting the core switches and level controls of the monostable trigger logic; the third to tenth NMOS transistors NM3 - NM10: cooperating with the PMOS transistors to complete signal path switching and delay control; the delay resistor R3: introducing signal delay to control the width of the monostable pulse; the enable signal EN: used to globally enable or disable the monostable circuit function; the input signal IN: the original signal triggering the monostable pulse; the output signal OUT: the generated positive pulse with a fixed width.

[0067] The feedback control monostable circuit can be divided into the following parts from its composition:

[0068] 1. The input - to - output path part, including PM1, NM3, PM8, NM8, PM9, NM10;

[0069] 2. The monostable trigger part (including the delay part), including PM2, NM4, PM3, PM5, R3, NM6, PM6, NM7, PM7, NM9;

[0070] 3. The feedback control part, including PM3, NM5, PM4.

[0071] The gates of PM1 and NM3 are connected to the signal input of the feedback control monostable module, respectively. The drains of PM9 and NM10 are connected to the signal output of the feedback control monostable module, respectively. The sources of PM1-PM3 and PM5-PM9 are connected to the power supply input VCC, respectively. The drain of PM1, the drain of NM3, the gate of PM2, the gate of NM4, and the gates of PM8 and NM8 are connected. The sources of NM3-NM7 and the sources of NM9-NM10 are connected and then grounded. The drain of PM2 is connected to the drain of NM4, the gate of PM5, and the gate of NM6, respectively.

[0072] The enable signal EN is input to the gate of PM3 and the gate of NM5 respectively; the drain of PM2 is connected to the drain of NM5 and the gate of PM4; the source of PM4 is connected to the drain of PM5 and one end of the delay resistor R3 respectively, and the drain of PM4 is connected to the other end of the delay resistor R3, the drain of NM6, the gate of PM6, and the gate of NM7 respectively;

[0073] The drain of PM6 is connected to the drain of NM7, the gate of PM7, and the gate of NM9 respectively;

[0074] The drain of PM7 is connected to the drain of PM8, the drain of NM8, the gate of PM9, and the gate of NM10 respectively; the source of NM8 is connected to the drain of NM9.

[0075] Furthermore, the feedback control monostable circuit works as follows:

[0076] 1. The enable signal is invalid (EN = low level), that is, the circuit has a normal monostable trigger function.

[0077] The monostable is triggered by the input signal: when the input signal switches from high level to low level, NM8 changes from off to on, and the delay resistor R3 makes NM9 temporarily remain on, and the output end is briefly pulled high; when the delay ends, NM9 turns off and the output end returns to low level, thereby outputting a monostable pulse.

[0078] 2. The enable signal is valid (EN = high level), that is, the monostable pulse width of the circuit is controlled by EN.

[0079] When the circuit is in a monostable state triggered by the input signal, if EN changes from low level to high level, PM4 is turned on, shorting resistor R3, immediately ending the delay and forcing the output end to return to a low level.

[0080] refer to Figure 5 The figure below shows the structure of the pull-up output circuit, which includes the following components:

[0081] The tenth to eighteenth PMOS transistors PM10-PM18 are used for output level driving, substrate voltage control and power-off protection;

[0082] The eleventh to twelfth NMOS transistors NM11-NM12 cooperate with the PMOS to control the connection status between the output terminal and the power supply;

[0083] The fourth resistor R4 provides a weak pull-up path to limit the static current.

[0084] PM10-PM14 form a substrate voltage control network, with PM10's gate and drain connected to the substrate potential and its source connected to power supply VCC. PM11's gate is connected to PM17's gate, its source to power supply VCC, and its drain to the substrate potential. PM12's gate is connected to power supply VCC, its source to the substrate potential, and its drain to PM17's gate. PM13's gate is connected to PM17's gate, its source to power supply VCC, and its drain to PM14's source. PM14's gate is connected to the output of the monostable module, and its drain is connected to the gate of PM15. PM15 serves as a large pull-up driver transistor, its gate connected to the feedback-controlled monostable module's output signal (positive pulse), its source connected to VCC, and its drain connected directly to the output.

[0085] PM16 and PM18 form a power-off protection network, with PM16's gate connected to the power supply VCC, its source connected to the gate of PM15, and its drain connected to the output. PM17's gate is connected to PM18's source, which is also connected to VCC. Its drain is connected to the output through resistor R4. PM18's gate is connected to the power supply VCC, its source is connected to the gate of PM17, and its drain is connected to the output.

[0086] NM11 and NM12 form a normally on control, where NM11's gate is connected to VCC, its source is grounded, and its drain is connected to the gate of PM17. NM12's gate is connected to the output of the monostable module, its source is grounded, and its drain is connected to the gate of PM15.

[0087] One end of the fourth resistor R4 is connected to the drain of PM17 , and the other end is connected to the output terminal, providing a weak pull-up path under normal conditions.

[0088] The pull-up output circuit operates as follows: When the power supply is powered on normally, NM11 and PM17 are turned on, connecting the output port to the power supply through large resistor R4. PM10 and PM11 are also turned on, connecting the substrates of all PMOS transistors to the power supply. When a pulse is applied to the input monostable circuit, PM15 briefly turns on. PM15 is a large MOS transistor with strong output capability, allowing it to quickly pull the output high. When the power supply voltage reaches zero, PM18 turns on, transmitting the higher voltage at the output port to the gate of PM17. This voltage is then transferred to the substrate of the PMOS transistor through the conducting PM12, causing PM17 to turn off. Simultaneously, PM16 turns on, transmitting the higher voltage at the output port to the gate of PM15, causing PM15 to turn off, disconnecting the output port from the power supply.

[0089] Functionally, the pull-up output circuit includes a normal power-on state and a power-off protection state, as follows:

[0090] 1. Normal power-on state (VCCA and VCCB are powered normally)

[0091] Substrate voltage control: PM10-PM11 is turned on, fixing the substrate potential to VCC to eliminate the influence of body effect.

[0092] Output drive: When the monostable module outputs a positive pulse, the PM15 gate voltage is pulled low, PM15 is turned on, and the large size design enables it to quickly pull the output end to a high level.

[0093] Weak pull-up maintenance: PM17 is turned on when NM11 is turned on (gate connected to high level), and the output end is weakly pulled up to VCC through R4 to maintain a low-power static level.

[0094] 2. Power failure protection (VCCB power failure or VCCA power failure)

[0095] PMOS shutdown: When VCC is powered off, the gate voltage of PM18 disappears, PM18 turns on, and transmits the residual voltage at the output to the gate of PM17, forcing PM17 to turn off and severing the pull-up path of R4. PM16 turns on due to the reduced output voltage, pulling the gate voltage of PM15 up to the output voltage, ensuring that PM15 is completely shut down.

[0096] Substrate isolation: PM10-PM11 is turned off due to VCCB power failure, PM12-PM14 is turned on, and the substrate potential is equal to the output terminal potential to prevent leakage current.

[0097] High-impedance state: The output terminal is disconnected from both VCC and ground, and only the residual potential is maintained by parasitic capacitance to achieve high-impedance state.

[0098] The above descriptions are only partial embodiments of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principles of the present invention. These improvements and modifications should also be regarded as within the scope of protection of the present invention.

Claims

1. A bidirectional level converter suitable for open-drain and push-pull applications, characterized in that include: An NMOS transmission tube, whose drain and source are connected to the first and second signal terminals respectively, and whose gate is connected to the gate driving module, is used to realize bidirectional signal transmission between the first and second signal terminals; A gate driving module, configured to control the conduction state of the NMOS transmission tube according to the lower voltage of the power supply voltage inputted from the first and second signal terminals; First and second NAND gates, wherein the first input terminal of the first NAND gate is connected to the first signal terminal, and the second input terminal thereof is connected to the output terminal of the second level conversion module; A first input terminal of the second NAND gate is connected to the second signal terminal, and a second input terminal thereof is connected to the output terminal of the first level conversion module; The output ends of the first and second NAND gates are connected to the input ends of the first and second level conversion modules respectively; The first and second level conversion modules, whose output terminals are connected to the input terminals of the first and second feedback-controlled monostable modules respectively, are used to convert the input signal level into the voltage of the corresponding power domain; The first and second feedback-controlled monostable modules have output terminals connected to the input terminals of the first and second pull-up output modules, respectively, for triggering a positive pulse on the rising edge of the input signal to drive the output; The first and second pull-up output modules have output terminals connected to the second and first signal terminals, respectively, for quickly pulling up the output level when receiving a positive pulse, and disconnecting from the power supply to maintain a high impedance state when the power supply is turned off; The feedback control monostable module includes: first to ninth PMOS transistors and third to tenth NMOS transistors, and a delay resistor; in The gates of the first PMOS transistor and the third NMOS transistor are respectively connected to the signal input terminal of the feedback control monostable module, and the drains of the ninth PMOS transistor and the tenth NMOS transistor are respectively connected to the signal output terminal of the feedback control monostable module; The sources of the first to third PMOS transistors and the fifth to ninth PMOS transistors are respectively connected to the power input terminal; The drain of the first PMOS transistor, the drain of the third NMOS transistor, the gate of the second PMOS transistor, the gate of the fourth NMOS transistor, the gate of the eighth PMOS transistor, and the gate of the eighth NMOS transistor are connected; The sources of the third to seventh NMOS transistors and the sources of the ninth to tenth NMOS transistors are connected and then grounded; The drain of the second PMOS transistor is connected to the drain of the fourth NMOS transistor, the gate of the fifth PMOS transistor, and the gate of the sixth NMOS transistor respectively; The enable signal is input to the gate of the third PMOS tube and the gate of the fifth NMOS tube respectively; the drain of the third PMOS tube is connected to the drain of the fifth NMOS tube and the gate of the fourth PMOS tube; The source of the fourth PMOS transistor is connected to the drain of the fifth PMOS transistor and one end of the delay resistor respectively; the drain of the fourth PMOS transistor is connected to the other end of the delay resistor respectively; the drain of the sixth NMOS transistor, the gate of the sixth PMOS transistor, and the gate of the seventh NMOS transistor are connected; The drain of the sixth PMOS transistor is connected to the drain of the seventh NMOS transistor, the gate of the seventh PMOS transistor, and the gate of the ninth NMOS transistor respectively; The drain of the seventh PMOS tube is respectively connected to the drain of the eighth PMOS tube, the drain of the eighth NMOS tube, the gate of the ninth PMOS tube, and the gate of the tenth NMOS tube; the source of the eighth NMOS tube is connected to the drain of the ninth NMOS tube.

2. The bidirectional level converter according to claim 1, wherein: The gate driving module includes: A first NMOS transistor and a second NMOS transistor, whose drains are connected to a first power supply voltage and a second power supply voltage respectively, and whose gates are connected to the second power supply voltage and the first power supply voltage respectively through a first resistor and a second resistor; The sources of the first NMOS transistor and the second NMOS transistor are commonly connected to the gate of the NMOS transmission transistor, and are used to output a lower voltage of the first power supply voltage and the second power supply voltage.

3. The bidirectional level converter according to claim 1, wherein: The pull-up output module includes: tenth to eighteenth PMOS transistors, eleventh to twelfth NMOS transistors, and a fourth resistor; Among them, the tenth to fourteenth PMOS transistors form a substrate voltage control network, the gate and drain of the tenth PMOS transistor are connected to the substrate potential, and the source is connected to the power supply; the gate of the eleventh PMOS transistor is connected to the gate of the seventeenth PMOS transistor, the source is connected to the power supply, and the drain is connected to the substrate potential; the gate of the twelfth PMOS transistor is connected to the power supply VCC, the source is connected to the substrate potential, and the drain is connected to the gate of the seventeenth PMOS transistor; the gate of the thirteenth PMOS transistor is connected to the gate of the seventeenth PMOS transistor, the source is connected to the power supply, and the drain is connected to the source of the fourteenth PMOS transistor; the gate of the fourteenth PMOS transistor is connected to the output of the monostable module, and the drain is connected to the gate of the fifteenth PMOS transistor; the fifteenth PMOS transistor serves as a large-size pull-up driver transistor, its gate is connected to the output signal of the feedback control monostable module, its source is connected to the power supply, and its drain is directly connected to the output end; The sixteenth to eighteenth PMOS transistors form a power-off protection network, wherein the gate of the sixteenth PMOS transistor is connected to the power supply, the source is connected to the gate of the fifteenth PMOS transistor, and the drain is connected to the output terminal; the gate of the seventeenth PMOS transistor is connected to the source of the eighteenth PMOS transistor, the source is connected to the power supply, and the drain is connected to the output terminal through a fourth resistor; the gate of the eighteenth PMOS transistor is connected to the power supply, the source is connected to the gate of the seventeenth PMOS transistor, and the drain is connected to the output terminal; The eleventh and twelfth NMOS transistors form a normally-on control, wherein the gate of the eleventh NMOS transistor is connected to the power supply, the source is grounded, and the drain is connected to the gate of the seventeenth PMOS transistor; the gate of the twelfth NMOS transistor is connected to the output of the monostable module, the source is grounded, and the drain is connected to the gate of the fifteenth PMOS transistor; One end of the fourth resistor is connected to the drain of the seventeenth PMOS transistor, and the other end is connected to the output end.

4. The bidirectional level converter according to claim 1, wherein: When the power supply voltage of any signal terminal is cut off, the gate drive module outputs zero voltage to turn off the NMOS transmission tube, and at the same time the pull-up output module is completely disconnected from the power supply, so that the input and output ports are in a high impedance state.

5. The bidirectional level converter according to claim 1, wherein: The first level conversion module and the second level conversion module adopt a standard level conversion circuit, which is used to convert the level of the input signal into the voltage of the corresponding power domain.

6. The bidirectional level converter according to claim 1, wherein: The NMOS transmission tube is a large-sized NMOS tube, which is used to enhance the driving capability when it is turned on.

7. The bidirectional level converter according to claim 1, wherein: The resistance value of the delay resistor is set so that the pulse width of the feedback control monostable module meets the stable switching requirement of the output level.

8. The bidirectional level converter according to claim 1, wherein: The first signal end and the second signal end are connected to the second feedback control monostable module and the first feedback control monostable module respectively. When the first signal end or the second signal end outputs a high level, the signal is returned to the second and first feedback control monostable circuits respectively to turn off the forward pulse.

9. The bidirectional level converter according to claim 3, wherein: The pull-up output module disconnects the signal terminal from the power supply through substrate voltage control when the power supply is cut off.

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