Voltage-controlled ring oscillator, electronic device and integrated circuit

Abstract

The embodiment of the invention relates to a voltage-controlled ring oscillator, an electronic device and an integrated circuit, and is characterized in that a bias current in each delay unit in an oscillation loop is controlled by using a bias control signal, and a frequency channel of an oscillation clock signal is determined through a component of a first current corresponding to frequency information; fine adjustment of the frequency in the frequency channel can be realized by adjusting the component of the second current corresponding to the voltage. Therefore, the voltage-controlled ring oscillator provided by the embodiment of the invention can output the oscillation clock signal with the corresponding frequency in an extremely wide frequency range according to control.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit design, and in particular to a voltage-controlled ring oscillator, electronic equipment and an integrated circuit. Background Art

[0002] A voltage-controlled oscillator (VCO) is an oscillator that adjusts the output frequency by controlling the input voltage. It is widely used in communication systems, clock generation, power electronics and other fields. The typical structure of a voltage-controlled oscillator includes a voltage-controlled ring oscillator. The existing voltage-controlled ring oscillator uses the transmission delay of multiple delay units in the ring structure to generate an oscillation signal. Designers expect that the voltage-controlled ring oscillator can have a wider frequency adjustable range, that is, it can be adjusted within a larger frequency range. Summary of the invention

[0003] In view of this, embodiments of the present invention provide a voltage-controlled ring oscillator, an electronic device, and an integrated circuit, which can output an oscillation clock signal of a corresponding frequency within an extremely wide frequency range according to control.

[0004] In a first aspect, a voltage-controlled ring oscillator is provided, wherein the voltage-controlled ring oscillator comprises:

[0005] A frequency-to-current converter, configured to convert a reference clock signal into a first current, wherein a strength value of the first current is associated with a frequency of the reference clock signal;

[0006] A voltage-to-current converter, used for converting the regulated voltage into a second current;

[0007] a bias control circuit that receives the first current and the second current as input and generates at least one bias control current; and

[0008] An oscillation loop includes a plurality of delay units, wherein each of the delay units is driven by a bias current proportional to the bias control current, delays and inverts an input signal and outputs it to generate an oscillation clock signal, and the delay time of the delay unit is associated with the bias current, thereby controlling the frequency of the oscillation clock signal.

[0009] In some embodiments, the transistors in the bias control circuit and the transistors in the delay unit form a current mirror, so that the bias current is proportional to the bias control current.

[0010] In some embodiments, the frequency of the oscillating clock signal is proportional to the reference clock signal, and is proportional or inversely proportional to the regulation voltage.

[0011] In some embodiments, the oscillation loop further includes at least one AC-coupled clock buffer, which is connected to an output end of at least one delay unit of the oscillation loop and is used to output an oscillation clock signal.

[0012] In some embodiments, the bias control current is a sum or a difference between the first current and the second current.

[0013] In some embodiments, the delay unit comprises:

[0014] A first CMOS inverter connected between an input terminal and an output terminal of the delay unit;

[0015] A first capacitor is arranged at an output end of the first CMOS inverter; and

[0016] A first bias current source is provided in a charging or discharging current path of the first capacitor, and is used to charge or discharge the first capacitor according to a first bias current according to a state of the first CMOS inverter, wherein the first bias current is proportional to the bias control current.

[0017] In some embodiments, the first bias current source is disposed between the CMOS inverter and a ground terminal to control a discharge time of the first capacitor.

[0018] In some embodiments, the delay unit further comprises:

[0019] The second bias current source is arranged between the first CMOS inverter and the power supply terminal, and is used for charging the first capacitor according to a second bias current, and the second bias current is proportional to the bias control current.

[0020] In some embodiments, the bias control circuit is used to combine the first current and the second current into a bias control current, and output a first bias control voltage corresponding to the bias control current;

[0021] The first bias current source is used to generate the first bias current according to the first bias control voltage.

[0022] In some embodiments, the bias control circuit includes a control voltage output circuit for converting the bias control current into a first bias control voltage, and the first bias current source and the voltage output circuit form a current mirror.

[0023] In some embodiments, the bias control circuit is used to combine the first current and the second current into a bias control current, and output a first bias control voltage and a second bias control voltage corresponding to the bias control current;

[0024] The first bias current source is used to generate the first bias current according to a first bias control voltage;

[0025] The second bias current source is used to generate the second bias current according to a second bias control voltage.

[0026] In some embodiments, the bias control circuit comprises:

[0027] a current combining circuit, configured to combine the first current and the second current into a bias control current;

[0028] A first current mirror, inputting the bias control current and outputting a first mirror current and a first control voltage;

[0029] The control voltage output circuit inputs the first mirror current and outputs the second control voltage.

[0030] In some embodiments, the delay unit comprises:

[0031] A differential inverter connected between an input terminal and an output terminal of the delay unit;

[0032] The third bias current source is arranged in the current path of the differential inverter.

[0033] In some embodiments, the delay unit further comprises:

[0034] a fourth bias current source, arranged between the differential inverter and the power supply terminal;

[0035] Wherein, the third bias current source is arranged between the differential inverter and the ground terminal.

[0036] In some embodiments, the bias control circuit is used to combine the first current and the second current into a bias control current, and output a third bias control voltage and a fourth bias control voltage corresponding to the bias control current;

[0037] The third bias current source is controlled by a third bias current corresponding to the third bias control voltage output;

[0038] The fourth bias current source is controlled by the fourth bias current corresponding to the fourth bias control voltage output.

[0039] In some embodiments, the frequency-to-current converter is configured to control charging and discharging of the capacitor according to a reference clock signal, and filter the discharge current, thereby converting a reference clock signal with a predetermined frequency into the first current.

[0040] In some embodiments, the frequency current converter comprises:

[0041] A second CMOS inverter, connected between the power supply terminal and the intermediate terminal, with an input terminal receiving the reference clock signal;

[0042] A second capacitor is arranged at an output end of the second CMOS inverter;

[0043] A third capacitor connected between the middle terminal and the ground terminal;

[0044] The second current mirror is connected between the middle terminal and the ground terminal, and is used for receiving the current input by the second CMOS inverter and generating the first current at the output terminal.

[0045] In some embodiments, the voltage-to-current converter comprises:

[0046] a first amplifier, a first input terminal inputting the regulated voltage, and a second input terminal connected to an output terminal;

[0047] A conversion resistor has one end connected to the reference voltage as an output end, and the other end connected to the output end of the first amplifier, thereby generating a second current corresponding to the adjustment voltage.

[0048] In some embodiments, the bias control circuit comprises:

[0049] a third current mirror, an input end of which is connected to the output end of the second current mirror, an output end of which is connected to a current merging end, and the current merging end is connected to the output end of the voltage-to-current converter;

[0050] a second amplifier, having a first input terminal inputting the reference voltage, a second input terminal connected to the current combining terminal, and an output terminal connected to the output terminal of the bias control circuit; and

[0051] The first current-controlled voltage source is connected to the current path of the bias control current, receives the combined bias control current, and generates a corresponding first bias control voltage.

[0052] In some embodiments, the bias control circuit comprises:

[0053] a fourth current mirror, whose input end is connected to the current merging end, whose output end outputs the bias control current, and wherein the current merging end is connected to the output end of the second current mirror and the output end of the voltage-to-current converter;

[0054] A third amplifier, having a first input terminal inputting the reference voltage, a second input terminal connected to the current combining terminal, and an output terminal connected to the control terminal of the current mirror;

[0055] The second current-controlled voltage source is connected to the output end of the fourth current mirror, receives the bias control current, and generates a corresponding first bias control voltage.

[0056] According to a second aspect, an electronic device is provided, comprising the voltage-controlled ring oscillator according to the first aspect.

[0057] According to a third aspect, an integrated circuit is provided, comprising the voltage-controlled ring oscillator as described in the first aspect.

[0058] The embodiment of the present invention uses a bias control signal to control the bias current in each delay unit, rather than adjusting the power supply, changing the delay level, or adjusting the number of resistors or capacitors in the delay unit as in the prior art. The voltage-controlled ring oscillator of the embodiment of the present invention converts the frequency information of the reference clock signal into a first current through a frequency-current converter, converts the adjustment voltage into a second current through a voltage-current converter, combines the first current and the second current to obtain a bias control current, and controls the bias current in each delay unit based on the bias control current, thereby achieving control of the delay time, and further achieving frequency control of the output oscillation clock signal. The frequency channel of the oscillation clock signal is determined by the component of the first current corresponding to the frequency information, and the fine adjustment of the frequency within the frequency channel can be achieved by adjusting the component of the second current corresponding to the voltage. Therefore, the voltage-controlled ring oscillator of the embodiment of the present invention can output an oscillation clock signal of a corresponding frequency according to control within an extremely wide frequency range. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0060] Figure 1 is a block diagram of a voltage-controlled ring oscillator according to an embodiment of the present invention;

[0061] Figure 2 is a circuit diagram of an oscillation loop according to a first embodiment of the present invention;

[0062] Figure 3 is a circuit diagram of the voltage-controlled ring oscillator except the oscillation loop of an embodiment of the present invention;

[0063] Figure 4 is a schematic diagram of the relationship between the output frequency and the regulation voltage of an embodiment of the present invention;

[0064] Figure 5 is a circuit diagram of a bias control circuit according to an embodiment of the present invention;

[0065] Figure 6 is a circuit diagram of an oscillation loop according to a second embodiment of the present invention;

[0066] Figure 7 is a circuit diagram of another bias control circuit according to an embodiment of the present invention;

[0067] Figure 8 is a circuit diagram of an oscillation loop according to a third embodiment of the present invention;

[0068] Fig. 9 Schematic diagram of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0069] The present invention is described below based on embodiments, but the present invention is not limited to these embodiments. In the detailed description of the present invention below, some specific details are described in detail. It is possible for a person skilled in the art to fully understand the present invention without the description of these details. In order to avoid confusing the essence of the present invention, known methods, processes, flows, components and circuits are not described in detail.

[0070] In addition, persons of ordinary skill in the art will appreciate that the drawings provided herein are for illustration purposes and are not necessarily drawn to scale.

[0071] At the same time, it should be understood that in the following description, "circuit" refers to a conductive loop composed of at least one element or subcircuit through electrical connection or electromagnetic connection. When an element or circuit is said to be "connected to" another element or an element / circuit is said to be "connected between" two nodes, it can be directly coupled or connected to another element or there can be an intermediate element, and the connection between the elements can be physical, logical, or a combination thereof. On the contrary, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.

[0072] In the description of the present invention, it should be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0073] Figure 1 is a block diagram of a voltage-controlled ring oscillator according to an embodiment of the present invention. Figure 1As shown, the voltage-controlled ring oscillator 1 of this embodiment includes a frequency-current converter 11, a voltage-current converter 12, a bias control circuit 13 and an oscillation loop 14. The frequency-current converter 11 is used to convert the reference clock signal Fref into a first current I1. The strength value of the first current I1 is associated with the frequency of the reference clock signal Fref. The voltage-current converter 12 is used to convert the adjustment voltage Vtune into a second current I2. The strength value of the second current I2 is proportional to the adjustment voltage and may contain information about the adjustment voltage. The second current I2 is used to be combined with the first current I1 by summing or subtracting to form a bias control current Ivco. The bias control circuit 13 inputs the first current I1 and the second current I2 to generate at least one bias control current Ivco. The oscillation loop 14 is used to generate an oscillation clock signal fosc based on the control of the bias control current Ivco or a corresponding parameter (such as the bias control voltage Vbn or the bias control voltages Vbn and Vbp in the figure). The frequency of the oscillation clock signal fosc is determined by the frequency of the reference clock signal Fref and the adjustment voltage. The oscillation loop 14 includes an oscillation loop and an AC-coupled clock buffer. The oscillation loop includes a plurality of delay units, wherein each delay unit is driven according to a bias current proportional to the bias control current Ivco, and performs an inversion operation as part of a phase-locked loop to control the delay time of the delay unit, so that the delay time of the delay unit is associated with the bias current, thereby controlling the output frequency. In some cases, the voltage-controlled ring oscillator 1 of this embodiment may also include a separately arranged power supply circuit 15. The power supply circuit 15 outputs a power supply voltage Vreg to the frequency-current converter 11, the voltage-current converter 12, and the power supply terminal Vreg of the oscillation loop 14.

[0074] The embodiment of the present invention utilizes a bias control current to control the bias current in each delay unit, and the bias current is determined by the sum or difference of a first current associated with a reference clock signal and a second current associated with an adjustment voltage. Thus, a simple circuit structure can be used to accurately adjust the output of a voltage-controlled ring oscillator within a wider frequency range.

[0075] Figure 2 1 is a circuit diagram of an implementation method of an oscillation loop according to an embodiment of the present invention. Figure 2As shown, the oscillation loop 2 of this embodiment includes an oscillation loop 21 and at least one AC-coupled clock buffer (AC-coupled clockbuffer) 22 (3 in the figure). The oscillation loop 21 includes a plurality of delay units S1-S3, wherein each delay unit S1-S3 is driven by a bias current Ib proportional to the bias control current Ivco, and the delay time of the delay unit S1-S3 is controlled to be associated with the bias current Ib, thereby controlling the frequency of the output oscillation clock signal. The AC-coupled clock buffer 22 is connected to the output end of at least one delay unit of the oscillation loop, and is used to output the oscillation clock signal.

[0076] Figure 2 FIG. 4 shows an exemplary circuit structure of the delay unit S1 of this embodiment. Figure 2 As shown, the delay unit S1 includes a CMOS inverter CMOS1 (also referred to as a first CMOS inverter), a capacitor C1 (also referred to as a first capacitor) and a bias current source NMOS2. Among them, the CMOS inverter CMOS1 includes transistors PMOS1 and NMOS1. The transistor PMOS1 is a P-type MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), and the transistor NMOS1 is an N-type MOSFET. The gates of the transistors PMOS1 and NMOS1 are connected to each other to form the input terminal in of the CMOS inverter CMOS1, and the drains are connected to each other to form the output terminal out of the CMOS inverter CMOS1. The input terminal in of the CMOS inverter CMOS1 serves as the input terminal of the delay unit S1, and the output terminal out of the CMOS inverter CMOS1 can serve as the output terminal of the delay unit S1. That is, the CMOS inverter CMOS1 is connected between the input terminal and the output terminal of the delay unit S1. The capacitor C1 is arranged between the output terminal and the ground terminal of the CMOS inverter. The source of the transistor PMOS1 is connected to the power supply terminal. The source of transistor NMOS1 is connected to bias current source NMOS2. Figure 2In the embodiment, the bias current source NMOS2 adopts an N-type MOSFET, which is presented as a voltage-controlled current source. The gate of the transistor NMOS2 is input with a bias control voltage Vbn, the drain is connected to the CMOS inverter CMOS1, and the source is connected to the ground terminal. The transistor NMOS2 is arranged in the current path from the power supply terminal to the ground terminal of the CMOS inverter. From another perspective, the transistor NMOS2 can also be considered to be arranged in the current path of the discharge current of the capacitor C1. The transistor NMOS2 generates a first bias current Ib according to the bias control voltage Vbn to control the falling slope of the discharge current of the capacitor C1, thereby controlling the voltage of the capacitor C1 to drop to the delay time for the output voltage to be inverted (that is, the output drops from a voltage value identified as 1 or 0 to a voltage value of an inverted voltage identified as 0 or 1). Specifically, if the input signal of the input terminal in of the CMOS inverter CMOS1 is low level, the transistor PMOS1 is turned on, the transistor NMOS1 is turned off, and the current from the power supply terminal charges the capacitor C1 through PMOS1, so that after the delay of the charging time, the output voltage of the capacitor C1 acting on the output terminal out reaches the high level of the delay unit S1. If the input signal of the input terminal in of the CMOS inverter is high level, the transistor PMOS1 is turned off, the transistor NMOS1 is turned on, and the capacitor C1 is discharged through the transistor NMOS1 and the transistor NMOS2. And because the transistor NMOS2 is controlled by the bias control voltage Vbn, a first bias current Ib is formed. Since the discharge rate of the capacitor C1, that is, the slope of the voltage drop across the capacitor C1 is associated with the bias current Ib, and then, the time for the output voltage of the capacitor C1 acting on the output terminal to drop from a high level to a low level (that is, the delay time of the delay unit) is determined by the first bias current Ib. Therefore, by accurately controlling the first bias current Ib within a wider range, the delay time of the delay unit can be accurately controlled, thereby controlling the output frequency within a wider frequency range.

[0077] exist Figure 2 In the oscillation loop shown, the structures of the three delay units S1-S3 are the same. At the same time, the input and output of each delay unit S1-S3 are connected in series to form a ring connection, so that a phase-locked loop is formed based on the output of each delay unit to output a clock signal. The clock signal needs to be removed from the DC bias (DC Blocking) and isolated and matched level by the AC coupling clock buffer 22 to output an oscillation clock signal fosc corresponding to the bias current Ib. Figure 2As shown, the AC-coupled clock buffer 22 includes buffers buf1 and buf2, a filter capacitor Cf, resistors R1 and R2, enable switches M1 and M2, and a transistor pair M3 connected in series with the resistors R1 and R2. Among them, the filter capacitor Cf is connected to the input terminal ckin of the AC-coupled clock buffer 22 to receive a signal outputted by any one of the delay units S1-S3. The buffers buf1 and buf2 and the filter capacitor Cf are connected between the input terminal and the output terminal ckout. The enable switch M2 is connected between the common terminal and the ground terminal of the buffers buf1 and buf2. The transistor pair M3 includes a pair of transistors whose drains and sources are connected to each other, including a P-type MOSFET and an N-type MOSFET, and the drain of one transistor is connected to the source of the other transistor to form a connection terminal of the transistor pair M3. The gates of the two transistors are respectively input with enable signals enb and enbb. The resistor R1 is connected to the first connection terminal of the transistor pair M3, and the resistor R2 is connected to the second connection terminal of the transistor pair M3. The enable switch M1 is connected between the power supply terminal and the connection terminal of the transistor pair M3. The enable switch M1 is controlled by the enable signal enbb, and the enable switch M2 is controlled by the enable signal enb which is inverse to the enable signal enbb. The above circuit structure can realize the output of the oscillation clock signal after removing the DC bias (DCBlocking) and isolating and matching the level of the signal generated by the oscillation loop. It should be understood that the AC coupling clock buffer 22 of this embodiment can also be implemented by using an existing circuit structure with a simpler or more complex structure. In some cases, the AC coupling clock buffer 22 can also be omitted. It should also be understood that the number of delay units in the oscillation loop of this embodiment can be other odd numbers.

[0078] Figure 3 It is a circuit diagram of the voltage-controlled oscillator except the oscillation loop according to an embodiment of the present invention. Figure 3 The circuit shown includes a frequency-current converter 31, a voltage-current converter 32 and a bias control circuit 33. The frequency-current converter 31 converts the input reference clock signal Fref into a first current I1 whose intensity value (average value or effective value) is proportional to the frequency of the reference clock signal Fref. The frequency-current converter 31 includes a CMOS inverter CMOS2 (i.e., a second CMOS inverter), capacitors C2 (i.e., a second capacitor) and C3 (i.e., a third capacitor) and a current mirror Mi2 (i.e., a second current mirror). The CMOS inverter CMOS2 includes transistors PMOS2 and NMOS8 whose drains are connected to each other and whose gates are connected to each other. The transistor PMOS2 is a P-type MOSFET, and the transistor NMOS8 is an N-type MOSFET. The capacitor C2 is connected to the output end of the CMOS inverter CMOS2. The source of the transistor PMOS2 is connected to the power supply terminal Vreg. As shown in FIG. Figure 3As shown, in order to provide necessary protection for the circuit, a transistor PMOS 2 for protection may be provided between the transistor PMOS 2 and the power supply terminal Vreg. pd . Transistor PMOS pd The gate of the current mirror Mi2 is input with a protection control signal Pdn, thereby being controlled to be turned on and off to protect the circuit from overcurrent. The current mirror Mi2 includes two transistors NMOS3 and NMOS4 connected with a common gate. Among them, the gate and drain of the transistor NMOS3 are connected. At the same time, the capacitor C3 is connected between the drain of the transistor NMOS3 and the ground terminal. The capacitor C3 is used to smooth the current flowing into the current mirror Mi2, so that the effective value of its current intensity or the average value over a period of time is proportional to the frequency of the reference clock signal Fref. The current mirror Mi2 generates a first current I1 on the drain side of the transistor NMOS4 in a mirror copy manner according to a ratio of 1:N (N is a predetermined integer). The intensity value of the first current I1 is N times the current on the input side. Therefore, the intensity value of the first current I1 carries the frequency information of the reference clock signal Fref and changes with the frequency of the reference clock signal Fref. During operation, the reference clock signal Fref controls the two transistors of the CMOS inverter CMOS2 to alternately turn on and off once in each cycle according to the corresponding frequency. This causes the capacitor C2 to be charged and discharged once in each cycle. When transistor PMOS2 is turned on, transistor NMOS8 is turned off, and current flows from the power supply terminal Vreg to capacitor C2 to charge capacitor C2. At the same time, capacitor C3 discharges to current mirror Mi2. Current flows from capacitor C3 to current mirror Mi2. Then, transistor PMOS2 is switched off, transistor NMOS8 is switched on, and capacitor C2 discharges to capacitor C3 and the input terminal of current mirror Mi2. Current flows from capacitor C2 to capacitor C3 to charge, and at the same time, flows into current mirror Mi2. Capacitor C3 can keep the current flowing into current mirror Mi2 relatively stable within the period of the reference clock signal. At the same time, by designing the capacitance values ​​of capacitors C2 and C3, the voltage difference between the two in a stable state can change with the frequency of the reference clock signal, so that the first current reflects the frequency of the reference clock signal.

[0079] At the same time, in order to provide necessary protection for the circuit, a transistor NMOS for protection can be set between the gate of the transistor of the current mirror Mi2 and the ground terminal. pd1 . Transistor NMOS pd1 The gate of is controlled by the protection control signal Pd to turn on and off, so as to achieve the purpose of protecting the circuit from overcurrent.

[0080] The voltage-to-current converter 32 includes an amplifier A1 (i.e., a first amplifier) ​​and a conversion resistor R3. The non-inverting input terminal of the amplifier A1 inputs a regulated voltage Vtune, and the inverting input terminal is connected to the output terminal. The conversion resistor R3 is arranged at the output terminal of the amplifier A1. As long as a predetermined reference voltage Vcm is applied to the end of the conversion resistor R3 that is not connected to the amplifier A1, a second current I2 corresponding to the input regulated voltage Vtune can be generated on the resistor R3. According to the setting of the voltage Vcm and Vtune, the second current I2 can flow to the output terminal of the voltage-to-current converter 32 or flow out from the output terminal.

[0081] The bias control circuit 33 inputs the first current I1 and the second current I2 to generate at least one bias control current Ivco. The bias control current Ivco is the sum of the first current I1 and the second current I2. The second current I2 can be a positive current or a negative current according to the settings of the voltage Vcm and Vtune. Figure 3 In the circuit shown, the bias control circuit 33 converts the bias control current Ivco into the first bias control voltage Vbn to control the bias current source in the delay unit S1-S3. The bias control circuit 33 includes a current mirror Mi3 (i.e., the third current mirror), an amplifier A2 (i.e., the second amplifier) ​​and a current control voltage source NMOS7. The current mirror Mi3 includes two transistors PMOS3 and PMOS4 with a common gate. The transistors PMOS3 and PMOS4 are P-type MOSFETs. The drain and gate of the transistor PMOS3 are connected. The sources of the transistors PMOS3 and PMOS4 are connected to the power supply terminal. At the same time, the drain of the transistor PMOS3 is connected to the output terminal of the current mirror Mi2 as the input terminal of the current mirror Mi3, thereby, the output current of the current mirror Mi2, i.e., the first current I1, can be proportionally replicated by the current mirror Mi3.

[0082] The drain of the transistor PMOS4 is connected to the current merging terminal X of this embodiment as the output terminal of the current mirror Mi3. The current merging terminal X is also connected to the output terminal of the voltage-to-current converter 32.

[0083] The current mirror Mi3 copies the first current I1 on one side of the transistor PMOS3 to one end of the transistor PMOS4 for output, and flows to the current merging terminal X. At the same time, the second current generated by the voltage-current converter 32 flows into the current merging terminal X or flows out from the current merging terminal X. As a result, the current in the current path below the current merging terminal X is the sum of the first current I1 and the second current I2. The amplifier A2 is used to keep the voltage of the current merging terminal X at the reference voltage Vcm. The non-inverting input terminal of the amplifier A2 is connected to the current merging terminal X, the reference voltage Vcm is input to the inverting input terminal, and the output terminal is connected to the output terminal of the bias control circuit.

[0084] The current control voltage source NMOS7 adopts an N-type MOSFET. The drain of the transistor NMOS7 is connected to the current merging terminal X, receiving the bias control current Ivco obtained after merging, the source is connected to the ground terminal, the gate is connected to the bias voltage output terminal, and the bias control voltage Vbn proportional to the bias control current Ivco is output.

[0085] In order to prevent the current from flowing in the reverse direction, a transistor NMOS5 with a drain and a gate connected can be set between the output end of the current mirror Mi2 and the input end of the current mirror Mi3. The function of the transistor NMOS5 is equivalent to a diode, which can prevent the current from flowing in the direction opposite to the expected direction. At the same time, a transistor NMOS6 with a drain and a gate connected can be set between the drain of the transistor NMOS7 and the current merging terminal X. The function of the transistor NMOS6 is equivalent to a diode, which can prevent the current from flowing in the direction opposite to the expected direction.

[0086] At the same time, in order to protect the circuit, a transistor NMOS for protection can be set between the output terminal of the bias control voltage Vbn and the ground terminal. pd2 . Transistor NMOS pd2 The gate of is controlled by the protection control signal Pd to turn on and off, so as to achieve the purpose of protecting the circuit from overcurrent.

[0087] Combination Figure 2 and Figure 3 It can be observed that the transistor NMOS7 of the bias control circuit 33 can form a multi-output current mirror with the bias current source NMOS2 in each delay unit S1-S3, thereby replicating the bias control current Ivco into a first bias current Ib proportional thereto, and controlling the delay time of each delay unit respectively. Among them, the amplifier A2 and the transistor NMOS6 together construct a feedback path between the gate and the drain of the transistor NMOS7 as one end of the current mirror.

[0088] According to Figure 2 and Figure 3From the description of the principle of the circuit diagram, it can be seen that the first bias current Ib carries the information of the frequency of the reference clock signal Fref, and the first current I1 as its component is proportional to the frequency value of the reference clock signal. At the same time, the first bias current Ib also carries the information of the adjustment voltage Vtune, and the second current I2 as its component is proportional to the adjustment voltage Vtune. Therefore, the bias current Ib is determined by the frequency of the reference clock signal Fref and the adjustment voltage Vtune. At the same time, the bias current Ib directly affects the delay time of the delay unit S1-S3, and is directly associated with the frequency of the oscillation clock signal output by the oscillation loop. The frequency of the oscillation clock signal changes in direct proportion to the frequency of the reference clock signal Fref and changes in direct proportion to the adjustment voltage Vtune. Therefore, by adjusting the frequency of the input reference clock signal Fref and the adjustment voltage Vtune, the output signal frequency of the voltage-controlled ring oscillator can be adjusted within an extremely wide range. This makes the output bandwidth of the voltage-controlled ring oscillator of this embodiment large.

[0089] Figure 4 Schematic diagram of the relationship between the output frequency and the regulation voltage of an embodiment of the present invention. Figure 4 As shown, the horizontal axis is the adjustment voltage Vtune, and the vertical axis is the frequency fosc of the output oscillation clock signal. The frequencies fref1 to frefN of different reference clock signals constitute a plurality of different frequency channels Channel1 to ChannelN. These frequency channels are Figure 4 It is presented as a straight line with a certain slope. As the adjustment voltage Vtune increases, in each frequency channel (that is, for the same reference clock frequency), the frequency fosc of the oscillation clock signal increases linearly.

[0090] Therefore, the output frequency can be preliminarily determined by the frequency of the reference clock signal, and the frequency can be finely adjusted in the frequency channel by adjusting the voltage Vtune, so that accuracy can be guaranteed while outputting the oscillation clock signal in a wide range.

[0091] The embodiment of the present invention uses a bias control signal to control the bias current in each delay unit, rather than adjusting the power supply, changing the delay level, or adjusting the number of resistors or capacitors in the delay unit as in the prior art. The voltage-controlled ring oscillator of the embodiment of the present invention converts the frequency information of the reference clock signal into a first current through a frequency-current converter, converts the adjustment voltage into a second current through a voltage-current converter, combines the first current and the second current to obtain a bias control current, and controls the bias current in each delay unit based on the bias control current, thereby achieving control of the delay time, and further achieving frequency control of the output oscillation clock signal. The frequency channel of the oscillation clock signal is determined by the component of the first current corresponding to the frequency information, and the fine adjustment of the frequency point can be achieved by adjusting the component of the second current corresponding to the voltage. Therefore, the voltage-controlled ring oscillator of the embodiment of the present invention can output an oscillation clock signal of a corresponding frequency according to control within an extremely wide frequency range.

[0092] In the embodiment of the present invention, different forms of bias control circuits may be used to realize the merging of the first current and the second current. Figure 5 is a circuit diagram of another bias control circuit according to an embodiment of the present invention. Figure 5 As shown, the bias control circuit 51 includes a current mirror Mi4 (i.e., the fourth current mirror), an amplifier A3 (i.e., the third amplifier) ​​and a current-controlled voltage source NMOS7'. The current mirror Mi4 includes two transistors PMOS3' and PMOS4' with a common gate. The sources of the transistors PMOS3' and PMOS4' are connected to the power supply terminal Vreg. At the same time, the drain of the transistor PMOS3' is connected to the current merging terminal X as the input terminal of the current mirror Mi4. The non-inverting input terminal of the amplifier A3 is connected to the current merging terminal X. At the same time, the current merging terminal X is connected to the output terminal of the voltage-current converter. The reference voltage Vcm is input to the inverting input terminal of the amplifier A3, and the output terminal is connected to the gates of the transistors PMOS3' and PMOS4'. The amplifier A3 keeps the voltage of the current merging terminal X equal to the reference voltage Vcm of the other input terminal. Therefore, for the current merging terminal X, the current flowing out of the branch toward the ground terminal side is the first current I1, that is, a current whose current intensity value is proportional to the frequency of the reference clock signal Fref. The branch between the current merging terminal X and the voltage-current converter flows in or out of the second current I2. The current of the branch connected to the current merging terminal X and the amplifier A3 is zero. Therefore, the current of the branch between the current merging terminal X and the current mirror Mi4, that is, the current flowing through the transistor PMOS3', is the current obtained by merging the first current I1 and the second current I2. This current is the bias control current Ivco' obtained by merging. The bias control current Ivco' is the difference between the first current I1 and the second current I2. According to the setting of the voltage Vcm and Vtune, the second current I2 can be a positive current or a negative current.

[0093] The current mirror Mi4 copies the bias control current to one side of the transistor PMOS4', and outputs the mirror bias control current Ivco along the current path connected to the current control voltage source NMOS7'. The current control voltage source NMOS7' is also implemented by an N-type MOSFET with a gate and a drain connected. The drain of the transistor NMOS7' is connected to the output end of the current mirror Mi4 to receive the mirror bias control current Ivco, the source is connected to the ground terminal, and the gate outputs a bias control voltage Vbn proportional to the bias control current Ivco. In this embodiment, the bias current Ib is determined by the frequency of the reference clock signal Fref and the adjustment voltage Vtune. At the same time, the bias current Ib directly affects the delay time of the delay unit S1-S3, and is directly related to the frequency of the oscillation clock signal output by the oscillation loop. The frequency of the oscillation clock signal changes in direct proportion to the frequency of the reference clock signal Fref and inversely proportional to the adjustment voltage Vtune.

[0094] In order to prevent the current from flowing in the reverse direction, a transistor NMOS5' with a drain and a gate connected can be set between the output end of the current mirror Mi2 and the input end of the current mirror Mi4. The function of the transistor NMOS5' is equivalent to a diode, which can prevent the current from flowing in the direction opposite to the expected direction. At the same time, a transistor NMOS6' with a drain and a gate connected can be set between the drain of the transistor NMOS7' and the output end of the current mirror Mi4. The function of the transistor NMOS6' is equivalent to a diode, which can prevent the current from flowing in the direction opposite to the expected direction.

[0095] At the same time, in order to protect the circuit, a transistor NMOS for protection can be set between the output terminal of the bias control voltage Vbn and the ground terminal. pd2 . Transistor NMOS pd2 The gate inputs a protection control signal Pd, which is controlled to turn on and off to protect the circuit from overcurrent.

[0096] Therefore, by combining the first current and the second current on different sides of the current mirror, flexible design options are provided. At the same time, the current mirror can also be used to amplify or reduce the combined bias control current to improve accuracy.

[0097] In the embodiment of the present invention, different forms of delay units may also be used. Figure 6 FIG. 1 is a circuit diagram of an oscillation loop according to another embodiment of the present invention. Figure 6 As shown, the oscillation loop 6 of this embodiment includes an oscillation loop 61 and an AC coupling clock buffer 62. The connection relationship and circuit structure of the AC coupling clock buffer 62 of this embodiment are similar to Figure 2The oscillation loop 61 of this embodiment includes delay units S1'-S3'. Each delay unit S1'-S3' inputs a first bias control voltage Vbn and a second bias control voltage Vbp, and generates corresponding first bias current Ibn and second bias current Ibp based on the first bias control voltage Vbn and the second bias control voltage Vbp to set the delay time, so that the output signal frequency of the oscillation loop 61 corresponds to the first bias control voltage Vbn and the second bias control voltage Vbp. The first bias current Ibn affects the rate at which the capacitor is discharged, and the second bias current Ibp affects the rate at which the capacitor is charged. That is, the first bias current Ibn affects the delay time from 1 to 0, and the second bias current Ibp affects the delay time from 0 to 1. The first bias current and the second bias current can be set to be the same or different. Relative to Figure 2 With the delay unit structure shown, the oscillation loop 61 of this embodiment can control the frequency of the output signal more accurately.

[0098] Figure 6 FIG. 4 shows an exemplary circuit structure of the delay units S1′-S3′ of this embodiment. Figure 6As shown, taking the delay unit S1' as an example, the delay unit S1' includes a CMOS inverter CMOS1, a capacitor C1 (also referred to as a first capacitor), a first bias current source NMOS2 and a second bias current source PMOS5. Among them, the CMOS inverter CMOS1 includes transistors PMOS1 and NMOS1. The transistor PMOS1 is a P-type MOSFET, and the transistor NMOS1 is an N-type MOSFET. The first bias current source NMOS2 adopts an N-type MOSFET, which presents a voltage-controlled current source. The gate of the transistor NMOS2 inputs the first bias control voltage Vbn, the drain is connected to the CMOS inverter CMOS1, and the source is connected to the ground terminal. At the same time, the second bias current source PMOS5 adopts a P-type MOSFET, which presents a voltage-controlled current source. The source of the transistor PMOS5 is connected to the power supply terminal Vreg, the drain is connected to the CMOS inverter CMOS1, and the gate is controlled by the second bias control voltage Vbp. In fact, such a structure enables the transistor NMOS2 to be set in the discharge current loop of the capacitor C1, and the transistor PMOS5 to be set in the charging current loop of the capacitor C1. When the transistor PMOS1 is turned on and the transistor NMOS1 is turned off, the current flows from the power supply terminal Vreg to charge the capacitor C1, and the charging current is controlled by the second bias control voltage Vbp, so that the voltage rising slope of the capacitor C1 can be controlled. When the transistor PMOS1 is turned off and the transistor NMOS1 is turned on, the capacitor C1 is discharged through the transistors NMOS1 and NMOS2, and the discharge current is controlled by the first bias control voltage Vbn, so that the voltage falling slope of the capacitor C1 can be controlled. By controlling the rising slope and falling slope of the capacitor voltage, the time for the voltage of the capacitor C1 to rise to the inverse phase or fall to the inverse phase can be controlled, thereby controlling the delay time of the inverse signal output by the delay unit S1'.

[0099] Figure 7 The embodiment of the present invention is adapted to Figure 6 In this embodiment, the frequency current converter and the voltage current converter can be used in the same manner as Figure 3 or Figure 5 The same circuit structure as shown in the circuit is realized in Figure 7 No further display and description will be given in the following. Figure 7As shown, the first bias control voltage Vbn can be generated in the same manner as in the previous embodiment. However, in order to generate the second bias control voltage Vbp, a current mirror Mi1 (i.e., the first current mirror) can be added to the bias control circuit. The current mirror Mi1 includes the transistor NMOS7 and the transistor NMOS9 that serve as the current control voltage source in the previous circuit. The two are connected through a common gate to form a current mirror Mi1. The bias control current Ivco is copied to flow through the transistor PMOS6 through the current mirror Mi1. The drain and gate of the transistor PMOS6 are connected, and the source is connected to the power supply terminal Vreg, so that the second bias control voltage Vbp can be output. Figure 7 In the circuit shown, the current mirror Mi3, transistors NMOS5 and NMOS6, and amplifier A2 form a current merging circuit to merge the first current I1 and the second current I2 into a bias control current Ivco. Transistor PMOS6 serves as a control voltage output circuit, inputs the first mirror current, and outputs the second bias control voltage Vbp.

[0100] At the same time, a part of the current mirror Mi1, the gate of the transistor NMOS7, outputs the first bias control voltage Vbn. Thus, the transistor PMOS6 can form a current mirror with the second bias current source in each delay unit S1'-S3', thereby generating a bias current Ibp proportional to the bias control current Ivco to control the charging process of the capacitor. The transistor NMOS7 can form a current mirror with the first bias current source in the delay unit S1'-S3', thereby generating a bias current Ibn proportional to the bias control current Ivco to control the discharge process of the capacitor.

[0101] Therefore, this embodiment can more accurately control the delay time of the delay unit by adding a bias current source in the charging current loop, thereby further improving the accuracy of the voltage-controlled ring oscillator.

[0102] In some embodiments, a differential inverter may be used to replace the CMOS inverter in the above embodiment as the core structure of the delay unit. Figure 8 FIG. 1 is a circuit diagram of an oscillation loop according to another embodiment of the present invention. Figure 8As shown, the oscillation loop 8 of this embodiment includes an oscillation loop 81 and an AC-coupled clock buffer 82. The number of the AC-coupled clock buffers 82 of this embodiment is set to twice the number of the delay units, and each AC-coupled clock buffer 82 is connected to one of the two outputs of the corresponding delay unit, and outputs the corresponding positive-phase oscillation clock signal Clkp or negative-phase oscillation clock signal Clkn. The structure of the AC-coupled clock buffer 82 of this embodiment is the same as that of the previous embodiment. The oscillation loop 81 of this embodiment includes delay units S4-S7. Each delay unit S4-S7 inputs the third bias control voltage Vbn' and the fourth bias control voltage Vbp', and generates the corresponding third bias current Ibn' and fourth bias current Ibp' based on the third bias control voltage Vbn' and the fourth bias control voltage Vbp' to set the delay time, so that the output signal frequency of the oscillation loop 81 corresponds to the third bias control voltage Vbn' and the fourth bias control voltage Vbp'.

[0103] Figure 8 FIG. 4 shows an exemplary circuit structure of the delay units S4-S7 of this embodiment. Taking the delay unit S4 as an example, Figure 8 As shown, the delay unit S4 includes a differential inverter, a third bias current source NMOS10 and a pair of fourth bias current sources VI1 and VI2. Among them, the differential inverter includes two N-type MOSFETs connected with a common source. The gates of the two transistors NMOS11 and NMOS12 serve as the two differential input terminals Vin+ and Vin- of the delay unit respectively, and the drains serve as the two differential output terminals Vo+ and Vo- of the delay unit respectively, that is, the differential inverter is connected between the input terminal and the output terminal of the delay unit. At the same time, the sources of the transistors NMOS11 and NMOS12 are connected to each other. The third bias current source NMOS10 is arranged in the current path of the differential inverter, specifically, connected between the source and the ground terminal of the transistors NMOS11 and NMOS12 of the differential inverter, and is used to control the current flowing to the ground terminal. The fourth bias current sources VI1 and VI2 are respectively connected between the power supply terminal and the drains of the transistors NMOS11 and NMOS12, and are used to control the current flowing from the power supply terminal to the differential inverter. Figure 8 In the illustrated embodiment, each of the fourth bias current sources VI1 and VI2 includes two P-type MOSFETs with a common source and a common drain, one of which has a gate connected to its own drain, and the other receives a fourth bias control voltage Vbp'. Thus, the third bias current Ibn' and the fourth bias current Ibp' for charging and discharging the parasitic capacitance in the differential inverter can be controlled by the third bias control voltage Vbn' and the fourth bias control voltage Vbp', so that the delay time of the delay unit can be controlled, thereby controlling the output signal frequency of the oscillation loop.

[0104] At the same time, in order to obtain the third bias control voltage Vbn' and the fourth bias control voltage Vbp', it is possible to use Figure 7 The circuit shown.

[0105] Using a differential inverter to replace a CMOS inverter can utilize the symmetry of the two transistors in the differential inverter design to more effectively eliminate common-mode noise in the input signal, improve gain and linearity, and enable the differential inverter to maintain good performance over a wider signal range.

[0106] It should be understood that the above Figure 8 The circuit shown is only an example, and other types of differential inverter structures can be applied to the embodiments of the present invention. For example, the fourth bias current source can be replaced by a resistor, and the current control from the power supply end to the differential inverter is not performed. The delay time of the delay unit can be controlled solely by the third bias control voltage Vbn', and the same technical effect can be achieved. For another example, the third bias current source can also be replaced by a resistor, and the delay time of the delay unit can also be controlled solely by the fourth bias control voltage Vbp'.

[0107] The voltage-controlled ring oscillator of the embodiment of the present invention can be applied to various scenarios, such as wireless communication systems, phase-locked loops (PLLs), frequency synthesizers, modems, radar systems, and test and measurement instruments. Fig. 9 Schematic diagram of an electronic device according to an embodiment of the present invention. Fig. 9 As shown, the circuit of the electronic device 9 is provided with the voltage-controlled ring oscillator 91 and the functional circuit 92. Based on the oscillation clock signal generated by the voltage-controlled ring oscillator 91, the functional circuit 92 can realize functions such as synthesizing communication carriers and controlling radio frequency circuits. The electronic device can be a complete electronic system with independent functions, or a circuit board or circuit component with independent functions used as a component in an electronic system.

[0108] Meanwhile, the voltage-controlled ring oscillator of the embodiment of the present invention may also be integrated into an integrated circuit chip alone or together with other functional circuits.

[0109] The embodiment of the present invention uses a bias control signal to control the bias current in each delay unit, rather than adjusting the power supply, changing the delay level, or adjusting the number of resistors or capacitors in the delay unit as in the prior art. The voltage-controlled ring oscillator of the embodiment of the present invention converts the frequency information of the reference clock signal into a first current through a frequency-current converter, converts the adjustment voltage into a second current through a voltage-current converter, combines the first current and the second current to obtain a bias control current, and controls the bias current in each delay unit based on the bias control current, thereby achieving control of the delay time, and further achieving frequency control of the output oscillation clock signal. The frequency channel of the oscillation clock signal is determined by the component of the first current corresponding to the frequency information, and the fine adjustment of the frequency point can be achieved by adjusting the component of the second current corresponding to the voltage. Therefore, the voltage-controlled ring oscillator of the embodiment of the present invention can output an oscillation clock signal of a corresponding frequency according to control within an extremely wide frequency range.

[0110] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A voltage-controlled ring oscillator, characterized in that: The voltage-controlled ring oscillator comprises: A frequency-to-current converter, configured to convert a reference clock signal into a first current, wherein a strength value of the first current is associated with a frequency of the reference clock signal; A voltage-to-current converter, used for converting the regulated voltage into a second current; a bias control circuit that receives the first current and the second current as input and generates at least one bias control current; and An oscillation loop includes a plurality of delay units, wherein each of the delay units is driven by a bias current proportional to the bias control current, delays and inverts an input signal and outputs it to generate an oscillation clock signal, and the delay time of the delay unit is associated with the bias current, thereby controlling the frequency of the oscillation clock signal.

2. The voltage-controlled ring oscillator according to claim 1, characterized in that: The transistors in the bias control circuit and the transistors in the delay unit form a current mirror, so that the bias current is proportional to the bias control current.

3. The voltage-controlled ring oscillator according to claim 1, wherein: The frequency of the oscillation clock signal is proportional to the reference clock signal, and is proportional or inversely proportional to the regulation voltage.

4. The voltage-controlled ring oscillator according to claim 1, wherein: The oscillation loop further includes at least one AC-coupled clock buffer, which is connected to the output end of at least one delay unit and is used to output an oscillation clock signal.

5. The voltage-controlled ring oscillator according to claim 1, wherein: The bias control current is the sum or difference of the first current and the second current.

6. The voltage-controlled ring oscillator according to claim 1, wherein: The delay unit comprises: A first CMOS inverter connected between an input terminal and an output terminal of the delay unit; A first capacitor is arranged at an output end of the first CMOS inverter; and A first bias current source is provided in a charging or discharging current path of the first capacitor, and is used to charge or discharge the first capacitor according to a first bias current according to a state of the first CMOS inverter, wherein the first bias current is proportional to the bias control current.

7. The voltage-controlled ring oscillator according to claim 6, characterized in that: The first bias current source is arranged between the CMOS inverter and a ground terminal, and is used to control a discharge time of the first capacitor.

8. The voltage-controlled ring oscillator according to claim 7, characterized in that: The delay unit further comprises: The second bias current source is arranged between the first CMOS inverter and the power supply terminal, and is used for charging the first capacitor according to a second bias current, and the second bias current is proportional to the bias control current.

9. The voltage-controlled ring oscillator according to claim 6, characterized in that: The bias control circuit is used to combine the first current and the second current into a bias control current, and output a first bias control voltage corresponding to the bias control current; The first bias current source is used to generate the first bias current according to the first bias control voltage.

10. The voltage-controlled ring oscillator according to claim 9, characterized in that: The bias control circuit comprises a control voltage output circuit for converting the bias control current into a first bias control voltage, and the first bias current source and the voltage output circuit form a current mirror.

11. The voltage-controlled ring oscillator according to claim 8, characterized in that: The bias control circuit is used to combine the first current and the second current into a bias control current, and output a first bias control voltage and a second bias control voltage corresponding to the bias control current; The first bias current source is used to generate the first bias current according to a first bias control voltage; The second bias current source is used to generate the second bias current according to a second bias control voltage.

12. The voltage-controlled ring oscillator according to claim 11, characterized in that: The bias control circuit comprises: a current combining circuit, configured to combine the first current and the second current into a bias control current; A first current mirror, inputting the bias control current and outputting a first mirror current and a first bias control voltage; The control voltage output circuit inputs the first mirror current and outputs the second bias control voltage.

13. The voltage-controlled ring oscillator according to claim 1, wherein: The delay unit comprises: A differential inverter connected between an input terminal and an output terminal of the delay unit; The third bias current source is arranged in the current path of the differential inverter.

14. The voltage-controlled ring oscillator according to claim 13, wherein: The delay unit further comprises: a fourth bias current source, arranged between the differential inverter and the power supply terminal; Wherein, the third bias current source is arranged between the differential inverter and the ground terminal.

15. The voltage-controlled ring oscillator according to claim 14, characterized in that: The bias control circuit is used to combine the first current and the second current into a bias control current, and output a third bias control voltage and a fourth bias control voltage corresponding to the bias control current; The third bias current source is controlled by a third bias current corresponding to the third bias control voltage output; The fourth bias current source is controlled by a fourth bias current corresponding to the output of the fourth bias control voltage.

16. The voltage-controlled ring oscillator according to claim 1, wherein: The frequency-to-current converter is configured to control charging and discharging of the capacitor according to a reference clock signal and filter the discharge current, thereby converting the reference clock signal having a predetermined frequency into the first current.

17. The voltage-controlled ring oscillator according to claim 14, wherein: The frequency current converter comprises: A second CMOS inverter, connected between the power supply terminal and the intermediate terminal, with an input terminal receiving the reference clock signal; A second capacitor is arranged at an output end of the second CMOS inverter; A third capacitor connected between the middle terminal and the ground terminal; The second current mirror is connected between the middle terminal and the ground terminal, and is used for receiving the current input by the second CMOS inverter and generating the first current at the output terminal.

18. The voltage-controlled ring oscillator according to claim 17, wherein: The voltage-to-current converter comprises: a first amplifier, a first input terminal inputting the regulated voltage, and a second input terminal connected to an output terminal; A conversion resistor has one end connected to the reference voltage as an output end, and the other end connected to the output end of the first amplifier, thereby generating a second current corresponding to the adjustment voltage.

19. The voltage-controlled ring oscillator according to claim 17, wherein: The bias control circuit comprises: a third current mirror, an input end of which is connected to the output end of the second current mirror, an output end of which is connected to a current merging end, and the current merging end is connected to the output end of the voltage-to-current converter; a second amplifier, having a first input terminal inputting a reference voltage, a second input terminal connected to the current combining terminal, and an output terminal connected to the output terminal of the bias control circuit; and The first current-controlled voltage source is connected to the current path of the bias control current, receives the combined bias control current, and generates a corresponding first bias control voltage.

20. The voltage-controlled ring oscillator according to claim 17, wherein: The bias control circuit comprises: a fourth current mirror, whose input end is connected to the current merging end, whose output end outputs the bias control current, and wherein the current merging end is connected to the output end of the second current mirror and the output end of the voltage-to-current converter; A third amplifier, having a first input terminal inputting a reference voltage, a second input terminal connected to the current combining terminal, and an output terminal connected to a control terminal of the current mirror; The second current-controlled voltage source is connected to the output end of the fourth current mirror, receives the bias control current, and generates a corresponding first bias control voltage.

21. An electronic device, characterized in that: Comprising the voltage-controlled ring oscillator as described in any one of claims 1-20.

22. An integrated circuit, characterized in that: Comprising the voltage-controlled ring oscillator as described in any one of claims 1-20.

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