Second order passive noise shaping successive approximation analog-to-digital converter and noise shaping method

Abstract

The application provides a second-order passive noise shaping successive approximation register analog-to-digital converter, a noise shaping method, equipment and a computer readable storage medium. In each conversion period, a timing control circuit controls a capacitive digital-to-analog conversion circuit to perform voltage sampling of the current conversion period according to the conversion result of the previous conversion period, and generates an output voltage that successively approximates the voltage to be measured based on the sampled voltage, until the residual voltage of the current conversion period is generated. During this period, on the one hand, a multi-input comparator performs conversion output according to the output voltage of the capacitive digital-to-analog conversion circuit and the integral voltage of the previous conversion period output by the passive loop filter circuit, to obtain the conversion result of the current conversion period, and on the other hand, the residual sampling unit collects the residual voltage of the current conversion period, and then charges the first integral unit and the second integral unit successively to obtain the integral voltage of the current conversion period, which is used for conversion output in the next conversion period. In this way, the KT / C noise and gain loss during residual sampling can be eliminated, the comparator noise is reduced, the signal-to-noise ratio and the spur-free dynamic range of the analog-to-digital converter are improved, and in addition, the power consumption and design complexity of the entire analog-to-digital converter are low due to the use of passive filtering.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of successive approximation analog-to-digital converter, in particular to a second-order passive noise shaping successive approximation analog-to-digital converter, a noise shaping method, a noise shaping device and a readable storage medium. BACKGROUND

[0002] Analog-to-digital converters are mainly divided into Nyquist rate analog-to-digital converters and oversampling analog-to-digital converters, one of the most representative types in Nyquist rate analog-to-digital converters is successive approximation analog-to-digital converter (SAR DAC for short), and the most widely used oversampling analog-to-digital converter is Σ-Δ ADC; SAR ADC is widely used in the field of medium speed and medium accuracy due to the existence of comparator noise and DAC establishment error; and Σ-Δ ADC has high accuracy, but since an integrator is needed in the internal active loop filter, the core unit in the integrator is an operational amplifier, which not only has high power consumption, but also reduces the conversion rate of the system, so Σ-Δ ADC is widely used in the field of low speed and high accuracy.

[0003] Noise shaping successive approximation analog-to-digital converter is an application of oversampling technology and noise shaping technology in SAR DAC, which has the advantages of medium speed and high efficiency of SAR DAC and high accuracy of Σ-Δ. Some existing noise shaping successive approximation analog-to-digital converters use active loop filters, which still have relatively high power consumption; and some use passive loop filter structures, which can effectively reduce system design complexity and power consumption, but usually only achieve first-order noise shaping, and when sampling the residual voltage using a switched capacitor, KT / C noise and gain loss are introduced, and the passive loop filter of this structure needs a multiple-input pair comparator, which increases the comparator noise, so the noise shaping effect is not very ideal. SUMMARY

[0004] The present application provides a second-order passive noise shaping successive approximation analog-to-digital converter with low power consumption and good noise shaping effect, a noise shaping method, a noise shaping device and a readable storage medium.

[0005] A second-order passive noise shaping successive approximation analog-to-digital converter, comprising a capacitive digital-to-analog conversion circuit, a multiple-input comparator, a SAR logic control circuit, two groups of passive loop filter circuits and a timing control circuit.

[0006] The input end of the capacitive digital-to-analog conversion circuit is connected with the SAR logic control circuit, the first differential output end of the capacitive digital-to-analog conversion circuit is connected with the first input end of the multiple-input comparator, and the second differential output end of the capacitive digital-to-analog conversion circuit is connected with the second input end of the multiple-input comparator.

[0007] Each of the passive loop filter circuits comprises a residual error sampling unit, a first integration unit and a second integration unit; each of the residual error sampling units is connected in one-to-one correspondence with the first differential output end and the second differential output end; the first integration unit and the second integration unit are connected with the residual error sampling units in the same group and connected with the multi-input comparator;

[0008] The timing control circuit is connected with the SAR logic control circuit, the multi-input comparator and each of the passive loop filter circuits, and is used to drive the SAR logic control circuit according to the conversion result of the last conversion period, so as to control the capacitive digital-to-analog conversion circuit to perform voltage sampling in the current conversion period, and generate an output voltage that successively approximates to the voltage to be measured based on the sampled voltage, until the residual error voltage in the current conversion period is generated;

[0009] The multi-input comparator is used to perform conversion output according to the output voltage of the capacitive digital-to-analog conversion circuit and the integral voltage of the last conversion period output by the passive loop filter circuit, to obtain the conversion result in the current conversion period;

[0010] The timing control circuit is further used to control the residual error sampling unit to collect the residual error voltage in the current conversion period, and to charge the first integration unit and the second integration unit based on the residual error voltage in the current conversion period, respectively, to obtain the integral voltage in the current conversion period, for conversion output in the next conversion period.

[0011] In one embodiment, the capacitance value of the residual error sampling unit is equal to one third of the capacitance value of the capacitive digital-to-analog conversion circuit; the capacitance value of the first integration unit and the capacitance value of the second integration unit are respectively equal to the capacitance value of the capacitive digital-to-analog conversion circuit.

[0012] In one embodiment, each of the residual error sampling units comprises a sampling capacitor and a sampling switch; a first end of the sampling switch is connected with a target differential output end, a second end of the sampling switch is connected with a first end of the sampling capacitor, the first integration unit and the second integration unit, respectively; a second end of the sampling capacitor is connected with a ground end; wherein the target differential output end is the first differential output end or the second differential output end.

[0013] In one embodiment, the first integration unit comprises a first switch and a first integration capacitor; the second integration unit comprises a second switch and a second integration capacitor; a first end of the first switch and a first end of the second switch are connected with a first end of the sampling capacitor respectively; a second end of the first switch and a first end of the first integration capacitor are connected with the multi-input comparator respectively; a second end of the first integration capacitor is connected with the ground end; a second end of the second switch and a first end of the second integration capacitor are connected with the multi-input comparator respectively; a second end of the second integration capacitor is connected with the ground end.

[0014] In one embodiment, the analog-to-digital converter further comprises a third switch; a first end of the third switch is connected with the residual error sampling unit, a second end of the third switch is connected with the ground end; the timing control circuit is further configured to control the third switch to be closed before controlling the residual error sampling unit to collect the residual error voltage of the current conversion period, so as to discharge the residual error sampling unit.

[0015] In one embodiment, the timing control circuit controls the capacitor type digital-to-analog conversion circuit to perform voltage sampling of the current conversion period at the end of charging of the first integration unit in the last conversion period.

[0016] A noise shaping method applied to a second-order passive noise shaping successive approximation register (SAR) analog-to-digital converter, the second-order passive noise shaping SAR analog-to-digital converter comprising a capacitor type digital-to-analog conversion circuit, a multi-input comparator, a SAR logic control circuit and two groups of passive loop filter circuits; the capacitor type digital-to-analog conversion circuit is connected with the SAR logic control circuit; a first differential output end of the capacitor type digital-to-analog conversion circuit is connected with a first input end of the multi-input comparator; a second differential output end of the capacitor type digital-to-analog conversion circuit is connected with a second input end of the multi-input comparator; each of the passive loop filter circuits comprises a residual error sampling unit, a first integration unit and a second integration unit; each of the residual error sampling units is connected with the first differential output end and the second differential output end one by one; the first integration unit and the second integration unit are connected with the residual error sampling unit of the same group and the multi-input comparator respectively;

[0017] The noise shaping method comprises: driving the SAR logic control circuit according to a conversion result of a last conversion period, to control the capacitor type digital-to-analog conversion circuit to perform voltage sampling of a current conversion period, and to generate an output voltage of a successive approximation of a to-be-measured voltage based on the sampled voltage, until a residual error voltage of the current conversion period is generated;

[0018] The multi-input comparator is configured to convert and output according to an output voltage of the capacitive digital-to-analog conversion circuit and an integral voltage of a previous conversion period output by the passive loop filter circuit, to obtain a conversion result of a current conversion period.

[0019] The noise shaping method further includes: controlling the residual error sampling unit to collect the residual error voltage of the current conversion period, and charging the first integral unit and the second integral unit based on the residual error voltage of the current conversion period in sequence, to obtain an integral voltage of the current conversion period, for conversion output in a next conversion period.

[0020] In one embodiment, a capacitance value of the residual error sampling unit is equal to one third of a capacitance value of the capacitive digital-to-analog conversion circuit; and capacitance values of the first integral unit and the second integral unit are respectively equal to the capacitance value of the capacitive digital-to-analog conversion circuit.

[0021] In one embodiment, each of the residual error sampling units includes a sampling capacitor and a sampling switch; a first end of the sampling switch is connected to a target differential output end, a second end of the sampling switch is connected to a first end of the sampling capacitor, the first integral unit and the second integral unit respectively; a second end of the sampling capacitor is connected to a ground end; wherein the target differential output end is the first differential output end or the second differential output end; and the control of the residual error sampling unit to collect the residual error voltage of the current conversion period includes:

[0022] controlling the sampling switch to be closed, so that the sampling capacitor collects the residual error voltage of the current conversion period.

[0023] In one embodiment, the first integral unit includes a first switch and a first integral capacitor; the second integral unit includes a second switch and a second integral capacitor; a first end of the first switch and a first end of the second switch are connected to the first end of the sampling capacitor respectively; a second end of the first switch and a first end of the first integral capacitor are connected to the multi-input comparator respectively; a second end of the first integral capacitor is connected to the ground end; a second end of the second switch and a first end of the second integral capacitor are connected to the multi-input comparator respectively; a second end of the second integral capacitor is connected to the ground end; and the charging of the first integral unit and the second integral unit based on the residual error voltage of the current conversion period in sequence includes:

[0024] opening the sampling switch and closing the first switch, so that the sampling capacitor charges the first integral capacitor;

[0025] opening the first switch and closing the second switch, so that the discharged sampling capacitor charges the second integral capacitor.

[0026] In one embodiment, the analog-to-digital converter further comprises a third switch, a first end of the third switch is connected with the residual voltage sampling unit, a second end of the third switch is connected with the ground, and the noise shaping method further comprises:

[0027] Before controlling the residual voltage sampling unit to collect the residual voltage of the current conversion period, the third switch is controlled to be closed so that the residual voltage sampling unit is discharged.

[0028] In one embodiment, the controlling the capacitive digital-to-analog conversion circuit to perform voltage sampling of the current conversion period comprises: controlling the capacitive digital-to-analog conversion circuit to perform voltage sampling of the current conversion period at the end of charging of the first integration unit in the previous conversion period.

[0029] A noise shaping device comprising a memory and a processor, the memory stores a computer program, and the processor implements the steps of the method of any one of the above when executing the computer program.

[0030] A computer readable storage medium having stored thereon a computer program, the computer program being executed by a processor to implement the steps of the method of any one of the above.

[0031] The above is achieved by, in each conversion period, controlling, by a timing control circuit, the capacitive digital-to-analog conversion circuit to perform voltage sampling of the current conversion period according to the conversion result of the previous conversion period, and generating an output voltage that successively approximates the voltage to be measured based on the sampled voltage, until the residual voltage of the current conversion period is generated, during which, on the one hand, a multi-input comparator performs conversion output according to the output voltage of the capacitive digital-to-analog conversion circuit and the integral voltage of the previous conversion period output by the passive loop filter circuit, to obtain the conversion result of the current conversion period, and on the other hand, the residual voltage sampling unit is controlled to collect the residual voltage of the current conversion period, and then the first integration unit and the second integration unit are successively charged to obtain the integral voltage of the current conversion period, for conversion output in the next conversion period, so that the KT / C noise and gain loss during residual voltage sampling can be eliminated, the comparator noise is reduced, the signal-to-noise ratio and the spur-free dynamic range of the analog-to-digital converter are improved, and in addition, the power consumption and design complexity of the entire analog-to-digital converter are low due to the use of passive filtering. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 A structure schematic diagram of a second-order passive noise shaping successive approximation analog-to-digital converter according to an embodiment of the present application;

[0033] Figure 2 A schematic diagram of sampling and integrating the residual voltage according to the present application;

[0034] Figure 3 A structure diagram of a second-order passive noise-shaping successive approximation analog-to-digital converter according to another embodiment of the present application;

[0035] Figure 4 A timing control diagram of a noise-shaping process according to the present application;

[0036] Figure 5 A flow chart of a noise-shaping process according to an embodiment of the present application;

[0037] Figure 6 A structure diagram of a computer device for implementing a noise-shaping method according to an embodiment of the present application. DETAILED DESCRIPTION

[0038] It should be understood that the specific embodiments described herein merely exemplify the present application and do not limit the present application.

[0039] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort fall within the scope of the present application.

[0040] It should be noted that all directional indications, such as up, down, left, right, front, back, etc., described herein are only used to explain the relative position relationship, movement condition, etc. between components in a certain posture (as shown in the drawings), and if the certain posture changes, the directional indications also change accordingly. The connection can be direct connection or indirect connection.

[0041] In addition, the descriptions such as "first", "second" and the like in the present application are only for the purpose of description, and cannot be understood as indicating or implying the relative importance of the technical features indicated or the number of the technical features indicated. Therefore, the features defined as "first", "second" can explicitly or implicitly include at least one of the features. In addition, the technical solutions of various embodiments can be combined with each other, but it must be based on the realization of a person skilled in the art, and when the combination of technical solutions contradicts each other or cannot be realized, it should be considered that the combination of technical solutions does not exist and is not within the scope of protection claimed by the present application.

[0042] Figure 1 A structure block diagram of a second-order passive noise-shaping successive approximation analog-to-digital converter according to an embodiment of the present application is shown in FIG. 1. Figure 1As shown, the analog-to-digital converter includes a capacitive digital-to-analog conversion circuit 110, a multi-input comparator 120, a SAR logic control circuit 130, two groups of passive loop filter circuits 140 and a timing control circuit 150; the capacitive digital-to-analog conversion circuit 110 is connected to the SAR logic control circuit, the first differential output terminal of the capacitive digital-to-analog conversion circuit 110 is connected to the first input terminal of the multi-input comparator 120, and the second differential output terminal of the capacitive digital-to-analog conversion circuit 110 is connected to the second input terminal of the multi-input comparator 120; each passive loop filter circuit 140 includes a residual sampling unit 141, a first integration unit 142 and a second integration unit 143; each residual sampling unit 141 is connected to the first differential output terminal and the second differential output terminal respectively; the first integration unit 142 and the second integration unit 143 are respectively connected to the residual sampling unit 141 of the same group and to the multi-input comparator 120; the timing control circuit 150 is respectively connected to the S The AR logic control circuit 130, the multi-input comparator 120, and each passive loop filter circuit 140 are connected and are used to drive the SAR logic control circuit 130 according to the conversion result of the previous conversion cycle to control the capacitive digital-to-analog conversion circuit 110 to perform voltage sampling for the current conversion cycle, and generate an output voltage that successively approximates the voltage to be measured based on the sampled voltage until a residual voltage for the current conversion cycle is generated; the multi-input comparator is used to convert and output based on the output voltage of the capacitive digital-to-analog conversion circuit 110 and the integrated voltage of the previous conversion cycle output by the passive loop filter circuit 140 to obtain the conversion result of the current conversion cycle; the timing control circuit 150 is also used to control the residual sampling unit 141 to collect the residual voltage of the current conversion cycle, and to charge the first integration unit 142 and the second integration unit 143 respectively based on the residual voltage of the current conversion cycle to obtain the integrated voltage of the current conversion cycle for use in the conversion output of the next conversion cycle.

[0043] Understandable, reference Figure 1 As shown, the capacitive digital-to-analog conversion circuit 110 is a differential structure, which includes a plurality of capacitors ( Figure 1 Only one is shown in the figure) composed of a positive capacitor array and a negative capacitor array, the input end of the capacitive digital-to-analog conversion circuit 110 includes the input end of the positive capacitor array and the input end of the negative capacitor array. In the sampling phase, it can be switched on and off at the switch Φ s The voltage to be measured (V in / V ip In the conversion phase, the comparison result of the multi-input comparator 120 received by the SAR logic control circuit 130 can be used to determine the voltage V to be measured. in / V ip Continuously search the binary interval and compare it with V ref / 2、V ref / 2±V ref / 4、Vref / 2±V ref / 4±V ref / 8……comparison, so as to gradually approach the to-be-measured voltage V in and V ip the interval, and finally obtain the digital signal for equivalent to-be-measured voltage V in and V ip .

[0044] The analog-to-digital converter can be a periodic working mode, wherein each conversion period can include two stages of conversion stage and residual error integration stage; taking the current conversion period as an example, in the conversion stage, the passive loop filter circuit 140 is in a non-working state, that is, the residual error sampling unit 141, the first integration unit 142 and the second integration unit 143 in the passive loop filter circuit 140 are all not working, and after receiving the conversion result of the last conversion period, the timing control circuit 150 enters a new conversion period, that is, starts to drive the SAR logic control circuit, and then the SAR logic control circuit controls the one end of the capacitor in each capacitor array of the capacitor type digital-to-analog conversion circuit 110 to receive the to-be-measured voltage and the other end to receive the common-mode voltage, so as to realize voltage sampling. After sampling is completed, the switch Φ sThe output voltage of the capacitive digital-to-analog conversion circuit 110 is adjusted by adjusting the switches in the capacitor array to gradually approach the to-be-measured voltage in each shift process, so that the output voltage gradually approaches the to-be-measured voltage in each shift process, until the shift ends to generate the residual voltage of the current conversion period. Assuming that the output voltage of the first differential output end of the capacitive digital-to-analog conversion circuit 110 in the gradual approximation process is VCP, and the output voltage of the second differential output end is VCN, wherein the output is converted by the multi-input comparator according to the current output voltage and the integral voltage of the previous conversion period during the shift, and then the next bit is shifted by the SAR logic control circuit controlled by the timing control circuit 150, until the shift of the current conversion period ends, the multi-input comparator 120 converts the output according to the output voltage of the capacitive digital-to-analog conversion circuit 110 after the last shift and the integral voltage of the previous conversion period output by the passive loop filter circuit 140, and finally the conversion result of the current conversion period can be obtained. After the timing control circuit 150 receives the conversion result of the current conversion period, the next conversion period starts, and so on. Wherein, the integral voltage of the previous conversion period is the integral voltage obtained by charging the first integral unit 142 and the second integral unit 143 in sequence after the residual voltage sampling unit 141 collects the residual voltage in the previous conversion period. Then enter the residual integral stage, after obtaining the residual voltage, the residual voltage sampling unit 141 collects the residual voltage of the current conversion period under the control of the timing control circuit 150, and charges the first integral unit 142 and the second integral unit 143 in sequence based on the residual voltage of the current conversion period to obtain the integral voltage of the current conversion period, which is used for the conversion stage of the next conversion period. Wherein, the output voltage of the first differential output end is VCP, and the output voltage of the second differential output end is VCN.

[0045] The following is proved by calculation that the analog-to-digital converter has good noise shaping effect.

[0046] The integral voltage includes the first integral voltage after charging the first integral unit 142 and the second integral voltage after charging the second integral unit 143. The multi-input comparator 120 can be a six-input comparator. The end connected with the first integral unit 142 is set as GM_INT1, the end connected with the second integral unit 143 is set as GM_INT2, and the end connected with the capacitive digital-to-analog converter is set as GM_VIN. The output ratio between each end is set as GM_INT1=4GM_VIN; GM_INT2=16GM_VIN, so that the output D out (z) is set as:

[0047] D out (z)=V in (z)+4V INT1 (z)+16V INT2 (z)+Q(z)

[0048] wherein V in (z) is the voltage to be measured converted to the complex frequency domain in , V INT1 (z) is the first integral voltage converted to the complex frequency domain INT2 (z) is the second integral voltage converted to the complex frequency domain, Q(z) includes quantization error and equivalent input noise of the comparator. In combination with the above formula, the residual voltage V res (z) in the complex frequency domain can be expressed as:

[0049] V res (z) = V in (z) - D out (z)

[0050] = -4V INT1 (z) - 16V INT2 (z) - Q(z)

[0051] Referring to Figure 2 , it is assumed that the residual voltage is V res , and the total capacitance value of the positive and negative capacitance matrices is C DAC , for ease of calculation, the capacitance value of the residual sampling unit 141 is , the capacitance value of the first integral unit 142 and the capacitance value of the second integral unit 143 are both C DAC ; the opening and closing of the switch S1 represents the control of charging the residual sampling unit 141, the opening and closing of the switch S2 represents the control of charging the first integral unit 142, and the opening and closing of the switch S3 represents the control of charging the second integral unit 143; when the residual sampling unit 141 collects the residual voltage (i.e., only the switch s1 is closed), the charges of the residual voltage are redistributed between the capacitance matrix and the residual sampling unit 141, and the voltage sampled by the residual sampling unit 141 is represented as V res ', then the residual sampling unit 141 charges the first integral unit 142 (i.e., only the switch s2 is closed), the charges of the voltage V res ' are redistributed between the residual sampling unit 141 and the first integral unit 142, and the voltage of the first integral unit 142 after charging is represented as V INTI

[0052] Then the residual sampling unit 141 charges the second integral unit 143 (i.e., only the switch s3 is closed), the charges of the voltage V res ' are redistributed between the residual sampling unit 141 and the first integral unit 142, and the voltage of the second integral unit 143 after charging is represented as V INT2 , assuming that the initial VINT1 and VINT2 are both 0, based on the charge conservation, it can be obtained that in the nth conversion period:

[0053]

[0054] After Z-transform, we have

[0055]

[0056] After arrangement, we have

[0057]

[0058] Similarly, we have

[0059]

[0060] After Z-transform, we have

[0061]

[0062] After arrangement, we have

[0063]

[0064] Again, because

[0065] V res (z) = V in (z) - D out (z) = -4V INT1 (z) - 16V INT2 (z) - Q(z)

[0066] V res (z) = V INT1 (z) and V INT2 (z) can be obtained as follows:

[0067] V res (z) = -4V INT1 (z) - 16V INT2 (z) - Q(z)

[0068]

[0069] Solving, we have

[0070]

[0071] Substituting

[0072] D out (z) = V in (z) - V res (z)

[0073] We have

[0074]

[0075] The noise transfer function (NTF) has two zeros at Z=0.75, and when Z=1, NTF=1 / 16. Therefore, based on the structure of the above-mentioned analog-to-digital converter, by reasonably setting the capacitance values of the residue sampling unit 141, the first integration unit 142, and the second integration unit 143, theoretically, noise suppression of -24 dB can be achieved.

[0076] The above-mentioned method is that, in each conversion period, the timing control circuit 150 controls the capacitive digital-to-analog conversion circuit 110 to perform voltage sampling of the current conversion period according to the conversion result of the previous conversion period, and generates an output voltage that successively approximates the voltage to be measured based on the sampled voltage, until the residue voltage of the current conversion period is generated. Then, on one hand, the multi-input comparator performs conversion output according to the output voltage of the capacitive digital-to-analog conversion circuit 110 and the integral voltage of the previous conversion period output by the passive loop filter circuit 140, to obtain the conversion result of the current conversion period. On the other hand, the timing control circuit 150 controls the residue sampling unit 141 to collect the residue voltage of the current conversion period, and based on the residue voltage of the current conversion period, the first integration unit 142 and the second integration unit 143 are successively charged to obtain the integral voltage of the current conversion period, which is used for conversion output in the next conversion period. In this way, by performing second-order integration of the residue voltage at the end of each conversion period and using it for conversion output in the next conversion period, the KT / C noise and gain loss during residue sampling can be eliminated, the comparator noise is reduced, the signal-to-noise ratio and the spur-free dynamic range of the analog-to-digital converter are improved, and in addition, since the passive loop filter circuit 140 is used, the power consumption and design complexity of the entire analog-to-digital converter are also low.

[0077] In one embodiment, the capacitance value of the residue sampling unit 141 is equal to one-third of the capacitance value of the capacitive digital-to-analog conversion circuit 110; the capacitance value of the first integration unit 142 and the capacitance value of the second integration unit 143 are each equal to the capacitance value of the capacitive digital-to-analog conversion circuit 110.

[0078] It can be understood that, assuming that the capacitance value of the capacitive digital-to-analog conversion circuit 110 is C DAC , the capacitance value of the residue sampling unit 141 is The capacitance value of the first integration unit 142 and the capacitance value of the second integration unit 143 are each C DAC . According to the calculation process of the above-mentioned embodiment, the final noise suppression can reach -24 dB. By setting the capacitance values in this way, the overall noise of the analog-to-digital converter can be greatly reduced.

[0079] In one embodiment, as Figure 3As shown, each residual sampling unit 141 includes a sampling capacitor Cs and a sampling switch S0; a first end of the sampling switch S0 is connected with the target differential output end, a second end of the sampling switch S0 is connected with a first end of the sampling capacitor Cs, the first integrating unit 142 and the second integrating unit 143 respectively; a second end of the sampling capacitor Cs is connected with the ground end; wherein the target differential output end is the first differential output end or the second differential output end.

[0080] It can be understood that the number of residual sampling units 141 is two, for the residual sampling unit 141 connected with the first differential output end, a first end of the sampling switch S0 in the residual sampling unit 141 is connected with the first differential output end, and for the residual sampling unit 141 connected with the second differential output end, a first end of the sampling switch S0 in the residual sampling unit 141 is connected with the second differential output end.

[0081] By controlling the sampling switch S0 to be closed, the charging of the sampling capacitor Cs can be realized, that is, the charging of the residual sampling unit 141 is realized. The residual sampling unit 141 has a simple structure and is easy to control.

[0082] In one embodiment, the first integrating unit 142 includes a first switch S1 and a first integrating capacitor C1; the second integrating unit 143 includes a second switch S2 and a second integrating capacitor C2; a first end of the first switch S1 and a first end of the second switch S2 are connected with the first end of the sampling capacitor Cs respectively; a second end of the first switch S1 and a first end of the first integrating capacitor C1 are connected with the multi-input comparator 120 respectively; a second end of the first integrating capacitor C1 is connected with the ground end; a second end of the second switch S2 and a first end of the second integrating capacitor C2 are connected with the multi-input comparator 120 respectively; a second end of the second integrating capacitor C2 is connected with the ground end.

[0083] It can be understood that the first integrating unit 142 and the second integrating unit 143 can respectively include a switch and a capacitor, and the charging of the capacitor is controlled by the opening and closing of the switch, which has a simple structure and is easy to control.

[0084] In one embodiment, the analog-to-digital converter further includes a third switch S3; a first end of the third switch S3 is connected with the residual sampling unit 141, a second end of the third switch S3 is connected with the ground end, and the timing control circuit 150 is further configured to control the third switch S3 to be closed before controlling the residual sampling unit 141 to collect the residual voltage of the current conversion period, so that the residual sampling unit 141 is discharged.

[0085] Specifically, when the residual sampling unit 141 includes a sampling capacitor Cs and a sampling switch S0, a first end of the third switch S3 is connected to the first end of the sampling capacitor Cs, and a second end of the third switch S3 is connected to the ground. The timing control circuit 150 is further configured to close the third switch S3 to discharge the sampling capacitor Cs before controlling the residual sampling unit 141 to collect the residual voltage of the current conversion cycle. This prevents the residual voltage from the previous conversion cycle from remaining on the sampling capacitor Cs, thereby preventing it from affecting the integrated voltage of the current conversion cycle.

[0086] In one embodiment, the timing control circuit 150 controls the capacitive digital-to-analog conversion circuit 110 to perform voltage sampling in the current conversion cycle at the moment when the charging of the first integration unit in the previous conversion cycle ends.

[0087] It can be understood that since the capacitive digital-to-analog conversion circuit 110 performs voltage sampling at the beginning of each conversion cycle, and since the voltage sampling process and the integration process of the residual voltage do not interfere with each other, in order to shorten the overall conversion time, the voltage sampling of the next conversion cycle can be started at the moment when the charging of the first integration unit 142 using the residual voltage is completed by the timing control circuit 150.

[0088] Specifically, the first switch S1 is used to control the charging of the first integration unit 142, the second switch S2 is used to control the charging of the second integration unit 143, and the switch Φ s Control the capacitor type digital-to-analog conversion circuit 110 to realize voltage acquisition, then the switch Φ s The closing time can be referred to Figure 4 The time t1 shown is the charging end time of the first integration unit 142. This allows the capacitive DAC circuit 110 to complete voltage acquisition for the next conversion cycle when the charging end time of the second integration unit 143, thus saving the overall DAC conversion time.

[0089] An embodiment of the present invention further provides a noise shaping method, which is applied to a second-order passive noise shaping successive approximation analog-to-digital converter. The second-order passive noise shaping successive approximation analog-to-digital converter includes a capacitive digital-to-analog conversion circuit 110, a multi-input comparator 120, a SAR logic control circuit 130, and two sets of passive loop filter circuits 140; the capacitive digital-to-analog conversion circuit 110 is connected to the SAR logic control circuit, the first differential output terminal of the capacitive digital-to-analog conversion circuit 110 is connected to the first input terminal of the multi-input comparator 120, and the second differential output terminal of the capacitive digital-to-analog conversion circuit 110 is connected to the second input terminal of the multi-input comparator 120; each passive loop filter circuit 140 includes a residual sampling unit 141, a first integration unit 142, and a second integration unit 143; each residual sampling unit 141 is connected to the first differential output terminal and the second differential output terminal respectively; the first integration unit 142 and the second integration unit 143 are connected in a one-to-one correspondence. 43 are respectively connected to the residual sampling unit 141 of the same group and are connected to the multi-input comparator 120; the SAR logic control circuit is driven according to the conversion result of the previous conversion cycle to control the capacitive digital-to-analog conversion circuit 110 to perform voltage sampling of the current conversion cycle, and an output voltage that successively approximates the voltage to be measured is generated based on the sampled voltage until the residual voltage of the current conversion cycle is generated; the multi-input comparator is used to convert and output according to the output voltage of the capacitive digital-to-analog conversion circuit 110 and the integrated voltage of the previous conversion cycle output by the passive loop filter circuit 140, to obtain the conversion result of the current conversion cycle; the noise shaping method also includes: controlling the residual sampling unit 141 to collect the residual voltage of the current conversion cycle, and charging the first integration unit 142 and the second integration unit 143 respectively based on the residual voltage of the current conversion cycle to obtain the integrated voltage of the current conversion cycle for use in the conversion output of the next conversion cycle.

[0090] It can be understood that the noise shaping method can be implemented by the timing control circuit 150. The timing control circuit 150 can be provided internally by the second-order passive noise shaping successive approximation analog-to-digital converter or provided by an external device.

[0091] The capacitive digital-to-analog conversion circuit 110 is a differential structure, which includes a plurality of capacitors ( Figure 1 The input end of the capacitive digital-to-analog conversion circuit 110 includes the input end of the positive capacitor array and the input end of the negative capacitor array. One end of each capacitor in the positive capacitor array is connected in common as the input end of the positive capacitor array, which can be switched on and off at the switch Φ s Under the control of the test voltage (V ip / V in By controlling each switch, the comparison result of the multi-input comparator 120 received by the SAR logic control circuit 130 can be measured voltage V inThe search of the two-partition interval is continuously carried out, which is compared with V ref / 2, V ref / 2±V ref / 4, V ref / 2±V ref / 4±V ref / 8... to gradually approach the interval where V in and V ip are located, and finally obtain the digital signal for equivalent V in and V ip .

[0092] The analog-to-digital converter can be a periodic working mode, wherein each conversion period can include two stages of conversion stage and residual error integration stage; taking the current conversion period as an example, in the conversion stage, the passive loop filter circuit 140 is in a non-working state, that is, the residual error sampling unit 141, the first integration unit 142 and the second integration unit 143 therein are all not working, after receiving the conversion result of the last conversion period, entering a new conversion period, that is, starting to drive the SAR logic control circuit, and then by the SAR logic control circuit, controlling the one end of the capacitor in each capacitor array of the capacitor type digital-to-analog conversion circuit 110 to receive the to-be-measured voltage and the other end to receive the common-mode voltage, to realize voltage sampling, after the sampling is completed, the switch Φ sThe output voltage of the capacitive digital-to-analog conversion circuit 110 is adjusted by adjusting each switch in the capacitor array to shift, so that the output voltage approaches the to-be-measured voltage step by step in each shifting process, until the shift ends to generate the residual error voltage of the current conversion period. It is assumed that the output voltage of the first differential output end of the capacitive digital-to-analog conversion circuit 110 is VCP, and the output voltage of the second differential output end is VCN in the step-by-step approximation process. During the shift, the multi-input comparator converts and outputs according to the current output voltage and the integral voltage of the previous conversion period, and then drives the SAR logic control circuit to control the shift of the next bit, until the shift of the current conversion period ends, and the conversion result of the current conversion period can be obtained. After receiving the conversion result of the current conversion period, the next conversion period is started, and so on. The multi-input comparator 120 converts and outputs according to the output voltage of the capacitive digital-to-analog conversion circuit 110 and the integral voltage of the previous conversion period output by the passive loop filter circuit 140 to obtain the conversion result of the current conversion period; wherein the integral voltage of the previous conversion period is obtained by successively charging the first integral unit 142 and the second integral unit 143 by the residual error sampling unit 141 after collecting the residual error voltage in the previous conversion period. Then, the residual error integration stage is entered, the residual error sampling unit 141 collects the residual error voltage of the current conversion period after obtaining the residual error voltage, and successively charges the first integral unit 142 and the second integral unit 143 based on the residual error voltage of the current conversion period to obtain the integral voltage of the current conversion period, which is used for the conversion stage of the next conversion period.

[0093] The noise shaping result achieved by the above manner can be referred to Figure 1 the analysis of the embodiments, which will not be described here.

[0094] The above-mentioned through in each conversion period, according to the conversion result of the last conversion period, the voltage sampling of the current conversion period is controlled by the capacitive digital-to-analog conversion circuit 110, and the output voltage which gradually approaches the voltage to be measured is generated based on the sampled voltage, until the residual voltage of the current conversion period is generated, then on the one hand, the conversion output is obtained by the multi-input comparator according to the output voltage of the capacitive digital-to-analog conversion circuit 110 and the integral voltage of the last conversion period output by the passive loop filter circuit 140, and the conversion result of the current conversion period is obtained, on the other hand, the residual voltage of the current conversion period is collected by the residual voltage sampling unit 141, and the first integral unit 142 and the second integral unit 143 are charged based on the residual voltage of the current conversion period, respectively, to obtain the integral voltage of the current conversion period, for the conversion output of the next conversion period, so that the KT / C noise and gain loss in the residual sampling are eliminated by performing the second-order integration of the residual voltage at the end of each conversion period and for the conversion output of the next conversion period, and the comparator noise is reduced, the signal-to-noise ratio and the spur-free dynamic range of the analog-to-digital converter are improved, and in addition, since the passive loop filter circuit 140 is used, the power consumption and design complexity of the entire analog-to-digital converter are low.

[0095] In one embodiment, the capacitance value of the residual voltage sampling unit 141 is equal to one-third of the capacitance value of the capacitive digital-to-analog conversion circuit 110; the capacitance value of the first integral unit 142 and the capacitance value of the second integral unit 143 are respectively equal to the capacitance value of the capacitive digital-to-analog conversion circuit 110.

[0096] According to the analysis result of the embodiment, Figure 1 It can be known from the analysis result of the embodiment that the noise of the entire analog-to-digital converter can be greatly reduced through the numerical setting of the capacitance value.

[0097] In one embodiment, each residual voltage sampling unit 141 includes a sampling capacitor Cs and a sampling switch S0; the first end of the sampling switch S0 is connected with the target differential output end, the second end of the sampling switch S0 is connected with the first end of the sampling capacitor Cs, the first integral unit 142 and the second integral unit 143 respectively; the second end of the sampling capacitor Cs is connected with the ground end; wherein the target differential output end is the first differential output end or the second differential output end; the control of the residual voltage sampling unit 141 to collect the residual voltage of the current conversion period includes: controlling the sampling switch S0 to be closed, so that the sampling capacitor Cs collects the residual voltage of the current conversion period.

[0098] It can be understood that the number of residual voltage sampling units 141 is two, for the residual voltage sampling unit 141 connected with the first differential output end, the first end of the sampling switch S0 in it is connected with the first differential output end, and for the residual voltage sampling unit 141 connected with the second differential output end, the first end of the sampling switch S0 in it is connected with the second differential output end.

[0099] The timing control of the sampling switch S0 can refer to Figure 4 which can be closed after the multi-input comparator 120 completes the comparison of each bit data of the capacitive digital-to-analog conversion circuit 110 (taking 6 bits as an example in the figure) to generate the next clock cycle of the residual voltage of the current conversion period. In addition, Figure 4 wherein EN is an enable signal controlled by the timing, CLK is a reference clock signal, and CLK_COMP is a clock signal for driving the multi-input comparator 120 to compare.

[0100] The charging of the sampling capacitor Cs can be achieved by controlling the closing of the sampling switch S0, that is, the charging of the residual sampling unit 141. The residual sampling unit 141 has a simple structure and is easy to control.

[0101] In one embodiment, the first integration unit 142 includes a first switch S1 and a first integration capacitor C1, and the second integration unit 143 includes a second switch S2 and a second integration capacitor C2. The first end of the first switch S1 and the first end of the second switch S2 are respectively connected to the first end of the sampling capacitor Cs. The second end of the first switch S1 and the first end of the first integration capacitor C1 are respectively connected to the multi-input comparator 120. The second end of the first integration capacitor C1 is connected to the ground. The second end of the second switch S2 and the first end of the second integration capacitor C2 are respectively connected to the multi-input comparator 120. The second end of the second integration capacitor C2 is connected to the ground. The charging of the first integration unit 142 and the second integration unit 143 based on the residual voltage of the current conversion period in sequence includes: opening the sampling switch S0 and closing the first switch S1 to charge the first integration capacitor C1 by the sampling capacitor Cs; opening the first switch S1 and closing the second switch S2 to charge the second integration capacitor C2 by the sampling capacitor Cs after discharging.

[0102] It can be understood that after the residual voltage is collected by closing the sampling switch S0, the sampling switch S0 is first opened and the first switch S1 is closed to charge the first integration capacitor C1 by the sampling capacitor Cs. The control timing of the first switch S1 can refer to Figure 4 which can be located in the next clock cycle after the sampling switch S0 is opened. After the first integration capacitor C1 is fully charged, the first switch S1 is opened and the second switch S2 is closed to charge the second integration capacitor C2 by the sampling capacitor Cs after discharging the first integration capacitor C1. The control timing of the second switch S2 can refer to Figure 4 which can be located in the next clock cycle after the first switch S1 is opened.

[0103] In one embodiment, the analog-to-digital converter further comprises a third switch S3, a first end of the third switch S3 is connected with the residual error sampling unit 141, a second end of the third switch S3 is connected with the ground, and the noise shaping method further comprises: before controlling the residual error sampling unit 141 to collect the residual error voltage of the current conversion period, controlling the third switch S3 to be closed, so that the residual error sampling unit 141 is discharged.

[0104] It can be understood that, before controlling the residual error sampling unit 141 to collect the residual error voltage of the current conversion period, the third switch S3 is closed to discharge the sampling capacitor Cs, so that the sampling capacitor Cs does not retain the residual error voltage of the last conversion period, thereby affecting the integral voltage of the current conversion period.

[0105] In one embodiment, the control of the capacitor type digital-to-analog conversion circuit 110 to perform voltage sampling of the current conversion period comprises: controlling the capacitor type digital-to-analog conversion circuit 110 to perform voltage sampling of the current conversion period at the end of charging of the first integral unit in the last conversion period.

[0106] It can be understood that, since the capacitor type digital-to-analog conversion circuit 110 performs voltage sampling at the beginning of each conversion period, and since the voltage sampling process and the integral process of the residual error voltage do not interfere with each other, in order to shorten the overall conversion time, voltage sampling of the next conversion period can be started at the end of charging of the first integral unit 142 using the residual error voltage.

[0107] Specifically, the first switch S1 is used to control charging of the first integral unit 142, the second switch S2 is used to control charging of the second integral unit 143, and the switch Φ s The closing time of the switch Φ s may refer to the t1 time point shown in FIG. 1, that is, the end of charging of the first integral unit 142. In this way, the capacitor type digital-to-analog conversion circuit 110 has completed voltage sampling of the next conversion period at the end of charging of the second integral unit 143, thereby saving the overall conversion time of the analog-to-digital converter. Figure 4

[0108] The embodiment of the present application further provides a noise shaping device, comprising a memory and a processor, the memory stores a computer program, and the processor implements the steps of the method of any of the above embodiments when executing the computer program.

[0109] The embodiment of the present application further provides a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement the steps of any of the above embodiments.

[0110] The entire process of the noise shaping method is briefly described below.

[0111] As​Figure 5 As shown, at the beginning of the conversion cycle, the SAR logic control circuit is first driven according to the conversion result of the last conversion cycle to control the capacitor type digital-to-analog conversion circuit 110 to perform voltage sampling, which realizes the common-mode voltage and the to-be-measured voltage V in and V ip The capacitor matrix is charged, and then the switch Φ s is opened after the sampling is completed. By adjusting each switch in the capacitor array, the output voltage of the capacitor type digital-to-analog conversion circuit 110 is adjusted, so that the output voltage gradually approaches the to-be-measured voltage in each displacement process, until the displacement ends to generate the residual voltage of the current conversion cycle. During the displacement, the multi-input comparator outputs according to the current output voltage and the integral voltage of the last conversion cycle, and then drives the SAR logic control circuit to control the displacement of the next bit, until the displacement of the current conversion cycle is completed. The multi-input comparator 120 outputs according to the output voltage of the capacitor type digital-to-analog conversion circuit 110 and the integral voltage of the last conversion cycle output by the passive loop filter circuit 140, and the conversion result of the current conversion cycle can be obtained. After receiving the conversion result of the current conversion cycle, the next conversion cycle is started, and so on. Then enter the residual error integration stage. After obtaining the residual error voltage, the sampling switch S0 is closed, so that the sampling capacitor Cs samples the residual error voltage. Then the sampling switch S0 is opened, and the first switch S1 is closed, so that the sampling capacitor Cs discharges to the first integral capacitor C1 to charge the first integral capacitor C1. After the charging is completed, the first switch S1 is opened and the second switch S2 is closed, so that the discharged sampling capacitor Cs charges the second integral capacitor C2. In this way, the integral voltage of the current conversion cycle, that is, the charging voltage on the first integral capacitor C1 and the second integral capacitor C2, can be obtained.

[0112] It should be understood that, unless otherwise explicitly stated herein, the execution of the above method steps is not strictly limited in sequence, and these steps can be executed in other sequences. Moreover, at least a part of the steps can include multiple steps or multiple stages, which do not necessarily be executed at the same time, but can be executed at different times, and the execution sequence of these steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least a part of other steps or steps or stages in other steps.

[0113] In one embodiment, a computer device is provided, which can be a terminal device, and its internal structure diagram can be as shown in Figure 6As shown in the figure. The computer device includes a processor, a memory, a communication interface, a display screen and an input device connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operating system and the computer program in the non-volatile storage medium to run. The communication interface of the computer device is used to communicate with external terminals in a wired or wireless manner. Wireless mode can be achieved through WIFI, operator network, NFC (near field communication) or other technologies. The computer program is executed by the processor to implement a computer method. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen. The input device of the computer device can be a touch layer overlaid on the display screen, or a key, trackball or touchpad arranged on the shell of the computer device, or an external keyboard, touchpad or mouse, etc.

[0114] Those skilled in the art can understand that, Figure 6 The structure shown in the figure is only a block diagram of part of the structure related to the scheme of the present application, and does not constitute a limitation on the noise shaping device to which the scheme of the present application is applied. The specific noise shaping device can include more or fewer components than those shown in the figure, or combine certain components, or have a different component arrangement.

[0115] In one embodiment, a noise shaping device is provided, including a memory and a processor, the memory stores a computer program, and the processor executes the computer program to implement the steps of the above method embodiments.

[0116] In one embodiment, a computer readable storage medium is provided, which stores a computer program. The computer program is executed by the processor to implement the steps of the above method embodiments.

[0117] In one embodiment, a computer program product or computer program is provided, which includes computer instructions stored in a computer readable storage medium. The processor of the computer device reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions to make the computer device execute the steps in the above method embodiments.

[0118] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer readable storage medium, and when executed, can include the processes in the above-mentioned embodiments of each method. Any reference to memory, storage, database or other medium used in each embodiment provided by the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory or optical memory, etc. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration but not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc.

[0119] The above only describes the preferred embodiments of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation using the content of the specification and drawings, or direct or indirect application in other related technical fields, is also included in the patent protection scope of the present application.

Claims

1. A second order passive noise-shaping successive approximation analog-to-digital converter, characterized by, The capacitor type digital-to-analog conversion circuit, the multi-input comparator, the SAR logic control circuit, two sets of passive loop filter circuits and a timing control circuit are included. The capacitor type digital-to-analog conversion circuit is connected with the SAR logic control circuit, a first differential output end of the capacitor type digital-to-analog conversion circuit is connected with a first input end of the multi-input comparator, and a second differential output end of the capacitor type digital-to-analog conversion circuit is connected with a second input end of the multi-input comparator. Each passive loop filter circuit includes a residual error sampling unit, a first integration unit and a second integration unit, each residual error sampling unit is connected with the first differential output end and the second differential output end one by one, and the first integration unit and the second integration unit are connected with the residual error sampling unit in the same group and the multi-input comparator. The timing control circuit is connected with the SAR logic control circuit, the multi-input comparator and each passive loop filter circuit, and is used to drive the SAR logic control circuit according to a conversion result of a previous conversion period, to control the capacitor type digital-to-analog conversion circuit to perform voltage sampling in a current conversion period, and to generate an output voltage which gradually approximates a voltage to be measured based on the sampled voltage, until a residual error voltage in the current conversion period is generated. The multi-input comparator is used to perform conversion output according to the output voltage of the capacitor type digital-to-analog conversion circuit and the integral voltage of the previous conversion period output by the passive loop filter circuit, to obtain the conversion result in the current conversion period. The timing control circuit is also used to control the residual error sampling unit to collect the residual error voltage in the current conversion period, and to charge the first integration unit and the second integration unit based on the residual error voltage in the current conversion period, to obtain the integral voltage in the current conversion period, for conversion output in a next conversion period.

2. The second-order passive noise-shaping successive approximation analog-to-digital converter of claim 1, wherein, The capacitance value of the residual error sampling unit is equal to one third of the capacitance value of the capacitor type digital-to-analog conversion circuit, and the capacitance value of the first integration unit and the capacitance value of the second integration unit are equal to the capacitance value of the capacitor type digital-to-analog conversion circuit.

3. The second-order passive noise-shaping successive approximation analog-to-digital converter of claim 1, wherein, Each residual error sampling unit includes a sampling capacitor and a sampling switch, a first end of the sampling switch is connected with a target differential output end, a second end of the sampling switch is connected with a first end of the sampling capacitor, the first integration unit and the second integration unit, a second end of the sampling capacitor is connected with a ground end, and the target differential output end is the first differential output end or the second differential output end.

4. The second-order passive noise-shaping successive approximation analog-to-digital converter of claim 3, wherein, The first integration unit comprises a first switch and a first integration capacitor; the second integration unit comprises a second switch and a second integration capacitor; a first end of the first switch and a first end of the second switch are connected with a first end of the sampling capacitor respectively; a second end of the first switch and a first end of the first integration capacitor are connected with the multi-input comparator respectively; a second end of the first integration capacitor is connected with the ground end; a second end of the second switch and a first end of the second integration capacitor are connected with the multi-input comparator respectively; and a second end of the second integration capacitor is connected with the ground end.

5. The second-order passive noise-shaping successive approximation analog-to-digital converter of claim 1, wherein, The analog-to-digital converter further comprises a third switch; a first end of the third switch is connected with the residual error sampling unit, a second end of the third switch is connected with the ground end; and the timing control circuit is further configured to control the third switch to be closed before controlling the residual error sampling unit to collect the residual error voltage of the current conversion period, so that the residual error sampling unit is discharged.

6. The second-order passive noise-shaping successive approximation analog-to-digital converter of claim 1, wherein, The timing control circuit controls the capacitor type digital-to-analog conversion circuit to perform voltage sampling of the current conversion period at the end of charging of the first integration unit in the previous conversion period.

7. A noise shaping method, characterized by, The application is applied to a second-order passive noise shaping successive approximation register (SAR) analog-to-digital converter, which comprises a capacitor type digital-to-analog conversion circuit, a multi-input comparator, a SAR logic control circuit and two groups of passive loop filter circuits; the capacitor type digital-to-analog conversion circuit is connected with the SAR logic control circuit; a first differential output end of the capacitor type digital-to-analog conversion circuit is connected with a first input end of the multi-input comparator; and a second differential output end of the capacitor type digital-to-analog conversion circuit is connected with a second input end of the multi-input comparator; each passive loop filter circuit comprises a residual error sampling unit, a first integration unit and a second integration unit; each residual error sampling unit is connected with the first differential output end and the second differential output end one by one; the first integration unit and the second integration unit are connected with the residual error sampling unit in the same group and connected with the multi-input comparator; The noise shaping method comprises the following steps: driving the SAR logic control circuit according to a conversion result of a previous conversion period, so as to control the capacitor type digital-to-analog conversion circuit to perform voltage sampling of a current conversion period, and generating an output voltage of a successive approximation voltage based on the sampled voltage, until a residual error voltage of the current conversion period is generated; The multi-input comparator is configured to perform conversion output according to an output voltage of the capacitor type digital-to-analog conversion circuit and an integration voltage of the previous conversion period output by the passive loop filter circuit, so as to obtain a conversion result of the current conversion period; The noise shaping method further comprises the following steps: controlling the residual error sampling unit to collect the residual error voltage of the current conversion period, and charging the first integration unit and the second integration unit based on the residual error voltage of the current conversion period in sequence, so as to obtain an integration voltage of the current conversion period, which is used for conversion output of a next conversion period.

8. The noise shaping method of claim 7, wherein, The capacitance value of the residual error sampling unit is equal to one third of the capacitance value of the capacitive digital-to-analog conversion circuit; the capacitance value of the first integration unit and the capacitance value of the second integration unit are respectively equal to the capacitance value of the capacitive digital-to-analog conversion circuit.

9. The noise shaping method of claim 7, wherein, Each of the residual error sampling units comprises a sampling capacitor and a sampling switch; a first end of the sampling switch is connected with a target differential output end, a second end of the sampling switch is connected with a first end of the sampling capacitor, the first integration unit and the second integration unit respectively; a second end of the sampling capacitor is connected with a ground end; wherein the target differential output end is the first differential output end or the second differential output end; the control of the residual error sampling unit to collect the residual error voltage of the current conversion period comprises: controlling the sampling switch to be closed, so that the sampling capacitor collects the residual error voltage of the current conversion period.

10. The noise shaping method of claim 9, wherein, The first integration unit comprises a first switch and a first integration capacitor; the second integration unit comprises a second switch and a second integration capacitor; a first end of the first switch and a first end of the second switch are connected with the first end of the sampling capacitor respectively; a second end of the first switch and a first end of the first integration capacitor are connected with the multi-input comparator respectively; a second end of the first integration capacitor is connected with the ground end; a second end of the second switch and a first end of the second integration capacitor are connected with the multi-input comparator respectively; a second end of the second integration capacitor is connected with the ground end; The charging of the first integration unit and the second integration unit based on the residual error voltage of the current conversion period comprises: opening the sampling switch and closing the first switch, so that the sampling capacitor charges the first integration capacitor; opening the first switch and closing the second switch, so that the discharged sampling capacitor charges the second integration capacitor.

11. The noise shaping method of claim 7, wherein, The analog-to-digital converter further comprises a third switch; a first end of the third switch is connected with the residual error sampling unit, a second end of the third switch is connected with the ground end, and the noise shaping method further comprises: before controlling the residual error sampling unit to collect the residual error voltage of the current conversion period, controlling the third switch to be closed, so that the residual error sampling unit is discharged.

12. The noise shaping method of claim 7, wherein, The control of the capacitive digital-to-analog conversion circuit to perform voltage sampling of the current conversion period comprises: controlling the capacitive digital-to-analog conversion circuit to perform voltage sampling of the current conversion period at the end of charging of the first integration unit in the last conversion period.

13. A noise shaping device comprising a memory and a processor, the memory storing a computer program, characterized in that, The processor executes the computer program to realize the steps of the method in any one of claims 7 to 12.

14. A computer readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to realize the steps of the method in any one of claims 7 to 12.

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