Preparation method of semiconductor structure and semiconductor structure

Abstract

The invention relates to a preparation method of a semiconductor structure and the semiconductor structure. The preparation method of the semiconductor structure comprises the steps of providing a substrate; forming a laminated structure on the substrate, wherein the laminated structure comprises a dielectric layer and a conductive layer which are sequentially laminated from bottom to top; forming a continuously distributed first covering layer on the surface of each first end part; removing the second filling layer in a gap region between the first end parts to form a second groove, and exposing the first covering layers and the channel material layers which are sequentially and alternately arranged along the second direction on the side wall of the second groove; and removing the channel material layers exposed by the side wall of the second groove to form channel layers, and enabling the channel layers to be in one-to-one correspondence contact with the second end parts of the channel layers. The channel material layer in contact with each dielectric layer is removed, and the channel material layer in contact with each conductive layer is reserved to form the channel layer, so that the device can be prevented from generating a parasitic transistor, and the performance of the device can be prevented from being reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure and a semiconductor structure. Background Art

[0002] With the development of semiconductor technology, the storage density of memory is getting higher and higher. However, as the feature size gets closer and closer to the theoretical limit, memory based on metal oxide semiconductor materials is expected to achieve high-density storage, which is a possible development direction for the next generation of memory. However, memory still faces many difficult challenges, such as the problem of parasitic transistors. In related technologies, metal oxide semiconductors are also deposited on the surface of each dielectric layer that acts as an insulator, which can cause the upper and lower layers of devices to be connected through the metal oxide semiconductor in the dielectric layer, thereby generating parasitic transistors, which can cause device performance to deteriorate. Summary of the invention

[0003] Based on this, it is necessary to provide a method for preparing a semiconductor structure and a semiconductor structure to address the parasitic transistor problem in the related art.

[0004] In a first aspect, the present invention provides a method for preparing a semiconductor structure, comprising:

[0005] providing a substrate;

[0006] A stacked structure is formed on the substrate, the stacked structure comprising dielectric layers and conductive layers stacked in sequence from bottom to top; each conductive layer comprises a main body extending along a first direction and a plurality of branch parts located on both sides of the main body, a gap region is provided between each branch part, each branch part and each spacing region are alternately arranged along the first direction, a first end of each branch part is connected to the main body, and a second end of each branch part is arranged away from the main body; each gap region is filled with a second filling layer;

[0007] forming a first covering layer distributed continuously on the surface of each of the first end portions;

[0008] Removing part of the stacked structure to form a first groove penetrating the first end of each layer along a second direction; the first direction intersects the second direction;

[0009] Depositing a channel material layer and an isolation layer on the inner wall of the first trench in sequence, and filling the first trench with a gate conductive layer;

[0010] Removing the second filling layer in the gap region between the first end portions to form a second trench, wherein the sidewalls of the second trench expose the first covering layers and the channel material layers alternately arranged in sequence along the second direction;

[0011] Each layer of the channel material layer exposed by the sidewall of the second trench is removed to form a channel layer, and each layer of the channel layer is in one-to-one contact with the second end of each layer.

[0012] The method for preparing the semiconductor structure comprises: providing a substrate; forming a stacked structure on the substrate, the stacked structure comprising a dielectric layer and a conductive layer stacked in sequence from bottom to top; each conductive layer comprises a main body extending along a first direction and a plurality of branch parts located on both sides of the main body, each branch part also has a gap region between them, each branch part and each gap region are alternately arranged along the first direction, a first end of each branch part is connected to the main body, and a second end of each branch part is arranged away from the main body; each gap region is filled with a second filling layer; a first covering layer is formed on the surface of each first end portion; removing Part of the stacked structure is formed to form a first groove that penetrates the first end of each layer along the second direction; the first direction intersects with the second direction; a channel material layer and an isolation layer are sequentially deposited on the inner wall of the first groove, and a gate conductive layer is filled in the first groove; the second filling layer located in the gap area between each first end is removed to form a second groove, and the sidewall of the second groove exposes the first covering layer and the channel material layer that are alternately arranged in sequence along the second direction; each layer of the channel material layer exposed by the sidewall of the second groove is removed to form a channel layer, and each layer of the channel layer is in one-to-one contact with the second end of each layer. Since the channel material layer in contact with each layer of the dielectric layer is removed, and the channel material layer in contact with each layer of the conductive layer is retained to form the channel layer, the device can be prevented from generating parasitic transistors, thereby preventing the performance of the device from being reduced.

[0013] In one embodiment, forming a continuously distributed first covering layer on the surface of each of the first ends includes:

[0014] Removing the first filling layer in the gap region between the first end portions to form a third groove penetrating the first filling layer along the second direction, wherein the sidewalls of the third groove expose the side surfaces of the dielectric layer and the side surfaces of the first end portions which are alternately arranged in sequence along the second direction;

[0015] removing each layer of the dielectric layer based on the third trench;

[0016] The first covering layer is formed on the inner wall of the third groove and the surface of the first end portion of each layer.

[0017] In one embodiment, the selective removal of each dielectric layer based on the third trench includes:

[0018] The third trench is laterally etched by a wet etching process to selectively remove each dielectric layer to form a fourth trench, wherein the fourth trench exposes surfaces of each layer opposite to the first end portion along the second direction.

[0019] In one embodiment, after forming the first covering layer on the inner wall of the third groove and the surface of the first end of each layer, the method further includes:

[0020] The second filling layer is filled in the third trench and the fourth trench, and the second filling layer filled in each of the fourth trenches serves as the dielectric layer between the first end portions of each layer.

[0021] In one embodiment, forming the first covering layer on the inner wall of the third groove and the surface of the first end of each layer includes:

[0022] An atomic layer deposition process is used to form the first covering layer which is continuously distributed on the inner wall of the third groove and the surface of the first end of each layer.

[0023] In one embodiment, forming a stacked structure on the substrate includes:

[0024] forming an initial stacked structure on the substrate, wherein the initial stacked structure comprises a dielectric layer and a conductive layer stacked sequentially from bottom to top;

[0025] forming a patterned hard mask layer on the initial stacked structure;

[0026] The initial stacked structure is etched based on the patterned hard mask layer to form the stacked structure.

[0027] In one embodiment, the patterned hard mask layer includes a plurality of opening patterns, and the position of each of the opening patterns corresponds to the position of each of the first ends; before etching the initial stacked structure based on the patterned hard mask layer, the method further includes:

[0028] Depositing a sacrificial material layer, wherein the sacrificial material layer covers the surface of the initial stacked structure and the surface of the patterned hard mask layer and fills the opening pattern;

[0029] The sacrificial material layer located on the surface of the initial stacked structure and the surface of the patterned hard mask layer is removed to obtain a sacrificial layer retained in the opening pattern.

[0030] In one embodiment, removing part of the stacked structure to form a first groove penetrating the first end of each layer along the second direction includes:

[0031] removing the sacrificial layer filled in the opening pattern so that the opening pattern exposes the surface of the stacked structure;

[0032] The stacked structure is etched based on the opening pattern to form the first trench.

[0033] In one embodiment, after forming the stacked structure on the substrate and before forming a continuously distributed first covering layer on the surface of each of the first end portions, the method further includes:

[0034] removing the first filling layer and the dielectric layer in contact with the surface of the second end;

[0035] A capacitor isolation layer and a capacitor plate layer are sequentially formed on the surface of the second end portion.

[0036] In one embodiment, removing the first filling layer and the dielectric layer in contact with the surface of the second end portion includes:

[0037] removing the first filling layer in the gap region between the second end portions to form a fifth groove;

[0038] The dielectric layers are laterally etched based on the fifth trench to form a sixth trench located between the second ends of the layers.

[0039] In one embodiment, the capacitor isolation layer and the capacitor plate layer are sequentially formed on the surface of the second end, including:

[0040] forming a continuously distributed capacitor isolation layer on the inner wall of the fifth groove and the inner wall of the sixth groove, wherein the capacitor isolation layer covers the surface of the second end portion;

[0041] A capacitor plate layer is filled in the fifth trench and the sixth trench, and the capacitor plate layer is in contact with the capacitor isolation layer.

[0042] In a second aspect, the present invention further provides a semiconductor structure, comprising: a substrate; a stacked structure located on the substrate, the stacked structure comprising a dielectric layer and a conductive layer stacked in sequence from bottom to top; each layer of the conductive layer comprises a main body extending along a first direction and a plurality of branch parts located on both sides of the main body, and a gap region is provided between each of the branch parts, each of the branch parts and each of the gap regions are alternately arranged along the first direction, a first end of each of the branch parts is connected to the main body, and a second end of each of the branch parts is arranged away from the main body; each of the gap regions is filled with a first filling layer; a first covering layer covers the side surfaces of the first end of each layer opposite to each other along the first direction; a device structure penetrates the first end of each layer along a second direction, the second direction intersecting with the first direction; the device structure comprises a gate conductive layer extending along the second direction, a multi-layer isolation layer surrounding the side wall of the gate conductive layer and arranged at intervals along the second direction, and a multi-layer channel layer correspondingly covering the surface of the isolation layer, and each of the channel layers is in contact with the second end of each layer. Since the channel material layer in contact with each dielectric layer is removed and the channel material layer in contact with each conductive layer is retained to form a channel layer, the device can be prevented from generating parasitic transistors, thereby preventing the performance of the device from being degraded.

[0043] In one embodiment, the semiconductor structure also includes a capacitor, which includes a first electrode, a capacitor isolation layer and a second electrode, the second end serves as the first electrode of the capacitor, the capacitor isolation layer covers the surface of the first electrode, and the surface of the capacitor isolation layer is covered with a capacitor plate layer, and the capacitor plate layer serves as the second electrode of the capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0045] Figure 1 is a flow chart of a method for preparing a semiconductor structure provided in an embodiment;

[0046] Figure 2 is a flowchart of step S20 in a method for preparing a semiconductor structure provided in an embodiment;

[0047] Figure 3 A schematic diagram of a 3D structure of a structure obtained in step S201 in a method for preparing a semiconductor structure provided in an embodiment;

[0048] Figure 4 A schematic diagram of a top view of a structure obtained in step S201 of a method for preparing a semiconductor structure provided in an embodiment;

[0049] Figure 5 A schematic diagram of a 3D structure of a structure obtained in step S202 in a method for preparing a semiconductor structure provided in an embodiment;

[0050] Figure 6 A schematic diagram of a top view of a structure obtained in step S202 of a method for preparing a semiconductor structure provided in an embodiment;

[0051] Figure 7 A schematic diagram of a 3D structure of a structure obtained in step S203 in a method for preparing a semiconductor structure provided in an embodiment;

[0052] Figure 8 A schematic diagram of a top view of a structure obtained in step S203 of a method for preparing a semiconductor structure provided in an embodiment;

[0053] Fig. 9 A flowchart of the steps of forming a sacrificial layer in a method for preparing a semiconductor structure provided in an embodiment;

[0054] Fig.10 A schematic diagram of a 3D structure of a structure obtained after a sacrificial layer is formed in a method for preparing a semiconductor structure provided in an embodiment;

[0055] Fig.11 A schematic diagram of a top view of a structure obtained after a sacrificial layer is formed in a method for preparing a semiconductor structure provided in an embodiment;

[0056] Fig.12 A schematic diagram of a 3D structure of a structure obtained after forming a patterned hard mask layer in a method for preparing a semiconductor structure provided in another embodiment;

[0057] Fig.13 A schematic top view of a structure obtained after forming a patterned hard mask layer in a method for preparing a semiconductor structure provided in another embodiment;

[0058] Fig.14 A schematic diagram of a 3D structure of a structure obtained after forming a first filling layer in a method for preparing a semiconductor structure provided in an embodiment;

[0059] Fig.15 A schematic diagram of a top view of a structure obtained after forming a first filling layer in a method for preparing a semiconductor structure provided in an embodiment;

[0060] Fig.16 A schematic diagram of a 3D structure of a structure obtained after a frame is formed in a method for preparing a semiconductor structure provided in an embodiment;

[0061] Fig.17 A schematic diagram of a top view of a structure obtained after a frame is formed in a method for preparing a semiconductor structure provided in an embodiment;

[0062] Fig.18 A flowchart of steps for forming a capacitor in a method for preparing a semiconductor structure provided in an embodiment;

[0063] Fig.19 A schematic diagram of a 3D structure of a structure obtained in step S21 of a method for preparing a semiconductor structure provided in an embodiment;

[0064] Fig. 20 A schematic diagram of a top view of a structure obtained in step S21 of a method for preparing a semiconductor structure provided in an embodiment;

[0065] Fig.21 A schematic diagram of a 3D structure of a structure obtained in step S22 of a method for preparing a semiconductor structure provided in an embodiment;

[0066] Fig. 22 A schematic diagram of a top view of a structure obtained in step S22 of a method for preparing a semiconductor structure provided in an embodiment;

[0067] Fig.23 is a flowchart of step S30 in a method for preparing a semiconductor structure provided in an embodiment;

[0068] Fig.24 A schematic diagram of a 3D structure of a structure obtained in step S302 in a method for preparing a semiconductor structure provided in an embodiment;

[0069] Fig.25 A schematic diagram of a top view of a structure obtained in step S302 of a method for preparing a semiconductor structure provided in an embodiment;

[0070] Fig.26 A schematic diagram of a 3D structure of a structure obtained in step S303 in a method for preparing a semiconductor structure provided in an embodiment;

[0071] Fig. 27 A schematic diagram of a top view of a structure obtained in step S303 of a method for preparing a semiconductor structure provided in an embodiment;

[0072] Fig.28 A schematic diagram of a 3D structure of a structure obtained in step S40 in a method for preparing a semiconductor structure provided in an embodiment;

[0073] Fig.29 A schematic diagram of a top view of a structure obtained in step S40 in a method for preparing a semiconductor structure provided in an embodiment;

[0074] Fig.30 A schematic diagram of a 3D structure of a structure obtained in step S50 in a method for preparing a semiconductor structure provided in an embodiment;

[0075] Fig.31 A schematic diagram of a top view of a structure obtained in step S50 in a method for preparing a semiconductor structure provided in an embodiment;

[0076] Fig.32 A schematic diagram of a 3D structure of a structure obtained in step S60 in a method for preparing a semiconductor structure provided in an embodiment;

[0077] Fig.33 A schematic diagram of a top view of a structure obtained in step S60 in a method for preparing a semiconductor structure provided in an embodiment;

[0078] Fig.34 A schematic diagram of a 3D structure of a structure obtained in step S70 in a method for preparing a semiconductor structure provided in an embodiment;

[0079] Fig.35 A schematic diagram of a top view of a structure obtained in step S70 in a method for preparing a semiconductor structure provided in an embodiment;

[0080] Fig.36 A schematic diagram of a 3D structure of a structure obtained after forming a third filling layer in a method for preparing a semiconductor structure provided in an embodiment;

[0081] Fig.37 It is a schematic diagram of a top view of a structure obtained after forming a third filling layer in a method for preparing a semiconductor structure provided in an embodiment.

[0082] Explanation of the reference numerals: 10-substrate, 101-first groove, 102-second groove, 20-dielectric layer, 30-conductive layer, 301-main body, 302-branch, 3021-first end, 3022-second end, 40-patterned hard mask layer, 401-opening pattern, 402-sacrificial layer, 403-second filling layer, 404-third filling layer, 50-first filling layer, 60-frame, 701-capacitor isolation layer, 702-capacitor plate layer, 801-first covering layer, 901-channel material layer, 902-isolation layer, 903-gate conductive layer, 904-channel layer. DETAILED DESCRIPTION

[0083] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0084] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0085] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0086] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0087] When used herein, the singular forms "a", "an" and " / the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0088] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of preferred embodiments of the invention (and intermediate structures), so that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.

[0089] See also Figure 1 The present invention provides a method for preparing a semiconductor structure, comprising the following steps:

[0090] S10: providing a substrate;

[0091] S20: forming a stacked structure on the substrate, the stacked structure comprising dielectric layers and conductive layers stacked in sequence from bottom to top; each conductive layer comprises a main body extending along a first direction and a plurality of branch parts located on both sides of the main body, each branch part further comprises a gap region, each branch part and each gap region are alternately arranged along the first direction, a first end of each branch part is connected to the main body, and a second end of each branch part is arranged away from the main body; each gap region is filled with a second filling layer;

[0092] S30: forming a continuously distributed first covering layer on the surface of each first end portion;

[0093] S40: removing part of the stacked structure to form a first groove penetrating the first end of each layer along the second direction, wherein the inner sidewall of the first groove exposes the side surface of the first filling layer; the first direction intersects with the second direction;

[0094] S50: depositing a channel material layer and an isolation layer in sequence on the inner wall of the first trench, and filling a gate conductive layer in the first trench;

[0095] S60: removing the second filling layer in the gap region between the first end portions to form a second trench, wherein the sidewalls of the second trench expose the first covering layer and the channel material layer alternately arranged in sequence along the second direction;

[0096] S70: removing each channel material layer exposed by the sidewall of the second trench to form a channel layer, wherein each channel layer is in one-to-one contact with each second end portion of the layer.

[0097] The semiconductor structure obtained after steps S10-S70 can be referred to Figure 33-Figure 34 .certainly, Figure 33-Figure 34 What is given is an example of a semiconductor structure prepared by the method for preparing a semiconductor structure of the present invention. There may be other suitable examples of a semiconductor structure prepared by the method for preparing a semiconductor structure of the present invention, and the present invention is not limited thereto.

[0098] In addition, to facilitate understanding of the present solution, the first direction involved in the present invention may be the X direction in the drawings, the second direction may be the Y direction in the drawings, and the third direction may be the Z direction in the drawings. Of course, in other suitable application scenarios, the first direction, the second direction, and the third direction may have other definitions, which are not limited here.

[0099] The method for preparing the semiconductor structure comprises: providing a substrate; forming a stacked structure on the substrate, the stacked structure comprising a dielectric layer and a conductive layer stacked in sequence from bottom to top; each conductive layer comprises a main body extending along a first direction and a plurality of branch parts located on both sides of the main body, each branch part also has a gap region, each branch part and each gap region are alternately arranged along the first direction, a first end of each branch part is connected to the main body, and a second end of each branch part is arranged away from the main body; each gap region is filled with a second filling layer; a first covering layer continuously distributed is formed on the surface of each first end ; remove part of the stacked structure to form a first groove that runs through the first end of each layer along the second direction; the first direction intersects with the second direction; deposit a channel material layer and an isolation layer on the inner wall of the first groove in sequence, and fill the gate conductive layer in the first groove; remove the second filling layer located in the gap area between the first ends to form a second groove, and the sidewall of the second groove exposes the first covering layer and the channel material layer that are alternately arranged in sequence along the second direction; remove the channel material layers exposed by the sidewall of the second groove to form a channel layer, and each channel layer is in one-to-one contact with the second end of each layer. Since the channel material layers in contact with each dielectric layer are removed, and the channel material layers in contact with each conductive layer are retained to form the channel layer, the device can be prevented from generating parasitic transistors, thereby preventing the performance of the device from being degraded.

[0100] like Figure 3-Figure 4As shown, in step S10 , a substrate 10 is provided.

[0101] The material of the substrate 10 may be any suitable substrate material known in the art, for example, at least one of the following materials: silicon (Si), germanium (Ge), red phosphorus, silicon germanium (SiGe), silicon carbide (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or double-sided polished silicon wafers (Double Side Polished Wafers, DSP), or ceramic substrates such as alumina, quartz or glass substrates, etc., which are not limited in this embodiment.

[0102] like Figure 7-Figure 8 As shown, in step S20, a stacked structure is formed on the substrate 10, and the stacked structure includes a dielectric layer 20 and a conductive layer 30 stacked sequentially from bottom to top.

[0103] Among them, each layer of the conductive layer 30 includes a main body 301 extending along the first direction and a plurality of branch parts 302 located on both sides of the main body 301, and there is also a gap area between each branch part 302. Each branch part 302 and each spacing area are alternately arranged along the first direction, and the first end 3021 of each branch part 302 is connected to the main body 301, and the second end 3022 of each branch part 302 is arranged away from the main body 301; each gap area is filled with a first filling layer 50.

[0104] In one embodiment, Figure 2 As shown, the above step S20 includes:

[0105] S201 : forming an initial stacked structure on a substrate 10 , wherein the initial stacked structure includes a dielectric layer 20 and a conductive layer 30 stacked sequentially from bottom to top.

[0106] like Figure 3-Figure 4 As shown, a plurality of dielectric layers 20 and conductive layers 30 may be deposited by using a deposition process for multiple times to form an initial stacked structure that is alternately stacked.

[0107] The material of the dielectric layer 20 may include any suitable dielectric material, such as an oxide material or a nitride material. Further, the oxide material may include at least one of silicon oxide, silicon oxynitride, silicon oxycarbide and silicon oxynitride and carbonitride; the nitride material may include silicon nitride, etc.

[0108] The material of the conductive layer 30 may include conductive materials, for example, metal materials such as tungsten, copper, gold, titanium, silver, aluminum, etc., or a multilayer metal composed of metals of the above materials, or a metal alloy, etc. The material of the conductive layer 30 may also include titanium nitride, which is not limited in this embodiment.

[0109] S202: forming a patterned hard mask layer 40 on the initial stacked structure.

[0110] like Figure 5-Figure 6 As shown, the pattern of the patterned hard mask layer 40 can be defined by photolithography. Specifically, a hard mask layer can be formed by a deposition process, and then a hard mask layer can be formed by photolithography, exposure, etching and other process steps. Figure 5-Figure 6 A patterned hard mask layer 40 is shown.

[0111] In addition, if Figure 6 As shown, the shapes and positions of the main body 301 and the branch 302 included in each conductive layer 30, and the first end 3021 and the second end 3022 included in the branch 302 can be defined by the patterned hard mask layer 40. Therefore, it should be noted that in Figure 6 The main body 301, the branch 302, and the first end 3021 and the second end 3022 of the branch 302 shown in the figure substantially correspond to the main body 301, the branch 302, and the first end 3021 and the second end 3022 of the branch 302 included in each conductive layer 30 located below the patterned hard mask layer 40. This is also reflected in other drawings of the present invention.

[0112] S203: etching the initial stacked structure based on the patterned hard mask layer 40 to form a stacked structure, such as Figure 7-Figure 8 shown.

[0113] In one embodiment, Figure 5-Figure 6 As shown, the patterned hard mask layer 40 includes a plurality of opening patterns 401, and the position of each opening pattern 401 corresponds to the position of each first end 3021. Fig. 9 As shown, before step S203, the method for preparing the semiconductor structure further includes:

[0114] S2021 : depositing a sacrificial material layer, the sacrificial material layer covers the surface of the initial stacked structure and the surface of the patterned hard mask layer 40 , and fills the opening pattern 401 .

[0115] The sacrificial material layer may include aluminum oxide. The sacrificial material layer may be deposited by atomic layer deposition. After deposition, the sacrificial material layer not only fills the opening pattern 401 but also covers the surface of the initial stacked structure and the surface of the patterned hard mask layer 40 .

[0116] S2022 : removing the sacrificial material layer located on the surface of the initial stacked structure and the surface of the patterned hard mask layer 40 to obtain a sacrificial layer 402 retained in the opening pattern 401 .

[0117] like Figure 10-11 As shown, the sacrificial material layer may be removed by a wet etching process to obtain a sacrificial layer 402 retained in the opening pattern 401 . The material of the sacrificial layer 402 may be different from that of the patterned hard mask layer 40 .

[0118] Optionally, after obtaining the sacrificial layer 402, a deposition process can be used to deposit another hard mask material layer on the surface of the obtained structure. The thickness of the hard mask material layer is less than the thickness of the patterned hard mask layer 40. The hard mask material layer can completely cover the surface of the sacrificial layer 402. At the same time, the hard mask material layer will also cover the surface of the stacked structure due to the characteristics of the deposition process. Further, the deposition process can be used to remove the hard mask material layer located on the surface of the stacked structure, so that the hard mask material layer only covers the surface of the sacrificial layer 402, so that the patterned hard mask layer 40 is formed as shown in FIG. Figure 12-13 The structure of the integrated patterned hard mask layer 40 is shown. Fig.12 and Fig.10 It can be seen that Fig.12 The patterned hard mask layer 40 is substantially formed in Fig.10 After a hard mask material layer with a smaller thickness is formed on the surface of the patterned hard mask layer 40, Fig.12 The patterned hard mask layer 40 in the first end portion 3021 is substantially filled with a sacrificial layer 402. Fig.12 In the following figures (e.g. Fig.14 In order to facilitate the display of the position of the sacrificial layer 402, the sacrificial layer 402 is directly drawn in the drawing. However, it should be understood that in some embodiments, the surface of the sacrificial layer 402 can actually be completely covered by the hard mask material layer.

[0119] Optionally, after forming the sacrificial layer 402, a step of filling the gap region between the branches 302 with a first filling layer 50 may be further included. Figure 14-15 In addition, in some embodiments, the first filling layer 50 and the dielectric layer 20 may be made of the same material, for example, both may be silicon oxide.

[0120] Optionally, after the first filling layer 50 is filled in the gap region, a frame 60 may be formed on both sides of the stacked structure, such as Figure 16-Figure 17Part of the stacked structure can be removed by photolithography and etching, and then a deposition process is used to form the frame 60 . The material of the frame 60 can be different from that of the dielectric layer 20 or the first filling layer 50 .

[0121] After step S20 and before step S30, Fig.18 As shown, the method for preparing the semiconductor structure also includes:

[0122] S21 : removing the first filling layer 50 and the dielectric layer 20 that are in contact with the surface of the second end portion 3022 .

[0123] like Figure 19-20 As shown, a process combining photolithography, dry etching and wet etching can be used to form Figure 19-20 The structure shown is such that the surface of the second end portion 3022 is completely exposed.

[0124] In one embodiment, the above step S21 includes:

[0125] S211 : removing the first filling layer 50 located in the gap region between the second end portions 3022 to form a fifth trench.

[0126] The first filling layer 50 may be removed by photolithography plus dry etching to form a fifth trench along the second direction. In this step, the dielectric layers 20 between the second end portions 3022 have not been removed.

[0127] S212 : etching each dielectric layer 20 laterally based on the fifth trench to form a sixth trench located between the second ends 3022 of each layer.

[0128] A steam etching process or a wet etching process can be used, and the isotropic etching and selective etching characteristics of the steam etching or the wet etching are utilized to directly introduce etching steam or etching liquid into the fifth groove to selectively remove the exposed dielectric layer 20 of each layer, thereby finally forming Figure 19-20 The structure shown is such that the surface of the second end portion 3022 is completely exposed.

[0129] S22 : forming a capacitor isolation layer 701 and a capacitor plate layer 702 in sequence on the surface of the second end portion 3022 .

[0130] like Figure 21-22 As shown, the material of the capacitor isolation layer 701 may include a dielectric material, such as a high-K material. The material of the capacitor plate layer 702 may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta) or other metals.

[0131] In one embodiment, the above step S22 includes:

[0132] S221 : forming a continuously distributed capacitor isolation layer 701 on the inner wall of the fifth trench and the inner wall of the sixth trench, wherein the capacitor isolation layer 701 covers the surface of the second end portion 3022 .

[0133] like Figure 21-22 As shown, the capacitor isolation layer 701 can be deposited on the surface of the second end 3022 by an atomic layer deposition process. The capacitor isolation layer 701 is also distributed on the inner wall of the fifth groove and the inner wall of the sixth groove. The formed capacitor isolation layer 701 is continuously distributed, that is, the capacitor isolation layer 701 is an integrated structure.

[0134] S222 : filling the capacitor plate layer 702 in the fifth trench and the sixth trench, wherein the capacitor plate layer 702 is in contact with the capacitor isolation layer 701 .

[0135] like Figure 21-22 As shown, the deposition process can be used to fill the capacitor plate layer 702 in the fifth groove and the sixth groove. Each second end 3022 and the capacitor isolation layer 701 and the capacitor plate layer 702 covering the surface thereof can form a capacitor, the second end 3022 can be used as the first electrode of the capacitor, the capacitor plate layer 702 can be used as the second electrode of the capacitor, and the first electrode and the second electrode are separated by the capacitor isolation layer 701.

[0136] In addition, since the process of forming the capacitor isolation layer 701 and the capacitor plate layer 702 involves a deposition process, according to the characteristics of the deposition process, the capacitor isolation layer 701 and the capacitor plate layer 702 will also be deposited on the upper surface of the patterned hard mask layer 40 and the upper surface of the stacked structure. Therefore, after forming the capacitor plate layer 702, the excess capacitor isolation layer 701 and the capacitor plate layer 702 can be further removed by a grinding process to obtain the following: Fig. 22 The structure is shown in top view.

[0137] like Figure 26-Figure 27 As shown, in step S30 , a first covering layer 801 is formed on the surface of each first end portion 3021 in a continuously distributed manner.

[0138] In one embodiment, Fig.23 As shown, the above step S30 includes:

[0139] S301: removing the first filling layer 50 located in the gap area between each first end 3021 to form a third groove penetrating the first filling layer 50 along the second direction, and the sidewall of the third groove exposes the side of the dielectric layer 20 and the side of the first end 3021 arranged alternately in sequence along the second direction.

[0140] The third groove may be formed by dry etching, and the anisotropic etching of the dry etching is used to make the third groove penetrate the first filling layer 50 along the second direction. At this time, the dielectric layer 20 located between the first ends 3021 of each layer is not removed due to the protection of the first ends 3021 of each layer, so the sidewall of the third groove will expose the side surfaces of the dielectric layer 20 and the side surfaces of the first ends 3021 that are alternately arranged in sequence along the second direction.

[0141] S302: removing each dielectric layer 20 based on the third trench.

[0142] In one embodiment, Figure 24-25 As shown, the above step S302 includes: performing lateral etching based on the third groove by using a wet etching process to selectively remove each dielectric layer 20 to form a fourth groove, wherein the fourth groove exposes the surface of the first end 3021 of each layer opposite to the second direction. By isotropic etching and selective etching of wet etching, the dielectric layer 20 located between the first end 3021 of each layer is removed to obtain Figure 24-25 The structure shown.

[0143] S303 : forming a first covering layer 801 on the inner wall of the third groove and the surface of the first end portion 3021 of each layer.

[0144] In one embodiment, Figure 26-Figure 27 As shown, an atomic layer deposition process is used to form a continuously distributed first covering layer 801 on the inner wall of the third trench and the surface of the first end portion 3021 of each layer.

[0145] In addition, Fig.26 In order to facilitate the display of the location of the sacrificial layer 402 , the upper surface of the patterned hard mask layer 40 does not appear to be covered by the first covering layer 801 . However, the first covering layer 801 can cover the entire surface of the patterned hard mask layer 40 .

[0146] In one embodiment, Figure 28-Figure 29 As shown, after step S303 , the method for preparing the semiconductor structure further includes: filling the third trench and the fourth trench with a second filling layer 403 , and the second filling layer 403 filled in each fourth trench serves as a dielectric layer 20 between the first ends 3021 of each layer.

[0147] The material of the second filling layer 403 can be the same as that of the dielectric layer 20. In other words, Fig.28The dielectric layer 20 shown in the figure can actually be formed by re-deposition. This is because in the above embodiment, in order to form the first covering layer 801 on the surface of the first end 3021 of each layer, the dielectric layer 20 located between the first end 3021 of each layer is first removed, and then the second filling layer 403 is deposited by re-deposition, so that the second filling layer 403 can be used as the dielectric layer 20 between the first end 3021 of each layer. Fig.28 The filling color blocks of the second filling layer 403 are consistent with the filling color blocks of the medium layer 20 .

[0148] Of course, in other suitable embodiments, in order to achieve the morphology of forming a continuously distributed first covering layer 801 on the surface of each first end 3021 in step S30, other suitable preparation processes may also be adopted. Step S30 is to make the side surface of each first end 3021 covered by the first covering layer 801, while the side surface of each dielectric layer 20 is not covered by the first covering layer 801, so that the first end 3021 and the dielectric layer 20 can be easily distinguished in subsequent processes.

[0149] like Figure 30-Figure 31 As shown, in step S40, part of the stacked structure is removed to form a first groove 101 penetrating the first end 3021 of each layer along the second direction; the first direction intersects with the second direction.

[0150] Optionally, if a sacrificial layer 402 is formed at a position corresponding to the patterned hard mask layer 40 and the first end 3021 in the aforementioned embodiment, the sacrificial layer 402 can be removed first to expose the position of the previously reserved opening pattern 401, and then etching can be performed directly based on the opening pattern 401 to obtain the first groove 101 located in the stacked structure. Alternatively, if a sacrificial layer 402 is not formed correspondingly in the aforementioned embodiment, a photomask can be redesigned, and then the patterned hard mask layer 40 is etched based on the photomask, and then the stacked structure is etched to form the first groove 101. These two methods can be flexibly selected according to different application scenarios, and this embodiment is not limited here. In addition, the former method can reserve the position of the first groove 101 while forming the patterned hard mask layer 40 using one photomask, and use the sacrificial layer 402 for temporary filling. In the subsequent process, only the sacrificial layer 402 needs to be removed to directly perform etching to form the first groove 101, while the latter method needs to design two photomasks, that is, one photomask needs to be formed when forming the patterned hard mask layer 40, and one photomask needs to be formed when forming the first groove 101. Therefore, compared with the latter method, the former method can save one photomask, which can better save process costs.

[0151] In addition, since the surface of the first end portion 3021 in step S30 is covered by the first covering layer 801, and the surface of each dielectric layer 20 is not covered by the first covering layer 801, when forming the Figure 30-Figure 31 When the first trench 101 is shown, the sidewall of the first trench 101 will expose the alternately stacked multiple layers of first covering layers 801 and multiple layers of second filling layers 403. It can be understood that the first covering layers 801 exposed on the sidewall of the first trench 101 correspond to the first covering layers 801 covering the side surfaces of the first end portions 3021 of each layer in step S30; the positions of the second filling layers 403 exposed on the sidewall of the first trench 101 correspond to the positions of the dielectric layers 20.

[0152] like Figure 32-Figure 33 As shown, in step S50 , a channel material layer 901 and an isolation layer 902 are sequentially deposited on the inner wall of the first trench 101 , and a gate conductive layer 90330 is filled in the first trench 101 .

[0153] The channel material layer 901 and the isolation layer 902 may be deposited on the inner wall of the first trench 101 in sequence by an atomic layer deposition process, and then the gate conductive layer 90330 may be filled in the first trench 101 by a physical vapor deposition process or a chemical vapor deposition process.

[0154] The material of the channel material layer 901 may include a metal oxide semiconductor material, such as indium gallium zinc oxide (IGZO). When the metal oxide semiconductor material is IGZO, the leakage current of the transistor is small (the leakage current is less than or equal to 10-15A), thereby ensuring a low refresh rate of the dynamic memory. It should be noted that the metal oxide semiconductor material can also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, IGO, IZO (indium-zinc-oxide), IZOx and other materials, as long as the leakage current of the transistor can meet the requirements, and the specific adjustment can be made according to the actual situation.

[0155] The material of the isolation layer 902 may include a high dielectric material, for example, at least one of HfO2, Al2O3, HfAlO, and HfLaO. The gate conductive layer 90330 may include a conductive material, for example, at least one of ITO, W, TiN, TiAl, and TaN.

[0156] like Figure 34-Figure 35 As shown, in step S60, the second filling layer 403 located in the gap area between the first end portions 3021 is removed to form a second trench 102, and the sidewalls of the second trench 102 expose the first covering layer 801 and the channel material layer 901 alternately arranged in sequence along the second direction.

[0157] Due to the characteristics of the deposition process, the channel material layer 901 formed in step S50 will simultaneously cover the sides of each first covering layer 801 and each dielectric layer 20 exposed on the sidewall of the first trench 101. After the second trench 102 is formed in step S60, the second filling layer 403 is removed to form the second trench 102. At this time, the sidewall of the second trench 102 exposes the first covering layer 801 and the channel material layer 901 alternately arranged in sequence along the second direction. At this time, each first covering layer 801 exposed in the second trench 102 is in corresponding contact with the channel material layer 901 on the side of each conductive layer 30, and each channel material layer 901 is in corresponding contact with each dielectric layer 20.

[0158] like Figure 36-Figure 37 As shown, in step S70 , each channel material layer 901 exposed by the sidewall of the second trench 102 is removed to form a channel layer 904 , and each channel layer 904 is in contact with each second end portion 3022 in a one-to-one correspondence.

[0159] As described above, since each layer of the channel material layer 901 exposed in the second trench 102 is in contact with each layer of the dielectric layer 20, wet etching or steam etching can be performed directly based on the second trench 102 to remove each layer of the channel material layer 901 exposed on the sidewall of the second trench 102. The channel material layer 901 protected by each layer of the first cover layer 801 will not be removed, and thus will be retained as the channel layer 904. Thus, the parasitic transistor problem caused by the mutual connection of the channel material layers 901 can be avoided, and at the same time, the channel material layer 901 located on the side of each layer of the conductive layer 30 can also be retained to form the channel layer 904.

[0160] Optional, such as Figure 36-Figure 37 As shown, in one embodiment, after step S70, the method for preparing the semiconductor structure further includes: filling the second trench 102 with a third filling layer 404. The material of the third filling layer 404 can be the same as that of the first filling layer 50 and the second filling layer 403.

[0161] The present invention also provides a semiconductor structure, such as Figure 34-Figure 35 The semiconductor structure comprises: a substrate 10; a stacked structure located on the substrate 10, the stacked structure comprising a dielectric layer 20 and a conductive layer 30 stacked in sequence from bottom to top; each conductive layer 30 comprises a main body 301 extending along a first direction and a plurality of branch portions 302 located on both sides of the main body 301, each branch portion 302 also has a gap region, each branch portion 302 and each gap region are alternately arranged along the first direction, a first end portion 3021 of each branch portion 302 is connected to the main body 301, and a second end portion 3022 of each branch portion 302 is away from the main body 301. 01 setting; each gap area is filled with a first filling layer 50; a first covering layer 801, covering the side surfaces of the first end 3021 of each layer opposite to each other along the first direction; a device structure, penetrating the first end 3021 of each layer along the second direction, the second direction intersects with the first direction; the device structure includes a gate conductive layer 903 extending along the second direction, a multi-layer isolation layer 902 surrounding the side wall of the gate conductive layer 903 and arranged at intervals along the second direction, and a multi-layer channel layer 904 corresponding to the surface of the isolation layer 902, and each channel layer 904 is in contact with the second end 3022 of each layer.

[0162] The semiconductor structure comprises a substrate 10; a stacked structure located on the substrate 10, the stacked structure comprising a dielectric layer 20 and a conductive layer 30 stacked in sequence from bottom to top; each conductive layer 30 comprises a main body 301 extending along a first direction and a plurality of branch portions 302 located on both sides of the main body 301, each branch portion 302 also has a gap region, each branch portion 302 and each spacing region are alternately arranged along the first direction, a first end portion 3021 of each branch portion 302 is connected to the main body 301, and a second end portion 3022 of each branch portion 302 is away from the main body 301 is set; each gap region is filled with a first filling layer 50; a first covering layer 801 covers the side surface of the first end 3021 of each layer opposite to each other along the first direction; a device structure penetrates the first end 3021 of each layer along the second direction, and the second direction intersects with the first direction; the device structure includes a gate conductive layer 903 extending along the second direction, a multi-layer isolation layer 902 surrounding the side wall of the gate conductive layer 903 and arranged at intervals along the second direction, and a multi-layer channel layer 904 corresponding to the surface of the isolation layer 902, and each channel layer 904 is in contact with each second end 3022. Since the channel material layer 901 in contact with each dielectric layer 20 is removed, and the channel material layer 901 in contact with each conductive layer 30 is retained to form the channel layer 904, the device can avoid the generation of parasitic transistors, thereby avoiding the performance degradation of the device.

[0163] In one embodiment, Figure 34-Figure 35As shown, the semiconductor structure also includes a capacitor, which includes a first electrode, a capacitor isolation layer 701 and a second electrode. The second end 3022 serves as the first electrode of the capacitor, the capacitor isolation layer 701 covers the surface of the first electrode, and the surface of the capacitor isolation layer 701 is covered with a capacitor plate layer 702, and the capacitor plate layer 702 serves as the second electrode of the capacitor.

[0164] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0165] The above embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; forming a stacked structure on the substrate, wherein the stacked structure comprises a dielectric layer and a conductive layer stacked sequentially from bottom to top; Each conductive layer includes a main body extending along a first direction and a plurality of branch parts located on both sides of the main body, and a gap area is provided between each branch part. Each branch part and each gap area are alternately arranged along the first direction, a first end of each branch part is connected to the main body, and a second end of each branch part is arranged away from the main body; each gap area is filled with a second filling layer; forming a first covering layer distributed continuously on the surface of each of the first end portions; Removing part of the stacked structure to form a first groove penetrating the first end of each layer along a second direction; The first direction intersects the second direction; Depositing a channel material layer and an isolation layer on the inner wall of the first trench in sequence, and filling the first trench with a gate conductive layer; Removing the second filling layer in the gap region between the first end portions to form a second trench, wherein the sidewalls of the second trench expose the first covering layers and the channel material layers alternately arranged in sequence along the second direction; Each layer of the channel material layer exposed by the sidewall of the second trench is removed to form a channel layer, and each layer of the channel layer is in one-to-one contact with the second end of each layer.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The first covering layer is formed on the surface of each of the first ends and is continuously distributed, comprising: Removing the first filling layer in the gap region between the first end portions to form a third groove penetrating the first filling layer along the second direction, wherein the sidewalls of the third groove expose the side surfaces of the dielectric layer and the side surfaces of the first end portions which are alternately arranged in sequence along the second direction; removing each layer of the dielectric layer based on the third trench; The first covering layer is formed on the inner wall of the third groove and the surface of the first end portion of each layer.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that: The selective removal of each dielectric layer based on the third trench comprises: The third trench is laterally etched by a wet etching process to selectively remove each dielectric layer to form a fourth trench, wherein the fourth trench exposes surfaces of each layer opposite to the first end portion along the second direction.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that: After forming the first covering layer on the inner wall of the third groove and the surface of the first end of each layer, the method further includes: The second filling layer is filled in the third trench and the fourth trench, and the second filling layer filled in each of the fourth trenches serves as the dielectric layer between the first end portions of each layer.

5. The method for preparing a semiconductor structure according to claim 2, characterized in that: The forming of the first covering layer on the inner wall of the third groove and the surface of the first end of each layer includes: An atomic layer deposition process is used to form the first covering layer which is continuously distributed on the inner wall of the third groove and the surface of the first end of each layer.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that: The forming of a stacked structure on the substrate comprises: forming an initial stacked structure on the substrate, wherein the initial stacked structure comprises a dielectric layer and a conductive layer stacked sequentially from bottom to top; forming a patterned hard mask layer on the initial stacked structure; The initial stacked structure is etched based on the patterned hard mask layer to form the stacked structure.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that: The patterned hard mask layer includes a plurality of opening patterns, and the position of each of the opening patterns corresponds to the position of each of the first end portions; Before etching the initial stacked structure based on the patterned hard mask layer, the method further includes: Depositing a sacrificial material layer, wherein the sacrificial material layer covers the surface of the initial stacked structure and the surface of the patterned hard mask layer and fills the opening pattern; The sacrificial material layer located on the surface of the initial stacked structure and the surface of the patterned hard mask layer is removed to obtain a sacrificial layer retained in the opening pattern.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that: The step of removing a portion of the stacked structure to form a first groove penetrating the first end portions of each layer along a second direction comprises: removing the sacrificial layer filled in the opening pattern so that the opening pattern exposes the surface of the stacked structure; The stacked structure is etched based on the opening pattern to form the first trench.

9. The method for preparing a semiconductor structure according to claim 1, characterized in that: After forming the stacked structure on the substrate and before forming a continuously distributed first covering layer on the surface of each of the first end portions, the method further includes: removing the first filling layer and the dielectric layer in contact with the surface of the second end; A capacitor isolation layer and a capacitor plate layer are sequentially formed on the surface of the second end portion.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that: The removing of the first filling layer and the dielectric layer in contact with the surface of the second end portion comprises: removing the first filling layer in the gap region between the second end portions to form a fifth groove; The dielectric layers are laterally etched based on the fifth trench to form a sixth trench located between the second ends of the layers.

11. The method for preparing a semiconductor structure according to claim 10, characterized in that: The capacitor isolation layer and the capacitor plate layer are sequentially formed on the surface of the second end, including: forming a continuously distributed capacitor isolation layer on the inner wall of the fifth groove and the inner wall of the sixth groove, wherein the capacitor isolation layer covers the surface of the second end portion; A capacitor plate layer is filled in the fifth trench and the sixth trench, and the capacitor plate layer is in contact with the capacitor isolation layer.

12. A semiconductor structure, characterized in that: include: substrate; A stacked structure is located on the substrate, the stacked structure includes dielectric layers and conductive layers stacked in sequence from bottom to top; each conductive layer includes a main body extending along a first direction and a plurality of branch parts located on both sides of the main body, and there is a gap area between each branch part, each branch part and each spacing area are alternately arranged along the first direction, a first end of each branch part is connected to the main body, and a second end of each branch part is arranged away from the main body; each gap area is filled with a first filling layer; a first covering layer, covering the side surfaces of the first end portions of each layer opposite to each other along the first direction; A device structure, which penetrates the first end of each layer along a second direction, and the second direction intersects with the first direction; the device structure includes a gate conductive layer extending along the second direction, a plurality of isolation layers surrounding the side walls of the gate conductive layer and arranged at intervals along the second direction, and a plurality of channel layers corresponding to the surface of the isolation layer, and each channel layer is in contact with the second end of each layer.

13. The semiconductor structure according to claim 12, characterized in that: The semiconductor structure also includes a capacitor, which includes a first electrode, a capacitor isolation layer and a second electrode, the second end serving as the first electrode of the capacitor, the capacitor isolation layer covering the surface of the first electrode, and the surface of the capacitor isolation layer covered with a capacitor plate layer, the capacitor plate layer serving as the second electrode of the capacitor.

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