Semiconductor device having transistors sharing source / drain regions therein

Abstract

The invention relates to a semiconductor device having transistors in which source / drain regions are shared. Disclosed herein is an apparatus comprising: a first diffusion region having a rectangular shape and comprising a first source / drain region and a second source / drain region arranged along the first direction; a second diffusion region having a rectangular shape and including third to fifth source / drain regions arranged in the first direction; a first gate electrode extending in a second direction and disposed between the first source / drain region and the second source / drain region and between the third source / drain region and the fourth source / drain region; and a second gate electrode extending in the second direction and disposed between the fourth source / drain region and the fifth source / drain region. The first source / drain region and the third source / drain region have the same potential as each other, and the second source / drain region and the fourth source / drain region have the same potential as each other.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application of the invention patent application with the invention name “Semiconductor device having transistors sharing source / drain regions therein”, application number 202010657486.1, and application date July 9, 2020. Technical Field

[0003] The present application relates to semiconductor devices. Background Art

[0004] In order to further reduce the chip size of the semiconductor device, it is important to design the layout of the transistor ingeniously and simplify the process. For example, when one of the source / drain regions of a transistor and one of the source / drain regions of another transistor have the same potential, these source / drain regions can be shared to reduce the occupied area on the chip. When the source / drain region is shared between transistors with different gate widths, the planar shape of the diffusion region becomes, for example, L-shaped. However, a diffusion region with a non-rectangular planar shape exhibits different characteristics from a diffusion region with a rectangular planar shape. Therefore, a layout in which the source / drain region is not shared is used to prevent the planar shape of the diffusion region from becoming, for example, L-shaped. In this case, the area reduction effect due to the shared source / drain region cannot be obtained. Summary of the invention

[0005] In one aspect, the present application provides a device comprising: a semiconductor substrate; a first diffusion region formed on a surface of the semiconductor substrate, the first diffusion region having a rectangular shape in which a length along a first direction is a first length, the first diffusion region including a first source / drain region and a second source / drain region arranged along the first direction; a second diffusion region formed on the surface of the semiconductor substrate, the second diffusion region having a rectangular shape in which a length along the first direction is a second length greater than the first length, the second diffusion region including a third source / drain region, a fourth source / drain region and a fifth source / drain region arranged along the first direction. a fifth source / drain region; a first gate electrode extending along a second direction substantially perpendicular to the first direction and disposed between the first source / drain region and the second source / drain region of the first diffusion region and between the third source / drain region and the fourth source / drain region of the second diffusion region; and a second gate electrode extending along the second direction and disposed between the fourth source / drain region and the fifth source / drain region of the second diffusion region, wherein the first source / drain region and the third source / drain region have the same potential as each other, and wherein the second source / drain region and the fourth source / drain region have the same potential as each other.

[0006] In another aspect, the present application provides a device comprising: a first transistor, in which the gate width is a first width; and a second transistor, in which the gate width is a second width smaller than the first width, wherein the source / drain region of the first transistor is divided into a first source / drain region and a second source / drain region, and wherein one of the first source / drain regions of the first transistor and one of the source / drain regions of the second transistor are shared so that the gate width of the first transistor in the first source / drain region is the second width.

[0007] In another aspect, the present application provides a device comprising: a first power line extending along a first direction and supplied with a first power potential; a second power line extending along the first direction and supplied with a second power potential; and a plurality of standard cells arranged between the first power line and the second power line along the first direction, wherein each of the standard cells operates at a voltage between the first power potential and the second power potential, wherein the plurality of standard cells include a plurality of first standard cells having the same structure as each other, wherein each of the first standard cells includes: a first diffusion region having a rectangular shape in which a length along the first direction is a first length, the first diffusion region including a first source / drain region and a second source / drain region arranged along the first direction; a second diffusion region having a rectangular shape in which a length along the first direction is a first length, the first diffusion region including a first source / drain region and a second source / drain region arranged along the first direction; and a second diffusion region having a rectangular shape in which a length along the first direction is a first length. A rectangular shape having a length in one direction that is a second length greater than the first length, the second diffusion region comprising a third source / drain region, a fourth source / drain region and a fifth source / drain region arranged along the first direction; a first gate electrode extending along a second direction substantially perpendicular to the first direction and disposed between the first source / drain region and the second source / drain region of the first diffusion region and between the third source / drain region and the fourth source / drain region of the second diffusion region; and a second gate electrode extending along the second direction and disposed between the fourth source / drain region and the fifth source / drain region of the second diffusion region, wherein the first source / drain region and the third source / drain region have the same potential as each other, and wherein the second source / drain region and the fourth source / drain region have the same potential as each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram of a semiconductor device according to an embodiment of the present disclosure.

[0009] Figure 2 is a schematic plan view showing an example of a layout of a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 3A is a plan view for explaining the layout of standard cells constituting a latch circuit.

[0011] Figure 3B is shown separately Figure 3A A layout diagram of gate electrodes and wiring patterns in the upper layer is shown in FIG.

[0012] Figure 4 yes Figure 3A and 3B The circuit diagram of the standard cell is shown in FIG.

[0013] Figure 5 is a plan view for explaining the layout of standard cells constituting a flip-flop circuit. DETAILED DESCRIPTION

[0014] Various embodiments of the present invention will be explained in detail below with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings that illustrate specific aspects and embodiments of the present invention that can be practiced by means of illustration. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present invention. Other embodiments may be utilized without departing from the scope of the present invention, and structural, logical and electrical changes may be made. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.

[0015] Figure 1 1 is a block diagram of a semiconductor device 10 according to an embodiment of the present disclosure. For example, the semiconductor device 10 may be an LPDDR4 SDRAM incorporated in a single semiconductor chip. The semiconductor device 10 may be mounted on an external substrate such as a memory module substrate or a motherboard. Figure 1 As shown in , the semiconductor device 10 includes a memory cell array 11. The memory cell array 11 includes a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC arranged at the intersections of the word lines WL and the bit lines BL. The selection of the word lines WL is performed by a row address control circuit 12, and the selection of the bit lines BL is performed by a column decoder 13. A sense amplifier 14 is connected to the corresponding bit lines BL and a pair of local I / O lines LIOT / B. The pair of local I / O lines LIOT / B is connected to a pair of main I / O lines MIOT / B via a transfer gate 15 acting as a switch. The memory cell array 11 is divided into (m+1) memory banks including memory banks BANK0 to BANKm.

[0016] A plurality of external terminals included in the semiconductor device 10 include a command address terminal 21, a clock terminal 22, a data terminal 23, and power supply terminals 24 and 25. The data terminal 23 is connected to the I / O circuit 16.

[0017] The command address signal CA is supplied to the command address terminal 21. One of the command address signals CA supplied to the command address terminal 21, which is related to the address, is transmitted to the address decoder 32 via the command address input circuit 31. The other command address signal related to the command is transmitted to the command control circuit 33 via the command address input circuit 31. The address decoder 32 decodes the address signal and generates a row address XADD and a column address YADD. The row address XADD is supplied to the row address control circuit 12, and the column address YADD is supplied to the column decoder 13. In addition, the command address signal CA serving as a clock enable signal CKE is supplied to the internal clock generator 35.

[0018] Complementary external clock signals CK and / CK are supplied to the clock terminal 22. Complementary external clock signals CK and / CK are inputs of the clock input circuit 34. The clock input circuit 34 generates an internal clock signal ICLK based on the complementary external clock signals CK and / CK. The internal clock signal ICLK is supplied to at least the command control circuit 33 and the internal clock generator 35. The internal clock generator 35 is activated by, for example, a clock enable signal CKE, and generates an internal clock signal LCLK based on the internal clock signal ICLK. The internal clock signal LCLK is supplied to the I / O circuit 16. The internal clock signal LCLK is used as a timing signal that defines the timing of outputting the read data DQ from the data terminal 23 at the time of the read operation. In the write operation, the write data is input to the data terminal 23 from the outside. In the write operation, the data mask signal DM can be input to the data terminal 23 from the outside.

[0019] The power supply potentials VDD and VSS are supplied to the power supply terminal 24. These power supply potentials VDD and VSS are supplied to the voltage generator 36. The voltage generator 36 generates various internal potentials VPP, VOD, VARY, and VPERI based on the power supply potentials VDD and VSS, for example. The internal potential VPP is mainly used in the row address control circuit 12. The internal potentials VOD and VARY are mainly used in the sense amplifier 14 included in the memory cell array 11. The internal potential VPERI is used in many other circuit blocks.

[0020] The power supply potentials VDDQ and VSSQ are supplied from the power supply terminal 25 to the I / O circuit 16. Although the power supply potentials VDDQ and VSSQ may be the same potentials as the power supply potentials VDD and VSS respectively supplied to the power supply terminal 24, dedicated power supply potentials VDDQ and VSSQ are assigned to the I / O circuit 16 in order to prevent power supply noise generated in the I / O circuit 16 from propagating to another circuit block.

[0021] The command control circuit 33 activates the active signal ACT when a valid command is issued, and activates the refresh signal AREF when a refresh command is issued. Both the active signal ACT and the refresh signal AREF are supplied to the row address control circuit 12. The row address control circuit 12 includes a refresh control circuit 40. The refresh control circuit 40 controls the refresh operation of the memory cell array 11 based on the row address XADD, the active signal ACT, and the refresh signal AREF. The refresh control circuit 40 will be described in detail later.

[0022] When a read command is issued from the outside, following the active command, the command control circuit 33 activates the column selection signal CYE. The column selection signal CYE is supplied to the column decoder 13. In response to this signal, read data is read out from the memory cell array 11. The read data read from the memory cell array 11 is transferred to the I / O circuit 16 via the read / write amplifier 17 and the FIFO circuit 18, and is output to the outside via the data terminal 23.

[0023] Figure 2 is a schematic plan view showing an example of the layout of the semiconductor device 10. Figure 2 In the example shown, four memory cell arrays 11 are arranged in the x direction, and two memory cell arrays 11 are arranged in the y direction. Peripheral circuits such as the address decoder 32 and the command control circuit 33 are placed in the peripheral circuit area 50, which is between the four memory cell arrays 11 arranged on one side along the y direction and the four memory cell arrays 11 arranged on the other side along the y direction. Some of the circuits placed in the peripheral circuit area 50 are composed of a combination of multiple standard cells. A standard cell is a small logic circuit such as an inverter circuit, a buffer circuit, a NAND gate circuit, a NOR gate circuit, a delay circuit, a latch circuit, and a trigger circuit, and has a shape in which the pattern shape of transistors and wiring is previously defined. Therefore, when a plurality of standard cells are combined, a desired circuit can be constructed only by determining the layout of wiring connecting the standard cells to each other.

[0024] like Figure 2 As shown in , the standard cells are arranged, for example, along the x-direction in a region between power supply lines 51 and 52 extending along the x-direction. Therefore, the respective heights of the standard cells along the y-direction are all constant. The size differences of the standard cells are caused by the width differences along the x-direction. Each of the standard cells operates at a voltage between a power supply potential (e.g., VPERI) supplied via power supply line 51 and a power supply potential (e.g., VSS) supplied via power supply line 52. A plurality of standard cells having the same function and the same layout are formed in the peripheral circuit region 50.

[0025] Figure 3A is a plan view for explaining the layout of standard cells constituting a latch circuit. Figure 3B In order to facilitate understanding of the diagram, the Figure 3A A layout diagram of gate electrodes and wiring patterns in the upper layer is shown in FIG.

[0026] Figure 3A and 3B The standard cell shown in FIG. 6 includes P-type impurity regions 61P to 63P, an N-type impurity region 64N, and gate electrodes 60G to 69G. The P-type impurity region 61P overlaps with two gate electrodes 60G and 61G extending in the y direction. The region that does not overlap with the gate electrodes 60G and 61G in the P-type impurity region 61P forms source / drain regions SD611 to SD613. The P-type impurity region 62P overlaps with five gate electrodes 60G, 61G, 65G, 64G, and 68G extending in the y direction. The region that does not overlap with the gate electrodes 60G, 61G, 65G, 64G, and 68G in the P-type impurity region 62P forms source / drain regions SD621 to SD626. The P-type impurity region 63P overlaps with one gate electrode 68G extending in the y direction. The region that does not overlap with the gate electrode 68G in the P-type impurity region 63P forms source / drain regions SD631 and SD632. The N-type impurity region 64N overlaps with five gate electrodes 63G, 62G, 66G, 67G, and 69G extending in the y direction. Regions not overlapping with the gate electrodes 63G, 62G, 66G, 67G, and 69G in the N-type impurity region 64N form source / drain regions SD641 to SD646.

[0027] For example, the length of the P-type impurity region 62P along the x direction is equal to the length of the N-type impurity region 64N along the x direction. The length of the P-type impurity region 62P along the x direction is greater than the length of each of the P-type impurity regions 61P and 63P along the x direction.

[0028] The gate electrodes 61G and 62G are connected to the wiring pattern 70 located in the upper layer through the via conductors 61V and 62V, respectively. The gate electrodes 63G and 65G are connected to the wiring pattern 71 located in the upper layer through the via conductors 63V and 65V, respectively. The gate electrodes 64G and 67G are connected to the wiring pattern 75 located in the upper layer through the via conductors 64V and 67V, respectively. The gate electrodes 60G and 66G are short-circuited to each other, and the gate electrodes 68G and 69G are short-circuited to each other. The gate electrodes 60G and 66G are connected to the wiring pattern 78 located in the upper layer through the via conductor 606V. The gate electrodes 68G and 69G are connected to the wiring pattern 74 located in the upper layer through the via conductor 689V.

[0029] The source / drain regions SD611 and SD621 are connected to the wiring pattern 72 located in the upper layer through via conductors 611V and 621V, respectively. The wiring pattern 72 is connected to the power supply line 51. The source / drain region SD641 is connected to the wiring pattern 73 located in the upper layer through a via conductor 641V. The wiring pattern 73 is connected to the power supply line 52. The source / drain regions SD613, SD623, and SD643 are connected to the wiring pattern 74 located in the upper layer through via conductors 613V, 623V, and 643V, respectively. As described above, the wiring pattern 74 is connected to the gate electrodes 68G and 69G. The source / drain regions SD626, SD632, and SD646 are connected to the wiring pattern 75 located in the upper layer through via conductors 626V, 632V, and 646V, respectively. As described above, the wiring pattern 75 is connected to the gate electrodes 64G and 67G. The source / drain regions SD625 and SD631 are connected to a wiring pattern 76 located in an upper layer through via conductors 625V and 631V, respectively. The wiring pattern 76 is connected to the power supply line 51. The source / drain region SD645 is connected to a wiring pattern 77 located in an upper layer through a via conductor 645V. The wiring pattern 77 is connected to the power supply line 52. Meanwhile, no via conductor is allocated to the source / drain regions SD612, SD622, SD624, SD642, and SD644.

[0030] Figure 4 yes Figure 3A and 3B The circuit diagram of the standard unit is shown in FIG. Figure 4 As shown in Figure 3A and 3B The standard cell shown in FIG. 1 is composed of transistors T60 to T69. Among these transistors, transistors T60, T61, T64, T65 and T68 are P-channel MOS transistors, and transistors T62, T63, T66, T67 and T69 are N-channel MOS transistors. Transistors T60 to T63 are connected in series, transistors T64 to T67 are connected in series, and transistors T68 and T69 are connected in series between a power supply line 51 supplied, for example, by a power supply potential VPERI and a power supply line 52 supplied, for example, by a power supply potential VSS.

[0031] The gate electrodes of transistors T61 and T62 are commonly connected to the wiring pattern 70 and are supplied with the input signal D via the wiring pattern 70. The gate electrodes of transistors T60 and T66 are commonly connected to the wiring pattern 78 and are supplied with the latch signal LAT via the wiring pattern 78. The gate electrodes of transistors T63 and T65 are commonly connected to the wiring pattern 71 and are supplied with the inverted latch signal LATf via the wiring pattern 71. The drains of transistors T61 and T62 are commonly connected to be commonly connected to the gate electrodes of transistors T68 and T69 via the wiring pattern 74. The drains of transistors T68 and T69 are commonly connected to be commonly connected to the gate electrodes of transistors T64 and T67 via the wiring pattern 75 and output the output signal Q via the wiring pattern 75. The drains are shared by transistors T65 and T66 and transistors T61 and T62, respectively. That is, the source / drain region SD623 is the common drain of the transistors T61 and T65, and the source / drain region SD643 is the common drain of the transistors T62 and T66. In addition, the source is shared by the transistors T64 and T68. That is, the source / drain region SD625 is the common source of the transistors T64 and T68.

[0032] With this circuit configuration, the input signal D is latched in response to the latch signals LAT and LATf, and the latched data is output as the output signal Q.

[0033] Each of the diffusion regions constituting transistors T60 and T61 is divided into P-type impurity regions 61P and 62P. That is, the source of transistor T60 is divided into source / drain regions SD611 and SD621, and the drain of transistor T60 is divided into source / drain regions SD612 and SD622. The potentials of source / drain regions SD611 and SD621 are the same, the potentials of source / drain regions SD612 and SD622 are the same, and a common gate electrode 60G is allocated thereto. Therefore, although the diffusion regions are divided, transistor T60 essentially acts as one transistor. Similarly, the source of transistor T61 is divided into source / drain regions SD612 and SD622, and the drain of transistor T61 is divided into source / drain regions SD613 and SD623. The potential of the source / drain regions SD612 and SD622 is the same, the potential of the source / drain regions SD613 and SD623 is the same, and a common gate electrode 61G is allocated thereto. Therefore, although the diffusion region is divided, the transistor T61 essentially functions as one transistor.

[0034] The diffusion region constituting the transistor T68 is divided into P-type impurity regions 62P and 63P. That is, the source of the transistor T68 is divided into source / drain regions SD625 and SD631, and the drain of the transistor T68 is divided into source / drain regions SD626 and SD632. The potentials of the source / drain regions SD625 and SD631 are the same, the potentials of the source / drain regions SD626 and SD632 are the same, and a common gate electrode 68G is allocated thereto. Therefore, although the diffusion region is divided, the transistor T68 essentially acts as one transistor.

[0035] As described above, because the diffusion regions constituting some transistors are Figure 3A and 3B In the standard cell shown in , the planar shape of the diffusion region can be formed into a rectangle, and transistors with different gate widths share the source / drain region. For example, because the drain of transistor T61 and the drain of transistor T65 have the same potential, the drains of these transistors can share a source / drain region. However, if the source / drain region is shared in practice, the diffusion region does not form a rectangular shape but an L shape, because the gate width of transistor T61 is greater than the gate width of transistor T65. Similarly, because the source of transistor T64 and the source of transistor T68 have the same potential, the sources of these transistors can share a source / drain region. However, if the source / drain region is shared in practice, the diffusion region does not form a rectangular shape but an L shape, because the gate width of transistor T68 is greater than the gate width of transistor T64.

[0036] A diffusion region with a non-rectangular planar shape has different characteristics than a diffusion region with a rectangular planar shape. Figure 3A and 3B In the standard cell shown in FIG. 1 , the diffusion region constituting the transistors T61 and T68 is divided into two parts so that the height along the y direction of one of the divided parts of the diffusion region matches the height along the y direction of the diffusion region constituting the transistor T65 or the transistor T64. Therefore, although the transistors T61 and T65 share a drain, and the transistors T68 and T64 share a drain, the planar shape of the diffusion region can be formed into a rectangle.

[0037] In the case where the diffusion area constituting the transistor T61 is not divided, the transistor T61 and the transistor T65 cannot share the drain and it is not clear that a separate source / drain area needs to be used to maintain the rectangular shape of the diffusion area. Therefore, the size of the standard cell along the x direction increases. Similarly, in the case where the diffusion area constituting the transistor T68 is not divided, the transistor T68 and the transistor T64 cannot share the source and need to use a separate source / drain area to maintain the rectangular shape of the diffusion area. Therefore, the size of the standard cell along the x direction increases. In the present embodiment, by contrast, the transistor T61 and the transistor T65 share the drain, and the transistor T68 and the transistor T64 share the source. Therefore, compared with the case where the source / drain area is not shared, the effect of reducing the area by 21.6% is obtained.

[0038] Figure 5 1 is a plan view for explaining the layout of a standard cell constituting a flip-flop circuit, and for easy understanding of the drawing, only some of the diffusion regions, gate electrodes, and upper wirings are shown. Figure 5 The standard cell shown in FIG. 1 includes P-type impurity regions 81P to 85P, N-type impurities 86N to 89N, and gate electrodes 90G to 97G and 100G to 105G. Gate electrodes 90G to 95G overlap both P-type impurity regions 81P and 82P, and gate electrodes 96G and 97G overlap only P-type impurity region 82P. That is, the gate widths of gate electrodes 90G to 95G are greater than the gate widths of gate electrodes 96G and 97G. Therefore, if a single P-type impurity region is used, its planar shape becomes non-rectangular. Similarly, gate electrodes 100G and 101G overlap both P-type impurity regions 83P and 84P, and gate electrodes 102G to 104G overlap only P-type impurity region 83P. That is, the gate widths of gate electrodes 100G and 101G are greater than the gate widths of gate electrodes 102G to 104G. Therefore, if a single P-type impurity region is used, its planar shape becomes non-rectangular. However, in Figure 5 In the standard cell shown in FIG. 1 , each of the transistors corresponding to gate electrodes 90G to 95G is divided into two, and each of the transistors corresponding to gate electrodes 100G and 101G is divided into two. Therefore, the planar shape of each of the impurity regions can be formed into a rectangle.

[0039] In the case where each of the transistors corresponding to gate electrodes 90G to 95G is not divided into two, the source / drain region SD82 of the transistors corresponding to gate electrodes 95G and 96G cannot be shared, and different source / drain regions need to be respectively allocated thereto to maintain the rectangular planar shape of each of the impurity regions. Similarly, in the case where each of the transistors corresponding to gate electrodes 100G and 101G is not divided into two, the source / drain region SD83 of the transistors corresponding to gate electrodes 101G and 102G cannot be shared, and different source / drain regions need to be respectively allocated thereto to maintain the rectangular planar shape of each of the impurity regions. In contrast, in Figure 5 In the standard cell shown in FIG. 1 , the source / drain region SD82 can be shared by the transistors corresponding to the gate electrodes 95G and 96G and can be connected to the common wiring pattern 110 through the via conductor 82V. Similarly, the source / drain region SD83 can be shared by the transistors corresponding to the gate electrodes 101G and 102G and can be connected to the common wiring pattern 120 through the via conductor 83V. Therefore, an effect of reducing the area by 10.4% is obtained.

[0040] Specifically, a transistor group that can share a source / drain region of a standard cell or functional block has a configuration characterized by sharing a source / drain region for a common gate width (gate width of a smaller transistor) and separating a differential gate width (from the gate width of a larger transistor). For example, in a case where there are two transistors having gate widths of 8 microns and 12 microns, respectively, and can share a source / drain region, the two transistors can share a source / drain region for 8 microns, which is the gate width of the smaller transistor, and separate a differential gate width that is 4 microns different from the gate width of the larger transistor, thereby obtaining two rectangular impurity diffusion regions. In the case of three or more transistors, so-called "gate division" (dividing a transistor having a gate width of 16 microns into two transistors having a gate width of 8 microns and positioning the drain region at the center) can be considered. For example, in the case where there are three transistors having gate widths of 8 microns, 12 microns, and 16 microns, respectively, considering 16 microns=8 microns×2, in the same manner as described above, all transistors share the source / drain region for the gate width of 8 microns, and similarly separate the differential gate width having a difference of 4 microns from the gate width of 12 microns to obtain two rectangular impurity diffusion regions. The same applies to the case where there are four or more transistors.

[0041] Although the present invention has been disclosed in the context of certain preferred embodiments and examples, it will be appreciated by those skilled in the art that the present invention extends beyond the specifically disclosed embodiments to other alternative embodiments and / or the present invention and its obvious modifications and use of equivalents. In addition, based on this disclosure, other modifications within the scope of the present invention will be apparent to those skilled in the art. It is also contemplated that various combinations or sub-combinations of the specific features and aspects of the embodiments may be performed and still be within the scope of the present invention. It will be appreciated that the various features and aspects of the disclosed embodiments may be combined or replaced with one another to form a variation pattern of the disclosed invention. Therefore, it is desirable that the scope of at least some of the present invention disclosed herein should not be limited by the specific disclosed embodiments described above.

Claims

1. A device comprising: a first diffusion region having a rectangular shape in which a length along a first direction is a first length, the first diffusion region including a first source / drain region and a second source / drain region arranged along the first direction; a second diffusion region having the rectangular shape in which the length along the first direction is a second length greater than the first length, the second diffusion region including a third source / drain region and a fourth source / drain region arranged along the first direction; A first gate electrode extends in a second direction substantially perpendicular to the first direction and is disposed between the first source / drain region and the second source / drain region of the first diffusion region and between the third source / drain region and the fourth source / drain region of the second diffusion region.

2. The device of claim 1, wherein the second diffusion region further comprises a fifth source / drain region, the device further comprising: A second gate electrode extends along the second direction and is disposed between the fourth source / drain region and the fifth source / drain region of the second diffusion region, wherein the first source / drain region and the third source / drain region have the same potential as each other.

3. The apparatus according to claim 2, further comprising: A first wiring is electrically connected between the second source / drain region and the fourth source / drain region, wherein the second source / drain region and the fourth source / drain region have the same potential as each other at least partially based on the first wiring.

4. The device of claim 1, wherein the first diffusion region further comprises a fifth source / drain region and the second diffusion region further comprises a sixth source / drain region, the device further comprising: A second gate electrode extends along the second direction and is disposed between the first source / drain region and the fifth source / drain region of the first diffusion region and between the third source / drain region and the sixth source / drain region of the second diffusion region.

5. The apparatus according to claim 4, further comprising: A second wiring is electrically connected between the fifth source / drain region and the sixth source / drain region, wherein the fifth source / drain region and the sixth source / drain region have the same potential as each other. The device according to claim 5 , wherein the second wiring is supplied with a power supply potential.

7. The apparatus of claim 1, wherein the first source / drain region and the third source / drain region are free of via conductors.

8. The apparatus of claim 1, wherein each of the first diffusion region and the second diffusion region has P-type conductivity.

9. The apparatus according to claim 1, further comprising: A first transistor, wherein a source / drain region of the first transistor is divided into a first source / drain region and a second source / drain region.

10. The apparatus of claim 9, further comprising: A second transistor, wherein one of the first source / drain regions of the first transistor and one of the source / drain regions of the second transistor are shared, and wherein the first transistor and the second transistor share a common drain.

11. A device comprising: A first power line extending along a first direction; a second power line extending along the first direction; and a plurality of standard cells arranged between the first power line and the second power line along the first direction, wherein each of the standard cells operates at a voltage between a first power potential and a second power potential, wherein each of the first standard cells comprises: a first diffusion region having a rectangular shape in which a length along the first direction is a first length, the The first diffusion region includes a first source / drain region and a second source / drain region arranged along the first direction; a second diffusion region having a rectangular shape in which a length along the first direction is a second length different from the first length, the second diffusion region including a third source / drain region and a fourth source / drain region arranged along the first direction; as well as A first gate electrode extends along a second direction and is disposed between the first source / drain region and the second source / drain region of the first diffusion region and between the third source / drain region and the fourth source / drain region of the second diffusion region.

12. The device of claim 11, wherein the second diffusion region further comprises a fifth source / drain region, the device further comprising: A second gate electrode extends along the second direction and is disposed between the fourth source / drain region and the fifth source / drain region of the second diffusion region, wherein the first source / drain region and the third source / drain region have the same potential as each other.

13. The apparatus of claim 12, wherein each of the first standard cells further comprises: A first wiring is electrically connected between the second source / drain region and the fourth source / drain region, wherein the second source / drain region and the fourth source / drain region have the same potential as each other at least partially based on the first wiring.

14. The apparatus of claim 11, wherein the first diffusion region further comprises a fifth source / drain region and the second diffusion region further comprises a sixth source / drain region, the apparatus further comprising: A second gate electrode extends along the second direction and is disposed between the first source / drain region and the fifth source / drain region of the first diffusion region and between the third source / drain region and the sixth source / drain region of the second diffusion region.

15. The apparatus of claim 14, wherein each of the first standard cells further comprises: A second wiring is electrically connected between the fifth source / drain region and the sixth source / drain region, wherein the fifth source / drain region and the sixth source / drain region have the same potential as each other.

16. The device according to claim 15, wherein the second wiring is supplied with the first power supply potential.

17. The apparatus of claim 11, wherein the first source / drain region and the third source / drain region are free of via conductors. 18 . The apparatus of claim 11 , wherein each of the first standard cells is a latch circuit or a flip-flop circuit.

19. An apparatus comprising: a first transistor in which the gate width is a first width; and A second transistor, wherein a gate width is a second width less than the first width, wherein a first source / drain region of the first transistor and a first source / drain region of the second transistor are shared so that a gate width of the first transistor in the first source / drain region is the second width, and wherein a gate width of the first transistor in a second source / drain region is the second width.

20. The apparatus of claim 19, further comprising: A first wiring is electrically connected between the first source / drain region of the first transistor and the second source / drain region of the first transistor.

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