Manufacturing method of semiconductor structure
By forming and removing multiple lower conductive layers on the DRAM substrate, the problem of difficult control of the edge groove etching depth is solved, and precise control of the lower conductive layer thickness and edge groove depth is achieved, thereby improving the overall performance of DRAM.
Patent Information
- Application Number
- CN202510083385.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-10-11
- Filing Date
- 2025-01-20
- Publication Date
- 2025-05-02
AI Technical Summary
In dynamic random access memory (DRAM), the edge groove etching depth between the array region and the surrounding region is difficult to control, resulting in bit line defect problems and a long measurement time.
By forming the first lower conductive layer on the substrate and removing portions thereof, then forming a second lower conductive layer so that it forms a lower conductive layer together with the first lower conductive layer, controlling the depth of the edge groove structure.
Accurate control of the thickness of the conductive layer and the depth of the edge groove structure under the array region is achieved, reducing the differences between wafers and improving overall performance.
Smart Images
Figure CN119922913A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a method for manufacturing a semiconductor structure. Background Art
[0002] In dynamic random access memory (DRAM), the moat between the array area and the peripheral area can reduce the bit line defect problem in the array area. However, in the current process, it is difficult to control the etching depth of the moat during the formation of the lower conductive layer. Therefore, a lot of time is required to measure the etching depth of the moat structure. Summary of the invention
[0003] According to one aspect of the present invention, a method for manufacturing a semiconductor structure is provided. The method comprises the following steps. A substrate is provided, the substrate having a first array area, a second array area and a peripheral area, wherein the second array area surrounds the first array area, and the peripheral area surrounds the second array area. A first lower conductive layer is formed on the substrate, the first lower conductive layer continuously having a first portion located in the first array area, a second portion located in the second array area and a third portion located in the peripheral area, wherein the top surface of the first portion is higher than the top surface of the second portion and the top surface of the third portion, and the top surface of the second portion is coplanar with the top surface of the third portion. The first portion of the first lower conductive layer and the second portion of the first lower conductive layer are removed. A second lower conductive layer is formed on the substrate, the second lower conductive layer continuously having a first portion located in the first array area, a second portion located in the second array area and a third portion located in the peripheral area. The top surface of the third portion of the second lower conductive layer is higher than the top surface of the first portion of the second lower conductive layer, and the first portion of the second lower conductive layer is higher than the top surface of the second portion of the second lower conductive layer, and the second lower conductive layer and the first lower conductive layer contain the same material so that the second lower conductive layer and the first lower conductive layer together form a lower conductive layer.
[0004] In some embodiments, the method further includes forming a sacrificial layer on the first lower conductive layer before removing the first portion of the first lower conductive layer and the second portion of the first lower conductive layer, wherein the sacrificial layer continuously has a first portion located in the first array area, a second portion located in the second array area, and a third portion located in the peripheral area, wherein a top surface of the first portion is higher than a top surface of the second portion.
[0005] In some embodiments, before removing the first portion of the first lower conductive layer and the second portion of the first lower conductive layer, a photoresist is formed on the third portion of the first lower conductive layer.
[0006] In some embodiments, the first lower conductive layer and the second lower conductive layer include polysilicon.
[0007] In some embodiments, the method further includes doping a portion of the lower conductive layer in the first array region to form a doped lower conductive layer.
[0008] In some embodiments, the method further includes forming an upper conductive layer on the lower conductive layer and the doped lower conductive layer.
[0009] In some embodiments, the method further includes forming a capping layer on the upper conductive layer.
[0010] In some embodiments, the method further includes performing an etching process to form a first bit line structure and a second bit line structure in the first array region, wherein the first bit line structure includes a capping layer, an upper conductive layer, and a lower conductive layer, and wherein the second bit line structure includes a capping layer, an upper conductive layer, and a doped lower conductive layer.
[0011] In some embodiments, a first angle between a sidewall of the lower conductive layer of the first bit line structure and a top surface of the substrate is different from a second angle between a sidewall of the doped lower conductive layer of the second bit line structure and the top surface of the substrate.
[0012] In some embodiments, the method further includes forming a first spacer on a sidewall of the first bit line structure and a sidewall of the second bit line structure, and forming a second spacer on the first spacer of the first bit line structure and the first spacer of the second bit line structure.
[0013] According to one aspect of the present invention, a method for manufacturing a semiconductor structure is provided. The method comprises the following steps. A substrate is provided, wherein the substrate has a first array region, a second array region and a peripheral region, wherein the top surface of the substrate in the first array region is higher than the top surface of the substrate in the second array region and the top surface of the substrate in the peripheral region, and the top surface of the substrate in the second array region is coplanar with the top surface of the substrate in the peripheral region. A first lower conductive layer is formed on the substrate, wherein the first lower conductive layer continuously has a first portion located in the first array region, a second portion located in the second array region and a third portion located in the peripheral region, wherein the first portion, the second portion and the third portion have the same thickness. The first portion of the first lower conductive layer and the second portion of the first lower conductive layer are removed. A second lower conductive layer is formed on the substrate, wherein the second lower conductive layer continuously has a first portion located in the first array region, a second portion located in the second array region and a third portion located in the peripheral region. The first portion, the second portion and the third portion of the second lower conductive layer have the same thickness, and wherein the second lower conductive layer and the first lower conductive layer include polysilicon, so that the second lower conductive layer and the first lower conductive layer together form a lower conductive layer.
[0014] In some embodiments, the method further comprises the following steps: doping a portion of the lower conductive layer in the first array region to form a doped lower conductive layer; forming an upper conductive layer on the lower conductive layer and the doped lower conductive layer; and forming a capping layer on the upper conductive layer.
[0015] In some embodiments, the method further includes performing an etching process to form a first bit line structure and a second bit line structure in the first array region, wherein the first bit line structure includes a capping layer, an upper conductive layer, and a lower conductive layer, and wherein the second bit line structure includes a capping layer, an upper conductive layer, and a doped lower conductive layer.
[0016] In some embodiments, a first angle between a sidewall of the lower conductive layer of the first pixel line structure and a top surface of the substrate is between 90 degrees and 180 degrees.
[0017] In some embodiments, a second angle between a sidewall of the doped lower conductive layer of the second bit line structure and a top surface of the substrate is 90 degrees. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] In order to make the purpose of the present invention more obvious and easy to understand, the embodiments of the present invention are further described in detail below with reference to the accompanying drawings:
[0019] Figure 1 is a schematic top view of a semiconductor structure according to some embodiments.
[0020] Figure 2 According to some embodiments, Figure 1 Schematic diagram of the cross-section of the semiconductor structure along line AA.
[0021] Figure 3 is a schematic cross-sectional view of a semiconductor structure after a sacrificial layer is formed according to some embodiments.
[0022] Figure 4 is a schematic cross-sectional view of a semiconductor structure after the sacrificial layer and the first lower conductive layer are removed according to some embodiments.
[0023] Figure 5 is a schematic cross-sectional view of a semiconductor structure after a second lower conductive layer is formed according to some embodiments.
[0024] Figure 6 is a schematic cross-sectional view of a semiconductor structure after a hard mask layer is formed according to some embodiments.
[0025] Figure 7 is a schematic cross-sectional view of a semiconductor structure after an upper conductive layer is formed according to some embodiments.
[0026] Figure 8 is a schematic cross-sectional view of a semiconductor structure after a capping layer is formed according to some embodiments.
[0027] Fig. 9 is a schematic cross-sectional view of a semiconductor structure after an etching process is performed according to some embodiments.
[0028] Fig.10 is a schematic cross-sectional view of a semiconductor structure after forming a first spacer and a second spacer according to some embodiments. DETAILED DESCRIPTION
[0029] Reference will now be made in detail to the embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.
[0030] It should be understood that the following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and configurations are described below to simplify the present invention. Of course, these are merely examples and are not intended to be restrictive. For example, forming a first feature above or below a second feature in the following description may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present invention may repeat reference numerals and / or symbols in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself dictate the relationship between the various embodiments and / or configurations discussed.
[0031] Furthermore, for ease of description, the present invention may use spatially relative terms, such as "below", "beneath", "lower", "above", "upper", etc., to describe the relationship of one element or feature to one or more other elements or features, as shown in the accompanying drawings. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.
[0032] It will be understood that when an element or layer is referred to as being “connected to” or “coupled to” another element or layer, it can be directly connected or coupled to the other element or layer or intervening elements or layers may be present.
[0033] Figures 1 to 101 is a schematic cross-sectional view of various intermediate stages in the formation of a semiconductor structure 100 according to some embodiments. The semiconductor structure 100 may be applied to an integrated circuit (IC) or a portion thereof, such as a logic circuit, a resistor, a capacitor, a sensor, a storage device (such as a dynamic random access memory (DRAM)). It should be understood that in order to simplify the drawings, Figures 1 to 10 Some components of the semiconductor structure 100 are not shown, and other embodiments of the semiconductor structure 100 may include additional components.
[0034] Figure 1 is a schematic top view of the semiconductor structure 100 . Figure 2 is along Figure 1 FIG. 1 is a cross-sectional schematic diagram of the semiconductor structure 100 along line AA. Figure 1 and Figure 2 As shown, the semiconductor structure 100 includes a first array region R1, a second array region R2, and a peripheral region R3, wherein the second array region R2 surrounds the first array region R1, and the peripheral region R3 surrounds the second array region R2. The semiconductor structure 100 includes a substrate 110. The top surface of the substrate 110 in the first array region R1 is higher than the top surfaces of the substrate 110 in the second array region R2 and the peripheral region R3. The top surface of the substrate 110 in the second array region R2 is substantially coplanar with the top surface of the substrate 110 in the peripheral region R3. In other words, there is a step structure between the first array region R1 and the second array region R2.
[0035] In some embodiments, the substrate 110 may be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, etc., wherein the insulator may be a buried oxide (BOX) layer, a silicon oxide layer, etc. In some embodiments, the substrate 110 may be doped (e.g., containing a p-type or n-type dopant) or undoped. In some embodiments, the semiconductor material of the substrate 110 may include silicon, germanium, a compound semiconductor (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide), an alloy semiconductor, or a combination thereof. The substrate 110 may also be formed of other materials, such as sapphire, indium tin oxide, etc.
[0036] like Figure 2As shown, a first lower conductive layer 120 is formed on a substrate 110. A first portion 120-1 of the first lower conductive layer 120 is located in the first array region R1. A second portion 120-2 of the first lower conductive layer 120 is located in the second array region R2. A third portion 120-3 of the first lower conductive layer 120 is located in the peripheral region R3. Similar to the substrate 110, a top surface of the first portion 120-1 of the first lower conductive layer 120 in the first array region R1 is higher than top surfaces of the second portion 120-2 and the third portion 120-3 of the first lower conductive layer 120. A top surface of the second portion 120-2 of the first lower conductive layer 120 is substantially coplanar with a top surface of the third portion 120-3 of the first lower conductive layer 120. As shown, a thickness T120-1 of the first portion 120-1, a thickness T120-2 of the second portion 120-2, and a thickness T120-3 of the third portion 120-3 are substantially the same. In other words, the first portion 120 - 1 , the second portion 120 - 2 , and the third portion 120 - 3 of the first lower conductive layer 120 are continuously formed on the substrate 110 .
[0037] In some embodiments, the first lower conductive layer 120 may be formed using a suitable deposition process, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), etc. In some embodiments, the first lower conductive layer 120 includes a conductive material, such as polysilicon.
[0038] refer to Figure 3 , a sacrificial layer 130 may be formed on the first lower conductive layer 120. A first portion 130-1 of the sacrificial layer 130 is located in the first array region R1. A second portion 130-2 of the sacrificial layer 130 is located in the second array region R2. A third portion 130-3 of the sacrificial layer 130 is located in the peripheral region R3. A photoresist 132 may be formed on the sacrificial layer 130 of the peripheral region R3. In other words, the first portion 130-1 of the sacrificial layer 130 and the second portion 130-2 of the sacrificial layer 130 are exposed. Similar to the first lower conductive layer 120, the top surface of the first portion 130-1 of the sacrificial layer 130 in the first array region R1 is higher than the top surfaces of the second portion 130-2 and the third portion 130-3 of the sacrificial layer 130. The top surface of the second portion 130-2 of the sacrificial layer 130 is substantially coplanar with the top surface of the third portion 130-3 of the sacrificial layer 130.
[0039] In some embodiments, the sacrificial layer 130 and the photoresist 132 may be formed using a suitable deposition process, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), etc. In some embodiments, the sacrificial layer 130 and the photoresist 132 include a dielectric material, such as an oxide.
[0040] refer to Figure 4 , a portion of the sacrificial layer 130 and a portion of the first lower conductive layer 120 are removed. Specifically, the first portion 130-1 and the second portion 130-2 of the sacrificial layer 130 are removed. Also, the first portion 120-1 and the second portion 120-2 of the first lower conductive layer 120 are removed. The first portion 130-1 and the second portion 130-2 of the sacrificial layer 130 and the first portion 120-1 and the second portion 120-2 of the first lower conductive layer 120 may be removed using an appropriate directional dry etching process, such as plasma reactive etching, ion beam etching, etc.
[0041] refer to Figure 5 , a second lower conductive layer 140 is formed on the substrate 110. Specifically, a first portion 140-1 of the second lower conductive layer 140 is formed on the first array region R1 of the substrate 110. A second portion 140-2 of the second lower conductive layer 140 is formed on the second array region R2 of the substrate 110. A third portion 140-3 of the second lower conductive layer 140 is formed on the third portion 120-3 of the first lower conductive layer 120.
[0042] like Figure 5 As shown, the top surface of the third portion 140-3 of the second lower conductive layer 140 is higher than the top surface of the first portion 140-1 of the second lower conductive layer 140. The top surface of the first portion 140-1 of the second lower conductive layer 140 is higher than the top surface of the second portion 140-2 of the second lower conductive layer 140. In other words, the top surface of the second portion 140-2 of the second lower conductive layer 140 is the lowest. The second portion 140-2 forms a moat structure. The moat structure can reduce bit line structural defects in subsequent processes. As shown, the thickness T140-1 of the first portion 140-1, the thickness T140-2 of the second portion 140-2, and the thickness T140-3 of the third portion 140-3 are substantially the same.
[0043] In some embodiments, the second lower conductive layer 140 may be formed using an appropriate deposition process, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), etc. In some embodiments, the second lower conductive layer 140 includes a conductive material, such as polysilicon. In the present invention, the first lower conductive layer 120 and the second lower conductive layer 140 are formed of the same material. Therefore, the second lower conductive layer 140 and the third portion 120-3 of the first lower conductive layer 120 are collectively referred to as the lower conductive layer 142 hereinafter.
[0044] refer to Figure 6 , a hard mask layer 150 is formed on the lower conductive layer 142, and an opening is formed in the hard mask layer 150 to expose a portion of the lower conductive layer 142. The opening is formed in the first array region R1. Then, a portion of the lower conductive layer 142 is doped through the opening to form a doped lower conductive layer 144. The doped lower conductive layer 144 may include an N-type material, such as phosphorus, arsenic, antimony, bismuth, and other suitable materials.
[0045] refer to Figure 7 , an upper conductive layer 160 is formed on the lower conductive layer 142 and the doped lower conductive layer 144. The upper conductive layer 160 has the same thickness in the first array region R1, the second array region R2, and the peripheral region R3. Therefore, the top surface of the upper conductive layer 160 has the same shape as the top surface of the lower conductive layer 142 below. In some embodiments, the upper conductive layer 160 can be formed using a suitable deposition process, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), etc. In some embodiments, the upper conductive layer 160 includes a conductive material, such as a metal. For example, the upper conductive layer 160 may include tungsten.
[0046] refer to Figure 8 , a capping layer 170 is formed on the upper conductive layer 160. The capping layer 170 has the same thickness in the first array region R1, the second array region R2, and the peripheral region R3. Therefore, the top surface of the capping layer 170 has the same shape as the top surface of the upper conductive layer 160 below. In some embodiments, the capping layer 170 can be formed using an appropriate deposition process, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), etc. In some embodiments, the capping layer 170 includes a dielectric material, such as a nitride.
[0047] refer to Fig. 9, an etching process may be performed to form a first bit line structure 180 and a second bit line structure 182. The first bit line structure 180 includes a lower conductive layer 142, an upper conductive layer 160, and a capping layer 170. The second bit line structure 182 includes a doped lower conductive layer 144, an upper conductive layer 160, and a capping layer 170. As shown, a first angle θ1 between a sidewall of the lower conductive layer 142 of the first bit line structure 180 and a top surface of the substrate 110 is greater than 90 degrees. A second angle θ2 between a sidewall of the doped lower conductive layer 144 of the second bit line structure 182 and a top surface of the substrate 110 is substantially equal to 90 degrees. A third angle θ3 between the sidewalls of the lower conductive layer 142 in the peripheral region R3 is greater than 90 degrees, and the third angle θ3 is substantially equal to the first angle θ1. In some embodiments, the etching process may be an all-in-one (AIO) dry etching process. In other embodiments, the etching process may combine more than one dry etching process such that the capping layer 170 , the upper conductive layer 160 , the doped lower conductive layer 144 , and the lower conductive layer 142 are removed through different etching stages.
[0048] refer to Fig.10 , the first spacer 190 is formed on the sidewalls of the first bit line structure 180 and the sidewalls of the second bit line structure 182, respectively. The second spacer 192 is formed on the sidewalls of the first spacer 190. In some embodiments, the first spacer 190 and the second spacer 192 may be formed using a suitable deposition process, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), etc. In some embodiments, the first spacer 190 and the second spacer 192 may include a suitable dielectric material. For example, the first spacer 190 may include an oxide, and the second spacer 192 may include a nitride.
[0049] The present invention provides a method for manufacturing a semiconductor structure. In the method provided by the present invention, the lower conductive layer is formed by a first lower conductive layer and a second lower conductive layer. Therefore, the depth of the edge groove structure can be controlled. The performance of the AIO dry etching process can be improved, thereby reducing parasitic capacitance. Through the method of the present invention, the thickness of the lower conductive layer in the array area and the depth of the edge groove structure can be controlled, thereby reducing the difference between wafers and improving the overall performance.
[0050] Although the present invention has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.
[0051] It will be apparent to those skilled in the art that various modifications and variations may be made to the structure of the present invention without departing from the scope or spirit of the present invention. In view of the foregoing, the present invention is intended to cover modifications and variations of the present invention that fall within the scope of the appended claims.
[0052]
Explanation of symbols
[0053] 100:Semiconductor structure
[0054] 110:Substrate
[0055] 120: first lower conductive layer
[0056] 120-1: Part 1
[0057] 120-2: Part 2
[0058] 120-3: Part 3
[0059] 130: Sacrificial layer
[0060] 130-1: Part 1
[0061] 130-2: Part 2
[0062] 130-3: Part 3
[0063] 132: Photoresist
[0064] 140: second lower conductive layer
[0065] 140-1: Part 1
[0066] 140-2: Part 2
[0067] 140-3: Part 3
[0068] 142: Lower conductive layer
[0069] 144: doping lower conductive layer
[0070] 150: Hard mask layer
[0071] 160: Upper conductive layer
[0072] 170: Covering layer
[0073] 180: First bit line structure
[0074] 182: Second bit line structure
[0075] 190: first spacer
[0076] 192: Second spacer
[0077] AA:Line
[0078] R1: first array region
[0079] R2: Second array area
[0080] R3: Surrounding area
[0081] T120-1, T120-2, T120-3: Thickness
[0082] T140-1, T140-2, T140-3: Thickness
[0083] θ1: first angle
[0084] θ2: Second angle
[0085] θ3: the third angle.
Claims
1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate having a first array region, a second array region and a peripheral region, wherein the second array region surrounds the first array region, and the peripheral region surrounds the second array region; Forming a first lower conductive layer on the substrate, the first lower conductive layer continuously having a first portion located in the first array region, a second portion located in the second array region, and a third portion located in the peripheral region, wherein a top surface of the first portion is higher than a top surface of the second portion and a top surface of the third portion, and the top surface of the second portion is coplanar with the top surface of the third portion; removing the first portion of the first lower conductive layer and the second portion of the first lower conductive layer; and forming a second lower conductive layer on the substrate, the second lower conductive layer continuously having a first portion located in the first array region, a second portion located in the second array region, and a third portion located in the peripheral region; The top surface of the third portion of the second lower conductive layer is higher than the top surface of the first portion of the second lower conductive layer, and the first portion of the second lower conductive layer is higher than the top surface of the second portion of the second lower conductive layer, and the second lower conductive layer and the first lower conductive layer contain the same material so that the second lower conductive layer and the first lower conductive layer together form a lower conductive layer.
2. The method according to claim 1, characterized in that: Further including: Before removing the first portion of the first lower conductive layer and the second portion of the first lower conductive layer, forming a sacrificial layer on the first lower conductive layer, The sacrificial layer continuously comprises a first portion located in the first array region, a second portion located in the second array region and a third portion located in the peripheral region, wherein a top surface of the first portion is higher than a top surface of the second portion.
3. The method according to claim 1, characterized in that Before removing the first portion of the first lower conductive layer and the second portion of the first lower conductive layer, a photoresist is formed on the third portion of the first lower conductive layer.
4. The method according to claim 1, characterized in that The first lower conductive layer and the second lower conductive layer include polysilicon.
5. The method according to claim 1, characterized in that Further including: A portion of the lower conductive layer located in the first array region is doped to form a doped lower conductive layer.
6. The method according to claim 5, characterized in that Further including: An upper conductive layer is formed on the lower conductive layer and the doped lower conductive layer.
7. The method according to claim 6, characterized in that Further including: A capping layer is formed on the upper conductive layer.
8. The method according to claim 7, characterized in that Further including: Performing an etching process to form a first bit line structure and a second bit line structure in the first array region; The first bit line structure includes the cover layer, the upper conductive layer and the lower conductive layer; and The second bit line structure includes the capping layer, the upper conductive layer and the doped lower conductive layer.
9. The method according to claim 8, characterized in that A first angle between a sidewall of the lower conductive layer of the first bit line structure and the top surface of the substrate is different from a second angle between a sidewall of the doped lower conductive layer of the second bit line structure and the top surface of the substrate.
10. The method according to claim 8, characterized in that Further including: forming a first spacer on a sidewall of the first bit line structure and a sidewall of the second bit line structure; and A second spacer is formed on the first spacer of the first bit line structure and the first spacer of the second bit line structure.
11. A method for manufacturing a semiconductor structure, characterized in that: include: A substrate is provided, the substrate having a first array region, a second array region and a peripheral region, wherein a top surface of the substrate in the first array region is higher than a top surface of the substrate in the second array region and a top surface of the substrate in the peripheral region, and the top surface of the substrate in the second array region and the top surface of the substrate in the peripheral region are coplanar; Forming a first lower conductive layer on the substrate, the first lower conductive layer continuously having a first portion located in the first array region, a second portion located in the second array region, and a third portion located in the peripheral region, wherein the first portion, the second portion, and the third portion have the same thickness; removing the first portion of the first lower conductive layer and the second portion of the first lower conductive layer; and forming a second lower conductive layer on the substrate, the second lower conductive layer continuously having a first portion located in the first array region, a second portion located in the second array region, and a third portion located in the peripheral region, wherein the first portion, the second portion and the third portion of the second lower conductive layer have the same thickness, and The second lower conductive layer and the first lower conductive layer include polysilicon, so that the second lower conductive layer and the first lower conductive layer together form a lower conductive layer.
12. The method according to claim 11, characterized in that Further including: doping a portion of the lower conductive layer located in the first array region to form a doped lower conductive layer; forming an upper conductive layer on the lower conductive layer and the doped lower conductive layer; and A capping layer is formed on the upper conductive layer.
13. The method according to claim 12, characterized in that Further including: Performing an etching process to form a first bit line structure and a second bit line structure in the first array region; The first bit line structure includes the cover layer, the upper conductive layer and the lower conductive layer; and The second bit line structure includes the capping layer, the upper conductive layer and the doped lower conductive layer.
14. The method according to claim 13, characterized in that A first angle between a sidewall of the lower conductive layer of the first bit line structure and the top surface of the substrate is between 90 degrees and 180 degrees.
15. The method according to claim 13, characterized in that A second angle between a sidewall of the doped lower conductive layer of the second bit line structure and the top surface of the substrate is 90 degrees.