Memory structure and preparation method thereof

Abstract

The invention provides a memory structure and a preparation method thereof. The method comprises the following steps: providing a substrate; depositing a floating gate layer on one side of the substrate; etching the floating gate layer to form a plurality of floating gate structures; a plurality of separated floating gates are formed through photoetching, a gap is formed between every two adjacent floating gates, the section of each floating gate is of a trapezoidal structure, the upper bottom of each trapezoidal structure faces the corresponding gap, and the lower bottom of each trapezoidal structure faces the corresponding selection gate; performing ion implantation on the substrate in alignment with a gap position between the floating gates to form a source end; a control gate is formed on one side of the source end, the control gate is located between every two adjacent floating gates, and the two floating gates located on the two sides of the control gate are symmetrically arranged relative to the control gate. The data retention capability of the memory is improved by changing the shape of the floating gate, damage to the tunneling oxide layer during source end ion implantation is avoided, part of existing process steps are reduced, the quality of the memory is improved, and the preparation efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor device technology, and in particular to a memory structure and a method for preparing the same. Background Art

[0002] Embedded Flash (eflash) memory cells have been playing an increasingly important role in the field of non-volatile memory due to their low cost, low power consumption, fast access speed and other performance advantages. With the continuous expansion of technology nodes, the important performance requirements of eflash memory include high density, high performance and high reliability. Data retention capability is the most important reliability parameter of eflash memory. Data loss is usually caused by the transfer of electrons through the dielectric layer around the floating gate, which causes the threshold voltage of the floating gate to change, resulting in a change in the floating gate channel read current, that is, read information errors.

[0003] Figure 1 It is a 1.5T eflash memory device structure. The left and right bits are symmetrical and can be read and written separately. The two bits share the same source (CS), control gate (CG) and erase gate (EP). Among them, the floating gate (FG) is formed by the sidewall etching process of the select gate (SG). The floating gate is triangular in shape. It is programmed by channel hot electron injection (CHEI) and erased by the top corner Fowler-Nordheim (FN) tunneling. There are strict requirements for the height and channel length of the floating gate, and its etching process window is related to the trench depth-to-width ratio of SG. At 65nm and below nodes, the left and right floating gates are prone to bridge defects (referring to the unexpected connection between the floating gate and other electrodes or adjacent structures), resulting in crosstalk between the left and right bits during programming operations. Since the floating gate is thinner as it gets closer to the source, the ion implantation process at the source will inevitably penetrate the sidewall (SIN) on one side of the floating gate and the tunnel oxide layer (Tunnel Oxide) below the floating gate damage. After programming, the electrons in the floating gate will tunnel to the substrate through the traps in the tunnel oxide layer, resulting in the loss of stored information.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] In response to the problems in the prior art, the purpose of the present application is to provide a memory structure and a method for preparing the same, which improves the data retention capability of the memory by changing the shape of the floating gate, avoids damage to the tunneling oxide layer during source ion implantation, and reduces some of the existing process steps, thereby improving the quality of the memory and the preparation efficiency.

[0006] The present application provides a memory structure, including:

[0007] Providing a substrate, wherein a select gate is formed on one side of the substrate;

[0008] depositing a floating gate layer on one side of the substrate;

[0009] Etching the floating gate layer to remove the floating gate layer on one side of the select gate to form a plurality of floating gate structures;

[0010] Coating photoresist on one side of the floating gate structure and the select gate, forming a plurality of separated floating gates by photolithography, and forming a gap between every two adjacent floating gates, wherein the cross section of the floating gate is a trapezoidal structure, the upper bottom of the trapezoidal structure faces the gap, and the lower bottom of the trapezoidal structure faces the select gate;

[0011] Aligning the gap between the floating gates, ion implantation is performed on the substrate to form a source terminal;

[0012] A control gate is formed on one side of the source end. The control gate is located between every two adjacent floating gates. The two floating gates located on both sides of the control gate are symmetrically arranged relative to the control gate.

[0013] In some embodiments, etching the floating gate layer to remove the floating gate layer on one side of the select gate includes the following steps:

[0014] Spin coating a bottom anti-reflective coating on a side of the floating gate layer facing away from the substrate;

[0015] The floating gate layer is etched using the select gate as an etch stop layer to remove the floating gate layer on one side of the select gate.

[0016] In some embodiments, after the floating gate layer is etched to remove the floating gate layer on one side of the select gate, the top surface of the floating gate structure between two adjacent select gates is in the shape of an arc with a depression in the middle.

[0017] In some embodiments, after the floating gate layer is etched to remove the floating gate layer on one side of the select gate, the floating gate thickness of the concave portion in the middle of the top surface of the floating gate structure between two adjacent select gates is 800 Å to 1200 Å.

[0018] In some embodiments, photoresist is coated on one side of the floating gate layer and the select gate, and a plurality of separated floating gates are formed by photolithography, including the following steps:

[0019] Performing a surface planarization process on a side of the floating gate structure facing away from the substrate to form a planarization layer;

[0020] A layer of photoresist is coated on the flat surface of the planarization layer, and after the photoresist is exposed and developed, the photoresist forms a through hole corresponding to the center position of each floating gate structure;

[0021] The floating gate structures are etched to divide each of the floating gate structures into two floating gates that are separated and symmetrically arranged.

[0022] In some embodiments, the planarization layer includes a spin-on carbon layer located on a side of the floating gate structure facing away from the substrate and a silicon-based anti-reflective coating located on a side of the spin-on carbon layer facing away from the substrate;

[0023] Etching the floating gate structure comprises the following steps:

[0024] Using the spin-on carbon layer as an etching stop layer, etching the silicon-based anti-reflective coating;

[0025] Using the floating gate structure as an etching stop layer, etching the spin-on carbon layer;

[0026] The floating gate structure is etched using the tunneling oxide layer on one side of the substrate as an etching stop layer.

[0027] In some embodiments, the floating gate thickness corresponding to the upper bottom of the trapezoidal structure of the floating gate is greater than or equal to 800 Å.

[0028] The embodiment of the present application further provides a memory structure, including a plurality of storage units, wherein the memory structure includes:

[0029] A substrate, wherein a source terminal is provided in the substrate, wherein two adjacent storage units share one source terminal;

[0030] A control gate located at one side of the source end, wherein every two adjacent storage cells share one control gate;

[0031] A floating gate located on one side of the substrate, wherein the floating gates of every two adjacent memory cells are symmetrically arranged relative to the control gate, and the cross-section of the floating gate is a trapezoidal structure, with the upper bottom side of the trapezoidal structure facing the control gate;

[0032] The selection gate is located on one side of the substrate and on the lower side of the trapezoidal structure of the floating gate.

[0033] In some embodiments, an erase gate is further included, and the erase gate is located on a side of the control gate away from the source end, wherein two adjacent storage cells share one erase gate.

[0034] In some embodiments, the cross-section of the control gate is a T-shaped structure.

[0035] The memory structure and preparation method thereof provided in this application have the following advantages:

[0036] By adopting the memory structure and preparation method of the present application, the data retention capability of the memory is improved by changing the shape of the floating gate, and damage to the tunneling oxide layer during source ion implantation is avoided. There is no need to adopt a sidewall structure to protect the tunneling oxide layer, which reduces some of the existing process steps, saves furnace tube deposition and dry etching processes, improves the quality of the memory, and improves the preparation efficiency and reduces the manufacturing cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The accompanying drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present invention, and together with the specification are used to explain the principles of the present invention. Obviously, the accompanying drawings described below are only some embodiments of the present invention, and for those of ordinary skill in the art, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0038] Figure 1 It is a schematic diagram of a memory structure in the prior art;

[0039] Figures 2 to 5 It is a schematic diagram of a preparation process of a memory structure in the prior art;

[0040] Figure 6 It is a schematic diagram of a floating grating mask layout in the prior art;

[0041] Figure 7 is a schematic diagram of a memory structure according to an embodiment of the present application;

[0042] Figure 8 is a flow chart of a method for preparing a memory structure according to an embodiment of the present application;

[0043] Figures 9 to 14 is a schematic diagram of a preparation process of a memory structure according to an embodiment of the present application;

[0044] Fig.15 Schematic diagram of a floating grating mask layout according to an embodiment of the present application. DETAILED DESCRIPTION

[0045] The example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as being limited to the embodiments set forth herein; on the contrary, these embodiments are provided so that the present application will be comprehensive and complete, and the concept of the example embodiments will be fully conveyed to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their repeated descriptions will be omitted. "Or" and "or" in the specification may both represent "and" or "or". Spatial relationship terms such as "on..." and the like can be used here to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of devices in use and operation. For example, if the device in the drawings is flipped, the element or feature described as "on..." will be oriented to be "under..." other elements or features. Therefore, the exemplary term "on..." may include both upper and lower orientations. In addition, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptions used herein are interpreted accordingly.

[0046] When used herein, the singular forms "a", "an" and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items. Although "first" or "second" etc. are used in this specification to represent certain features, they are only used to represent the role, and are not used as a limitation on the number and importance of specific features.

[0047] Figure 1 It is a schematic diagram of a memory structure in the prior art. Figures 2 to 5 FIG. 1 is a schematic diagram of a preparation process of a memory structure in the prior art. POLY in the figure represents a structure prepared from a polymer material. Figure 1 As shown in the figure, two bits share the same source terminal (Common Source, CS), control gate (Control Gate, CG) and erase gate (Erase Poly, EP). Among them, the floating gate (Floating Gate, FG) is formed by the sidewall etching process of the select gate (Select Gate, SG). The floating gate is in a triangular shape. It is programmed by channel hot electron injection (CHEI) and erased by the top corner Fowler-Nordheim (FN) tunneling. Figure 2 As shown in FIG. 1 , a floating gate layer is formed on one side of the substrate. Figure 3As shown, the floating gate layer is etched by the select gate (SG) sidewall etching process to form a floating gate (FG). The cross section of the floating gate is a triangular structure, which is programmed by channel hot electron injection (CHEI) and erased by the top corner Fowler-Nordheim (FN) tunneling. Figure 4 As shown, after etching to form the floating gate, a Nitride (SIN, silicon nitride) sidewall structure is made to control the diffusion rate of the source end. Figure 5 As shown in the figure, the source terminal (CS) is formed by ion implantation (IMP). Since the floating gate is thinner as it is closer to the source terminal, the ion implantation process at the source terminal will inevitably penetrate the sidewall structure and the floating gate and damage the tunnel oxide layer underneath. After programming, the electrons in the floating gate will tunnel to the substrate through the traps in the tunnel oxide layer, resulting in the loss of stored information.

[0048] In order to solve the technical problems in the prior art, the present application provides a memory structure and a method for preparing the same. In one embodiment, the memory structure includes a plurality of memory cells. Figure 7 As shown, the memory structure includes:

[0049] A substrate, wherein a source terminal is provided in the substrate, wherein two adjacent storage units share one source terminal; Figure 7 In the figure, CS represents the source terminal, BL represents the bit line, and the arrow represents the flow direction of electrons e in the memory structure;

[0050] A control gate located at one side of the source end, wherein every two adjacent storage cells share one control gate; Figure 7 In the embodiment, the control gate is represented by CG; in this embodiment, the cross section of the control gate is a T-shaped structure, which is different from the inverted trapezoidal structure of the existing control gate;

[0051] A floating gate located on one side of the substrate, wherein the floating gates of every two adjacent memory cells are symmetrically arranged relative to the control gate, and the cross-section of the floating gate is a trapezoidal structure, with the upper bottom side of the trapezoidal structure facing the control gate; Figure 7 In the example, the floating gates of every two adjacent memory cells are represented as FG1 and FG2 respectively;

[0052] A selection gate is located on one side of the substrate and on a lower side of the trapezoidal structure of the floating gate; Figure 7 In the figure, the selection gate is represented by SG, and the selection gates of every two adjacent memory cells are represented by SG1 and SG2 respectively.

[0053] like Figure 7As shown, the memory structure further includes an erase gate, which is located on a side of the control gate away from the source end, wherein two adjacent storage cells share one erase gate. Figure 7 Indicated by EP.

[0054] By adopting this memory structure, the data retention capability of the memory is improved by changing the shape of the floating gate, and the damage to the tunneling oxide layer during source ion implantation is avoided. The quality of the memory is improved, and the crosstalk problem between the left and right adjacent memory cells caused by the bridge defect of the floating gate is reduced.

[0055] like Figure 8 As shown, in one embodiment, the method for preparing the memory structure includes the following steps:

[0056] S100: providing a substrate, wherein a select gate is formed on one side of the substrate;

[0057] S200: depositing a floating gate layer on one side of the substrate;

[0058] S300: etching the floating gate layer to remove the floating gate layer on one side of the select gate to form a plurality of floating gate structures;

[0059] S400: coating a photoresist on one side of the floating gate structure and the select gate, forming a plurality of separated floating gates by photolithography, and forming a gap between every two adjacent floating gates, wherein the cross section of the floating gate is a trapezoidal structure, the upper bottom of the trapezoidal structure faces the gap, and the lower bottom of the trapezoidal structure faces the select gate;

[0060] S500: Aligning the gap between the floating gates, and performing ion implantation on the substrate to form a source terminal;

[0061] S600: forming a control gate at one side of the source end, wherein the control gate is located between every two adjacent floating gates, and the two floating gates located on both sides of the control gate are symmetrically arranged relative to the control gate.

[0062] By adopting the preparation method of the memory structure of the present application, the data retention capability of the memory is improved by changing the shape of the floating gate, and the damage to the tunneling oxide layer during source ion injection is avoided. There is no need to adopt a sidewall structure to protect the tunneling oxide layer, which reduces some of the existing process steps, saves furnace tube deposition and dry etching processes, improves the quality of the memory, and improves the preparation efficiency and reduces the manufacturing cost.

[0063] In this embodiment, the step S300 of etching the floating gate layer to remove the floating gate layer on one side of the select gate includes the following steps:

[0064] Spin coating a bottom anti-reflective coating (BARC) on a side of the floating gate layer facing away from the substrate;

[0065] The floating gate layer is etched using the select gate as an etch stop layer to remove the floating gate layer on one side of the select gate.

[0066] In this embodiment, the floating gate layer is etched to remove the floating gate layer on one side of the selection gate, and the top surface of the floating gate structure between the two adjacent selection gates is an arc shape with a depression in the middle. Optionally, the floating gate thickness of the depressed portion in the middle of the top surface of the floating gate structure between the two adjacent selection gates is 800A to 1200A. Thus, the floating gate thickness corresponding to the upper bottom of the trapezoidal structure of the floating gate is greater than or equal to 800A, so there is no need to use a SIN side wall to protect the tunneling oxide layer, which saves the furnace tube deposition and dry etching process when forming the SIN side wall in the prior art, and the preparation method is simpler and the preparation efficiency is higher. The size of the floating gate is only an example and is not intended to limit the scope of protection of this application.

[0067] In this embodiment, the step S400: coating a photoresist on one side of the floating gate layer and the select gate, and forming a plurality of separated floating gates by photolithography, comprises the following steps:

[0068] A surface planarization process is performed on a side of the floating gate structure facing away from the substrate to form a planarization layer; in this embodiment, the planarization layer includes a spin-on carbon layer (SOC) located on a side of the floating gate structure facing away from the substrate and a silicon-based anti-reflection coating (Si-ARC) located on a side of the spin-on carbon layer facing away from the substrate;

[0069] A layer of photoresist is coated on the flat surface of the planarization layer, and after the photoresist is exposed and developed, the pattern on the floating gate mask is transferred to the floating gate photoresist, and the photoresist forms a through hole corresponding to the center position of each floating gate structure;

[0070] The floating gate structures are etched to divide each of the floating gate structures into two floating gates that are separated and symmetrically arranged.

[0071] Figure 6 This is a schematic diagram of a floating gate mask layout in the prior art. After etching the floating gate layer through the sidewall etching process, the floating gate above the trench isolation (STI) in the Bit Line (BL) direction is cut off through photolithography and dry etching processes to form repeated independent memory structures. Fig.14 is a schematic diagram of the floating grating mask layout used in this application, Fig.14The FG in the figure represents a floating gate mask, which corresponds to the structure after the photoresist is exposed and developed. The floating gate mask of the present application not only cuts off the floating gate layer of the shallow trench isolation in the bit line direction, but also opens the floating gate layer above the corresponding source end in the select gate direction. This design is conducive to increasing the process window for etching the floating gate sidewall, improving the bridge defect of the floating gate, and can solve the crosstalk problem between the left and right adjacent storage cells. In addition, the spacing size of the trapezoidal floating gate in the bit line direction is defined by the floating gate mask, and no additional SIN sidewall structure is required to adjust. The present application can cancel the source end SIN sidewall deposition and dry etching process, saving manufacturing cost and manufacturing time. The present application optimizes the layout on the existing floating gate mask without adding an additional mask, and reduces some of the original process steps.

[0072] In this embodiment, etching the floating gate structure includes the following steps:

[0073] Using the spin-on carbon layer as an etching stop layer, etching the silicon-based anti-reflective coating;

[0074] Using the floating gate structure as an etching stop layer, etching the spin-on carbon layer;

[0075] The floating gate structure is etched using the tunneling oxide layer on one side of the substrate as an etching stop layer.

[0076] Combine the following Figures 9 to 14 The implementation process of a method for preparing a memory structure in a specific embodiment is introduced.

[0077] like Fig. 9 As shown, corresponding to step S100, a substrate is provided, and a selection gate is formed on one side of the substrate; the selection gates of two adjacent memory cells are Fig. 9 Corresponding to step S200, a floating gate layer is deposited on one side of the substrate. Fig. 9 The step of depositing the floating gate layer specifically includes: using a furnace tube LPCVD (Low-Pressure Chemical Vapor Deposition, low pressure chemical vapor deposition) process to grow amorphous silicon poly with a thickness of 1300-2000A to form a floating gate layer.

[0078] like Fig.10 As shown, a bottom anti-reflection coating with a thickness of about 800-1000 Å is spin-coated on the top surface of the floating gate layer to planarize the wafer surface.

[0079] like Fig.11As shown, corresponding to step S300, the floating gate layer is etched to remove the floating gate layer on one side of the select gate to form multiple floating gate structures, specifically including: performing dry etching on the entire wafer, removing the floating gate layer above the select gate with a high selectivity etching gas (poly to oxide selectivity greater than 8:1), and using the TEOS oxide layer (a silicon dioxide layer formed on the substrate surface by chemical vapor deposition or other deposition techniques using tetraethyl orthosilicate as a precursor) above the select gate as an etching stop layer, while retaining a floating gate structure with a thickness range of 800-1200A in two adjacent select gate trenches. The top surface of the floating gate structure is a circular arc surface with a downward depression in the center.

[0080] like Fig.12 and Fig.13 As shown, corresponding to step S400, a tri-layer process is first used to flatten the wafer surface, specifically, a spin-coated carbon layer with a thickness of about 2500-3000A is firstly spin-coated, and then a silicon-based anti-reflective coating layer with a thickness of about 200-400A is spin-coated. Photoresist is coated on one side of the floating gate structure and the select gate, and a plurality of separated floating gates are formed by photolithography, and a gap is formed between every two adjacent floating gates. The cross-section of the floating gate is a trapezoidal structure, the upper bottom of the trapezoidal structure faces the gap, and the lower bottom of the trapezoidal structure faces the select gate. The floating gates of two adjacent storage cells are at Fig.13 They are represented by FG1 and FG2 respectively.

[0081] After exposure and development are completed, the floating gate structure is dry-etched, firstly, the spin-coated carbon layer is used as an etching stop layer to etch the silicon-based anti-reflective coating (the selectivity of the spin-coated carbon is greater than 4:1); the floating gate structure is used as an etching stop layer, and the gas is switched to etch the spin-coated carbon layer (the selectivity of the poly is greater than 50:1); the tunneling oxide layer on one side of the substrate is used as an etching stop layer, and the gas is switched to etch the floating gate structure, and the floating gate on the shallow trench isolation in the bit line direction and the floating gate above the source end position in the floating gate direction are opened.

[0082] like Fig.14 As shown, after the floating gate etching step is completed, the photoresist will be removed, and then corresponding to step S500, the gap between the floating gates is aligned, and ion implantation is performed on the substrate to form a source terminal. Since the thinnest position of the floating gate is also about 800A, there is no need to set a SIN sidewall to protect the tunnel oxide layer, saving furnace tube deposition and dry etching processes.

[0083] S600: forming a control gate at one side of the source end, wherein the control gate is located between every two adjacent floating gates, and the two floating gates located on both sides of the control gate are symmetrically arranged relative to the control gate.

[0084] In summary, the memory structure and preparation method thereof provided in this application have the following advantages:

[0085] By adopting the memory structure and preparation method of the present application, the data retention capability of the memory is improved by changing the shape of the floating gate, and damage to the tunneling oxide layer during source ion implantation is avoided. There is no need to adopt a sidewall structure to protect the tunneling oxide layer, which reduces some of the existing process steps, saves furnace tube deposition and dry etching processes, improves the quality of the memory, and improves the preparation efficiency and reduces the manufacturing cost.

[0086] The above content is a further detailed description of the present application in combination with specific preferred implementation methods, and it cannot be determined that the specific implementation of the present application is limited to these descriptions. For ordinary technicians in the technical field to which the present application belongs, several simple deductions or substitutions can be made without departing from the concept of the present application, which should be deemed to fall within the scope of protection of the present application.

Claims

1. A method for preparing a memory structure, characterized in that: The steps include: Providing a substrate, wherein a select gate is formed on one side of the substrate; depositing a floating gate layer on one side of the substrate; Etching the floating gate layer to remove the floating gate layer on one side of the select gate to form a plurality of floating gate structures; A photoresist is coated on one side of the floating gate structure and the select gate, and a plurality of separated floating gates are formed by photolithography, and a gap is formed between every two adjacent floating gates, and the cross section of the floating gate is a trapezoidal structure, the upper bottom of the trapezoidal structure faces the gap, and the lower bottom of the trapezoidal structure faces the select gate; Aligning the position of the gap between the floating gates, and performing ion implantation on the substrate to form a source terminal; A control gate is formed on one side of the source end, the control gate is located between every two adjacent floating gates, and the two floating gates located on both sides of the control gate are symmetrically arranged relative to the control gate.

2. The method for preparing a memory structure according to claim 1, characterized in that: Etching the floating gate layer to remove the floating gate layer on one side of the select gate comprises the following steps: Spin coating a bottom anti-reflective coating on a side of the floating gate layer facing away from the substrate; The floating gate layer is etched using the select gate as an etch stop layer to remove the floating gate layer on one side of the select gate.

3. The method for preparing a memory structure according to claim 1, characterized in that: After the floating gate layer is etched to remove the floating gate layer on one side of the select gate, the top surface of the floating gate structure between two adjacent select gates is in an arc shape with a depression in the middle.

4. The method for preparing a memory structure according to claim 3, characterized in that: After the floating gate layer is etched to remove the floating gate layer on one side of the select gate, the floating gate thickness of the concave portion in the middle of the top surface of the floating gate structure between two adjacent select gates is 800 Å to 1200 Å.

5. The method for preparing a memory structure according to claim 1, characterized in that: A photoresist is coated on one side of the floating gate structure and the select gate, and a plurality of separated floating gates are formed by photolithography, comprising the following steps: Performing a surface planarization process on a side of the floating gate structure facing away from the substrate to form a planarization layer; A layer of photoresist is coated on the flat surface of the planarization layer, and after the photoresist is exposed and developed, the photoresist forms a through hole corresponding to the center position of each floating gate structure; The floating gate structures are etched to divide each of the floating gate structures into two floating gates that are separated and symmetrically arranged.

6. The method for preparing a memory structure according to claim 5, characterized in that: The planarization layer includes a spin-on carbon layer located on a side of the floating gate structure facing away from the substrate and a silicon-based anti-reflection coating located on a side of the spin-on carbon layer facing away from the substrate; Etching the floating gate structure comprises the following steps: Using the spin-on carbon layer as an etching stop layer, etching the silicon-based anti-reflective coating; Using the floating gate structure as an etching stop layer, etching the spin-on carbon layer; The floating gate structure is etched using the tunneling oxide layer on one side of the substrate as an etching stop layer.

7. The method for preparing a memory structure according to claim 1, characterized in that: The floating gate thickness corresponding to the upper bottom of the trapezoidal structure of the floating gate is greater than or equal to 800 Å.

8. A memory structure, characterized in that: Comprising a plurality of storage units, the memory structure comprises: A substrate, wherein a source terminal is provided in the substrate, wherein two adjacent storage units share one source terminal; A control gate located at one side of the source end, wherein every two adjacent storage cells share one control gate; A floating gate located on one side of the substrate, wherein the floating gates of every two adjacent memory cells are symmetrically arranged relative to the control gate, and the cross-section of the floating gate is a trapezoidal structure, with the upper bottom side of the trapezoidal structure facing the control gate; The selection gate is located on one side of the substrate and on the lower side of the trapezoidal structure of the floating gate.

9. The memory structure according to claim 8, characterized in that: It also includes an erase gate, which is located on a side of the control gate away from the source end, wherein two adjacent storage units share one erase gate.

10. The memory structure according to claim 8, characterized in that: The cross section of the control gate is a T-shaped structure.

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