Storage device

Abstract

The memory device may include: a substrate; a semiconductor chip on the substrate; a housing including a plurality of heat dissipation fins, a cavity, and a capacitor module, the capacitor module configured to be electrically connected to the substrate, the plurality of heat dissipation fins configured to be electrically connected to the substrate, the plurality of heat dissipation fins being arranged in a first direction and spaced apart from each other in a second direction perpendicular to the first direction; and an upper cover on the housing. The capacitor module may include a capacitor in the cavity, and the capacitor may be configured to supply power to the substrate.

Description

[0001] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0147065 filed on October 30, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The inventive concept relates to a memory device, and more particularly, to a memory device including a removable capacitor module. Background Art

[0003] Generally, a storage device including a memory device and a memory controller operates using power supplied from the outside. A sudden power outage (SPO) may occur in which power is suddenly cut off while the storage device is operating. At this time, the memory controller stores data by using a volatile memory, and therefore, the data stored in the volatile memory may be lost, or the current operation (e.g., an erase operation, a write operation, etc.) of the memory device may not be completed. In this case, the storage device completes the current operation and performs data backup by using an auxiliary power supply including a capacitor. Summary of the invention

[0004] The inventive concept provides a storage device capable of ensuring a space on a substrate of the storage device by arranging a capacitor module in a housing of the storage device, wherein the capacitor module can be obtained by modularizing a capacitor on the substrate of the storage device. A semiconductor chip can be arranged in the ensured space, and thus the capacity of the storage device can be increased.

[0005] The inventive concept also provides a memory device capable of reducing manufacturing costs by adjusting the number of capacitors included in the memory device using a removable capacitor module.

[0006] Aspects of the inventive concept are not limited to those mentioned above, and unmentioned aspects of the inventive concept will be clearly understood by those skilled in the art from the following description.

[0007] According to an embodiment of the inventive concept, a storage device may include: a substrate; a semiconductor chip on the substrate; a housing including a plurality of heat dissipation fins, a cavity, and a capacitor module, the capacitor module being configured to be electrically connected to the substrate, the plurality of heat dissipation fins being arranged in a first direction and spaced apart from each other in a second direction perpendicular to the first direction; and an upper cover on the housing. The capacitor module may include a capacitor in the cavity, and the capacitor may be configured to supply power to the substrate.

[0008] According to an embodiment of the inventive concept, a storage device may include: a substrate; a first semiconductor chip on a top surface of the substrate; a second semiconductor chip on a bottom surface of the substrate; a housing including a plurality of heat dissipation fins, a cavity, and a capacitor module, the capacitor module being configured to be electrically connected to the substrate, the plurality of heat dissipation fins being arranged in a first direction and spaced apart from each other in a second direction perpendicular to the first direction; and an upper cover on the housing. The capacitor module may include a capacitor in the cavity, and the capacitor may be configured to supply power to the substrate.

[0009] According to an embodiment of the inventive concept, a storage device may include: a substrate; a semiconductor chip on the substrate; an upper housing including a plurality of heat dissipation fins, a cavity, and a capacitor module, the capacitor module being configured to be electrically connected to the substrate, the plurality of heat dissipation fins being arranged in a first direction and spaced apart from each other in a second direction perpendicular to the first direction; a lower housing configured to be coupled to the upper housing; and an upper cover on the upper housing. The substrate may be in the lower housing. The capacitor module may include a capacitor in the cavity. The upper housing may be configured to be coupled to the lower housing and allow power to be supplied to the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0011] Figures 1 to 3 is a diagram of a storage device according to an embodiment.

[0012] Figure 4 is a cross-sectional view of a storage device according to an embodiment.

[0013] Figure 5 is a cross-sectional view of a storage device according to an embodiment.

[0014] Figure 6 is a diagram illustrating a capacitor module according to an embodiment.

[0015] Figure 7 is a cross-sectional view of a storage device according to an embodiment.

[0016] Figure 8 is a cross-sectional view of a storage device according to an embodiment.

[0017] Fig. 9 is a cross-sectional view of a storage device according to an embodiment.

[0018] Fig.10 is a diagram of a system including a storage device according to an embodiment.

[0019] Fig.11 is a block diagram of an example of applying a storage device to a solid state drive (SSD) system according to an embodiment. DETAILED DESCRIPTION

[0020] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. Unless the context clearly indicates otherwise, the singular forms are intended to include the plural forms as well.

[0021] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings. In the accompanying drawings, the same reference symbols represent the same elements, and redundant descriptions thereof will be omitted.

[0022] Figures 1 to 3 is a diagram of a storage device according to an embodiment. In detail, Figure 1 is a perspective view of a storage device 10 according to an embodiment. Figure 2 is an exploded perspective view of the storage device 10 according to the embodiment. Figure 3 is a plan view illustrating the storage device 10 from which the upper cover 150 is removed according to the embodiment.

[0023] Reference Figures 1 to 3 , the storage device 10 may include a housing 100 , a base 140 and an upper cover 150 .

[0024] The storage device 10 may operate using power provided from the outside. Here, the mode in which the storage device 10 operates using power provided from the outside may be referred to as a normal power mode. A sudden power outage (SPO) may occur in which power is suddenly cut off while the storage device 10 is operating. At this time, data stored in the storage device 10 may be lost, or the current operation of the storage device 10 (e.g., an erase operation, a write operation, etc.) may not be completed. In this case, the storage device 10 may use an auxiliary power supply to perform operations. The storage device 10 may include a power-off protection (PLP) integrated circuit (IC). Here, the mode in which the storage device 10 operates using power from the auxiliary power supply may be referred to as an auxiliary power mode. The auxiliary power supply may represent the first capacitor module 120_1 to the fourth capacitor module 120_4.

[0025] The housing 100 may include an upper housing 100U and a lower housing 100L. The upper housing 100U may be (e.g., removably) coupled to the lower housing 100L and may allow power to be supplied to the substrate 140. The housing 100 may include a material having a high thermal conductivity suitable for releasing heat generated from a component (e.g., a semiconductor chip 142) in the housing 100 to the outside of the housing 100. The housing 100 may be composed of a single material or a combination of different materials. The housing 100 may include a metal, a carbon-based material, a polymer, or a combination thereof. For example, the housing 100 may include copper (Cu), aluminum (Al), zinc (Zn), tin (Sn), stainless steel, or a composite metal including the same. For example, the housing 100 may include graphite, graphene, carbon fiber, or a carbon nanotube composite material. For example, the housing 100 may include epoxy resin, polymethyl methacrylate (PMMA), polycarbonate (PC), polyethylene (PE), or polypropylene (PP).

[0026] The upper housing 100U may include first to fourth cavities 110_1 to 110_4 , first to fourth capacitor modules 120_1 to 120_4 , and a heat dissipation structure 130 .

[0027] In one embodiment, the upper housing 100U may include at least one cavity. Figure 2 and Figure 3 1 to 110_4, but fewer or more cavities may be included in the upper housing 100U. The upper housing 100U may also include at least one capacitor module. Figure 2 and Figure 3 Four capacitor modules (eg, 120_1 to 120_4 ) are shown in FIG. 1 , but fewer or more capacitor modules may be included in the upper case 100U.

[0028] The first to fourth cavities 110_1 to 110_4 may be formed in the upper case 100U. The depths of the first to fourth cavities 110_1 to 110_4 (eg, the lengths of the first to fourth cavities 110_1 to 110_4 in the third direction D3 as the vertical direction of the case 100) may be smaller than the length of the upper case 100U in the third direction D3.

[0029] The first to fourth capacitor modules 120_1 to 120_4 may be electrically connected to the substrate 140. In detail, the capacitor included in each capacitor module may be electrically connected to the substrate 140 via a lead of the capacitor passing through a hole formed in the upper case 100U to contact the substrate 140. In one embodiment, the capacitor included in each capacitor module may supply power to the substrate 140.

[0030] In one embodiment, when SPO occurs, the storage device 10 may operate in the auxiliary power mode. In other words, the storage device 10 may use the energy stored in the first to fourth capacitor modules 120_1 to 120_4 to complete the current operation, thereby limiting and / or preventing the loss of data to be stored in the storage device 10.

[0031] The first capacitor module 120_1 may include a first capacitor 121_1 and a first housing 122_1. The first capacitor 121_1 may store energy required to operate the storage device 10 in the SPO situation. In one embodiment, the first housing 122_1 may accommodate the first capacitor 121_1. The first housing 122_1 may include a lock, and the first capacitor 121_1 may be fixed via the lock. The configuration of each of the second to fourth capacitor modules 120_2 to 120_4 may be the same as that of the first capacitor module 120_1 (for example, similarly, the second capacitor module 120_2 may include a second capacitor 121_2 and a second housing 122_2, the third capacitor module 120_3 may include a third capacitor 121_3 and a third housing 122_3, and the fourth capacitor module 120_4 may include a fourth capacitor 121_4 and a fourth housing 122_4), and therefore, repeated descriptions thereof are omitted. Each of the first to fourth capacitor modules 120_1 to 120_4 may include various components (such as a fixing pad, an adhesive member, and a spring pin) in addition to the housing. Figures 4 to 9 Embodiments of the first to fourth capacitor modules 120_1 to 120_4 are described.

[0032] In one embodiment, the first to fourth capacitor modules 120_1 to 120_4 may be configured to be attachable to and detachable from the upper housing 100U. For example, the energy required by the storage device 10 in the SPO situation may be sufficiently provided by a single capacitor module. In this case, the manufacturer of the storage device 10 may release the storage device 10 after removing the second to fourth capacitor modules 120_2 to 120_4 except the first capacitor module 120_1 during the production process of the storage device 10. As described above, by adjusting the number of capacitor modules required in the storage device 10, the manufacturing cost of the storage device 10 may be reduced.

[0033] The heat dissipation structure 130 may include a plurality of heat dissipation fins 131. Heat from the plurality of semiconductor chips 142 may be dissipated to the outside through the heat dissipation structure 130. Heat from the semiconductor chips 142 may be dissipated to the outside through a heat path formed in the memory device 10.

[0034] Each of the heat dissipation fins 131 may extend in the first direction D1. The heat dissipation fins 131 may be spaced apart from each other in a second direction D2 perpendicular to the first direction D1.

[0035] In one embodiment, the heat generated in each semiconductor chip 142 may be dissipated to the outside through a thermal path from the semiconductor chip 142 to the bottom surface of the upper housing 100U, the heat dissipation fins 131, and the upper cover 150. In one embodiment, a thermal interface material (TIM) may be disposed on the top surface of each semiconductor chip 142. For example, the TIM may include thermal paste, thermal adhesive, gap filler, or thermal pad.

[0036] The substrate 140 may be arranged inside the housing 100. In one embodiment, the substrate 140 may be arranged in the lower housing 100L. The substrate 140 may include a printed circuit board (PCB). For example, the substrate 140 may include a double-sided PCB or a multi-layer PCB. For example, the substrate 140 may include a base layer and wiring layers formed in the top surface and the bottom surface of the base layer, respectively. The base layer may include at least one material selected from the group consisting of phenolic resin, epoxy resin and polyimide. The wiring layer may include a conductive material (e.g., aluminum (Al), copper (Cu), nickel (Ni) or tungsten (W)). The semiconductor chip 142 and the electronic components mounted on the substrate 140 may be electrically connected to each other through the wiring layer of the substrate 140. At least one semiconductor chip 142 may include a controller chip and a memory semiconductor chip. Each semiconductor chip 142 may be referred to as a semiconductor package.

[0037] The controller chip may control the memory semiconductor chip. The control circuit unit may be embedded in the controller chip. The control circuit unit of the controller chip may control access to data stored in the memory semiconductor chip. The control circuit unit of the controller chip may control a write operation or a read operation of a flash memory or the like according to a control command of an external host. The control circuit unit of the controller chip may be constructed as a separate control semiconductor chip (e.g., an application specific IC (ASIC)). For example, when the storage device 10 is connected to an external host, the control circuit unit of the controller chip may be constructed to be automatically operated by the operating system of the external host. The control circuit unit of the controller chip may provide a standard protocol (such as Parallel Advanced Technology Attachment (PATA), Serial Advanced Technology Attachment (SATA), Small Computer System Interface (SCSI) standard, or Peripheral Component Interconnect Express (PCIe). The control circuit unit of the controller chip may also execute wear leveling, garbage collection, bad block management, and error correction code for driving a non-volatile memory device. In this case, the control circuit of the controller chip may include a script for automatic execution and an application program executable by an external host.

[0038] The memory semiconductor chip may include a nonvolatile memory device. For example, the nonvolatile memory device may include flash memory, phase change random access memory (PRAM), resistive RAM (RRAM), ferroelectric RAM (FeRAM), or magnetic RAM (MRAM), but is not limited thereto. For example, the flash memory may include NAND flash memory. For example, the flash memory may include vertical NAND (V-NAND) flash memory. The nonvolatile memory device may include a single semiconductor die or a stack of multiple semiconductor dies.

[0039] The memory semiconductor chip may include a volatile memory device. For example, the volatile memory device may include a dynamic RAM (DRAM) or a static RAM (SRAM), but is not limited thereto. The volatile memory device may provide a cache memory function for storing data frequently used when an external host accesses the memory device 10, so that access time and data transfer performance may be scaled according to the processing performance of the external host.

[0040] Although not specifically shown, resistors, inductors, switches, temperature sensors, direct current to direct current (DC-DC) converters, active components, and / or passive components may also be mounted on the substrate 140 .

[0041] In one embodiment, the semiconductor chip 142 may be mounted on the top surface of the substrate 140. In one embodiment, the semiconductor chip may also be mounted on the bottom surface of the substrate 140. This will be described below with reference to Figure 5 Detailed description.

[0042] The base 140 may include an external connector 141. The external connector 141 may be exposed to the outside through a groove formed in the housing 100. The external connector 141 may be inserted into a socket of an external device and may be configured to electrically connect the storage device 10 to the external device. Through the external connector 141, the storage device 10 may exchange electrical signals with the external device and receive power required for the operation of the storage device 10 from the external device.

[0043] The upper cover 150 may be on the housing 100. In one embodiment, the upper cover 150 may be coupled to the upper housing 100U. In detail, the upper cover 150 may be arranged on the top surface of the upper housing 100U so that the first to fourth capacitors 121_1 to 121_4 are not exposed to the outside of the housing 100. The upper cover 150 may overlap with the heat dissipation fins 131 and the first to fourth capacitor modules 120_1 to 120_4 in the third direction D3.

[0044] According to an embodiment, when SPO occurs, the storage device 10 may operate using an auxiliary power supply. In this case, the auxiliary power supply may be provided by the first to fourth capacitor modules 120_1 to 120_4 arranged in the housing 100. In the storage device 10 according to the embodiment, since the first to fourth capacitor modules 120_1 to 120_4 are arranged in the housing 100, a space for the semiconductor chip 142 may be sufficiently ensured on the substrate 140. Since many semiconductor chips 142 may be arranged on the substrate 140 of the storage device 10 due to the sufficiently ensured space on the substrate 140, the capacity of the storage device 10 may be increased.

[0045] Figure 4 is a cross-sectional view of a storage device 10a according to an embodiment. In detail, Figure 4 Along with Figure 3 The cross section of the storage device 10 taken along the line II' in FIG. Figures 1 to 3 describe Figure 4 , and its repeated description is omitted.

[0046] Reference Figure 4 , the storage device 10a can be connected with Figures 1 to 3 The storage device 10 corresponds to.

[0047] The storage device 10 a may include a housing 100 , a base 140 , and an upper cover 150 .

[0048] The first capacitor module 120_1 may include a first capacitor 121_1 and a first housing 122_1. The first capacitor 121_1 may be fixed to the first cavity 110_1 through the first housing 122_1. The first capacitor 121_1 may be electrically connected to the substrate 140 through a lead 123_1. The lead 123_1 may penetrate the upper housing 100U through a hole formed in the upper housing 100U, and may contact the substrate 140. The second capacitor module 120_2 may include a second capacitor 121_2 and a second housing 122_2. The second capacitor 121_2 may be fixed to the second cavity 110_2 through the second housing 122_2. The second capacitor 121_2 may be electrically connected to the substrate 140 through a lead 123_2. The lead 123_2 may penetrate the upper housing 100U through a hole formed in the upper housing 100U, and may contact the substrate 140. Reference Figure 6 Let's describe the shell in detail.

[0049] The first semiconductor chips 142_1U to 142_4U may be mounted on the substrate 140. The TIMs 143_1U to 143_4U may be arranged between the first semiconductor chips 142_1U to 142_4U and the upper case 100U, respectively. Here, the semiconductor chip on the top surface of the substrate 140 may be referred to as a first semiconductor chip, and the semiconductor chip on the bottom surface of the substrate 140 may be referred to as a second semiconductor chip.

[0050] In one embodiment, the TIM 143_1U may be between the first semiconductor chip 142_1U and the upper housing 100U. The TIM 143_1U may thermally connect the first semiconductor chip 142_1U to the upper housing 100U. The heat dissipation fins 131 of the upper housing 100U may thermally connect the upper housing 100U to the upper cover 150. Therefore, the heat generated in the first semiconductor chip 142_1U may be released through the first thermal path HP1 formed between the first semiconductor chip 142_1U and the upper cover 150. In detail, the heat generated in the first semiconductor chip 142_1U may be transmitted to the upper housing 100U through the TIM 143_1U, and then released to the outside through the heat dissipation fins 131 and the upper cover 150.

[0051] In one embodiment, the TIM 143_2U may be between the first semiconductor chip 142_2U and the upper housing 100U. The TIM 143_2U may thermally connect the first semiconductor chip 142_2U to the upper housing 100U. The heat dissipation fins 131 of the upper housing 100U may thermally connect the upper housing 100U to the upper cover 150. Therefore, the heat generated in the first semiconductor chip 142_2U may be released through the second thermal path HP2 formed between the first semiconductor chip 142_2U and the upper cover 150. In detail, the heat generated in the first semiconductor chip 142_2U may be transmitted to the upper housing 100U through the TIM 143_2U, and then released to the outside through the heat dissipation fins 131 and the upper cover 150.

[0052] In one embodiment, the TIM 143_3U may be between the first semiconductor chip 142_3U and the upper housing 100U. The TIM 143_3U may thermally connect the first semiconductor chip 142_3U to the upper housing 100U. The heat dissipation fins 131 of the upper housing 100U may thermally connect the upper housing 100U to the upper cover 150. Therefore, the heat generated in the first semiconductor chip 142_3U may be released through the third thermal path HP3 formed between the first semiconductor chip 142_3U and the upper cover 150. In detail, the heat generated in the first semiconductor chip 142_3U may be transmitted to the upper housing 100U through the TIM 143_3U, and then released to the outside through the heat dissipation fins 131 and the upper cover 150.

[0053] In one embodiment, the TIM 143_4U may be between the first semiconductor chip 142_4U and the upper housing 100U. The TIM 143_4U may thermally connect the first semiconductor chip 142_4U to the upper housing 100U. The heat dissipation fins 131 of the upper housing 100U may thermally connect the upper housing 100U to the upper cover 150. Therefore, the heat generated in the first semiconductor chip 142_4U may be released through the fourth thermal path HP4 formed between the first semiconductor chip 142_4U and the upper cover 150. In detail, the heat generated in the first semiconductor chip 142_4U may be transmitted to the upper housing 100U through the TIM 143_4U, and then released to the outside through the heat dissipation fins 131 and the upper cover 150.

[0054] Figure 5 is a cross-sectional view of a storage device 10b according to an embodiment. In detail, Figure 5 Along with Figure 3 The cross section of the storage device 10 taken along the line II' in FIG. Figures 1 to 4 describe Figure 5 , and its repeated description is omitted.

[0055] Reference Figure 5 , the storage device 10b can be connected with Figures 1 to 3 The storage device 10 corresponds to the storage device 10. Figure 4 The second semiconductor chips 142_1L to 142_4L and the TIMs 143_1L to 143_4L are additionally arranged on the bottom surface of the substrate 140 of the memory device 10a to obtain Figure 5 Therefore, the focus is on the storage device 10b. Figure 4 to describe the difference Figure 5 .

[0056] The first semiconductor chips 142_1U to 142_4U may be mounted on the top surface of the substrate 140. The TIMs 143_1U to 143_4U may be respectively arranged between the first semiconductor chips 142_1U to 142_4U and the upper housing 100U. The second semiconductor chips 142_1L to 142_4L may be mounted on the bottom surface of the substrate 140. The TIMs 143_1L to 143_4L may be respectively arranged between the second semiconductor chips 142_1L to 142_4L and the lower housing 100L.

[0057] In one embodiment, the TIM 143_1L may be between the second semiconductor chip 142_1L and the lower housing 100L. The TIM 143_1L may thermally connect the second semiconductor chip 142_1L to the lower housing 100L. Therefore, the heat generated in the second semiconductor chip 142_1L may be released through the fifth thermal path HP5 formed between the second semiconductor chip 142_1L and the lower housing 100L. In detail, the heat generated in the second semiconductor chip 142_1L may be transferred to the lower housing 100L through the TIM 143_1L, and then may be released to the outside.

[0058] In one embodiment, the TIM 143_2L may be between the second semiconductor chip 142_2L and the lower housing 100L. The TIM 143_2L may thermally connect the second semiconductor chip 142_2L to the lower housing 100L. Therefore, the heat generated in the second semiconductor chip 142_2L may be released through the sixth thermal path HP6 formed between the second semiconductor chip 142_2L and the lower housing 100L. In detail, the heat generated in the second semiconductor chip 142_2L may be transmitted to the lower housing 100L through the TIM 143_2L, and then may be released to the outside.

[0059] In one embodiment, the TIM 143_3L may be between the second semiconductor chip 142_3L and the lower housing 100L. The TIM 143_3L may thermally connect the second semiconductor chip 142_3L to the lower housing 100L. Therefore, the heat generated in the second semiconductor chip 142_3L may be released through the seventh thermal path HP7 formed between the second semiconductor chip 142_3L and the lower housing 100L. In detail, the heat generated in the second semiconductor chip 142_3L may be transmitted to the lower housing 100L through the TIM 143_3L, and then may be released to the outside.

[0060] In one embodiment, the TIM 143_4L may be between the second semiconductor chip 142_4L and the lower housing 100L. The TIM 143_4L may thermally connect the second semiconductor chip 142_4L to the lower housing 100L. Therefore, the heat generated in the second semiconductor chip 142_4L may be released through the eighth thermal path HP8 formed between the second semiconductor chip 142_4L and the lower housing 100L. In detail, the heat generated in the second semiconductor chip 142_4L may be transmitted to the lower housing 100L through the TIM 143_4L, and then may be released to the outside.

[0061] Figure 6 is a diagram showing a capacitor module according to an embodiment. In detail, Figure 6 The first capacitor module 120_1 can be connected to Figure 4 and Figure 5The first capacitor module 120_1 corresponds to the first capacitor module 120_1. Figures 1 to 3 describe Figure 6 , and its repeated description is omitted.

[0062] Reference Figure 6 , the first capacitor module 120_1 may include a first capacitor 121_1 and a first housing 122_1.

[0063] The first capacitor 121_1 may be coupled to the first housing 122_1. In detail, the first capacitor 121_1 may be fixed to the first housing 122_1 by a first lock 122_1LT of the first housing 122_1.

[0064] In one embodiment, the first capacitor module 120_1 may be removed from the upper case 100U when it is necessary to adjust the amount of capacitance in the storage device 10. In one embodiment, the amount of capacitors of the storage device 10 may be adjusted by removing only the first capacitor 121_1 from the first case 122_1 of the first capacitor module 120_1 while retaining the first case 122_1 in the upper case 100U.

[0065] At least one hole 122_1H may be formed in the first housing 122_1. The lead 123_1 of the first capacitor 121_1 may penetrate the first housing 122_1 through the hole 122_1H of the first housing 122_1.

[0066] Each of the second to fourth capacitor modules 120_2 to 120_4 may have a similar configuration (or the same configuration) as the first capacitor module 120_1 , and thus, a repeated description thereof is omitted.

[0067] Figure 7 is a cross-sectional view of a storage device 20a according to an embodiment. Figures 1 to 4 describe Figure 7 , and its repeated description is omitted.

[0068] Reference Figure 7 , the storage device 20a can be connected with Figure 4 Corresponding to the storage device 10a. Figure 7 The storage device 20a and Figure 4The difference between the storage device 10a and the housing 100 may be that the capacitor is fixed to the cavity by a fixing pad. For example, the fixing pad may include a first fixing pad (or referred to as an "upper fixing pad") arranged between the capacitor and the upper cover and a second fixing pad (or referred to as a "lower fixing pad") arranged between the capacitor and the semiconductor chip. Here, the fixing pad may include a silicon pad, a polyurethane pad, a thermally conductive pad, a foam pad, a rubber pad, or a combination of two or more of these, but is not limited thereto. The fixing pad may include any material capable of fixing the capacitor to the housing 100. In some embodiments, the fixing pad may be referred to as a buffer pad.

[0069] The first capacitor module 120_1a may include a first capacitor 121_1, a first upper fixing pad 124_1, and a first lower fixing pad 125_1. The first capacitor 121_1 may be electrically connected to the substrate 140 through a lead 123_1. The lead 123_1 may penetrate the upper case 100U through a hole formed in the upper case 100U and may contact the substrate 140.

[0070] In one embodiment, the first capacitor 121_1 may be fixed to the first cavity 110_1 by a first upper fixing pad 124_1 and a first lower fixing pad 125_1. In detail, the first upper fixing pad 124_1 may be arranged between the upper cover 150 and the first capacitor 121_1, and thus the first capacitor 121_1 may be fixed to the first cavity 110_1. The first lower fixing pad 125_1 may be arranged between the upper case 100U and the first capacitor 121_1, and thus the first capacitor 121_1 may be fixed to the first cavity 110_1.

[0071] The second capacitor module 120_2a may include a second capacitor 121_2, a second upper fixing pad 124_2, and a second lower fixing pad 125_2. The second capacitor 121_2 may be electrically connected to the substrate 140 through a lead 123_2. The lead 123_2 may penetrate the upper case 100U through a hole formed in the upper case 100U and may contact the substrate 140.

[0072] In one embodiment, the second capacitor 121_2 may be fixed to the second cavity 110_2 by a second upper fixing pad 124_2 and a second lower fixing pad 125_2. In detail, the second upper fixing pad 124_2 may be arranged between the upper cover 150 and the second capacitor 121_2, so that the second capacitor 121_2 may be fixed to the second cavity 110_2. The second lower fixing pad 125_2 may be arranged between the upper housing 100U and the second capacitor 121_2, so that the second capacitor 121_2 may be fixed to the second cavity 110_2.

[0073] In one embodiment, the second semiconductor chip may be mounted on the bottom surface of the substrate 140 .

[0074] Figure 8 is a cross-sectional view of a storage device 20b according to an embodiment. Figures 1 to 4 describe Figure 8 , and its repeated description is omitted.

[0075] Reference Figure 8 , the storage device 20b can be connected with Figure 4 Corresponding to the storage device 10a. Figure 8 The storage device 20b and Figure 4 The difference between the storage device 10a and the storage device 10a may be that the capacitor is fixed to the cavity by an adhesive member. For example, the adhesive member may be arranged between the capacitor and the surface of the housing defining the cavity. Here, the adhesive member may include epoxy resin, silicon adhesive, polyvinyl alcohol (PVA) adhesive, adhesive film, adhesive tape, light-cured adhesive, Velcro, glue, or a combination of two or more of these. In addition, any material that is suitable for the bottom surface of the capacitor and can fix the capacitor to the housing 100 can be used.

[0076] The first capacitor module 120_1b may include a first capacitor 121_1 and a first adhesive member 126_1. The first capacitor 121_1 may be electrically connected to the substrate 140 through a lead 123_1. The lead 123_1 may penetrate the upper case 100U through a hole formed in the upper case 100U and may contact the substrate 140.

[0077] In one embodiment, the first capacitor 121_1 may be fixed to the first cavity 110_1 by a first adhesive member 126_1. In detail, the first adhesive member 126_1 may be disposed between the first capacitor 121_1 and the upper case 100U, and thus may fix the first capacitor 121_1 to the first cavity 110_1.

[0078] The second capacitor module 120_2b may include a second capacitor 121_2 and a second adhesive member 126_2. The second capacitor 121_2 may be electrically connected to the substrate 140 through a lead 123_2. The lead 123_2 may penetrate the upper case 100U through a hole formed in the upper case 100U and may contact the substrate 140.

[0079] In one embodiment, the second capacitor 121_2 may be fixed to the second cavity 110_2 by a second adhesive member 126_2. In detail, the second adhesive member 126_2 may be disposed between the second capacitor 121_2 and the upper case 100U, and thus the second capacitor 121_2 may be fixed to the second cavity 110_2.

[0080] Fig. 9 is a cross-sectional view of a storage device 20c according to an embodiment. Figures 1 to 4 describe Fig. 9, and its repeated description is omitted.

[0081] Reference Fig. 9 , the storage device 20c can be connected with Figure 4 Corresponding to the storage device 10a. Fig. 9 The storage device 20c and Figure 4 The memory device 10a may be distinguished in that the capacitor is fixed to the cavity through the sub-substrate and the spring pins.

[0082] The first capacitor module 120_1c may include a first capacitor 121_1, a first sub-substrate 127_1, and a first spring pin 128_1. The substrate 140c may include a first connection pad 144_1 and a second connection pad 144_2.

[0083] The first sub-substrate 127_1 may be arranged in the first cavity 110_1. The first capacitor 121_1 may be electrically connected to the first sub-substrate 127_1 through the lead 123_1. The first sub-substrate 127_1 may be connected to the first connection pad 144_1 of the substrate 140c through the first spring pin 128_1. In other words, the first sub-substrate 127_1 may be electrically connected to the substrate 140c through the first spring pin 128_1. The first spring pin 128_1 may penetrate the upper housing 100U through a hole formed in the upper housing 100U and may contact the first connection pad 144_1.

[0084] In one embodiment, the first capacitor 121_1 may be mounted on the first sub-substrate 127_1. The first capacitor 121_1 may be fixed to the first sub-substrate 127_1 by soldering the lead 123_1 of the first capacitor 121_1 to the first sub-substrate 127_1.

[0085] The second capacitor module 120_2c may include a second capacitor 121_2, a second sub-substrate 127_2, and a second spring pin 128_2. The second sub-substrate 127_2 may be arranged in the second cavity 110_2. The second capacitor 121_2 may be electrically connected to the second sub-substrate 127_2 through a lead 123_2. The second sub-substrate 127_2 may be connected to a second connection pad 144_2 of the substrate 140c through a second spring pin 128_2. In other words, the second sub-substrate 127_2 may be electrically connected to the substrate 140c through the second spring pin 128_2. The second spring pin 128_2 may penetrate the upper housing 100U through a hole formed in the upper housing 100U, and may contact the second connection pad 144_2.

[0086] In one embodiment, the second capacitor 121_2 may be mounted on the second sub-substrate 127_2. The second capacitor 121_2 may be fixed to the second sub-substrate 127_2 by soldering the lead 123_2 of the second capacitor 121_2 to the second sub-substrate 127_2.

[0087] Although not shown, reference Fig. 9 The structure described in which the capacitor is fixed to the cavity by the sub-base and the spring pins can also be applied to the reference Figure 5 The structure described is that semiconductor chips are respectively arranged on the top surface and the bottom surface of the substrate.

[0088] Fig.10 is a diagram of a system 1000 including a storage device according to an embodiment.

[0089] Fig.10 The system 1000 may basically correspond to a mobile system such as a mobile phone, a smart phone, a tablet personal computer (PC), a wearable device, a healthcare device, or an Internet of Things (IoT) device. However, Fig.10 The system 1000 is not limited thereto and may correspond to a PC, a laptop computer, a server, a media player, or a car device such as a navigation device.

[0090] Reference Fig.10 , the system 1000 may include a main processor 1100, memories 1200a and 1200b, and storage devices 1300a and 1300b, and may also include at least one selected from the group consisting of an image capture device 1410, a user input device 1420, a sensor 1430, a communication device 1440, a display 1450, a speaker 1460, a power supply device 1470, and a connection interface 1480. At this time, Fig.10 Each of the elements in the system 1000 (e.g., the main processor 1100, the memories 1200a and 1200b, the storage devices 1300a and 1300b, the image capture device 1410, the user input device 1420, the sensor 1430, the communication device 1440, the display 1450, the speaker 1460, the power supply device 1470, and the connection interface 1480) can be used with reference to the above. Figures 1 to 9 The described embodiments are implemented.

[0091] The main processor 1100 may generally control the operation of the system 1000, and more specifically, the operations of other elements of the system 1000. The main processor 1100 may correspond to a general-purpose processor, a dedicated processor, or an application processor.

[0092] The main processor 1100 may include at least one central processing unit (CPU) core 1110, and also include a controller 1120 that controls memories 1200a and 1200b and / or storage devices 1300a and 1300b. According to an embodiment, the main processor 1100 may further include an accelerator 1130, which is a dedicated circuit for high-speed data operations (such as artificial intelligence (AI) data operations). The accelerator 1130 may include a graphics processing unit (GPU), a neural processing unit (NPU) and / or a data processing unit (DPU), and may be implemented as a separate chip physically independent of other elements of the main processor 1100.

[0093] Memories 1200a and 1200b may be used as main memory devices of system 1000 and may include volatile memory (such as SRAM and / or DRAM) or nonvolatile memory (such as flash memory, PRAM and / or RRAM). Memories 1200a and 1200b may be implemented in the same package as main processor 1100.

[0094] The storage devices 1300a and 1300b may include nonvolatile storage devices that retain data regardless of power supply, and may have a larger capacity than the memories 1200a and 1200b. The storage devices 1300a and 1300b may include storage controllers (STRG CTRL) 1310a and 1310b, respectively, and may include nonvolatile memories (NVM) 1320a and 1320b, respectively. The nonvolatile memory 1320a may store data under the control of the storage controller 1310a, and the nonvolatile memory 1320b may store data under the control of the storage controller 1310b. The nonvolatile memories 1320a and 1320b may include flash memory or other types of nonvolatile memories (such as PRAM and / or RRAM) having a vertical NAND (V-NAND) structure of two dimensions (2D) or three dimensions (3D).

[0095] The storage devices 1300a and 1300b may be physically separated from the main processor 1100 in the system 1000, or may be implemented in the same package as the main processor 1100. The storage devices 1300a and 1300b may have the form of a solid state drive (SSD) or a memory card, and thus may be removably coupled to other elements of the system 1000 through an interface (such as a connection interface 1480 to be described below). The storage devices 1300a and 1300b may include devices to which a protocol (such as the UFS standard, the eMMC standard, or the non-volatile memory express (NVMe) standard) is applied, but are not necessarily limited thereto.

[0096] Each of the storage devices 1300a and 1300b may include a plurality of capacitors. When SPO occurs, the energy stored in the capacitors may be used to complete the current operation of each of the storage devices 1300a and 1300b, so that the loss of data to be stored in each of the storage devices 1300a and 1300b may be limited and / or prevented.

[0097] The image capture device 1410 may capture still images or moving images and may include a camera, a camcorder, and / or a webcam.

[0098] The user input device 1420 may receive various types of data input by a user of the system 1000 , and may include a touch panel, a key pad, a keyboard, a mouse, and / or a microphone.

[0099] The sensor 1430 may sense various types of physical quantities that may be acquired from outside the system 1000, and may convert the sensed physical quantities into electrical signals. The sensor 1430 may include a temperature sensor, a pressure sensor, an illumination sensor, a position sensor, an acceleration sensor, a biosensor, and / or a gyro sensor.

[0100] The communication device 1440 may transmit or receive signals to or from other devices outside the system 1000 according to various communication protocols. The communication device 1440 may include an antenna, a transceiver, and / or a modem.

[0101] Display 1450 and speaker 1460 may be used as output devices for outputting visual information and auditory information, respectively, to a user of system 1000 .

[0102] The power supply device 1470 may appropriately convert power from a battery (not shown) embedded in the system 1000 and / or an external power source, and may supply the converted power to each element in the system 1000 .

[0103] The connection interface 1480 may provide a connection between the system 1000 and an external device, which is connected to the system 1000 and may exchange data with the system 1000. The connection interface 1480 may include various interfaces such as an ATA interface, a SATA interface, an e-SATA interface, a SCSI interface, a Serial Attached SCSI (SAS) interface, a PCI interface, a PCIe interface, an NVMe interface, an Institute of Electrical and Electronics Engineers (IEEE) 1394 interface, a USB interface, an SD card interface, a MultiMediaCard (MMC) interface, an embedded MMC (eMMC) interface, a UFS interface, an embedded UFS (eUFS) interface, and a Compact Flash (CF) card interface.

[0104] Fig.11is a block diagram of an example of applying a storage device to an SSD system according to an embodiment.

[0105] Reference Fig.11 , the SSD system 2000 may include a host 2100 and an SSD 2200. The SSD 2200 may exchange a signal SIG with the host 2100 through a signal connector, and may receive power PWR through a power connector. The SSD 2200 may include an SSD controller 2210, an auxiliary power supply 2220, and memory devices (MEM) 2230, 2240, and 2250. Each of the memory devices 2230, 2240, and 2250 may include a vertically stacked NAND flash memory device. The SSD controller 2210 may communicate with the memory devices 2230, 2240, and 2250 through a first channel Ch1 to an nth channel Chn.

[0106] Auxiliary power supply 2220 can use the above reference Figures 1 to 10 In one embodiment, the auxiliary power supply 2220 may include a first capacitor module 2221 to an Nth capacitor module 222N. When SPO occurs and the power PWR supplied from the host 2100 to the SSD 220 is suddenly cut off, the auxiliary power supply 2220 may enable the SSD 2200 to continuously perform the current operation by using the capacitance stored in the first capacitor module 2221 to the Nth capacitor module 222N. Therefore, when SPO occurs, the auxiliary power supply 2220 may limit and / or prevent the loss of data to be stored in the SSD 2200.

[0107] One or more of the elements disclosed above may include a processing circuit system (such as hardware including logic circuits; a hardware / software combination (such as a processor that executes software); or a combination thereof) or be implemented with a processing circuit system (such as hardware including logic circuits; a hardware / software combination (such as a processor that executes software); or a combination thereof). For example, the processing circuit system may more specifically include (but not limited to) a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0108] While aspects of the inventive concept have been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A storage device, comprising: substrate; a semiconductor chip, on a substrate; a housing including a plurality of heat dissipation fins, a cavity, and a capacitor module configured to be electrically connected to a substrate, the plurality of heat dissipation fins being arranged in a first direction and spaced apart from each other in a second direction perpendicular to the first direction; as well as An upper cover, on the housing, wherein The capacitor module includes a capacitor in the cavity, and the capacitor is configured to supply power to the substrate.

2. The storage device according to claim 1, wherein: The leads of the capacitor pass through the holes in the housing and make contact with the substrate.

3. The storage device according to claim 1, further comprising: Thermal interface material, between semiconductor chip and housing, where The thermal interface material is configured to thermally connect the semiconductor chip to the housing.

4. The storage device according to claim 3, wherein: The plurality of heat dissipation fins are configured to thermally connect the housing to the upper cover.

5. The storage device according to claim 1, wherein: The upper cover overlaps the plurality of heat dissipation fins and the capacitor module in a vertical direction.

6. The storage device according to claim 1, wherein: The capacitor module further includes a housing configured to accommodate the capacitor and to fix the capacitor by a lock.

7. The storage device according to claim 1, wherein: The capacitor module further includes an adhesive member between the capacitor and a surface of the case defining the cavity.

8. The storage device according to claim 1, wherein: The capacitor module also includes: A first fixing pad, between the capacitor and the upper cover; and The second fixing pad is between the capacitor and the semiconductor chip.

9. The storage device according to claim 1, wherein: The substrate includes connection pads, The capacitor module also includes a sub-base and spring pins, The sub-substrate is electrically connected to the capacitor, The pogo pins make contact with the substrate's connection pads, and The spring pins are configured to electrically connect the substrate to the sub-substrate.

10. A storage device, comprising: substrate; a first semiconductor chip on a top surface of the substrate; a second semiconductor chip on the bottom surface of the substrate; a housing including a plurality of heat dissipation fins, a cavity, and a capacitor module configured to be electrically connected to a substrate, the plurality of heat dissipation fins being arranged in a first direction and spaced apart from each other in a second direction perpendicular to the first direction; as well as An upper cover, on the housing, wherein The capacitor module includes a capacitor in the cavity, and the capacitor is configured to supply power to the substrate.

11. The storage device according to claim 10, wherein: The leads of the capacitor pass through the holes in the housing and make contact with the substrate.

12. The storage device according to claim 10, further comprising: a first thermal interface material between the first semiconductor chip and the housing, the first thermal interface material being configured to thermally connect the first semiconductor chip to the housing; as well as A second thermal interface material is provided between the second semiconductor chip and the housing, the second thermal interface material being configured to thermally connect the second semiconductor chip to the housing.

13. The storage device according to claim 12, wherein: The plurality of heat dissipation fins are configured to thermally connect the housing to the upper cover.

14. The storage device according to claim 10, wherein: The capacitor module further includes a housing configured to accommodate the capacitor and to fix the capacitor by a lock.

15. The storage device according to claim 10, wherein: The substrate includes connection pads, The capacitor module also includes a sub-base and spring pins, The sub-substrate is electrically connected to the capacitor, The pogo pins make contact with the substrate's connection pads, and The spring pins are configured to electrically connect the substrate to the sub-substrate.

16. A storage device, comprising: substrate; a semiconductor chip, on a substrate; an upper housing including a plurality of heat dissipation fins, a cavity, and a capacitor module configured to be electrically connected to the substrate, the plurality of heat dissipation fins being arranged in a first direction and spaced apart from each other in a second direction perpendicular to the first direction; a lower housing configured to be coupled to the upper housing; as well as An upper cover, on the upper shell, wherein The base is in the lower shell, The capacitor module includes a capacitor in a cavity, and The upper case is configured to be coupled to the lower case, and allows power to be supplied to the substrate.

17. The storage device according to claim 16, wherein: The leads of the capacitor pass through the holes in the upper case and contact the base.

18. The storage device according to claim 16, wherein: The capacitor module further includes a housing configured to accommodate the capacitor and to fix the capacitor by a lock.

19. The storage device according to claim 17, further comprising: Thermal interface material, between the semiconductor chip and the upper housing, wherein The thermal interface material is configured to thermally connect the semiconductor chip to the upper housing.

20. The storage device according to claim 19, wherein: The plurality of heat dissipation fins are configured to thermally connect the upper housing to the upper cover.

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