Power semiconductor device with high turn-off capability and preparation method thereof

Abstract

The invention relates to the technical field of semiconductors, and discloses a power semiconductor device with high turn-off capability and a preparation method, the device comprises a unit cell structure, the unit cell structure comprises an anode structure, a base region structure, a cathode structure and a gate pole structure which are stacked in sequence, the base region structure comprises a floating junction region, the doping type of the floating junction region is opposite to that of the base region structure, and the gate pole structure comprises a gate pole structure; the floating junction region comprises an upper platform region, a lower platform region and a wavy region for connecting the two platform regions; the floating junction region is locally irradiated and formed in the base region structure through a metal baffle and is used for shunting current on a path between the anode structure and the cathode structure to a region between the cathode structure and the gate pole structure and promoting redistribution of carriers in a dynamic avalanche mode in the region. According to the invention, the transverse voltage drop of the base region at the edge of the outer side of the cathode structure can be reduced, so that the rapid commutation effect of the cathode structure and the gate pole structure is achieved, the breakdown of the device caused by retriggering due to the convergence of local current is effectively prevented, and the turn-off capability of the device is effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a power semiconductor device with high shutdown capability and a preparation method thereof. Background Art

[0002] In the power system, reliable DC transmission of large-capacity electric energy over long distances is one of the key issues that need to be solved urgently. In the fields of smart grid, new energy, industrial power conversion and other high-power medium and high-voltage application systems where circuit miniaturization and integration are more common, gate commutated thyristors (GCTs) with low conduction loss, fast switching speed, low switching loss and strong current capacity are generally used as fully controlled power electronic switch devices.

[0003] An important criterion for measuring the performance of GCT devices is the shutdown capability. The key to improving the shutdown capability is to reduce the risk of shutdown failure caused by cathode current re-triggering during the shutdown process. However, the existing technologies for improving the shutdown capability of GCT are relatively scarce. One of the technologies, a wavy base region structure, does effectively improve the shutdown capability of GCT. However, under the current stringent requirements of high blocking voltage and large shutdown current, the effect of the wavy base region on improving the shutdown capability gradually approaches the upper limit.

[0004] Therefore, how to further improve the shutdown capability of power semiconductor devices has become an urgent problem to be solved in the current field of semiconductor technology. Summary of the invention

[0005] The object of the present invention is to provide a power semiconductor device with high shutdown capability and a preparation method, which can shunt the current on the path between the anode structure and the cathode structure to the area between the cathode structure and the gate structure, and promote the redistribution of carriers in this area in a dynamic avalanche manner, thereby reducing the lateral voltage drop in the base region at the outer edge of the cathode structure, and can achieve the effect of rapid current commutation between the cathode structure and the gate structure, effectively preventing the device from being broken down due to re-triggering caused by the convergence of local current, thereby effectively improving the shutdown capability of the power semiconductor device.

[0006] In order to achieve the above-mentioned purpose, the first aspect of the present invention provides a power semiconductor device with high shutdown capability, wherein the power semiconductor device includes: a unit cell structure, wherein the unit cell structure includes: an anode structure, a base structure, a cathode structure, and a gate structure stacked in sequence, wherein the base structure includes a floating junction region, the doping type of the floating junction region is opposite to the doping type of the base structure, and the floating junction region includes an upper platform region, a lower platform region, and a wavy region for connecting the upper platform region and the lower platform region, wherein the floating junction region is formed in the base structure by local irradiation and through a metal baffle, and wherein the floating junction region is used to shunt the current on the path between the anode structure and the cathode structure to the region between the cathode structure and the gate structure, and promote the redistribution of carriers in the region between the cathode structure and the gate structure in a dynamic avalanche manner.

[0007] Preferably, the gate structure includes: a first gate and a second gate; the floating junction region includes a first floating junction region and a second floating junction region, the lateral size of the first floating junction region is at least equal to the gap between the first gate and the cathode structure; the lateral size of the second floating junction region is at least equal to the gap between the second gate and the cathode structure.

[0008] Preferably, the unit cell structure further includes: a buffer region structure located between the base region structure and the anode structure.

[0009] Preferably, the base region structure includes: a first type base region and a second type base region, which are stacked sequentially on the anode structure, wherein the first type base region includes the floating junction region, and the doping type of the floating junction region is opposite to the doping type of the first type base region.

[0010] Preferably, the second type base region comprises: a first sub-type base region and a second sub-type base region, which are sequentially stacked on the first type base region, wherein the first sub-type base region is a wavy base region.

[0011] Preferably, the anode structure comprises: an anode and an anode region, wherein the anode region is located between the anode and the base region structure.

[0012] Through the above technical scheme, the present invention creatively adds a wavy inversion floating junction area in the base structure, which can divert the current on the path between the anode structure and the cathode structure to the area between the cathode structure and the gate structure, and promotes the redistribution of carriers in this area in a dynamic avalanche manner, thereby reducing the lateral voltage drop in the base area at the outer edge of the cathode structure, and can achieve the effect of rapid commutation between the cathode structure and the gate structure, effectively preventing the device from being broken down due to re-triggering caused by the convergence of local current, thereby effectively improving the shutdown capability of the power semiconductor device.

[0013] A second aspect of the present invention provides a method for preparing a power semiconductor device, the method comprising: forming an anode structure, a base structure, a cathode structure and a gate structure stacked in sequence; and forming a floating junction region in the base structure by local irradiation and through a metal baffle, wherein the doping type of the floating junction region is opposite to the doping type of the base structure, and the floating junction region comprises an upper platform region, a lower platform region and a wavy region for connecting the upper platform region and the lower platform region, wherein the floating junction region is used to shunt the current on the path between the anode structure and the cathode structure to the region between the cathode structure and the gate structure, and promote the redistribution of carriers in the region between the cathode structure and the gate structure in a dynamic avalanche manner.

[0014] Preferably, the window size W of the metal baffle satisfies , wherein D is the gap between the gate and cathode of the power semiconductor device.

[0015] Preferably, the lateral size of the floating junction region is equal to the window size of the metal baffle.

[0016] Preferably, the irradiation energy of the local irradiation is E Determined by the following formula: , in, is the range of local irradiation; a and b are respectively the first related constant and the second related constant of the material of the substrate of the power semiconductor device.

[0017] Preferably, the thickness of the upper platform region and the lower platform region of the floating junction region is the energy dispersion width of local irradiation, wherein the energy dispersion width is determined by the irradiation energy.

[0018] Preferably, the local irradiation dose is Determined by the following formula: , in, ρ、E d are the density and displacement threshold of the substrate material of the power semiconductor device, respectively; NIEL is the non-ionizing energy loss of locally irradiated particles; is the doping concentration of the base region structure.

[0019] Through the above technical scheme, the present invention creatively implements local irradiation of the unit cell structure of an existing power semiconductor device (such as a GCT device) through a metal baffle to achieve the addition of a wavy inversion floating junction region in the base structure, and the current on the path between the anode structure and the cathode structure can be diverted to the area between the cathode structure and the gate structure, and the redistribution of carriers in this area is promoted in a dynamic avalanche manner, thereby reducing the lateral voltage drop in the base region at the outer edge of the cathode structure, and achieving the effect of rapid commutation between the cathode structure and the gate structure, effectively preventing the device from being broken down due to re-triggering caused by the convergence of local current, thereby effectively improving the shutdown capability of the power semiconductor device, and the process is simple and the cost is low.

[0020] Other features and advantages of the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the following specific implementations, they are used to explain the embodiments of the present invention, but do not constitute a limitation on the embodiments of the present invention. In the accompanying drawings: Figure 1 It is a schematic structural diagram of a power semiconductor device with high shutdown capability provided by an embodiment of the present invention; Figure 2 is a schematic structural diagram of a power semiconductor device with high shutdown capability provided by an embodiment of the present invention; and Figure 3 It is a schematic diagram of the structure of a power semiconductor device with high shutdown capability provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0022] The specific implementation of the present invention is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described here is only used to illustrate and explain the present invention, and is not used to limit the present invention.

[0023] Figure 1 1 is a schematic diagram of a power semiconductor device with high turn-off capability provided by an embodiment of the present invention. The power semiconductor device includes a unit cell structure. For example, the power semiconductor device includes one or more unit cell structures. Figure 1 As shown, the unit cell structure includes: an anode structure 10, a base structure 20, a cathode structure 30, and a gate structure 40 which are stacked in sequence.

[0024] like Figure 1As shown, the base structure 20 includes a floating junction area 201, the doping type of the floating junction area 201 is opposite to the doping type of the base structure 20, and the floating junction area 201 includes an upper platform area A, a lower platform area B, and a wavy area C for connecting the upper platform area A and the lower platform area B (that is, the shape of the floating junction area is the same as the step shape of the cathode structure 30). In other words, the floating junction area 201 is an inversion area with a wavy junction morphology, that is, a wavy inversion floating junction area.

[0025] Wherein, the floating junction region is formed in the base region structure by local irradiation and through a metal baffle.

[0026] The floating junction region 201 is used to divert the current on the path between the anode structure 10 and the cathode structure 30 to the region between the cathode structure 30 and the gate structure 40, and promote the redistribution of carriers in the region between the cathode structure 30 and the gate structure 40 in a dynamic avalanche manner.

[0027] The anode structure 10 may be composed of a plurality of semiconductor layers, and the doping types of the semiconductor layers may be the same or different, and the doping types include at least one of P-type, P-type, P+ type, N-type, N-type, and N+ type. The base structure 20 may be composed of a plurality of semiconductor layers, and the doping types of the semiconductor layers may be the same or different, and the doping types include at least one of P-type, P-type, P+ type, N-type, N-type, and N+ type. The cathode structure 30 may be composed of a plurality of semiconductor layers, and the doping types of the semiconductor layers may be the same or different, and the doping types include at least one of P-type, P-type, P+ type, N-type, N-type, and N+ type. The structure of the power semiconductor device may be, but is not limited to, reverse-blocking, asymmetric, and reverse-conducting structures.

[0028] The number of the above-mentioned floating junction regions 201 can be one or more. Preferably, in a unit cell structure, the number of floating junction regions 201 can be the same as the number of gate structures 40, or the number of floating junction regions 201 can be the same as the number of regions between the cathode structure 30 and the gate structure 40.

[0029] The doping type of the floating junction region 201 includes at least one of P type, P- type, P+ type, N type, N- type, and N+ type. The position of the floating junction region 201 can be set according to actual needs. Preferably, the floating junction region 201 is set in the upper half of the base structure 20, specifically, it can be set in the area between the cathode structure 30 and the gate structure 40. The thickness of the upper platform area and the lower platform area of ​​the floating junction region 201 T It can be set according to actual needs. Preferably, the thickness of the floating junction area 201 is TThe range is 5 μm to 50 μm. The width of the floating junction area 201 can be set according to actual needs. The spacing between each floating junction area 201 can be set according to actual needs. Preferably, the spacing between the floating junction areas 201 can be determined by the location of the area between the cathode structure 30 and the gate structure 40. The doping concentration of the floating junction area 201 is greater than the doping concentration of the base structure 20.

[0030] Since the window of the metal baffle corresponds to the gap between the gate cathode, when radiating downward from the upper surface of the power semiconductor device, the step blocking of the cathode structure 30 forms a floating junction area with the same shape as the step, that is, a wavy floating junction area. Considering that the doping concentration of the floating junction area is opposite to the doping concentration of the base area, the floating junction area can be called a wavy inversion floating junction area.

[0031] The power semiconductor device with high turn-off capability provided in this embodiment can shunt the current on the path between the anode structure and the cathode structure to the area between the cathode structure and the gate structure by adding a wavy inversion floating junction area in the base structure, thereby reducing the lateral voltage drop in the base at the outer edge of the cathode structure, and achieving the effect of rapid current commutation between the cathode structure and the gate structure, thereby effectively improving the turn-off capability of the power semiconductor device; and, the wavy inversion floating junction area can make the unit cell of the power semiconductor device more inclined to undergo a dynamic avalanche process in the area corresponding to the cathode and the gate, and through a series of negative feedback processes (i.e., redistribution of carriers), it can effectively prevent the device from being broken down due to re-triggering caused by the convergence of local current, thereby improving the turn-off current capability of the device under the same anode and cathode voltage conditions, and expanding the safe working area of ​​the entire device.

[0032] In one embodiment, if Figure 2 As shown, the gate structure 40 includes a first gate 401 and a second gate 402. Correspondingly, the floating junction region 201 includes a first floating junction region 2011 and a second floating junction region 2012.

[0033] The lateral size of the first floating junction region 2011 is at least equal to the gap between the first gate 401 and the cathode structure 30 ; the lateral size of the second floating junction region 2012 is at least equal to the gap between the second gate 402 and the cathode structure 30 .

[0034] The doping type of the first floating junction area 2011 includes at least one of P type, P- type, P+ type, N type, N- type, and N+ type. The thickness of the first floating junction area 2011 can be set according to actual needs. Preferably, the thickness of the upper platform area and the lower platform area of ​​the first floating junction area 2011 is TThe range is 5μm to 50μm. The width of the first floating junction area 2011 can be set according to actual needs. The doping type of the second floating junction area 2012 includes at least one of P type, P- type, P+ type, N type, N- type, and N+ type. The thickness of the second floating junction area 2012 can be set according to actual needs. Preferably, the thickness of the upper platform area and the lower platform area of ​​the second floating junction area 2012 T The range is 5 μm to 50 μm. The width of the second floating junction region 2012 can be set according to actual needs.

[0035] In one embodiment, if Figure 2 As shown, the power semiconductor device further includes: a buffer structure 50 located between the base structure 20 and the anode structure 10 .

[0036] Specifically, the buffer structure 50 is stacked below the base structure 20 , and the buffer structure 50 is stacked above the anode structure 10 ; the doping type of the buffer structure determines whether the structure of the power semiconductor device is symmetrical.

[0037] The buffer structure 50 may be composed of one or more semiconductor layers, and the doping types of the semiconductor layers may be the same or different, and the doping types include at least one of P type, P- type, P+ type, N type, N- type, and N+ type.

[0038] The structure of the power semiconductor device may be, but is not limited to, a reverse-blocking, asymmetric, and reverse-conducting structures. If the doping type of the buffer structure 50 is the same as the doping type of the anode structure 10, the structure of the power semiconductor device is determined to be a symmetric type; if the doping type of the buffer structure 50 is the same as the doping type of the base structure 20, the structure of the power semiconductor device is determined to be an asymmetric type.

[0039] In one embodiment, if Figure 2 As shown, the base region structure 20 includes: a first type base region 202 and a second type base region 203, which are stacked in sequence on the anode structure 10, wherein the first type base region 202 includes the floating junction region 201, and the doping type of the floating junction region 201 is opposite to the doping type of the first type base region 202.

[0040] Specifically, the first type base region 202 is stacked on the anode structure, and the second type base region 203 is stacked on the first type base region 202 .

[0041] The doping type of the first type base region 202 includes at least one of P type, P-type, P+ type, N type, N-type, and N+ type. The doping type of the second type base region 203 includes at least one of P type, P-type, P+ type, N type, N-type, and N+ type. The second type base region 203 may be composed of a plurality of semiconductor layers, and the doping types of the semiconductor layers may be the same or different.

[0042] In one embodiment, if Figure 2 As shown, the second type base region 203 includes a first sub-type base region 2031 and a second sub-type base region 2032, which are sequentially stacked on the first type base region 202, wherein the first sub-type base region 2031 is a wavy base region.

[0043] Specifically, the first subtype base region 2031 is stacked on the first type base region 202, and the second subtype base region 2032 is stacked on the first subtype base region 2031. The first subtype base region 2031 is a wavy base region, which is similar to the wavy structure of the floating junction region 201.

[0044] The doping type of the first subtype base region 2031 includes at least one of P type, P- type, P+ type, N type, N- type, and N+ type. The doping type of the second subtype base region 2032 includes at least one of P type, P- type, P+ type, N type, N- type, and N+ type.

[0045] In one embodiment, if Figure 2 As shown, the anode structure 10 comprises: an anode 100 and an anode region 101 stacked in sequence, wherein the anode region 101 is located between the anode 100 and the base structure 20 .

[0046] Specifically, the anode region 101 is stacked under the base region structure 20. The anode region 101 may be composed of one or more semiconductor layers, and the doping types of the semiconductor layers may be the same or different, and the doping types include at least one of P type, P-type, P+ type, N type, N-type, and N+ type.

[0047] In one embodiment, if Figure 2 As shown, the cathode structure 30 includes: an emitter region 301 and a cathode 300 stacked in sequence; the emitter region 301 is stacked on the base region structure 20 .

[0048] The doping type of the emitter region 301 includes at least one of P type, P- type, P+ type, N type, N- type, and N+ type.

[0049] In summary, the present invention adds a wavy inversion floating junction area to the base structure through local irradiation and the use of a metal baffle, which can divert the current on the path between the anode structure and the cathode structure to the area between the cathode structure and the gate structure, and promote the redistribution of carriers in this area in a dynamic avalanche manner, thereby reducing the lateral voltage drop in the base at the outer edge of the cathode structure, and achieving the effect of rapid current commutation between the cathode structure and the gate structure, effectively preventing device breakdown caused by re-triggering due to local current convergence, thereby effectively improving the shutdown capability of the power semiconductor device.

[0050] At present, it is difficult to break through the technical bottleneck of improving the shutdown capability of power semiconductor devices (such as GCT devices). For example, it can usually be achieved by changing the device structure, but the process is relatively complex and the cost is high. Therefore, the present invention proposes a method of increasing the irradiation defect and changing the commutation path by proton / heavy ion irradiating the local area between the gate and cathode of the unit cell of the power semiconductor device (such as GCT device) to improve the shutdown capability of the unit cell of the device (such as GCT). It can be achieved by only partially irradiating the existing power semiconductor device (such as GCT device) structure through a metal baffle. The process is simple and the cost is low, providing a method for improving the shutdown capability of the unit cell of the power semiconductor device (such as GCT device).

[0051] An embodiment of the present invention provides a method for preparing a power semiconductor device, the method comprising: forming an anode structure, a base structure, a cathode structure and a gate structure stacked in sequence; and forming a floating junction region in the base structure by local irradiation and through a metal baffle.

[0052] The doping type of the floating junction region is opposite to the doping type of the base region structure, and the floating junction region includes an upper platform region, a lower platform region, and a wavy region for connecting the upper platform region and the lower platform region.

[0053] The floating junction region is used to shunt the current on the path between the anode structure and the cathode structure to the region between the cathode structure and the gate structure, and promote the redistribution of carriers in the region between the cathode structure and the gate structure in a dynamic avalanche manner.

[0054] In this embodiment, by performing proton / heavy ion He irradiation on the local area between the gate and cathode of the unit cell of the power semiconductor device (such as GCT), the commutation path is changed by increasing the irradiation defects to form an inversion region, so that the current on the path between the anode structure and the cathode structure can be diverted to the area between the cathode structure and the gate structure, and the redistribution of carriers in this area is promoted in a dynamic avalanche manner, thereby reducing the lateral voltage drop in the base region at the outer edge of the cathode structure, and achieving the effect of rapid commutation between the cathode structure and the gate structure, effectively preventing the device from being broken down due to re-triggering caused by the convergence of local current, thereby effectively improving the shutdown capability of the power semiconductor device, thereby improving the safe working area of ​​the device.

[0055] In one embodiment, the gate structure includes: a first gate and a second gate; the floating junction region includes a first floating junction region and a second floating junction region, the lateral size of the first floating junction region is at least equal to the gap between the first gate and the cathode structure; the lateral size of the second floating junction region is at least equal to the gap between the second gate and the cathode structure.

[0056] In one embodiment, the power semiconductor device further includes: a buffer structure located between the base structure and the anode structure.

[0057] In one embodiment, the base region structure includes: a first type base region and a second type base region, which are stacked sequentially on the anode structure, wherein the first type base region includes the floating junction region, and the doping type of the floating junction region is opposite to the doping type of the first type base region.

[0058] In one embodiment, the second type base region includes: a first sub-type base region and a second sub-type base region, which are sequentially stacked on the first type base region, wherein the first sub-type base region is a wavy base region.

[0059] In one embodiment, the anode structure comprises: an anode and an anode region, wherein the anode region is located between the anode and the base region structure.

[0060] The preparation method described in this embodiment adds a wavy inversion floating junction area to the base structure by local irradiation, which can divert the current on the path between the anode structure and the cathode structure to the area between the cathode structure and the gate structure, and promote the redistribution of carriers in this area in a dynamic avalanche manner, thereby reducing the lateral voltage drop in the base at the outer edge of the cathode structure, and achieving the effect of rapid commutation between the cathode structure and the gate structure, effectively preventing device breakdown due to re-triggering caused by local current convergence, thereby effectively improving the shutdown capability of the power semiconductor device.

[0061] In one embodiment, the window size W of the metal baffle satisfies , wherein D is the gap between the gate and cathode of the power semiconductor device.

[0062] The window of the metal baffle corresponds to the gap between the gate and cathode. For example, the center of the window of the metal baffle is located at the junction of the gate and cathode on the upper surface of the chip.

[0063] Accordingly, the lateral size of the floating junction region is equal to the window size of the metal baffle.

[0064] In one embodiment, when the local irradiation is proton irradiation, the irradiation energy of the local irradiation is E Determined by the following formula: (1), in, is the range of local irradiation (which determines the distance between the center position of the upper platform area of ​​the floating junction area and the upper surface of the substrate of the power semiconductor device); a and b are the first related constant and the second related constant of the material of the substrate of the power semiconductor device, respectively.

[0065] Accordingly, the thickness of the upper platform region and the lower platform region of the floating junction region (i.e. T ) is the energy dispersion width of local irradiation.

[0066] The energy dispersion width is determined by the irradiation energy. For example, the energy dispersion width Δz can be determined by the following formula: E is the irradiation energy: (2).

[0067] Specifically, the distance between the center position of the upper platform area of ​​the floating junction area and the upper surface of the substrate of the power semiconductor device can be determined as the range R , then the irradiation energy can be determined according to the above formula (1): E , and then the energy dispersion width Δz can be determined according to formula (2).

[0068] In one embodiment, if Figure 2 As shown, the second type base region 203 includes a first sub-type base region 2031 and a second sub-type base region 2032, which are sequentially stacked on the first type base region 202, wherein the first sub-type base region 2031 is a wavy base region. Accordingly, if the distance from the lower surface of the first sub-type base region 2031 to the longitudinal center position of the upper platform region of the floating junction region is H , the range can be further determined R , and then determine the irradiation energy E And the energy dispersion width Δz.

[0069] In one embodiment, the local irradiation dose is Determined by the following formula: (3), in, ρ、E d are the density and displacement threshold of the substrate material of the power semiconductor device, respectively; NIEL is the non-ionizing energy loss of locally irradiated particles; is the doping concentration of the base region structure.

[0070] According to the radiation dose ϕ And the following formula can determine the doping concentration Conc of the floating junction area: (4).

[0071] Therefore, the energy through E The local proton / heavy ion irradiation is at a depth of R The energy dispersion width is Δ z , the inversion region with a wavy junction morphology with defect concentration Conc (such as Figure 3 As shown in the figure), a commutation path is effectively formed when the device is turned off, thereby improving the turn-off capability of the device.

[0072] The present invention mainly utilizes high energy proton / heavy ion irradiation to locally irradiate the gate cathode region of a power semiconductor device (such as a GCT device) through a metal baffle with a window (i.e., slot width) of W, and irradiates the N-base region to form a gate cathode region with a depth of R , the energy dispersion width is Δ z , and the irradiation area with the highest defect concentration Conc in the middle (such as Figure 3 As shown), by N - The base region forms an inversion doped P type irradiation area, and because the shape of this area is consistent with the shape of the cathode step, a secondary wave junction morphology is formed between the gate and the cathode, which effectively improves the carrier distribution during the shutdown process, optimizes the transient electric field distribution of the shutdown, realizes the formation of a commutation path during shutdown, and improves the shutdown capability of the device.

[0073] The structures of the power semiconductor devices provided in the above-mentioned embodiments can be implemented by the local irradiation method described above, and the formation of other structures except the floating junction area can refer to the existing preparation method, which is not the main improvement of the present invention and will not be described in detail here.

[0074] In summary, the present invention creatively implements local irradiation of the unit cell structure of an existing power semiconductor device (such as a GCT device) through a metal baffle to achieve the addition of a wavy inversion floating junction region in the base structure, and can shunt the current on the path between the anode structure and the cathode structure to the region between the cathode structure and the gate structure, and promote the redistribution of carriers in this region in a dynamic avalanche manner, thereby reducing the lateral voltage drop in the base region at the outer edge of the cathode structure, and achieving the effect of rapid current commutation between the cathode structure and the gate structure, effectively preventing device breakdown caused by re-triggering due to the convergence of local current, thereby effectively improving the shutdown capability of the power semiconductor device, and the process is simple and the cost is low.

[0075] In the above embodiments, GCT (Gate Commutated Thyristor) is mainly used as an example for explanation and description, wherein, of course, the present invention is not only applicable to GCT devices, but also to IGBT (Insulate-Gate Bipolar Transistor), MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), GTO (gate turn-off thyristor), and other power devices with radial and annular distribution of cathode regions. The substrate material of the power device is not limited to silicon, but can also be a third-generation semiconductor material such as silicon carbide or gallium nitride.

[0076] The power semiconductor device in each embodiment of the present invention may be a GCT device, an IGBT device, a MOSFET device, a GTO device, etc.

[0077] The preferred embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, a variety of simple modifications can be made to the technical solution of the present invention, and these simple modifications all belong to the protection scope of the present invention.

[0078] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not further describe various possible combinations.

[0079] In addition, various embodiments of the present invention may be arbitrarily combined, and as long as they do not violate the concept of the present invention, they should also be regarded as the contents disclosed by the present invention.

Claims

1. A power semiconductor device with high turn-off capability, characterized in that: The power semiconductor device comprises: a unit cell structure, the unit cell structure comprises: an anode structure, a base structure, a cathode structure, and a gate structure which are stacked in sequence, wherein the base structure comprises a floating junction region, the doping type of the floating junction region is opposite to the doping type of the base structure, and the floating junction region comprises an upper platform region, a lower platform region, and a wavy region for connecting the upper platform region and the lower platform region, The floating junction region is formed in the base region structure by local irradiation and through a metal baffle, and The floating junction region is used to shunt the current on the path between the anode structure and the cathode structure to the region between the cathode structure and the gate structure, and promote the redistribution of carriers in the region between the cathode structure and the gate structure in a dynamic avalanche manner.

2. The power semiconductor device according to claim 1, characterized in that: The gate structure includes: a first gate and a second gate; the floating junction area includes a first floating junction area and a second floating junction area, the lateral size of the first floating junction area is at least equal to the gap between the first gate and the cathode structure; the lateral size of the second floating junction area is at least equal to the gap between the second gate and the cathode structure.

3. The power semiconductor device according to claim 1, characterized in that: The unit cell structure further includes: a buffer region structure located between the base region structure and the anode structure.

4. The power semiconductor device according to claim 1, characterized in that: The base region structure includes: a first type base region and a second type base region, which are sequentially stacked on the anode structure, wherein the first type base region includes the floating junction region, and the doping type of the floating junction region is opposite to the doping type of the first type base region.

5. The power semiconductor device according to claim 4, characterized in that: The second type base region includes: a first sub-type base region and a second sub-type base region, which are sequentially stacked on the first type base region, wherein the first sub-type base region is a wavy base region.

6. The power semiconductor device according to any one of claims 1 to 5, characterized in that: The anode structure includes: an anode and an anode region, wherein the anode region is located between the anode and the base region structure.

7. A method for preparing a power semiconductor device, characterized in that: The preparation method comprises: forming an anode structure, a base structure, a cathode structure and a gate structure stacked in sequence; and A floating junction region is formed in the base region structure by local irradiation and through a metal baffle, wherein the doping type of the floating junction region is opposite to the doping type of the base region structure, and the floating junction region includes an upper platform region, a lower platform region, and a wavy region for connecting the upper platform region and the lower platform region, The floating junction region is used to shunt the current on the path between the anode structure and the cathode structure to the region between the cathode structure and the gate structure, and promote the redistribution of carriers in the region between the cathode structure and the gate structure in a dynamic avalanche manner.

8. The preparation method according to claim 7, characterized in that: The window size W of the metal baffle satisfies , wherein D is the gap between the gate and cathode of the power semiconductor device.

9. The preparation method according to claim 8, characterized in that: The lateral size of the floating junction region is equal to the window size of the metal baffle.

10. The preparation method according to claim 7, characterized in that: In the case where the local irradiation is proton irradiation, the irradiation energy of the local irradiation E Determined by the following formula: ， in, is the range of local irradiation; a and b are respectively the first related constant and the second related constant of the material of the substrate of the power semiconductor device.

11. The preparation method according to claim 10, characterized in that: The thickness of the upper platform region and the lower platform region of the floating junction region is the energy dispersion width of the local irradiation, wherein the energy dispersion width is determined by the irradiation energy.

12. The preparation method according to claim 7, characterized in that: Radiation dose of local irradiation Determined by the following formula: ， in, ρ、E d are the density and displacement threshold of the substrate material of the power semiconductor device, respectively; NIEL is the non-ionizing energy loss of locally irradiated particles; is the doping concentration of the base region structure.

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