Power semiconductor device with high turn-off ability and preparation method

Abstract

The present invention relates to the field of semiconductor technology, and discloses a power semiconductor device with high turn-off ability and a preparation method. The device includes: a unit cell structure, which includes: an anode structure, a base region structure, a cathode structure, and a gate structure formed in a stacked manner in sequence. The base region structure includes a floating junction region, the doping type of the floating junction region is opposite to that of the base region structure, the floating junction region includes an upper platform region, a lower platform region, and a wavy region connecting the two platform regions. The floating junction region is formed in the base region structure by local irradiation and through a metal baffle, and is used to divert the current on the path between the anode structure and the cathode structure to the region between the cathode structure and the gate structure and promote the redistribution of carriers in this region in a dynamic avalanche manner. The present invention can reduce the lateral voltage drop in the base region at the outer edge of the cathode structure, so as to achieve the effect of rapid commutation between the cathode structure and the gate structure, effectively prevent the device from breakdown caused by re-triggering due to the convergence of local current, and effectively improve the turn-off ability of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a power semiconductor device with high turn-off ability and a manufacturing method thereof. Background Art

[0002] In the power system, the reliable DC transmission of long-distance and large-capacity electric energy is one of the key problems to be urgently solved. In the fields of smart grid, new energy, and industrial current conversion and other high-power medium-voltage application systems where circuit miniaturization and integration are relatively common, a gate commutated thyristor (GCT), which has low on-state loss, fast switching speed, small switching loss, and strong current-carrying capacity, is generally used as a fully controlled power electronic switching device.

[0003] An important criterion for measuring the performance of GCT devices is the turn-off ability. The key to improving the turn-off ability lies in reducing the risk of retriggering of the cathode current during the turn-off process of the device, which may lead to turn-off failure. However, the existing technologies for improving the turn-off ability of GCTs are relatively scarce. Although a wavy base structure effectively improves the turn-off ability of GCTs, under the current strict requirements of high blocking voltage and large turn-off current, the effect of the wavy base structure in improving the turn-off ability gradually approaches its upper limit.

[0004] Therefore, how to further improve the turn-off ability of power semiconductor devices has become an urgent problem to be solved in the current field of semiconductor technology. Summary of the Invention

[0005] The object of the present invention is to provide a power semiconductor device with high turn-off ability and a manufacturing method thereof, which can divert the current on the path between the anode structure and the cathode structure to the region between the cathode structure and the gate structure, and promote the redistribution of carriers in this region in a dynamic avalanche manner, thereby reducing the lateral base voltage drop at the outer edge of the cathode structure, achieving the effect of rapid commutation between the cathode structure and the gate structure, effectively preventing device breakdown caused by the concentration of local current and retriggering, and thus effectively improving the turn-off ability of the power semiconductor device.

[0006] To achieve the above object, a first aspect of the present invention provides a power semiconductor device with high turn-off capability. The power semiconductor device includes: a unit cell structure, and the unit cell structure includes: an anode structure, a base region structure, a cathode structure, and a gate structure formed in a stacked manner in sequence. Among them, the base region structure includes a floating junction region, the doping type of the floating junction region is opposite to that of the base region structure, and the floating junction region includes an upper platform region, a lower platform region, and a wavy region for connecting the upper platform region and the lower platform region. Among them, the floating junction region is formed in the base region structure by means of local irradiation and through a metal baffle, and among them, the floating junction region is used to divert the current on the path between the anode structure and the cathode structure to the region between the cathode structure and the gate structure, and promotes the redistribution of carriers in the region between the cathode structure and the gate structure in a dynamic avalanche manner.

[0007] Preferably, the gate structure includes: a first gate and a second gate; the floating junction region includes a first floating junction region and a second floating junction region, and the lateral dimension of the first floating junction region is at least equal to the gap between the first gate and the cathode structure; the lateral dimension of the second floating junction region is at least equal to the gap between the second gate and the cathode structure.

[0008] Preferably, the unit cell structure further includes: a buffer region structure located between the base region structure and the anode structure.

[0009] Preferably, the base region structure includes: a first-type base region and a second-type base region, which are stacked on the anode structure in sequence. Among them, the floating junction region is included in the first-type base region, and the doping type of the floating junction region is opposite to that of the first-type base region.

[0010] Preferably, the second-type base region includes: a first sub-type base region and a second sub-type base region, which are stacked on the first-type base region in sequence. Among them, the first sub-type base region is a wavy base region.

[0011] Preferably, the anode structure includes: an anode and an anode region, where the anode region is located between the anode and the base region structure.

[0012] Through the above technical solution, the present invention creatively adds a wavy inverted floating junction region in the base region structure, which can divert the current on the path between the anode structure and the cathode structure to the region between the cathode structure and the gate structure, and promotes the redistribution of carriers in this region in a dynamic avalanche manner, thereby reducing the lateral base voltage drop at the outer edge of the cathode structure, achieving the effect of rapid commutation between the cathode structure and the gate structure, effectively preventing device breakdown caused by re-triggering due to the convergence of local current, and further effectively improving the turn-off capability of the power semiconductor device.

[0013] In a second aspect of the present invention, a method for manufacturing a power semiconductor device is provided. The manufacturing method includes: forming an anode structure, a base region structure, a cathode structure, and a gate structure stacked in sequence; and forming a floating junction region in the base region structure by means of local irradiation through a metal baffle. The doping type of the floating junction region is opposite to that of the base region structure, and the floating junction region includes an upper platform region, a lower platform region, and a wavy region for connecting the upper platform region and the lower platform region. The floating junction region is configured to divert the current on the path between the anode structure and the cathode structure to the region between the cathode structure and the gate structure, and promote the redistribution of carriers in a dynamic avalanche manner in the region between the cathode structure and the gate structure.

[0014] Preferably, the window size W of the metal baffle satisfies , where D is the gap between the gate and the cathode of the power semiconductor device.

[0015] Preferably, the lateral size of the floating junction region is equal to the window size of the metal baffle.

[0016] Preferably, the irradiation energy E of the local irradiation is determined by the following formula:

[0017] ,

[0018] where is the range of the local irradiation; a and b are the first correlation constant and the second correlation constant of the material of the substrate of the power semiconductor device, respectively.

[0019] Preferably, the thicknesses of the upper platform region and the lower platform region of the floating junction region are the energy straggling widths of the local irradiation, where the energy straggling width is determined by the irradiation energy.

[0020] Preferably, the irradiation dose of the local irradiation is determined by the following formula:

[0021] ,

[0022] where ρ, E d are the density, displacement threshold of the substrate material of the power semiconductor device, respectively; NIEL is the non-ionizing energy loss of the particles of the local irradiation; is the doping concentration of the base region structure.

[0023] Through the above technical solution, the present invention creatively irradiates the unit cell structure of an existing power semiconductor device (such as a GCT device) locally with a metal baffle, so as to realize adding a wavy inversion floating junction region in the base region structure, which can divert the current on the path between the anode structure and the cathode structure to the region between the cathode structure and the gate structure, and promote the redistribution of carriers in this region in a dynamic avalanche manner, thereby reducing the base region lateral voltage drop at the outer edge of the cathode structure, achieving the effect of rapid commutation between the cathode structure and the gate structure, effectively preventing device breakdown caused by retriggering due to the convergence of local current, and further effectively improving the turn-off ability of the power semiconductor device. The process is simple and the cost is low.

[0024] Other features and advantages of the present invention will be described in detail in the subsequent specific implementation section. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The drawings are used to provide a further understanding of the embodiments of the present invention, and constitute a part of the specification, and are used to explain the embodiments of the present invention together with the following specific implementation, but do not constitute a limitation to the embodiments of the present invention. In the drawings:

[0026] Figure 1 is a schematic structural diagram of a power semiconductor device with high turn-off ability provided by an embodiment of the present invention;

[0027] Figure 2 is a schematic structural diagram of a power semiconductor device with high turn-off ability provided by an embodiment of the present invention; and

[0028] Figure 3 is a schematic structural diagram of a power semiconductor device with high turn-off ability provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0029] The following will describe in detail the specific implementation of the present invention with reference to the drawings. It should be understood that the specific implementation described here is only used to illustrate and explain the present invention, and is not used to limit the present invention.

[0030] Figure 1 is a schematic structural diagram of a power semiconductor device with high turn-off ability provided by an embodiment of the present invention. The power semiconductor device includes a unit cell structure. For example, the power semiconductor device includes one or more unit cell structures. As Figure 1 shown, the unit cell structure includes: an anode structure 10, a base region structure 20, a cathode structure 30, and a gate structure 40 formed in a stacked manner in sequence.

[0031] As Figure 1As shown, the base region structure 20 includes a floating junction region 201. The doping type of the floating junction region 201 is opposite to that of the base region structure 20. And the floating junction region 201 includes an upper platform region A, a lower platform region B, and a wavy region C for connecting the upper platform region A and the lower platform region B (i.e., the shape of the floating junction region is the same as the stepped shape of the cathode structure 30). That is to say, the floating junction region 201 is an inverted region with a wavy junction morphology, namely, a wavy inverted floating junction region.

[0032] Among them, the floating junction region is formed in the base region structure by means of local irradiation and through a metal baffle.

[0033] Among them, the floating junction region 201 is used to shunt the current on the path between the anode structure 10 and the cathode structure 30 to the region between the cathode structure 30 and the gate structure 40, and promotes the redistribution of carriers in the region between the cathode structure 30 and the gate structure 40 in a dynamic avalanche manner.

[0034] The above-mentioned anode structure 10 can be composed of multiple semiconductor layers. The doping types of the semiconductor layers can be the same or different, and the doping types include at least one of P-type, P-type, P+-type, N-type, N-type, N+-type. The above-mentioned base region structure 20 can be composed of multiple semiconductor layers. The doping types of the semiconductor layers can be the same or different, and the doping types include at least one of P-type, P-type, P+-type, N-type, N-type, N+-type. The above-mentioned cathode structure 30 can be composed of multiple semiconductor layers. The doping types of the semiconductor layers can be the same or different, and the doping types include at least one of P-type, P-type, P+-type, N-type, N-type, N+-type. The structure of the above-mentioned power semiconductor device can be, but is not limited to, a reverse blocking type, an asymmetric type, and a reverse conducting type structure.

[0035] The number of the above-mentioned floating junction regions 201 can be one or multiple. Preferably, in a unit cell structure, the number of the floating junction regions 201 can be the same as the number of the gate structures 40, or the number of the floating junction regions 201 can be the same as the number of the regions between the cathode structure 30 and the gate structure 40.

[0036] The doping type of the floating junction region 201 includes at least one of P-type, P-type, P+-type, N-type, N-type, N+-type. The position of the floating junction region 201 can be set according to actual needs. Preferably, the floating junction region 201 is arranged in the upper half region of the base region structure 20, and specifically can be arranged corresponding to the region between the cathode structure 30 and the gate structure 40. The thickness of the upper platform region and the lower platform region of the floating junction region 201 T can be set according to actual needs. Preferably, the thickness of the floating junction region 201 TThe range is from 5 μm to 50 μm. The width of the floating junction region 201 can be set according to actual requirements. The spacing between the floating junction regions 201 can be set according to actual requirements. Preferably, the spacing between the floating junction regions 201 can be determined by the position of the region between the cathode structure 30 and the gate structure 40. The doping concentration of the floating junction region 201 is greater than that of the base region structure 20.

[0037] Since the window of the metal baffle corresponds to the gap between the gate cathode, when radiating downward from the upper surface of the power semiconductor device, the step of the cathode structure 30 blocks to form a floating junction region with the same shape as the step, that is, a wavy floating junction region is formed. And considering that the doping concentration of the floating junction region is opposite to that of the base region, the floating junction region can be called a wavy inverted floating junction region.

[0038] For the power semiconductor device with high turn-off ability provided in this embodiment, by adding a wavy inverted floating junction region in the base region structure, the current on the path between the anode structure and the cathode structure can be shunted to the region between the cathode structure and the gate structure, thereby reducing the lateral voltage drop of the base region at the outer edge of the cathode structure, achieving the effect of rapid commutation between the cathode structure and the gate structure, and further effectively improving the turn-off ability of the power semiconductor device; moreover, the wavy-shaped inverted floating junction region can make the unit cell of the power semiconductor device more likely to undergo a dynamic avalanche process in the region corresponding to the cathode and the gate. Through a series of negative feedback processes (i.e., the redistribution of carriers), it can effectively prevent the device from breakdown due to the re-triggering caused by the convergence of local current, improve the turn-off current ability of the device under the condition of the same anode-cathode voltage, and expand the safe operating area of the entire device.

[0039] In one embodiment, as Figure 2 shown, the gate structure 40 includes a first gate 401 and a second gate 402. Correspondingly, the floating junction region 201 includes a first floating junction region 2011 and a second floating junction region 2012.

[0040] The lateral dimension of the first floating junction region 2011 is at least equal to the gap between the first gate 401 and the cathode structure 30; the lateral dimension of the second floating junction region 2012 is at least equal to the gap between the second gate 402 and the cathode structure 30.

[0041] The doping type of the above-mentioned first floating junction region 2011 includes at least one of P-type, P-type, P+-type, N-type, N-type, and N+-type. The thickness of the first floating junction region 2011 can be set according to actual requirements. Preferably, the thickness of the upper platform region and the lower platform region of the first floating junction region 2011 TThe range is from 5 μm to 50 μm. The width of the first floating junction region 2011 can be set according to actual requirements. The doping types of the second floating junction region 2012 include at least one of P-type, P-type, P+-type, N-type, N-type, and N+-type. The thickness of the second floating junction region 2012 can be set according to actual requirements. Preferably, the thicknesses of the upper platform region and the lower platform region of the second floating junction region 2012 T The range is from 5 μm to 50 μm. The width of the second floating junction region 2012 can be set according to actual requirements.

[0042] In one embodiment, as Figure 2 shown, the power semiconductor device further includes: a buffer structure 50 located between the base region structure 20 and the anode structure 10.

[0043] Specifically, the buffer structure 50 is stacked under the base region structure 20, and the buffer structure 50 is stacked on the anode structure 10; the doping type of the buffer structure determines whether the structure of the power semiconductor device is symmetric.

[0044] The buffer structure 50 may be composed of one or more semiconductor layers. The doping types of the semiconductor layers may be the same or different, and the doping types include at least one of P-type, P-type, P+-type, N-type, N-type, and N+-type.

[0045] The structure of the power semiconductor device may be, but is not limited to, a reverse blocking type, an asymmetric type, and a reverse conducting type structure. If the doping type of the buffer structure 50 is the same as the doping type of the anode structure 10, the structure of the power semiconductor device is determined to be a symmetric type; if the doping type of the buffer structure 50 is the same as the doping type of the base region structure 20, the structure of the power semiconductor device is determined to be an asymmetric type.

[0046] In one embodiment, as Figure 2 shown, the base region structure 20 includes: a first type base region 202 and a second type base region 203, which are sequentially stacked on the anode structure 10. Among them, the floating junction region 201 is included in the first type base region 202, and the doping type of the floating junction region 201 is opposite to the doping type of the first type base region 202.

[0047] Specifically, the first type base region 202 is stacked on the anode structure, and the second type base region 203 is stacked on the first type base region 202.

[0048] The doping type of the first type of base region 202 includes at least one of P type, P- type, P+ type, N type, N- type, and N+ type. The doping type of the second type of base region 203 includes at least one of P type, P- type, P+ type, N type, N- type, and N+ type. The second type of base region 203 may be composed of multiple semiconductor layers, and the doping types of the semiconductor layers may be the same or different.

[0049] In one embodiment, as Figure 2 shown, the second type of base region 203 includes a first subtype base region 2031 and a second subtype base region 2032, which are sequentially stacked on the first type of base region 202. Among them, the first subtype base region 2031 is a wavy base region.

[0050] Specifically, the first subtype base region 2031 is stacked on the first type of base region 202 layer, and the second subtype base region 2032 is stacked on the first subtype base region 2031. The first subtype base region 2031 is a wavy base region, which is similar to the wavy structure of the floating junction region 201.

[0051] The doping type of the above-mentioned first subtype base region 2031 includes at least one of P type, P- type, P+ type, N type, N- type, and N+ type. The doping type of the second subtype base region 2032 includes at least one of P type, P- type, P+ type, N type, N- type, and N+ type.

[0052] In one embodiment, as Figure 2 shown, the anode structure 10 includes: an anode 100 and an anode region 101 stacked in sequence, where the anode region 101 is located between the anode 100 and the base region structure 20.

[0053] Specifically, the anode region 101 is stacked under the base region structure 20. The above-mentioned anode region 101 may be composed of one or more semiconductor layers, and the doping types of the semiconductor layers may be the same or different. The doping type includes at least one of P type, P- type, P+ type, N type, N- type, and N+ type.

[0054] In one embodiment, as Figure 2 shown, the cathode structure 30 includes: an emission region 301 and a cathode 300 stacked in sequence; the emission region 301 is stacked on the base region structure 20.

[0055] Among them, the doping type of the emission region 301 includes at least one of P type, P- type, P+ type, N type, N- type, and N+ type.

[0056] In summary, through the local irradiation method and by using a metal baffle to add a wavy inverted floating junction region in the base region structure, the present invention can divert the current on the path between the anode structure and the cathode structure to the region between the cathode structure and the gate structure, and promote the redistribution of carriers in a dynamic avalanche manner in this region, thereby reducing the lateral base voltage drop at the outer edge of the cathode structure, achieving the effect of rapid commutation between the cathode structure and the gate structure, effectively preventing device breakdown caused by re-triggering due to the convergence of local current, and thus effectively improving the turn-off ability of the power semiconductor device.

[0057] At present, it is very difficult to break through the technical bottleneck of improving the turn-off ability of power semiconductor devices (such as GCT devices). For example, it can usually be achieved by changing the device structure, but the process is relatively complex and the cost is high. Therefore, the present invention proposes a method for increasing irradiation defects by proton / heavy ion irradiation of the local area between the gate and cathode of the unit cell of a power semiconductor device (such as a GCT device) to change the commutation path, so as to improve the turn-off ability of the unit cell of the device (such as a GCT). It can be realized only by locally irradiating the structure of the existing power semiconductor device (such as a GCT device) through a metal baffle. The process is simple and the cost is low, providing a realization method for improving the turn-off ability of the unit cell of a power semiconductor device (such as a GCT device).

[0058] An embodiment of the present invention provides a method for manufacturing a power semiconductor device, the manufacturing method including: forming an anode structure, a base region structure, a cathode structure and a gate structure stacked in sequence; and forming a floating junction region in the base region structure by using a local irradiation method and through a metal baffle.

[0059] Wherein, the doping type of the floating junction region is opposite to the doping type of the base region structure, and the floating junction region includes an upper platform region, a lower platform region and a wavy region for connecting the upper platform region and the lower platform region.

[0060] Wherein, the floating junction region is used to divert the current on the path between the anode structure and the cathode structure to the region between the cathode structure and the gate structure, and promote the redistribution of carriers in a dynamic avalanche manner in the region between the cathode structure and the gate structure.

[0061] In this embodiment, by performing proton / heavy ion He irradiation on the local area between the gate and cathode of the power semiconductor device (such as a GCT) cell, and changing the commutation path by increasing the irradiation defects to form an inversion region, the current on the path between the anode structure and the cathode structure can be shunted to the region between the cathode structure and the gate structure, and the redistribution of carriers can be promoted in a dynamic avalanche manner in this region, thereby reducing the base lateral voltage drop at the outer edge of the cathode structure, achieving the effect of rapid commutation between the cathode structure and the gate structure, effectively preventing device breakdown caused by retriggering due to the convergence of local current, and further effectively improving the turn-off ability of the power semiconductor device, thus improving the safe operating area of the device.

[0062] In one embodiment, the gate structure includes: a first gate and a second gate; the floating junction region includes a first floating junction region and a second floating junction region, and the lateral dimension of the first floating junction region is at least equal to the gap between the first gate and the cathode structure; the lateral dimension of the second floating junction region is at least equal to the gap between the second gate and the cathode structure.

[0063] In one embodiment, the power semiconductor device further includes: a buffer structure located between the base region structure and the anode structure.

[0064] In one embodiment, the base region structure includes: a first-type base region and a second-type base region, which are stacked on the anode structure in sequence, wherein the floating junction region is included in the first-type base region, and the doping type of the floating junction region is opposite to the doping type of the first-type base region.

[0065] In one embodiment, the second-type base region includes: a first-subtype base region and a second-subtype base region, which are stacked on the first-type base region in sequence, wherein the first-subtype base region is a wavy base region.

[0066] In one embodiment, the anode structure includes: an anode and an anode region, wherein the anode region is located between the anode and the base region structure.

[0067] The preparation method described in this embodiment can shunt the current on the path between the anode structure and the cathode structure to the region between the cathode structure and the gate structure by adding a wavy inverted floating junction region to the base region structure in a local irradiation manner, and promote the redistribution of carriers in a dynamic avalanche manner in this region, thereby reducing the base lateral voltage drop at the outer edge of the cathode structure, achieving the effect of rapid commutation between the cathode structure and the gate structure, effectively preventing device breakdown caused by retriggering due to the convergence of local current, and further effectively improving the turn-off ability of the power semiconductor device.

[0068] In one embodiment, the window size W of the metal baffle satisfies , where D is the gap between the gate and the cathode of the power semiconductor device.

[0069] Wherein, the gap between the window of the metal baffle and the gate-cathode corresponds. For example, the center position of the window of the metal baffle is located at the junction of the gate and the cathode on the upper surface of the chip.

[0070] Correspondingly, the lateral dimension of the floating junction region is equal to the window dimension of the metal baffle.

[0071] In one embodiment, when the local irradiation is proton irradiation, the irradiation energy of the local irradiation E is determined by the following formula:

[0072] (1),

[0073] Wherein, is the range of the local irradiation (which determines the distance from the center position of the upper platform region of the floating junction region to the upper surface of the substrate of the power semiconductor device); a and b are the first correlation constant and the second correlation constant of the material of the substrate of the power semiconductor device, respectively.

[0074] Correspondingly, the thickness of the upper platform region and the lower platform region of the floating junction region (i.e., T ) is the energy dispersion width of the local irradiation.

[0075] Wherein, the energy dispersion width is determined by the irradiation energy. For example, the energy dispersion width Δz can be determined by the following formula, where E is the irradiation energy:

[0076] (2).

[0077] Specifically, the distance from the center position of the upper platform region of the floating junction region to the upper surface of the substrate of the power semiconductor device can be determined as the range R , then the irradiation energy E can be determined according to the above formula (1), and further the energy dispersion width Δz can be determined according to formula (2).

[0078] In one embodiment, as Figure 2 shown, the second type base region 203 includes a first subtype base region 2031 and a second subtype base region 2032, which are sequentially stacked on the first type base region 202. Wherein, the first subtype base region 2031 is a wavy base region. Correspondingly, if it is required to achieve the distance from the lower surface of the first subtype base region 2031 to the longitudinal center position of the upper platform region of the floating junction region to be H , then the range R can be further determined, and then the irradiation energy E and the energy dispersion width Δz can be determined.

[0079] In one embodiment, the irradiation dose of the local irradiation is Determined by the following formula:

[0080] (3),

[0081] in, ρ, E d are the density and displacement threshold of the substrate material of the power semiconductor device, respectively; NIEL is the non-ionizing energy loss of locally irradiated particles; is the doping concentration of the base region structure.

[0082] According to the radiation dose ϕ And the following formula can determine the doping concentration Conc of the floating junction area:

[0083] (4).

[0084] Therefore, the energy through E The local proton / heavy ion irradiation is at a depth of R The energy dispersion width is Δ z , the inversion region with a wavy junction morphology with defect concentration Conc (such as Figure 3 As shown in the figure), a commutation path is effectively formed when the device is turned off, thereby improving the turn-off capability of the device.

[0085] The present invention mainly utilizes high energy proton / heavy ion irradiation to locally irradiate the gate cathode region of a power semiconductor device (such as a GCT device) through a metal baffle with a window (i.e., slot width) of W, and irradiates the N-base region to form a gate cathode region with a depth of R , the energy dispersion width is Δ z , and the irradiation area with the highest defect concentration Conc in the middle (such as Figure 3 As shown), by N - The base region forms an inversion doped P type irradiation area, and because the shape of this area is consistent with the shape of the cathode step, a secondary wave junction morphology is formed between the gate and the cathode, which effectively improves the carrier distribution during the shutdown process, optimizes the transient electric field distribution of the shutdown, realizes the formation of a commutation path during shutdown, and improves the shutdown capability of the device.

[0086] The structures of the power semiconductor devices provided in the above-mentioned embodiments can be implemented by the local irradiation method described above, and the formation of other structures except the floating junction area can refer to the existing preparation method, which is not the main improvement of the present invention and will not be described in detail here.

[0087] In summary, the present invention creatively irradiates the unit cell structure of an existing power semiconductor device (such as a GCT device) locally through a metal baffle, so as to realize adding a wavy inverse floating junction region in the base region structure, which can divert the current on the path between the anode structure and the cathode structure to the region between the cathode structure and the gate structure, and promote the redistribution of carriers in this region in a dynamic avalanche manner, thereby reducing the base region lateral voltage drop at the outer edge of the cathode structure, achieving the effect of rapid commutation between the cathode structure and the gate structure, effectively preventing device breakdown caused by retriggering due to the convergence of local current, and further effectively improving the turn-off ability of the power semiconductor device, with a simple process and low cost.

[0088] In the above embodiments, the GCT (Gate Commutated Thyristor) is mainly taken as an example for explanation and illustration. Of course, the present invention is not only applicable to GCT devices, but also applicable to IGBT (Insulate-Gate Bipolar Transistor), MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), GTO (gate turn-off thyristor), and other power devices with radial and annular distributions of the cathode region. The substrate material of the power device is not limited to silicon, and can also be a third-generation semiconductor material such as silicon carbide or gallium nitride.

[0089] The power semiconductor device in each embodiment of the present invention can be a GCT device, an IGBT device, a MOSFET device, a GTO device, etc.

[0090] The preferred embodiments of the present invention have been described in detail above with reference to the drawings. However, the present invention is not limited to the specific details in the above embodiments. Within the scope of the technical concept of the present invention, various simple modifications can be made to the technical solutions of the present invention, and these simple modifications all fall within the protection scope of the present invention.

[0091] In addition, it should be noted that, in the above specific embodiments, the various specific technical features described can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, the present invention will not separately describe various possible combination methods.

[0092] In addition, any combination can be made between different embodiments of the present invention, as long as it does not violate the idea of the present invention, it should also be regarded as the content disclosed by the present invention.

Claims

1. A power semiconductor device with high turn-off capability, characterized in that: The power semiconductor device comprises: a unit cell structure, the unit cell structure comprises: an anode structure, a base structure, a cathode structure, and a gate structure which are stacked in sequence, wherein the base structure comprises a floating junction region, the doping type of the floating junction region is opposite to the doping type of the base structure, and the floating junction region comprises an upper platform region, a lower platform region, and a wavy region for connecting the upper platform region and the lower platform region, wherein the projections of the upper platform region and the lower platform region along the stacking direction do not overlap with each other, The floating junction region is formed in the base region structure by local irradiation and through a metal baffle, and The floating junction region is used to shunt the current on the path between the anode structure and the cathode structure to the region between the cathode structure and the gate structure, and promote the redistribution of carriers in the region between the cathode structure and the gate structure in a dynamic avalanche manner.

2. The power semiconductor device according to claim 1, characterized in that: The gate structure includes: a first gate and a second gate; the floating junction area includes a first floating junction area and a second floating junction area, the lateral size of the first floating junction area is at least equal to the gap between the first gate and the cathode structure; the lateral size of the second floating junction area is at least equal to the gap between the second gate and the cathode structure.

3. The power semiconductor device according to claim 1, characterized in that: The unit cell structure further includes: a buffer region structure located between the base region structure and the anode structure.

4. The power semiconductor device according to claim 1, characterized in that: The base region structure includes: a first type base region and a second type base region, which are sequentially stacked on the anode structure, wherein the first type base region includes the floating junction region, and the doping type of the floating junction region is opposite to the doping type of the first type base region.

5. The power semiconductor device according to claim 4, characterized in that: The second type base region includes: a first sub-type base region and a second sub-type base region, which are sequentially stacked on the first type base region, wherein the first sub-type base region is a wavy base region.

6. The power semiconductor device according to any one of claims 1 to 5, characterized in that: The anode structure includes: an anode and an anode region, wherein the anode region is located between the anode and the base region structure.

7. A method for preparing a power semiconductor device, characterized in that: The preparation method comprises: forming an anode structure, a base structure, a cathode structure and a gate structure stacked in sequence; and A floating junction region is formed in the base region structure by local irradiation and through a metal baffle, wherein the doping type of the floating junction region is opposite to the doping type of the base region structure, and the floating junction region includes an upper platform region, a lower platform region, and a wavy region for connecting the upper platform region and the lower platform region, wherein the projections of the upper platform region and the lower platform region along the stacking direction do not overlap with each other, The floating junction region is used to shunt the current on the path between the anode structure and the cathode structure to the region between the cathode structure and the gate structure, and promote the redistribution of carriers in the region between the cathode structure and the gate structure in a dynamic avalanche manner.

8. The preparation method according to claim 7, characterized in that: The window size W of the metal baffle satisfies , wherein D is the gap between the gate and cathode of the power semiconductor device.

9. The preparation method according to claim 8, characterized in that: The lateral size of the floating junction region is equal to the window size of the metal baffle.

10. The preparation method according to claim 7, characterized in that: In the case where the local irradiation is proton irradiation, the irradiation energy of the local irradiation E Determined by the following formula: ， in, is the range of local irradiation; a and b are respectively the first related constant and the second related constant of the material of the substrate of the power semiconductor device.

11. The preparation method according to claim 10, characterized in that: The thickness of the upper platform region and the lower platform region of the floating junction region is the energy dispersion width of the local irradiation, wherein the energy dispersion width is determined by the irradiation energy.

12. The preparation method according to claim 7, characterized in that: Radiation dose of local irradiation Determined by the following formula: ， in, ρ、E d are the density and displacement threshold of the substrate material of the power semiconductor device, respectively; NIEL is the non-ionizing energy loss of locally irradiated particles; is the doping concentration of the base region structure.

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