Power semiconductor device and preparation method thereof

Abstract

The invention discloses a power semiconductor device and a preparation method thereof, the power semiconductor device comprises a central region and a peripheral region located at the periphery of the central region, the central region and the peripheral region both comprise a plurality of cellular structures, and the cellular structures and pseudo cellular structures both comprise buffer regions and base regions which are sequentially arranged along a first direction, the central region further comprises a pseudo cell structure with a conductive channel, and a buffer region in the pseudo cell structure is provided with a contact surface with the base region and a first surface opposite to the contact surface along a first direction; at least part of the conductive channel is embedded in a preset area in the buffer area, the preset area is spaced from the contact surface, the part, embedded in the preset area, of the conductive channel extends into the preset area from the second surface, and the preset area is used for forming a breakdown area under the condition that the power semiconductor device bears designed breakdown voltage. The problem of poor breakdown voltage consistency caused by an overvoltage protection technology applied to a power semiconductor device in the prior art is solved.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular to a power semiconductor device and a method for preparing the same. Background Art

[0002] In the field of power electronics, high power density and high reliability are the two major driving forces for technological innovation in semiconductor devices. However, an important challenge faced by devices under extreme working conditions is overvoltage protection, that is, ensuring that the device can safely conduct or bypass excessive voltage when the design voltage specification is exceeded to prevent damage to the entire system. Although traditional overvoltage protection mechanisms, such as edge passivation technology and diode (Breakdown Over Diode, BOD) structure for overvoltage protection, have improved the overvoltage resistance of devices to a certain extent, they have obvious limitations in temperature stability, process complexity, and breakdown voltage consistency.

[0003] Among them, edge passivation technology reduces electric field concentration by modifying the physical and chemical properties of the device edge, thereby increasing the device's breakdown voltage. However, this method is difficult to overcome the voltage dispersion caused by material defects and process variations, especially in high-voltage applications, where such dispersion may seriously threaten the safety and reliability of the system. The BOD structure, as an intrinsic protection mechanism, achieves overvoltage protection through pre-designed weak points. Although BOD can effectively stabilize the breakdown voltage in some cases, the same structure may show significant performance differences at different temperatures because the avalanche breakdown mechanism is extremely sensitive to temperature, which limits its broad-spectrum applicability in applications with large temperature changes and high power density.

[0004] In recent years, with the rapid development of power electronics technology, especially the widespread application of high-density modular multi-level converters, more stringent requirements have been put forward for power semiconductor devices, especially in overvoltage breakdown control. Although it is feasible to directly use external circuits to achieve overvoltage protection, it may be affected by electromagnetic interference and system power supply abnormalities, resulting in failure of the protection mechanism. Therefore, research and development of overvoltage protection technology that can be implemented at the chip structure level has become a key direction for improving the performance and stability of power electronics systems. Summary of the invention

[0005] The present application provides a power semiconductor device and a method for preparing the same, in order to solve the problem of poor breakdown voltage consistency caused by an overvoltage protection technology applied to a power semiconductor device in the related art.

[0006] According to one aspect of the present application, a power semiconductor device is provided, comprising a central region and a peripheral region located outside the central region, wherein the central region and the peripheral region both comprise a plurality of cellular structures, the central region further comprises a pseudo-cellular structure, the cellular structure and the pseudo-cellular structure both comprise a buffer region and a base region sequentially arranged along a first direction, the pseudo-cellular structure further comprises a conductive channel, wherein: the buffer region has a contact surface with the base region and a first surface opposite to the contact surface along the first direction; at least part of the conductive channel is embedded in a predetermined region in the buffer region, the predetermined region has a second surface located in the first surface, and the predetermined region is spaced from the contact surface, a portion of the conductive channel embedded in the predetermined region extends from the second surface to the inside of the predetermined region, and the predetermined region is used to form a breakdown region when the power semiconductor device is subjected to a breakdown voltage.

[0007] Optionally, the conductive pathway comprises nanowires.

[0008] Optionally, the nanowires are selected from any one or more of carbon nanotubes, silicon nanowires, silicon germanium nanowires, silicon carbide nanowires and metallic nanowires.

[0009] Optionally, the base region includes a first doping region and a second doping region sequentially distributed along the first direction, and the first doping region and the second doping region have different doping types.

[0010] Optionally, the buffer zone has the same doping type as the first doping zone, wherein: the buffer zone is a third doping zone, or the buffer zone includes a fourth doping zone and a fifth doping zone distributed along the second direction, the predetermined area is located in the fourth doping zone, the doping concentration of the fourth doping zone is less than the doping concentration of the fifth doping zone, and the second direction is perpendicular to the first direction.

[0011] Optionally, the buffer zone includes along the fourth doping zone and the fifth doping zone, a surface of the buffer zone facing away from the base zone is a third surface, the orthographic projection of the fourth doping zone on the third surface is a first projection, the orthographic projection of the fifth doping zone on the third surface is a second projection, and the area of ​​the first projection is smaller than the area of ​​the second projection.

[0012] Optionally, the power semiconductor device is an integrated gate-commutated thyristor, which further includes a first electrode structure, a second electrode structure and a third electrode, wherein: the first electrode structure is located on a side of the buffer region away from the base region, and the first electrode structure includes an anode and an anode emitter sequentially distributed along the first direction; the second electrode structure and the third electrode are located on the same side of the base region, the second electrode structure includes a cathode and a cathode emitter sequentially distributed along the first direction, a portion of the cathode emitter is located in the second doping region, and the third electrode is a gate in contact with the second doping region; the conductive path extends from a surface of the anode emitter away from the buffer region to the inside of the predetermined region; the first doping region and the cathode emitter have a first doping type, and the second doping region and the anode emitter have a second doping type.

[0013] According to another aspect of the present application, a method for preparing a power semiconductor device is provided, which is used for the power semiconductor device, and the preparation method includes the following steps: providing a first substrate, in which a buffer zone and a base zone are sequentially distributed along a first direction, the buffer zone has a contact surface with the base zone and a first surface opposite to the contact surface along the first direction; embedding at least a portion of a conductive channel in a predetermined area of ​​the buffer zone, and obtaining a power semiconductor device with a pseudo-cellular structure, the predetermined area has a second surface located in the first surface, and the predetermined area is spaced from the contact surface, and a portion of the conductive channel embedded in the predetermined area extends from the second surface to the inside of the predetermined area, the power semiconductor device includes a central area and a peripheral area located outside the central area, and the central area has the pseudo-cellular structure.

[0014] Optionally, the step of embedding at least a portion of the conductive path in the predetermined area includes: forming at least one hole in the predetermined area, the hole extending at least from the second surface to the inside of the predetermined area; filling the hole with conductive material and curing it to form the conductive path.

[0015] Optionally, the power semiconductor device is an integrated gate-commutated thyristor, the base region includes a first doped region and a second doped region sequentially distributed along the first direction, the first substrate also includes an anode emitter and a cathode emitter, the anode emitter is located on a side of the base region close to the first doped region, a portion of the cathode emitter is located on a side of the base region close to the second doped region, and another portion of the cathode emitter is located in the second doped region, and the step of forming the hole includes: forming the hole from a side surface of the anode emitter away from the buffer zone to penetrate into the predetermined area; after the step of forming the conductive path, the conductive path extends from a side surface of the anode emitter away from the buffer zone to the inside of the predetermined area.

[0016] Through the present application, a power semiconductor device is proposed, including a central area and a peripheral area located outside the central area. The central area also has a pseudo-cellular structure. By embedding a conductive channel in a predetermined area of ​​the buffer zone in the pseudo-cellular structure to change the local conductivity, the breakdown point can be guided to occur precisely in the predetermined area to form a breakdown area, so that at a certain high voltage, the electric field can reach the predetermined area with the conductive channel in advance, so that the area is broken down. The introduction of the above-mentioned conductive channel not only overcomes the limitations of traditional methods, such as poor temperature stability and uncontrollable breakdown point position, but also can achieve precise control of overvoltage breakdown points without significantly increasing manufacturing complexity, thereby improving the reliability of the device under extreme conditions. In addition, the present application also locally optimizes the electric field distribution by introducing the above-mentioned conductive channel, thereby avoiding the need for complex design of each doping area in the entire buffer zone structure and dependence on process control, and achieving a more consistent breakdown voltage. Therefore, the cellular structure provided in the present application can achieve overvoltage protection with high breakdown voltage consistency and controllable breakdown point, so as to overcome the limitations of traditional edge passivation and BOD structure, especially in high voltage and high power applications, and solve the problem of poor breakdown voltage consistency caused by the overvoltage protection technology applied to power semiconductor devices in the related technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings constituting a part of the present application are used to provide a further understanding of the present application. The illustrative embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0018] Figure 1 A schematic diagram of a partial cross-sectional structure of a power semiconductor device according to an embodiment of the present application is shown;

[0019] Figure 2 Shows Figure 1 A schematic cross-sectional structure diagram of a pseudo-cell structure in a power semiconductor device shown in FIG.

[0020] Figure 3 A schematic cross-sectional structure diagram of a buffer zone embedded in a conductive channel in a power semiconductor device according to an embodiment of the present application is shown;

[0021] Figure 4 A schematic cross-sectional structure diagram of a buffer zone embedded in a conductive channel in another power semiconductor device according to an embodiment of the present application is shown;

[0022] Figure 5 Shows Figure 1 A schematic cross-sectional structure diagram of a cell structure in a power semiconductor device shown in FIG.

[0023] Figure 6 A schematic diagram of the structure of a process of manufacturing a power semiconductor device according to an embodiment of the present application is shown.

[0024] The above drawings include the following reference numerals:

[0025] 1. Pseudo-cell structure; 2. Cell structure; 10. First electrode structure; 110. Anode; 120. Anode emitter; 20. Buffer zone; 201. Predetermined region; 210. Fourth doping region; 220. Fifth doping region; 30. Base region; 310. First doping region; 320. Second doping region; 40. Second electrode structure; 410. Cathode emitter; 420. Cathode; 50. Third electrode; 60. Conductive channel; 70. Insulating layer. DETAILED DESCRIPTION

[0026] It should be noted that the following detailed descriptions are illustrative and are intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present application belongs.

[0027] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0028] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so as to describe the embodiments of the present invention described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0029] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be intermediate elements. Moreover, in the specification and claims, when it is described that an element is "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element through a third element.

[0030] As introduced in the background technology, although traditional overvoltage protection mechanisms, such as edge passivation technology and the diode (Breakdown Over Diode, BOD) structure used for overvoltage protection, have improved the overvoltage resistance of the device to a certain extent, they have obvious limitations in terms of temperature stability, process complexity, and breakdown voltage consistency. In order to solve the problem that the overvoltage protection technology applied to power semiconductor devices in the prior art leads to poor breakdown voltage consistency, the embodiments of the present application provide a power semiconductor device and a preparation method thereof.

[0031] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0032] According to an embodiment of the present application, a power semiconductor device is provided, such as Figures 1 to 5 As shown, Figure 1 FIG. 4 shows a partial cross-sectional structure of a power semiconductor device. Figure 2 It is shown in Figure 1 The cross-sectional structure of the pseudo-cell structure 1 in Figure 3 and Figure 4 The Figure 2 The cross-sectional structure of the buffer zone 20 in different embodiments, Figure 5 It is shown in Figure 1The cross-sectional structure of the cellular structure 2 in the power semiconductor device includes a central area A and a peripheral area B located on the periphery of the central area A. The central area A and the peripheral area B each include a plurality of cellular structures 2. The central area A also includes a pseudo-cellular structure 1. The cellular structure 2 and the pseudo-cellular structure 1 each include a buffer area 20 and a base area 30 sequentially arranged along a first direction a. The pseudo-cellular structure 1 also includes a conductive channel 60. In the pseudo-cellular structure 1; at least part of the conductive channel 60 is embedded in a predetermined area 201 of the buffer area 20. The predetermined area 201 has a second surface located in the first surface, and the predetermined area 201 is spaced from the contact surface. The portion of the conductive channel 60 embedded in the predetermined area 201 extends from the second surface to the inside of the predetermined area 201. The predetermined area 201 is used to form a breakdown region when the power semiconductor device is subjected to a breakdown voltage.

[0033] In the above embodiment of the present application, by embedding the conductive channel 60 in the predetermined area of ​​the buffer zone 20 in the pseudo-cell structure 1 to change the local conductivity, the breakdown point can be guided to occur precisely in the predetermined area to form a breakdown area, so that at a certain high voltage, the electric field can reach the predetermined area with the conductive channel in advance, so that the area is broken down. The introduction of the above conductive channel 60 not only overcomes the limitations of the traditional method, such as poor temperature stability and uncontrollable breakdown point position, but also can achieve precise control of the overvoltage breakdown point without significantly increasing the manufacturing complexity, thereby improving the reliability of the device under extreme conditions. In addition, the present application also optimizes the electric field distribution locally by introducing the above conductive channel 60, thereby avoiding the need for complex design of each doping area in the entire buffer zone 20 structure and the reliance on process control, and achieving a more consistent breakdown voltage. Therefore, the present application can achieve overvoltage protection with high breakdown voltage consistency and controllable breakdown point, so as to overcome the limitations of traditional edge passivation and BOD structure, especially in high voltage and high power applications, and solves the problem of poor breakdown voltage consistency caused by the overvoltage protection technology applied to power semiconductor devices in the related art.

[0034] Furthermore, in the mass production of power semiconductor devices, the breakdown voltage of each device varies within a certain range. Although traditional edge passivation treatment and BOD structure can improve the breakdown voltage to a certain extent, they are affected by process stability and temperature fluctuations, and it is difficult to achieve ideal breakdown voltage consistency, especially under extreme working conditions. The embodiment of the present application embeds a conductive channel 60 (such as a nanowire) in a predetermined area of ​​the buffer zone 20 to achieve precise control of local conductivity, thereby guiding the breakdown point to occur precisely in the predetermined area. This design can significantly improve the consistency of the breakdown voltage, because it not only reduces the voltage difference caused by process and material uncertainties, but also ensures that the breakdown voltage is more uniform and controllable in all devices through local optimization, and maintains good performance and reliability even under temperature changes and high voltage and high current applications, thereby solving the limitations of traditional technologies in terms of breakdown voltage consistency.

[0035] In some optional embodiments, such as Figures 1 to 5 As shown, the conductive channel 60 embedded in the buffer zone 20 includes nanowires. Nanowires have extremely high aspect ratios and excellent electrical properties, and can significantly improve the conductive properties of power semiconductor devices. For example, carbon nanotubes are widely considered to be ideal conductive channel materials due to their unique structure and extremely low resistivity. Silicon nanowires and silicon germanium nanowires can effectively improve the conductivity of devices without destroying the overall structure of the device due to their good compatibility with silicon-based semiconductor materials.

[0036] Furthermore, temperature stability is a key performance indicator in power semiconductor devices, especially in high temperature or temperature fluctuation working environments. The breakdown voltage or avalanche breakdown voltage of conventional power semiconductor devices, such as IGBT, MOSFET, and thyristor devices such as GTO and IGCT, may be affected by temperature changes, resulting in performance degradation or instability. This is because temperature changes affect the carrier concentration, mobility and recombination rate of the material, thereby affecting the conductivity and breakdown characteristics of the device. In the embodiment of the present application, by embedding the conductive channel 60 in the predetermined area of ​​the buffer zone 20, a region with highly controllable conductivity can be created to improve the local conductivity, so that a conductivity distribution map that is relatively insensitive to temperature changes can be formed in the predetermined area of ​​the buffer zone 20 by precisely controlling the type, size, distribution and density of the nanowires. This is because the nanostructure may have different thermoelectric properties from bulk materials, such as a smaller thermal expansion coefficient, different temperature-dependent carrier concentration or mobility, and possible quantum confinement effects.

[0037] For example, some metal nanoparticles have relatively stable conductivity within a specific temperature range, which can reduce the sensitivity of the overall device conductivity to temperature; the band structure and carrier behavior of semiconductor nanowires may be less affected by temperature than bulk semiconductor materials, especially quantum effects common in low-dimensional structures can provide additional temperature stabilization mechanisms.

[0038] Therefore, when the conductivity of the predetermined area 201 in the buffer zone 20 is relatively stable to temperature changes, the electric field distribution and breakdown characteristics of the overall device will also remain stable with temperature changes. This means that even if the ambient temperature rises or falls, the breakdown voltage of the device can be maintained at a relatively constant level, thereby improving the performance reliability and stability of the power semiconductor device under different temperature conditions. This improvement in temperature stability is crucial for the operation of power semiconductor devices in extreme environments, allowing them to maintain high efficiency and safety over a wider temperature range.

[0039] In some optional embodiments, the nanowires are selected from any one or more of carbon nanotubes, silicon nanowires, silicon germanium nanowires, carbon silicide nanowires and metallic nanowires.

[0040] Specifically, carbon nanotubes, silicon nanowires, silicon germanium nanowires, carbon silicide nanowires and metallic nanowires are selected as materials for the conductive channel based on the excellent electrical properties of these materials and their compatibility with semiconductor devices. Carbon nanotubes, due to their unique structure and high conductivity, can effectively reduce energy loss during current transmission and improve the efficiency of the device. Silicon nanowires and silicon germanium nanowires, due to their compatibility with silicon-based materials, can optimize the electrical performance of the device without changing the basic structure of the device. Carbon silicide nanowires and metallic nanowires, due to their high conductivity and stability, can maintain stable performance of the device under extreme conditions. The use of these materials not only solves the problem of performance degradation of traditional power semiconductor devices in high-voltage and high-current applications, but also improves the reliability of the device, enabling it to maintain a stable working state in harsh environments.

[0041] It should be noted that the material selection for the conductive channel also includes but is not limited to other types of highly conductive nanomaterials. The use of these materials should be based on the performance requirements and application environment of the device. In the case of multiple conductive channels, their distribution can be reasonably set according to actual needs.

[0042] In the embodiments of the present application, graphene and / or two-dimensional materials (such as transition metal dichalcogenides, TMDs) can also be used as materials for the conductive channel. The two-dimensional structure of the above materials has high electron mobility and excellent thermal conductivity, thereby improving the conductivity and thermal stability of the device compared to traditional nanowires such as silicon nanowires or carbon nanotubes.

[0043] Specifically, the material of the conductive channel in the embodiment of the present application can be graphene, which can significantly reduce the conductivity loss in the device and improve the efficiency of the device; and graphene also has an abnormally high thermal conductivity (theoretically up to 5300 W / mK), which enables it to effectively conduct heat out of the device to avoid local overheating, thereby enhancing the thermal stability of the device; in addition, the chemical stability of graphene also enables it to maintain its electrical performance without attenuation under harsh conditions.

[0044] Specifically, the material of the conductive channel in the embodiment of the present application can also be TMDs. TMDs (such as MoS2, WS2) have semiconductor properties and their band structure can be adjusted to obtain better electrical properties, thereby being able to exhibit higher carrier mobility under specific conditions; and, TMDs materials also have high thermal stability and can maintain structural integrity under high temperature conditions.

[0045] In some optional embodiments, metal nanoparticles and / or semiconductor nanoparticles, such as gold, silver or indium particles, are also embedded in the predetermined area of ​​the buffer zone. By embedding the above nanoparticles, the local electrical conductivity can be enhanced, and the high thermal conductivity of the nanoparticles can be used to improve the thermal management of the device.

[0046] In some optional embodiments, arrayed nanowires, such as carbon nanotube arrays, are used. The arrayed nanowires can effectively adjust the conductivity of the buffer zone and improve the thermal stability of the device by increasing the heat dissipation path.

[0047] For example, Figure 2 As shown, in the first direction a, the thickness of the buffer zone 20 is 20-50 μm, the conductive channel 60 is a nanowire with a height in the range of 10-35 μm and a diameter in the range of 3-50 μm, and the nanowire is a plurality of nanowires arranged in an array along the second direction and the third direction. The arrangement of the nanowires in the predetermined area 201, and the process dimensions of the buffer zone and the nanowires are not limited to the above ranges, and can be adjusted in combination with the nanowire process and the deep trench etching process, and are not specifically limited in the present embodiment of the application.

[0048] In some optional embodiments, such as Figure 2As shown, the base region 30 includes a first doping region 310 and a second doping region 320 sequentially distributed along a first direction a, and the first doping region 310 and the second doping region 320 have different doping types. When the power semiconductor device in the embodiment of the present application is subjected to a breakdown voltage, an electric field is generated in the first doping region 310 and the second doping region 320.

[0049] In the above optional implementation, if Figure 2 As shown, the first doping region 310 and the second doping region 320 have different doping types, that is, the first doping region 310 and the second doping region 320 are P-type doping and N-type doping, respectively. Specifically, when the first doping region 310 is a P-type doping region, the second doping region 320 is an N-type doping region, and when the first doping region 310 is an N-type doping region, the second doping region 320 is a P-type doping region.

[0050] In the above optional implementation, if Figure 2 As shown, the buffer region 20 has the same doping type as the first doping region 310. In this case, the buffer region 20 may be a third doping region, such as Figure 2 and Figure 3 As shown, the buffer zone 20 is a region having a single doping concentration and the same doping type as the first doping region 310. When the power semiconductor device in the embodiment of the present application is subjected to a breakdown voltage, the third doping region will be subjected to the electric field generated in the first doping region and the second doping region, and breakdown will occur in a predetermined region 201 of the third doping region.

[0051] In other optional embodiments, such as Figure 4 As shown, the buffer region 20 includes a fourth doping region 210 and a fifth doping region 220 distributed along the second direction b, the predetermined region 201 is located in the fourth doping region 210, the doping concentration of the fourth doping region 210 is less than the doping concentration of the fifth doping region 220, and the second direction b is perpendicular to Figure 2 The first direction a is shown in .

[0052] In the above optional embodiment, the buffer zone 20 can be divided into a plurality of regions with different doping concentrations and the same doping type as the first doping zone 310. Taking the buffer zone 20 having the fourth doping zone 210 and the fifth doping zone 220 as an example, when the power semiconductor device in the embodiment of the present application is subjected to a breakdown voltage, since the doping concentration of the fourth doping zone 210 is less than the doping concentration of the fifth doping zone 220, the fourth doping zone 210 will be subjected to the electric field generated in the first doping zone 310 and the second doping zone 320, and breakdown will occur in a predetermined area 201 of the fourth doping zone 210.

[0053] In some optional embodiments, such as Figure 2 and Figure 4As shown, the side surface of the buffer zone 20 facing away from the base region 30 is the third surface, the orthographic projection of the fourth doping region 210 on the third surface is the first projection, and the orthographic projection of the fifth doping region 220 on the third surface is the second projection, and the area of ​​the first projection is smaller than the area of ​​the second projection.

[0054] By adopting the above optional implementation, the electric field distribution inside the device can be optimized and the breakdown voltage of the device can be improved. Specifically, if the area of ​​the first projection is smaller than the area of ​​the second projection, then when the device is working, the current will be more concentrated through the predetermined area 201 in the fourth doping region 210, reducing the energy loss during the current transmission process and improving the efficiency of the device. At the same time, the control of the size of the fourth doping region 210 can also optimize the electrical performance of the device and improve its stability under high voltage and high current conditions. Therefore, the above optional implementation not only solves the problem of performance degradation of traditional power semiconductor devices in high voltage and high current applications, but also improves the reliability of the device, enabling it to maintain a stable working state in harsh environments.

[0055] The power semiconductor device may be an integrated gate-commutated thyristor (IGCT), a gate turn-off thyristor (GTO), an insulated gate bipolar transistor (IGBT), etc., which is not specifically limited in the embodiments of the present application.

[0056] Taking the power semiconductor device in the embodiment of the present application as an integrated gate-commutated thyristor as an example, Figures 1 to 3 as well as Figure 5 As shown, the integrated gate-commutated thyristor further includes a first electrode structure 10, a second electrode structure 40 and a third electrode 50, wherein: the first electrode structure 10 is located on a side of the buffer region 20 away from the base region 30, and the first electrode structure 10 includes an anode 110 and an anode emitter 120 sequentially distributed along a first direction a; the second electrode structure 40 and the third electrode 50 are located on the same side of the base region 30, and in the first direction a, the base region 30 includes a first doping region 310 and a second doping region 320 sequentially distributed, the second electrode structure 40 includes a cathode 420 and a cathode emitter 410, a portion of the cathode emitter 410 is located in the second doping region 320, and the third electrode 50 in the cell structure 2 is a gate in contact with the second doping region 320; the conductive channel 60 extends from a side surface of the anode emitter 120 away from the buffer region 20 to the inside of the predetermined region 201; the first doping region 310 and the cathode emitter 410 have a first doping type, and the second doping region 320 and the anode emitter 120 have a second doping type.

[0057] Specifically, in the integrated gate-commutated thyristor, the arrangement of the first doping region 310 and the second doping region 320, as well as the distribution of the first electrode structure 10 and the second electrode structure 40, are based on the specific working principle and performance requirements of the device. Among them, the base region 30 is the core of the IGCT, which is composed of the first doping region 310 and the second doping region distributed in sequence. The first doping region 310 has a first doping type (such as N-type doping), which provides a path for the transmission of electrons when the IGCT is turned on. The second doping region 320 has a second doping type (such as P-type doping) and is adjacent to the first doping region 310. It provides a path for the transmission of holes when the IGCT is turned on; the anode 110 and the cathode 420 are respectively used as ports for the positive and negative flow of current, while the anode emitter 120 and the cathode emitter 410 are used to enhance current control. The gate is used as a control element, and the fast turn-on and turn-off control of the IGCT is realized by contacting the second doping region 320.

[0058] For example, the first doping region 310 and the cathode emitter 410 are N-type doped, and the second doping region 320 and the anode emitter 120 are P-type doped, or the first doping region 310 and the cathode emitter 410 are P-type doped, and the second doping region 320 and the anode emitter 120 are N-type doped. The P-type dopant may include boron, and the N-type dopant may include phosphorus and / or arsenic.

[0059] In some optional embodiments, such as Figure 5 As shown, the cell structure 2 further includes a plurality of insulating layers 70, and the insulating layer 70 is located between the third electrode 50 and the second electrode structure 40, and is used to insulate the third electrode 50 and the second electrode structure 40. Taking the power semiconductor device in the embodiment of the present application as an IGCT as an example, the insulating layer 70 is located between the gate and the second electrode structure 40 composed of the cathode emitter 410 and the cathode 420, and the insulating layer 70 is in contact with the gate and the cathode 420 and covers the side wall of the cathode emitter 410. The material of the above-mentioned insulating layer 70 can be an insulating material such as silicon dioxide, silicon oxide and silicon oxynitride, which is not specifically limited in the embodiment of the present application.

[0060] According to an embodiment of the present application, a method for preparing a power semiconductor device is also provided, which is used for the power semiconductor device.

[0061] Figure 6 FIG. 1 is a flow chart of a method for preparing a cell structure of a power semiconductor device tube according to an embodiment of the present application. Figure 6 As shown, the method comprises the following steps:

[0062] Step S201, providing a first substrate, wherein a buffer region and a base region sequentially distributed along a first direction are formed in the first substrate, wherein the buffer region has a contact surface with the base region and a first surface opposite to the contact surface along the first direction;

[0063] Step S202, embedding at least a portion of the conductive channel in a predetermined area of ​​the buffer zone, and obtaining a power semiconductor device with a pseudo-cellular structure, wherein the predetermined area has a second surface located in the first surface, and the predetermined area is spaced from the contact surface, and a portion of the conductive channel embedded in the predetermined area extends from the second surface to the inside of the predetermined area, and the power semiconductor device includes a central area and a peripheral area located outside the central area, and the central area has a pseudo-cellular structure.

[0064] In the above-mentioned embodiments of the present application, by embedding a conductive channel in a predetermined area of ​​the buffer zone in the pseudo-cellular structure to change the local conductivity, the breakdown point can be guided to occur precisely in the predetermined area to form a breakdown area, so that at a certain high voltage, the electric field can reach the predetermined area with the conductive channel in advance, so that the area is broken down. The introduction of the above-mentioned conductive channel not only overcomes the limitations of traditional methods, such as poor temperature stability and uncontrollable breakdown point position, but also can achieve precise control of overvoltage breakdown points without significantly increasing manufacturing complexity, thereby improving the reliability of the device under extreme conditions. In addition, the present application also locally optimizes the electric field distribution by introducing the above-mentioned conductive channel, thereby avoiding the need for complex design of each doping area in the entire buffer zone structure and dependence on process control, and achieving a more consistent breakdown voltage. Therefore, the cellular structure provided in the present application can achieve overvoltage protection with high breakdown voltage consistency and controllable breakdown point, so as to overcome the limitations of traditional edge passivation and BOD structures, especially in high voltage and high power applications, and solves the problem of poor breakdown voltage consistency caused by overvoltage protection technology applied to power semiconductor devices in related technologies.

[0065] The following is a more detailed description of exemplary embodiments of the method for preparing a power semiconductor device provided in the present application. However, these exemplary embodiments can be implemented in a variety of different forms and should not be interpreted as being limited to the embodiments described herein. It should be understood that these embodiments are provided to make the disclosure of the present application thorough and complete, and to fully convey the concepts of these exemplary embodiments to those of ordinary skill in the art.

[0066] First, step S201 is performed: providing a first substrate, in which a buffer region and a base region sequentially distributed along a first direction are formed, and the buffer region has a contact surface with the base region and a first surface opposite to the contact surface along the first direction.

[0067] The first substrate is obtained by performing ion implantation in a substrate to form a buffer region and a base region. The material of the substrate may be any one of silicon, silicon carbide, gallium nitride, diamond, gallium arsenide, aluminum gallium arsenide, zinc oxide and aluminum gallium nitrogen, and the substrate may be a doped substrate.

[0068] After providing the first substrate, step S202 is performed: embedding at least a portion of the conductive channel in a predetermined area of ​​the buffer zone, and obtaining a power semiconductor device having a pseudo-cellular structure, wherein the predetermined area has a second surface located in the first surface, and the predetermined area is spaced from the contact surface, and a portion of the conductive channel embedded in the predetermined area extends from the second surface to the inside of the predetermined area, and the power semiconductor device includes a central area and a peripheral area located outside the central area, and the central area has a pseudo-cellular structure.

[0069] In some optional embodiments, the step of embedding a conductive path in a predetermined area of ​​the buffer zone includes: forming at least one hole in the predetermined area, the hole extending from the second surface to the interior of the predetermined area; filling the hole with a conductive material and curing it to form a conductive path.

[0070] Exemplarily, embedding the conductive channel may include the following steps:

[0071] Electrochemical treatment: Electrochemical treatment is performed on a predetermined area of ​​the buffer in a specific electrolyte. Electrochemical treatment can form nanoscale holes or grooves to create space for the embedding of nanomaterials.

[0072] Nanomaterial embedding: introducing a solution containing the target nanomaterial (such as a solution containing Si NWs) into the holes or grooves of the predetermined area, and embedding the nanomaterial into the predetermined area by electrochemical deposition or infiltration;

[0073] Curing and cleaning: After the embedding process is completed, cleaning and curing are performed to remove excess materials and ensure that the embedded nanowires or particles are stably fixed in the predetermined area. The above curing method can be reasonably selected according to the existing technology, such as annealing or standing.

[0074] It should be noted that the embodiments of the present application are not limited to the above-mentioned implementation of embedding a conductive channel in the buffer zone. In other implementations, nanoimprinting technology, laser induced doping technology, and embedding technology based on etching and deposition may also be used.

[0075] Exemplarily, embedding the conductive channel using nanoimprinting technology includes the following steps:

[0076] Using electron beam lithography or nanoimprint lithography technology, a mold containing nanowire or particle patterns is prepared, and the concave-convex structure on the mold surface corresponds to the target nanostructure one by one;

[0077] A mask layer is arranged on the surface of the buffer region on the side away from the base region, a mold is placed on the mask layer, and appropriate pressure and temperature are applied to transfer the nanostructure on the mold to the mask layer to obtain a patterned mask layer;

[0078] A barrier layer is disposed on the patterned mask layer to expose a predetermined area in the patterned mask layer, and the buffer layer is etched through the exposed patterned mask layer to form grooves corresponding to the target nanostructures in the predetermined area of ​​the buffer zone;

[0079] A solution of the target nanomaterial (such as a solution containing Si NWs) is filled into the grooves and solidified to form nanowires using a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process. The solidification method can be reasonably selected according to existing technologies, such as annealing or standing.

[0080] In another example, embedding the conductive channel using laser induced doping technology includes the following steps:

[0081] Laser pretreatment: Use high-energy laser pulses to treat the predetermined area of ​​the buffer. The laser pulses can be precisely focused on the predetermined area, causing the surface melting of the local material, creating conditions for the subsequent embedding of dopants;

[0082] Dopant embedding: After laser pretreatment, dopants containing nanoparticles or nanowires (such as doped Si NWs) are sprayed or deposited onto the above-mentioned predetermined area immediately. Since the surface material of the predetermined area is in a molten state, the nanomaterial can penetrate into the material to form an embedded structure;

[0083] Annealing: Through a heat treatment process such as annealing or rapid thermal annealing (RTA), the doped area is recrystallized to ensure that the nanowires or particles are firmly embedded and evenly distributed.

[0084] After the conductive channel is embedded in the buffer region, step S203 is performed: a first electrode structure is formed on a side of the second substrate close to the buffer region, and a second electrode structure and a third electrode are formed on a side of the second substrate close to the base region.

[0085] Specifically, taking the integrated gate-commutated thyristor (IGCT) as an example of a power semiconductor device, the first electrode structure includes an anode and an anode emitter, the second electrode structure includes a cathode and a cathode emitter, a portion of the cathode emitter is located in the second doping region, and the third electrode is a gate in contact with the second doping region. The types of materials for the anode, anode emitter, cathode, cathode emitter and gate can be reasonably selected according to the prior art, and are not specifically limited in the embodiments of the present application.

[0086] The power semiconductor device may be an integrated gate-commutated thyristor (IGCT), a gate turn-off thyristor (GTO), an insulated gate bipolar transistor (IGBT), etc., which is not specifically limited in the embodiments of the present application.

[0087] Taking the power semiconductor device in the embodiment of the present application as an integrated gate-commutated thyristor as an example, the base region includes a first doping region and a second doping region sequentially distributed along a first direction, and the first substrate also includes an anode emitter and a cathode emitter. The anode emitter is located on a side of the base region close to the first doping region, a portion of the cathode emitter is located on a side of the base region close to the second doping region, and another portion of the cathode emitter is located in the second doping region.

[0088] At this time, the step of forming a hole in step S202 may include: forming a hole from the side surface of the anode emitter away from the buffer zone to the predetermined area. After the step of forming a conductive channel, the conductive channel extends from the side surface of the anode emitter away from the buffer zone to the inside of the predetermined area.

[0089] After the conductive channel is embedded in the predetermined area of ​​the buffer zone, the above step S203 may include: forming an anode on the side of the anode emitter away from the buffer zone, forming a cathode on the side of the cathode emitter away from the base zone, and forming a gate on the second doped region. The types of the above anode, cathode and gate and their preparation processes can be reasonably selected according to actual needs, and the embodiments of the present application do not specifically limit them.

[0090] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0091] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

1. A power semiconductor device, characterized in that: The invention comprises a central region and a peripheral region located outside the central region, wherein the central region and the peripheral region both comprise a plurality of cellular structures, the central region further comprises a pseudo cellular structure, the cellular structure and the pseudo cellular structure both comprise a buffer region and a base region sequentially arranged along a first direction, the pseudo cellular structure further comprises a conductive channel, and in the pseudo cellular structure: The buffer region has a contact surface with the base region and a first surface opposite to the contact surface along the first direction; At least part of the conductive path is embedded in a predetermined area in the buffer zone, the predetermined area has a second surface located in the first surface, and the predetermined area is spaced from the contact surface, and the part of the conductive path embedded in the predetermined area extends from the second surface to the inside of the predetermined area, and the predetermined area is used to form a breakdown area when the power semiconductor device is subjected to a breakdown voltage.

2. The power semiconductor device according to claim 1, characterized in that: The conductive pathway comprises nanowires.

3. The power semiconductor device according to claim 2, characterized in that: The nanowires are selected from any one or more of carbon nanotubes, silicon nanowires, silicon germanium nanowires, silicon carbide nanowires and metallic nanowires.

4. The power semiconductor device according to any one of claims 1 to 3, characterized in that: The base region includes a first doping region and a second doping region sequentially distributed along the first direction, and the first doping region and the second doping region have different doping types.

5. The power semiconductor device according to claim 4, characterized in that: The buffer region and the first doping region have the same doping type, wherein: The buffer region is a third doping region, or The buffer zone includes a fourth doping region and a fifth doping region distributed along a second direction, the predetermined area is located in the fourth doping region, the doping concentration of the fourth doping region is less than the doping concentration of the fifth doping region, and the second direction is perpendicular to the first direction.

6. The power semiconductor device according to claim 5, characterized in that: The buffer zone includes a surface along the fourth doping zone and the fifth doping zone, a surface of the buffer zone facing away from the base zone is a third surface, an orthographic projection of the fourth doping zone on the third surface is a first projection, an orthographic projection of the fifth doping zone on the third surface is a second projection, and an area of ​​the first projection is smaller than an area of ​​the second projection.

7. The power semiconductor device according to claim 4, characterized in that: The power semiconductor device is an integrated gate-commutated thyristor, and the integrated gate-commutated thyristor further comprises a first electrode structure, a second electrode structure and a third electrode, wherein: The first electrode structure is located at a side of the buffer region away from the base region, and the first electrode structure includes an anode and an anode emitter sequentially distributed along the first direction; The second electrode structure and the third electrode are located on the same side of the base region, the second electrode structure comprises a cathode metal and a cathode emitter sequentially distributed along the first direction, a portion of the cathode emitter is located in the second doping region, and the third electrode is a gate in contact with the second doping region; The conductive channel extends from a surface of the anode emitter facing away from the buffer zone to the inside of the predetermined area; The first doping region and the cathode emitter have a first doping type, and the second doping region and the anode emitter have a second doping type.

8. A method for preparing a power semiconductor device, characterized in that: For preparing a power semiconductor device according to any one of claims 1 to 7, the preparation method comprises the following steps: Providing a first substrate, in which a buffer region and a base region are sequentially distributed along a first direction, the buffer region having a contact surface with the base region and a first surface opposite to the contact surface along the first direction; At least a portion of the conductive channel is embedded in a predetermined area of ​​the buffer zone to obtain a power semiconductor device with a pseudo-cellular structure, wherein the predetermined area has a second surface located in the first surface, and the predetermined area is spaced from the contact surface, and a portion of the conductive channel embedded in the predetermined area extends from the second surface to the inside of the predetermined area, and the power semiconductor device includes a central area and a peripheral area located outside the central area, and the pseudo-cellular structure is provided in the central area.

9. The preparation method according to claim 8, characterized in that: The step of embedding at least part of the conductive path in the predetermined area comprises: forming at least one hole in the predetermined area, wherein the hole extends from the second surface to the inside of the predetermined area; The holes are filled with conductive material and cured to form the conductive paths.

10. The preparation method according to claim 9, characterized in that: The power semiconductor device is an integrated gate-commutated thyristor, the base region includes a first doping region and a second doping region sequentially distributed along the first direction, the first substrate also includes an anode emitter and a cathode emitter, the anode emitter is located on a side of the base region close to the first doping region, a portion of the cathode emitter is located on a side of the base region close to the second doping region, and another portion of the cathode emitter is located in the second doping region, The step of forming the hole comprises: forming the hole penetrating from a surface of the anode emitter away from the buffer zone to the predetermined area; After the step of forming the conductive channel, the conductive channel extends from a surface of the anode emitter facing away from the buffer zone to the inside of the predetermined region.

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