Shield grid process method for improving electric leakage problem of traditional trench MOSFET
By introducing deep trench structure and optimized manufacturing process into traditional trench MOSFETs, the leakage problem is solved, the voltage withstandability and reliability of the device are significantly improved, and more uniform electric field distribution and better heat dissipation efficiency are achieved.
Patent Information
- Application Number
- CN202411881856.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-19
- Publication Date
- 2025-05-02
- Estimated Expiration
- Not applicable · inactive patent
AI Technical Summary
Traditional trench MOSFETs have leakage problems in practical applications, resulting in increased device operating temperature, reduced reliability and increased energy loss.
By adopting the shielded gate process method, by opening a deep trench structure on the substrate, the manufacturing process is optimized to enhance the thickness of the oxide layer at the bottom of the gate, and a deep trench protection layer is formed through thermal oxidation process and CVD film formation, the electric field is evenly distributed and the local electric field strength is reduced.
It significantly reduces the risk of leakage, improves the voltage withstandability and reliability of the device, improves the overall electrical performance and heat dissipation efficiency, and extends the service life of the device.
Smart Images
Figure CN119922934A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the technical field of semiconductor power device manufacturing, in particular to a shielded gate process method for improving the leakage problem of a traditional trench MOSFET. Background Art
[0002] With the continuous advancement of power electronics technology, efficient, reliable and low-loss power devices are becoming increasingly important in various applications. As a common power semiconductor device, trench MOSFET is widely used in power management and motor drive due to its low on-resistance, high switching speed and good thermal stability. Traditional planar trench MOSFET forms a planar structure by lateral layout of the source and drain regions with the gate located above the source and drain regions.
[0003] Traditional MOSFET still faces some problems in practical applications, especially leakage problems. During the manufacturing process, the oxide layer at the bottom of the gate is usually thin, and it is easy to break down due to excessive voltage, resulting in leakage. This leakage not only increases the operating temperature of the device and affects its long-term reliability, but also causes additional energy loss and reduces the overall efficiency of the system. Therefore, how to effectively solve the leakage problem and improve the performance and reliability of trench MOSFET has become a technical problem that needs to be solved urgently. The existing patent literature has given some corresponding solutions, such as the terminal structure of the MOSFET device disclosed in patent number CN111725300A, its preparation method and application, which improves the voltage resistance of the terminal area, reduces leakage, and enhances the reliability of the device. However, the leakage risk of the gate has not been solved. For this reason, this patent proposes a shielded gate process method for improving the leakage problem of traditional trench MOSFET. Summary of the invention
[0004] In order to solve the above problems, the present invention proposes a new process method, which aims to improve the leakage problem of traditional trench MOSFET by introducing a shielded gate structure. Specifically, the present invention effectively increases the thickness of the oxide layer at the bottom of the gate by optimizing the manufacturing process, thereby improving the voltage resistance and reliability of the device. At the same time, the method can significantly reduce the leakage risk without changing the basic structure and electrical performance of the device, and further improve the overall performance of the trench MOSFET.
[0005] In order to achieve the above object, the present invention proposes the following technical solutions:
[0006] A shielded gate process method for improving the leakage problem of traditional trench MOSFET is characterized in that it includes the following steps: using a semiconductor process to open a deep trench structure on a substrate. This step can significantly improve the electric field distribution, on-resistance, thermal performance, parasitic effects and reliability of traditional trench MOSFET. In traditional planar MOSFET, the electric field is mainly concentrated in the oxide layer area under the gate, which easily leads to excessive local electric field strength, thereby causing breakdown. By introducing a deep trench structure, the electric field can be dispersed to the entire trench area, making the electric field distribution more uniform and reducing the problem of excessive local electric field.
[0007] The deep trench protection layer is formed by thermal oxidation process and CVD film formation. First, a thermal oxidation process is used to form an oxide film with a thickness of 60-100nm; then a second layer of silicon dioxide film is formed by CVD method with a film thickness of 300-700nm. The bottom polysilicon film is formed and etched. First, the deep trench described in step 1 is filled with polysilicon, and then the polysilicon is etched into the deep trench by dry etching, and the etching depth is 1 / 3-1 / 2 of the trench depth. The protective layer etching mainly adopts wet etching to etch away the surface and trench sidewall protective layer, and etch the protective layer in the trench until the polysilicon is exposed. The bottom polysilicon etching mainly adopts dry etching to etch away the exposed polysilicon and over-etch to 10-20nm below the protective layer. The gate oxide layer and gate polysilicon are formed by first forming a gate oxide layer with a thickness of 50-200nm through a high temperature thermal process; then polysilicon is formed as gate polysilicon through the process of step 3, and the excess polysilicon on the surface is etched away by dry etching. The doped ion well and source are formed by using semiconductor technology to form semiconductor wells and sources to form PN junctions.
[0008] With respect to claim 2, the present invention can significantly improve the electric field distribution, on-resistance, thermal performance, parasitic effects and reliability of conventional trench MOSFETs by opening a deep trench structure on the substrate. In conventional planar MOSFETs, the electric field is mainly concentrated in the oxide layer region below the gate, which easily leads to excessive local electric field strength, thereby causing breakdown. By introducing a deep trench structure, the electric field can be dispersed to the entire trench region, making the electric field distribution more uniform and reducing the problem of excessive local electric field. Uniform electric field distribution helps to improve the voltage resistance of the device, enabling the device to work stably at higher voltages, thereby expanding its scope of application.
[0009] Furthermore, the source and drain regions of the trench MOSFET are perpendicular to the semiconductor surface, forming a vertical conductive path. This structure can significantly reduce the on-resistance and improve the conductivity of the device. The vertical structure allows more current to pass through the unit area, thereby increasing the current density of the device and making it perform better in high-current applications. Furthermore, the trench structure can provide a better heat dissipation path, making it easier for heat to be conducted from the inside of the device to the outside, thereby reducing the operating temperature of the device and improving its long-term reliability. And it can reduce the parasitic capacitance between the gate and the drain, thereby reducing the gate charge and increasing the switching speed. Reduce parasitic resistance, the vertical structure reduces parasitic resistance and helps reduce conduction losses. Uniform electric field distribution and good heat dissipation performance help extend the service life of the device and improve its durability.
[0010] In view of claim 3, a deep trench protection layer is formed by a thermal oxidation process and CVD film formation. First, a thermal oxidation process is used to form an oxide film with a thickness of 60-100nm; then a second silicon dioxide film is formed by a CVD method with a film thickness of 300-700nm. The oxide film formed by the thermal oxidation process has a thickness of 60-100nm. This step can initially form a dense and uniform oxide layer, which effectively protects the sidewalls and bottom of the trench from the influence of subsequent processes. Subsequently, a silicon dioxide film with a thickness of 300-700nm is formed by a chemical vapor deposition (CVD) method. This step further enhances the thickness of the protective layer, making it stronger and more uniform. The combination of the two oxide layers can provide a more uniform electric field distribution, reduce the problem of excessive local electric field, and thus reduce the risk of breakdown of the oxide layer at the bottom of the gate. Reduce interface trap states and improve the electrical performance of the device. The silicon dioxide film formed by the CVD method can further improve the stability of the interface, reduce the generation of interface states, and improve the reliability of the device.
[0011] Further, with respect to claim 4, the shielded gate process method for improving the leakage problem of traditional trench MOSFET is characterized in that step 3) bottom polysilicon film formation and etching, which first fills the deep trench described in step 1) with polysilicon, and then etches the polysilicon to the inside of the deep trench by dry etching, and the etching depth is 1 / 3-1 / 2 of the trench depth. First, the deep trench is completely filled with polysilicon to ensure that there are no voids or uneven filling inside the trench, providing a good foundation for subsequent processes. Complete filling can ensure the uniform distribution of polysilicon inside the trench and avoid inconsistent performance caused by insufficient local filling. By dry etching, the polysilicon is etched to 1 / 3-1 / 2 of the trench depth, which can optimize the electric field distribution inside the trench and reduce the problem of excessive local electric field. The process parameters of dry etching such as etching gas, pressure, temperature, etc. can be precisely controlled to ensure consistent performance of each batch of devices.
[0012] With respect to claim 5, the step 4) of etching the protective layer mainly adopts wet etching to etch away the protective layer on the surface and the sidewall of the groove and to etch the protective layer in the groove until the polysilicon is exposed. Wet etching can effectively remove the protective layer on the surface and ensure the smooth progress of subsequent processes. By controlling the etching time and the concentration of the solution, it can be ensured that the protective layer in the groove is etched until the polysilicon is exposed without damaging the polysilicon structure. Wet etching is a commonly used process in semiconductor manufacturing, which is compatible with existing manufacturing processes and does not require additional special equipment or complicated process steps.
[0013] Preferably, the wet etching can provide a smooth surface and sidewalls, improve the interface characteristics between the polysilicon and the oxide layer, and reduce interface trap states. The smooth interface helps to improve the electrical performance and reliability of the device.
[0014] Further, with respect to claim 6, by using dry etching to etch away the exposed polysilicon and over-etch to 10-20nm below the protective layer, the removal depth of the polysilicon can be precisely controlled. This method not only optimizes the electric field distribution in the trench and reduces the problem of excessive local electric field, but also improves the insulation performance and reliability of the device. In addition, the high selectivity and process controllability of dry etching ensure the consistency and repeatability of the process, which is compatible with existing processes and suitable for large-scale production.
[0015] With respect to claim 7, the gate oxide layer and gate polysilicon are formed in step 6), and the main process sequence is to first form a gate oxide layer with a thickness of 50-200nm through a high-temperature thermal process, and then form polysilicon as gate polysilicon through the process of step 3), and etch away the excess polysilicon on the surface through dry etching. The gate oxide layer formed by the high-temperature thermal process has a uniform thickness and good quality, and the thickness is controlled within the range of 50-200nm, which can effectively protect the silicon substrate under the gate. High-temperature thermal oxidation can form a uniform and dense oxide layer, reduce interface trap states, and improve the electrical performance of the device.
[0016] Preferably, with respect to claim 8, the shielded gate process method for improving the leakage problem of the traditional trench MOSFET is characterized in that step 7) is formed by doping ion wells and sources, and the method is to form semiconductor wells and sources using semiconductor processes to form PN junctions. The doping concentration is precisely controlled by semiconductor processes to ensure uniform doping of the well region and the source region, thereby improving the electrical performance of the device. Modern semiconductor processes can achieve high-precision doping control to ensure that the doping concentration of each region meets the design requirements. Optimized doping can provide a better heat dissipation path, making it easier for heat to be conducted from the inside of the device to the outside, thereby reducing the operating temperature of the device. Optimized doping can reduce thermal resistance and further improve heat dissipation efficiency.
[0017] The above technical solution can achieve the following beneficial effects:
[0018] Compared with the prior art, the present invention has the following advantages and positive effects:
[0019] (1) The shielded gate process method provided by the present invention is used to improve the leakage problem of traditional trench MOSFET. By optimizing the manufacturing process, the thickness of the oxide layer at the bottom of the gate is effectively increased, and the voltage resistance and reliability of the device are improved. This helps to prevent breakdown when the voltage is too high and significantly reduces the risk of leakage.
[0020] (2) The shielded gate process method provided by the present invention is used to improve the leakage problem of traditional trench MOSFET. The uniform electric field distribution reduces the problem of excessive local electric field and reduces the breakdown risk of the oxide layer at the bottom of the gate. This not only improves the voltage resistance of the device, but also improves the overall electrical performance.
[0021] (3) The optimized doping and structural design of the present invention reduces the on-resistance and improves the conductivity and current density of the device. At the same time, the optimized structure and doping design provide a better heat dissipation path, reduce the operating temperature of the device, and improve the heat dissipation efficiency.
[0022] (4) The shielded gate process method provided by the present invention for improving the leakage problem of traditional trench MOSFET reduces interface defects and trap states, and improves the reliability and long-term stability of the device. All process steps adopt mature semiconductor processes, with controllable parameters, easy to monitor and adjust, ensuring the consistent performance of each batch of devices, and improving production efficiency and economy. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art are briefly introduced below.
[0024] Figure 1 It is a schematic diagram of the shielded gate MOSFET structure model provided by the present invention.
[0025] Figure 2 This is a flowchart of step 1 in a shielded gate process method for improving the leakage problem of a traditional trench MOSFET provided by the present invention.
[0026] Figure 3 This is a flowchart of step 2 in a shielded gate process method for improving leakage problems of conventional trench MOSFETs provided by the present invention.
[0027] Figure 4 This is a flowchart of step 3 in a shielded gate process method for improving leakage problems of conventional trench MOSFETs provided by the present invention.
[0028] Figure 5 This is a flowchart of step 4 in a shielded gate process method for improving leakage problems of conventional trench MOSFETs provided by the present invention.
[0029] Figure 6 This is a flowchart of step 5 in a shielded gate process method for improving leakage problems of conventional trench MOSFETs provided by the present invention.
[0030] Figure 7 This is a flowchart of step 6 in a shielded gate process method for improving leakage problems of conventional trench MOSFETs provided by the present invention.
[0031] Figure 8 This is a flowchart of step 7 in a shielded gate process method for improving leakage problems of conventional trench MOSFETs provided by the present invention.
[0032] Fig. 9 It is a scanning electron microscope image of the shielded gate MOSFET structure provided by the present invention.
[0033] In the figure: (1) silicon substrate, (2) protective layer SiO2, (3) polysilicon film, (4) shielding gate, (5) source, (6) well. DETAILED DESCRIPTION
[0034] The present invention is further explained below with reference to the accompanying drawings and specific embodiments.
[0035] The embodiments of the present invention relate to a shielded gate process method for improving the leakage problem of a conventional trench MOSFET. Figure 1 and Figure 2 As shown, a deep trench structure is opened on the silicon substrate 1 using a semiconductor process. This step can significantly improve the electric field distribution, on-resistance, thermal performance, parasitic effects and reliability of the traditional trench MOSFET. In the traditional planar MOSFET, the electric field is mainly concentrated in the oxide layer area under the gate, which easily leads to excessive local electric field strength, thereby causing breakdown. By introducing a deep trench structure, the electric field can be dispersed to the entire trench area, making the electric field distribution more uniform and reducing the problem of excessive local electric field.
[0036] like Figure 3 As shown, a polysilicon film 3 is first formed on the sidewall and bottom of the trench by a thermal oxidation process, and the oxide film thickness is 60-100nm. Then, a silicon dioxide film is deposited on the formed oxide film by a chemical vapor deposition (CVD) method, and the film thickness is 300-700nm to form a protective layer SiO2. This step further increases the thickness of the protective layer, making it more solid and uniform.
[0037] like Figure 4As shown, the deep trench described in step 1 is first filled with polysilicon 3, and then the polysilicon 3 is etched into the deep trench by dry etching, and the etching depth is 1 / 3-1 / 2 of the trench depth. This ensures uniform distribution of polysilicon inside the trench and avoids inconsistent performance caused by insufficient local filling.
[0038] like Figure 5 As shown, the wet etching is mainly used to etch away the surface and trench sidewall protection layer, and the protection layer SiO22 in the trench is etched until the polysilicon is exposed. This step can provide a smooth surface and sidewall, improve the interface characteristics between the polysilicon and the oxide layer, and reduce interface trap states.
[0039] like Figure 6 As shown, the dry etching is mainly used to etch away the exposed polysilicon and over-etch to 10-20nm below the protective layer. This step can accurately control the removal depth of the polysilicon, optimize the electric field distribution in the trench, and reduce the problem of excessive local electric field.
[0040] like Figure 7 As shown, a gate oxide layer with a thickness of 50-200 nm is first formed on the top of the trench through a high temperature thermal process. Then, polysilicon is formed on the gate oxide layer as the gate 4 through the process of step 3, and the excess polysilicon on the surface is etched away by dry etching. This step ensures the uniformity and quality of the oxide layer of the gate 4 and improves the electrical performance of the device.
[0041] like Figure 8 As shown, a semiconductor well 6 and source 5 are formed on both sides of the trench using a semiconductor process to form a PN junction. This step ensures uniform doping of the well 6 region and the source 5 region by precisely controlling the doping concentration, thereby improving the electrical performance of the device.
[0042] like Fig. 9 As shown, this SEM image shows the shielded gate MOSFET structure actually manufactured in this embodiment, and the details of the trench, shield gate, and gate can be seen. It can be intuitively verified whether the process steps are correctly executed and the quality of the final product. The shape of the trench is regular, without deformation and damage. The depth and width of the trench should meet the design requirements and can be measured by the magnification and ruler of the SEM image. The sidewalls and bottom of the trench should be smooth, without residual impurities and uneven oxide layers.
[0043] The shield gate is filled evenly without voids or incomplete filling. The interface between the shield gate and the surrounding materials is clear, without obvious defects or contamination, and has good contact with the sidewalls and bottom of the trench. The pole and well regions should be located in appropriate positions on both sides of the trench and have good connection with the trench.
[0044] The thickness of the gate should be uniform, without obvious thickness variation. The interface between the gate and the gate oxide layer should be smooth, without obvious defects. The source and well regions should be located in the appropriate positions on both sides of the trench and have good connection with the trench. The doping of the source and well regions should be uniform, without obvious doping unevenness or defects. The interface between the source and well regions and the trench should be clear, without obvious contamination or defects.
[0045] A further embodiment is to uniformly distribute the electric field. By introducing a deep trench structure, the electric field can be dispersed to the entire trench area, making the electric field distribution more uniform and reducing the problem of excessive local electric field. The conductive path is optimized. The source and drain regions of the trench MOSFET are perpendicular to the semiconductor surface, forming a vertical conductive path. This structure can significantly reduce the on-resistance and improve the conductivity of the device. The heat dissipation performance is improved. The trench structure can provide a better heat dissipation path, making it easier for heat to be conducted from the inside of the device to the outside, reducing the operating temperature of the device and improving its long-term reliability. Reduce parasitic effects. Optimized doping can reduce the parasitic capacitance between the gate and the drain, reduce the gate charge, and increase the switching speed. At the same time, reducing parasitic resistance helps to reduce conduction losses.
[0046] The present invention provides a shielded gate process method for improving the leakage problem of traditional trench MOSFET. By optimizing the manufacturing process, the thickness of the oxide layer at the bottom of the gate is effectively increased, and the voltage resistance and reliability of the device are improved. At the same time, the uniform electric field distribution, optimized conductive path and heat dissipation performance significantly improve the overall performance of the device. All process steps use mature semiconductor processes, with controllable parameters, easy to monitor and adjust, ensuring that the performance of each batch of devices is consistent, improving production efficiency and economy.
[0047] The above-mentioned configuration can also be set in other embodiments, and the scope of protection of the present invention includes but is not limited to the situations listed in this embodiment. Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the scope of protection of the present invention shall be subject to the scope defined by the claims.
[0048] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.
Claims
1. The present invention provides a shielded gate process method for improving the leakage problem of a traditional trench MOSFET, which mainly includes the following seven steps: 1) providing a substrate with a deep trench, 2) forming a deep trench protection layer by a thermal oxidation process and CVD film formation, 3) bottom polysilicon film formation and etching, 4) protective layer etching, 5) bottom polysilicon etching, 6) gate oxide layer and gate polysilicon formation, 7) doped ion well and source formation.
2. A shielded gate process method for improving leakage problems of conventional trench MOSFET according to claim 1, characterized in that A substrate with a deep trench is provided. The method comprises the following steps: using a semiconductor process to open a deep trench structure on the substrate.
3. A shielded gate process method for improving leakage problems of conventional trench MOSFET according to claim 1, characterized in that Step 2) A protective layer is formed by thermal oxidation process and CVD film formation, wherein a thermal oxidation process is first used to form an oxide film with a thickness of 60-100nm; and then a second silicon dioxide film is formed by CVD method with a film thickness of 300-700nm.
4. A shielded gate process method for improving leakage problems of conventional trench MOSFET according to claim 1, characterized in that Step 3) bottom polysilicon film formation and etching, which first fills the deep trench in step 1) with polysilicon, and then etches the polysilicon into the deep trench by dry etching, and the etching depth is 1 / 3-1 / 2 of the trench depth.
5. A shielded gate process method for improving leakage problems of conventional trench MOSFET according to claim 1, characterized in that Step 4) etching the protective layer, mainly using wet etching, etching away the protective layer on the surface and the sidewall of the trench and etching the protective layer in the trench until the polysilicon is exposed.
6. A shielded gate process method for improving leakage problems of conventional trench MOSFET according to claim 1, characterized in that Step 5) etching of the bottom polysilicon, mainly using dry etching, etching away the exposed polysilicon and over-etching to 10-20 nm below the protective layer.
7. A shielded gate process method for improving leakage problems of conventional trench MOSFET according to claim 1, characterized in that Step 6) The gate oxide layer and gate polysilicon are formed. The main process sequence is to first form a gate oxide layer with a thickness of 50-200nm through a high-temperature thermal process, and then form polysilicon as gate polysilicon through the process of step 3), and etch away the excess polysilicon on the surface through dry etching.
8. A shielded gate process method for improving leakage problems of conventional trench MOSFET according to claim 1, characterized in that Step 7) forming an ion well and source by using a semiconductor process to form a semiconductor well and source to form a PN junction.