Semiconductor device and method of forming semiconductor device

Abstract

A semiconductor device includes: a first surface contact disposed on a first surface of the semiconductor device; a second surface contact disposed on the first surface and physically separated from the first surface contact; a third surface contact disposed on the first surface between the first surface contact and the second surface contact; a semiconductor device includes a first surface, a third surface contacting the first surface, and a first trench disposed in the first surface and extending from the first surface into the device, and a conductive plug disposed in the trench, where the trench is located in a region of the first surface between an end of the third surface contacting and an edge of the first surface, and wherein the first surface contact and the second surface contact cover the first trench, and the conductive plug in the first trench provides a conductive path between the first and second surface contacts.

Description

Technical Field

[0001] Embodiments described herein generally relate to semiconductor devices and methods of forming semiconductor devices. Background Art

[0002] Semiconductor devices typically include multiple identical cells that need to be contacted. For example, a power MOSFET may include multiple individual MOSFETs or cells, each of which will have its own gate, source, and drain. A gate may be provided in a trench, and a conductive plug may be provided in the trench to contact the gate. The conductive plug is then covered with a surface contact, which may be in the form of a busbar. The conductive plug allows good contact to be formed between the surface contact and the gate. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The present disclosure will now be described with reference to the accompanying drawings, which are provided to aid explanation and understanding. The drawings should not be considered to limit the present disclosure to the specific embodiments described herein:

[0004] Figure 1 is a schematic diagram showing an arrangement of contacts for a device according to an embodiment;

[0005] Figure 2A is a schematic diagram showing a cross section of a single conductive trench that can be used in a semiconductor device according to an embodiment, and Figure 2B is a schematic diagram showing a cross section of a pair of conductive trenches separated by a moat that can be used in a semiconductor device according to an embodiment;

[0006] Figure 3 is a schematic diagram of a contact arrangement with a sealing ring that can be used with a device according to an embodiment;

[0007] Figure 4A and 4B is an example cross section of a split-gate power MOSFET device;

[0008] Figure 5 is an example stereogram of a split-gate power MOSFET device;

[0009] Figures 6(a) to 6(e) yes Figure 5 An exploded view of the device, showing the through Figure 5 Slicing of the device;

[0010] Figure 7 is a view of the top surface of a power MOSFET device;

[0011] Figure 8 is shown similar to reference Figure 7 Photographs of cracks in the passivation layer of the described device;

[0012] Fig. 9 is a view of an upper surface of a MOSFET device according to an embodiment;

[0013] Fig.10 According to another embodiment Figure 1 Variations of contact arrangements;

[0014] Fig.11 According to yet another embodiment Figure 1 Variations of contact arrangements;

[0015] Fig.12 is a cross section along a conductive trace in a device according to an embodiment; and

[0016] Fig.13 is a cross section of a conductive trace through a device according to an embodiment. DETAILED DESCRIPTION

[0017] In a first aspect, a semiconductor device is provided, comprising:

[0018] a first surface contact disposed on a first surface of the semiconductor device;

[0019] a second surface contact, the second surface contact being disposed on the first surface and physically separated from the first surface contact;

[0020] a third surface contact disposed on the first surface between the first surface contact and the second surface contact; and

[0021] a first trench disposed in the first surface and extending from the first surface into the device, and a conductive plug disposed in the trench,

[0022] Wherein the trench is located in a region of the first surface between an end of the third surface contact and an edge of the first surface, and wherein the first surface contact and the second surface contact overlie the first trench, and the conductor in the first trench provides a conductive path between the first and second surface contacts.

[0023] In the above, one or more trenches are arranged towards the edge of the semiconductor device including the conductive plug. This arrangement has many advantages.

[0024] The first groove is used to connect the two surface contacts of the semiconductor device covering the first surface. The connection mechanism allows to provide a physically stable (robust) connection between the two surface contacts. For example, the two surface contacts can be two aspects of the same electrode, or two electrodes connected to the same voltage terminal or two areas of the same electrical terminal. In addition, the connection can be formed simultaneously with other manufacturing steps, and therefore no further manufacturing steps are required to make these connections. This type of connection using a conductive plug also allows the active area of ​​the device to be expanded. In addition, the groove with a conductive plug prevents ion migration towards the active area of ​​the device. The use of recessed contacts also enhances the robustness (robustness) of the device.

[0025] The trench may be formed in other areas of the device, for example as a trench to receive a gate and a polysilicon source electrode. Thus, no further manufacturing steps are required to make the first trench as it can be made simultaneously with the other trenches. Thus, the device may further comprise at least one further trench arranged to connect a gate or source within the device, the first trench and the at least one further trench extending to the same depth in the device, the at least one further trench extending under said third surface contact.

[0026] The first trench and at least one further trench may be provided with the same conductive plug. The conductive plugs in the first trench and possibly at least one further trench are selected from one or more of W, Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, Ni, Pd, Pt, Cu, Ag, Au or Zn.

[0027] In an embodiment, there will be a plurality of transistor cells comprising a plurality of sources, gates and drains, at least one additional trench containing a source or a gate. Here, a first plurality of sources may be connected by a first surface contact, and a second plurality of sources may be connected by a second surface contact. For example, a cell of the plurality of transistor cells may be a split gate transistor cell, each split gate transistor cell comprising a gate, a buried first source and a second source, a first surface contact connecting the buried first source, and a second surface contact connecting a plurality of second sources, which may sometimes be referred to as "moat sourcees".

[0028] The at least one further trench may be a plurality of further trenches, each of the plurality of further trenches comprising a gate and a buried first source, the buried first source being located in the further trench further away from the first surface than the gate, wherein a contact metal is disposed in the further trench to contact the gate, and the third surface contact covers the contact metal connected to the gate in the further trench. The buried first source may be connected to the first surface contact via a conductive plug disposed in the further trench.

[0029] In an embodiment, there is a plurality of first trenches providing electrical connections between the first and second surface contacts.

[0030] In other embodiments, the corners of the first, second and third surface contacts are rounded or tilted at an angle less than 90°. This helps prevent cracking of the passivation layer. The angle may be between 20° and 70°, and may be 45°.

[0031] The same sealing ring as the conductive trench may also be provided. Thus, in further embodiments, the trench need not be connected to anything, but only exists completely or partially around the circumference of the active area to prevent the ingress of contaminants.

[0032] Therefore, in a further embodiment, the device further comprises a perimeter trench extending around the first, second and third surface contacts, the perimeter trench being disposed in the first surface and extending from the first surface into the device, the perimeter trench comprising a conductive plug in the trench that is identical to a conductive plug present in the first trench.

[0033] The sealing ring need not be used in a device having a conductive trench. However, there may be some advantages in providing it in such a device, since both use the same manufacturing steps. Therefore, in a second aspect, there is provided a semiconductor device comprising:

[0034] a sealing ring disposed in a first surface of the device, the sealing ring comprising a first trench disposed in the first surface and extending from the first surface into the device, and a conductive plug disposed in the trench,

[0035] The seal ring extends around an active area in the first surface of the device.

[0036] The sealing ring may extend around the entire perimeter of the active area.

[0037] As described above, the conductive trench can be formed simultaneously with other trenches. Therefore, in a third aspect, a method for forming a semiconductor device is provided, the method comprising:

[0038] providing a semiconductor substrate;

[0039] etching a plurality of trenches in the first surface of the substrate;

[0040] specifying a first subset of the plurality of grooves and a second subset of the plurality of grooves;

[0041] providing a gate electrode in a first subset of said plurality of said trenches;

[0042] disposing conductive plugs in first and second subsets of the plurality of trenches;

[0043] A first, a second and a third surface contact are arranged on the first surface, wherein the third surface contact is arranged to contact the conductive plugs in the grooves in the first subset of the plurality of grooves, the first, the second and the third surface contacts are physically separated from each other on the first surface, and the first and the second surface contacts are arranged to cover the conductive plugs in the second subset of the plurality of grooves, so that the first and the second surface contacts are electrically connected via the conductive plugs in the second subset of the plurality of grooves.

[0044] Figure 1 1 is a schematic diagram of the surface contact of the semiconductor device 100 shown in a stereogram. The semiconductor device can be any type of semiconductor device and any type of material. In this specific example, the device will be referred to as a silicon device formed on a silicon substrate. However, this is purely for illustration.

[0045] In the simplified diagram, there is a first surface contact 101 , a second surface contact 102 , and a third surface contact 103 .

[0046] Three surface contacts 101, 102 and 103 are located on the surface of the semiconductor device. They can be any suitable surface contact metallization, such as Au, AuCu, Ag, Pd, Ni, NiCr, etc. The first surface contact 101 and the second surface contact 102 are elongated contacts arranged on opposite sides of the third surface contact 103. The third surface contact 103 is also an elongated contact. The first, second and third surface contacts are arranged parallel to each other and extend towards the edge of the device in their elongated direction. The first, second and third surface contacts are physically separated from each other so that they do not contact each other.

[0047] In this example, it is desired to electrically connect the first surface contact 101 and the second surface contact 102. However, they are arranged in such a way that the third surface contact 103 is provided.

[0048] The first surface contact 101, the second surface contact 102 and the third surface contact 103 are each elongated in the first direction and are arranged in the order of the first surface contact, the third surface contact and then the second surface contact in a direction perpendicular to the first direction.

[0049] The edge of the semiconductor device is not shown in this figure. However, the first direction extends towards the edge of the semiconductor device. The first contact 101 and the second contact 102 extend so that they end closer to the edge of the device than the end of the third surface contact 103. In other words, the edge of the third surface contact 103 is set back slightly from the edge of the device compared to the first surface contact 101 and the second surface contact 102.

[0050] It is desirable to connect the first and second surface contacts, and to achieve this, a plurality of trench contacts 104 are provided between the first surface contact 101 and the second surface contact 102. The trench contacts are a plurality of trenches in the device surface, and they are provided with conductive plugs. The first surface contact 101 and the second surface contact 102 at least partially cover the conductive trenches, and are therefore electrically connected through the conductive trenches.

[0051] exist Figure 1 In , there are multiple conductive trenches 104. However, there may be a single trench. Figure 1 , the conductive trenches are shown as straight trenches arranged perpendicular to the first direction. However, the conductive trenches 104 need not be straight and may be curved, zigzag, or any other shape as long as they allow current to flow between the first surface contact 101 and the second surface contact 102.

[0052] In addition, Figure 1 In the embodiment, a plurality of conductive grooves 104 are shown to be parallel to each other and equally spaced from each other. In addition, although the conductive grooves 104 can be arranged at regular intervals, they can also be arranged at different intervals. In addition, the conductive grooves can each have the same cross-sectional profile, or they can have different cross-sectional profiles.

[0053] The conductive plug in the conductive trench allows the first surface contact 101 and the second surface contact 102 to be electrically connected. Figure 2A A schematic diagram of a cross section of a trench is shown. A trench 113 is formed in the surface 111 of the semiconductor and extends through the surface. The bottom of the trench is filled with a material such as polysilicon 115. A moat for a conductive plug 117 is provided at the top of the trench 113 covering the polysilicon 115. Region 115 (polysilicon) is insulated on the left, right and bottom. Its upper portion needs to be electrically connected to 117 so that the interface is not insulated. These trenches used as conductive trenches are the same as the trenches used as building blocks of the device.

[0054] Figure 2B Shown is a reference Figure 2A In order to avoid any unnecessary repetition, the same reference numerals will be used to denote the same features. A p+ body 119 with a moat contact 121 is disposed between the pair of trenches 113 .

[0055] Back to Figure 1 , the first surface contact 101 and the second surface contact 102 at least partially cover the trench 104. The conductive plug of the conductive trench directly contacts the surface contacts 101 and 102. In an embodiment, the conductive plug is tungsten (W), or any one of Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, Ni, Pd, Pt, Cu, Ag, Au or Zn.

[0056] The third surface contact 103 does not contact the conductive trench 104. Instead, the conductive material is removed around the third surface contact 103 to avoid the contact 103 being electrically connected to the conductive trench 104.

[0057] As will be described later, you can use Figure 1 Other trenches identical to the conductive trench 104 are formed during the fabrication of the device for contacting the first surface 101 and the second surface 102. Therefore, no additional fabrication steps are required to form the conductive trench 104. The conductive trench 104 is used to allow electrical contact between the first surface contact 101 and the second surface contact 102. However, the conductive trench 104 is also used to prevent the ingress of contaminants toward the active area of ​​the device and provides advantages in terms of the mechanical robustness of the device and helps to allow more device area to be utilized.

[0058] Figure 3 Shows Figure 1 A variation of the arrangement of in which a sealing ring 105 is provided around the circumference of the device. This sealing ring 105 is not used to provide electrical contact. However, it allows a barrier to be provided around the entire device to prevent contaminants from entering. The sealing ring 105 has the same cross-section and composition as described for the conductive trench of FIG. 2 .

[0059] Next, the use of reference Figures 1 to 3 Specific examples of devices with contact arrangements are described.

[0060] Figure 4A and 4B Schematic diagram showing a cross section of a silicon split-gate power MOSFET device based on reduced surface field (RESURF). However, the device may alternatively be based on other semiconductor material systems, such as GaN, SiC, GaAs and / or have other types or architectures, such as IGBT.

[0061] MOSFET 210 allows current to flow from source contact 201 to drain contact 280, and the flow of current is controlled by gate 250. Figure 4A In the depicted example, two gates 250 are disposed in parallel trenches 235. In addition, two types of sources are provided. A moat source 285 is disposed in the top surface between the trenches 235, and a polysilicon source 255 is disposed in each trench 235 below the gate 250. The term "below" will be taken to mean that a feature "below" another feature is further away from the top surface of the device than the other feature.

[0062] In other embodiments, the gate may be arranged in a side gate configuration 251, which is arranged towards the top of the trench on either side of the polysilicon source, such as Figure 4BIn this arrangement, the polysilicon source extends toward the surface of the device between the two side gates 251 in each trench 235. The side gates 251 are then connected to the edge terminals. Figures 6(a) to 6(e) describe Figure 4A The edge terminal of the device.

[0063] The device 210 includes a Si body region having an upper surface 200 and a lower surface. Two parallel trenches 235 are provided extending from the upper surface 200 into the Si body region. The trenches 235 are laterally spaced apart from each other and lined with an insulating material 240 provided on the sidewalls of the trenches 235. Each trench 235 has a split gate structure, wherein the upper portion of the trench 235 includes a gate electrode 250 and the lower portion of the trench 235 includes a polysilicon source electrode 255. The gate electrode 250 and the polysilicon source electrode 255 are separated by an insulating material 240 provided between the electrodes.

[0064] The polysilicon source electrode 255 is also referred to as a trench shield. The gate electrode 250 is wider than the source polysilicon electrode 255. Therefore, the thickness of the insulating material 240 disposed on the sidewalls around the source polysilicon electrode 255 in the lower portion of the trench 235 is greater than the thickness of the insulating material 240 disposed on the sidewalls around the gate electrode 250 in the upper portion of the trench 235. Therefore, the source polysilicon electrode 255 acts as a field plate at the source potential.

[0065] A moat source is provided between the two trenches 235, and the moat source includes a groove (or moat) provided in the upper surface 200 of the Si body. The moat is filled with a contact material. The contact material includes a barrier metal layer (usually Ti+TiN) and a metal plug. Specifically, the moat 285 is lined with a barrier metal layer, and the metal plug is provided on the barrier metal layer. Two n+ regions 270 are provided on either side of the moat 285. The moat extends into the p+ body region 260 formed below the moat 285.

[0066] Furthermore, a drain contact 280 is provided on the lower surface 290 of the device. The potential difference established between the source contact and the drain contact causes current to flow between the source and the drain via the drift region 230. The flow of current is controlled by the gate 250.

[0067] A challenge with devices of the type described with reference to Figure 4 is how to make electrical connections to the various electrodes. Furthermore, in practice, there will be many devices of the type described with reference to Figure 4 disposed on a single chip, and these devices will need to be connected in parallel and in a manner that will allow connections to be made to the devices in an efficient and robust manner.

[0068] Figure 5 There is shown a perspective view of the structure described with reference to Figure 4. In order to avoid any unnecessary repetition, the same reference numerals will be used to denote the same features. Figures 6(a) to 6(e) Shows Figure 5 is a perspective view and is an exploded view to more easily illustrate the contacts.

[0069] The trench containing the gate is shown extending across the surface of the structure, and the moat contact is also shown extending across the surface of the structure.

[0070] As shown in the exploded view of FIG6(a) and Figure 5 As can be seen in FIG. 2 , in region 201 , an insulating layer covering gate 250 is provided, and thus it is possible to contact moat 285 without contacting gate 250 . Figure 5 In section 203 of , which corresponds to FIG6( b ), a contact is made to the gate electrode. This can be seen more clearly in FIG6( b ), where the gate metallization is brought to the surface.

[0071] Next, in Figure 5 6, it can be seen that the contact to the buried source or polysilicon source contact is brought to the surface to make a connection in section 202. Returning to the exploded view of FIG6, the source polysilicon contact is shown in FIG6(d). To prevent shorting from the gate to the source polysilicon, a separation section is provided between the gate contact and the source polysilicon contact as shown in FIG6(c). Finally, the terminal section 220 at the edge of the device is shown in FIG6(e).

[0072] from Figure 5 As can be seen from Figure 6, the source polysilicon contacts are brought to the surface to allow connections to them towards the edge of the device. However, the gate contact must be brought to the surface before the polysilicon source (which is deeper in the device than the gate electrode). This means that the contact to the source polysilicon is separated from the moat source contact via the gate contact.

[0073] return Figure 5 , in an embodiment, there will be many devices arranged adjacent to each other, e.g. Figure 5 Each device is generally referred to as a cell. The gate contacts of all cells will be connected together using a gate bus bar that will extend across region 203 of all devices. Similarly, the source polysilicon contact and the moat contact will also extend through the cell.

[0074] As described above, the device contacts may be provided as metal busbars on the surface 210. In particular, the surface 200 may have a moat source busbar, a gate busbar, and a source polysilicon busbar. The source polysilicon busbar may additionally be used for an additional moat source contact 201 provided near the source polysilicon contact 202. A passivation region (not shown) may be provided on the metal busbars.

[0075] Figure 7 Shown includes reference Figure 5 and 6(a) A corner of a device having multiple transistors of the type described in 6(e) to 6(e). Two enlarged portions are shown to show details of the moat contact and the gate contact.

[0076] exist Figure 7 There is an extension through Figure 7 These vertical lines represent the trench 301 containing the gate electrode, which is located at the right hand corner of Figure 7 The trench 301 for the gate is similar to that already described with reference to Figure 5 and 6(a) The same grooves as described in 6(e).

[0077] In region 303, multiple gate contacts are provided to the gates in the trenches. The gate contacts are made using conductive plugs of the type discussed with reference to FIG2, for example, tungsten plugs, which are connected to the top of the gates. Gate contacts 305 are provided at the top of trench 301, which contains the gates covering and contacting the gates.

[0078] A source moat 307 is provided between the trenches containing the gate, shown in more detail in the enlarged portion. The contact to the moat source is found in region 309. The moat source contact is shown as 311 in the enlarged portion.

[0079] A second set of trench contacts is shown in region 315. In addition, contacts to the source polysilicon are shown in region 313. As can be seen, contacts to the source polysilicon are shown at the edge of the device. This is due to the reference Figure 5 and 6(a) 6(e) to describe the structure, which shows that the source polysilicon contact needs to be brought to the surface towards the edge of the device so that it is separated from the moat source contact by the gate contact.

[0080] and Figure 5 In contrast, the moat contact shown in region 309 corresponds to Figure 5 The trench contact area 201, Figure 7 The gate contact region 303 corresponds to Figure 5 The gate contact region 203, and Figure 7 The source polysilicon contact region 313 corresponds to Figure 5 The source polysilicon contact region 202. It should be noted that, in order to aid the clarity of the figure, Figure 5 The second moat contact region 315 is not shown in FIG. However, it should be understood that a second set of moat contacts may be provided to contact the Figure 5 A trench source is formed between the gate contact region 203 and the source polysilicon contact region 202 .

[0081] In reference Figures 5 to 7In the device described, it is necessary to connect all source contacts, i.e. both source polysilicon contacts and source trench contacts, together. This is accomplished via surface contact metallization in the form of source region metallization 319, which extends across the surface of the device perpendicular to the direction of trench 301. The gate contacts 305 in region 303 are also connected together by elongated gate busbars 321 covering each of the gate contacts. As described above, the gate metallization busbars 321 are in contact with the gate via conductive plugs. The surface metallization layer can be formed of AlCu metal.

[0082] The gate contact should not be connected to the source contact. Therefore, it is necessary to isolate the gate contact busbar 321 from the source contact source region metallization 319. Figure 7 In FIG. 3 , this is accomplished by providing a gap 317 between the metallization 319 of the source contact and the contact metallization of the gate contact busbar 321 .

[0083] Gap 317 is shown as a U-shaped layout, which has two major disadvantages.

[0084] (i) It produces Figure 7 The electrically inactive region shown on the left has no active trench.

[0085] (ii) It provides a mechanical connection between the two source regions through a narrow neck that is subject to a large amount of stress. Figure 8 This is explained.

[0086] Figure 8 Shown is a reference Figures 5 to 7 Describes the type of device. Figure 7 Only the corners of the device are shown, and Figure 8 The entire device 400 is shown with two gate busbars 401, 403 and a U-shaped gap is formed in the metallization around the two gate busbars 401, 403. A passivation layer is provided on the metallization.

[0087] Figure 8 Figure 4 shows cracks in the passivation layer caused by thermomechanical stress, which can be transferred from one area to another, thereby reducing the lifetime of the device. The passivation layer 402 can be formed of Si3N4 or SiO2. When a U-shaped layout is used, when the device undergoes thermomechanical cycling (TMCL), cracks will eventually appear in the passivation layer due to yielding and ratcheting effects that occur in the surface metallization. This phenomenon is Figure 8Thermomechanical stress caused by TMCL will be borne by all materials constituting the bulk of the device, i.e. by the Si3N4 / SiO2 passivation, the AlCu powdered metal and the bulk of the MOSFET crystal. This leads to overall degradation of the semiconductor device, resulting in reduced performance and eventual failure of the device.

[0088] Fig. 9 is a plan view of a top surface 500 of a semiconductor device according to an embodiment. Fig. 9 The metallization shown in Figure 7 However, the active areas of the underlying devices are identical and therefore, like reference numerals are used to denote like features.

[0089] Fig. 9 The surface metallization of the gate electrode leads to three different surface contact areas: gate busbar 505, trench source region metallization 501 and polysilicon source region metallization 502. The polysilicon source region metallization 502 is connected to the polysilicon source electrode under the gate in the trench. Figure 7 As explained, the second set of moat source contacts 315 are also disposed on the same side of the gate busbar 505 , which allows a single source region metallization to cover both the moat contacts 315 and the source polysilicon contacts 313 .

[0090] The gate bus 505, the moat source region metallization 501 and the polysilicon source region metallization 502 are each elongated regions and are arranged parallel to each other. The moat source region metallization 501 and the polysilicon source region metallization 502 extend closer to the edge 507 than the gate bus 505. In other words, the gate bus 505 is slightly retreated from the edge 507 compared to the moat source region metallization 501 and the polysilicon source region metallization 502.

[0091] As reference Figure 7 As explained, it is necessary to electrically connect to the moat source region metallization 501 and the polysilicon source region metallization 502. Figure 7 In the embodiment, this is achieved by a surface metallization layer covering the edge region of the gate source busbar 505. However, in Fig. 9 In the example of FIG. 5 , the moat source region metallization 501 and the polysilicon source region metallization 502 are connected using a trench with a conductive plug 509 .

[0092] The groove is a reference Figure 1and 2. Here, the conductive plug is set in the top of the trench. Below the conductive plug is polysilicon, which in this case is only used to prevent contaminants from entering the trench and support the conductive plug. The conductive plug itself provides the transmission of current and voltage between the moat source region metallization 501 and the polysilicon source region metallization 502. There can be multiple conductive trenches 509 between the moat source region metallization 501 and the polysilicon source region metallization.

[0093] It will be noted that the moat source region metallization 501 and the polysilicon source region metallization 502 are also electrically connected via some of the polysilicon source extending under the gate bus 505. This is because both the moat source bus 501 and the polysilicon source bus 502 cover the moat contact. However, the source polysilicon in the trench has a relatively high resistance and therefore, the source polysilicon does not form an electrically effective conductive path to couple regions 501 and 502.

[0094] In addition to using conductive trenches 509 to connect moat source region metallization 501 and polysilicon source region metallization 502, a seal ring 511 is provided around the outside of the device that has the same configuration as the conductive trenches and is used to prevent contaminants from entering the active area of ​​the device.

[0095] The conductive traces 509 may have the same depth from the upper surface into the semiconductor device.

[0096] Fig.10 Show Figure 1 To avoid any unnecessary repetition, the same reference numerals will be used to denote the same Figure 1 The first surface contact 101 corresponds to Fig. 9 The trench contacts the busbar, and the second surface contact 102 corresponds to Fig. 9 The polysilicon busbars, and the third surface contact corresponds to Fig. 9 The gate busbar.

[0097] exist Fig.10 The corners where the first, second and third surfaces meet are modified in FIG. Instead of 90° corners, the corners are "cut off" so that they are flattened to 45° with the plane. This configuration is more robust against cracking. In another variation, as Fig.11 As shown, the corners are rounded to provide a larger bend radius on the 90° corner.

[0098] exist Fig.10 In the figure, a 45° corner is shown. However, it will be appreciated that other angles, such as 20° to 70°, may be used. Alternatively, it may be desirable to make the corner less sharp than a 90° corner.

[0099] Fig.12 It is shown Fig. 9 Schematic diagram of a cross section of one of the conductive trenches. Fig.12 In FIG. 5 , a cross section is taken along the length of the conductive trench 509. The conductive trench 701 extends down to the line 702. The conductive trench 701 is filled with polysilicon 703. On top of the polysilicon, a conductive plug 705 is provided. Fig.12 In FIG, since the cross section is taken along the length of the trench, polysilicon exists throughout the cross section.

[0100] A first surface contact 707 covers the conductive trench at one end, and a second surface contact 709 covers the conductive trench at a second opposite end. Thus, the conductive trench electrically connects the first and second surface contacts.

[0101] Fig.13 Shown by Fig. 9 A cross section of a device taken from Fig. 9 The edge 507 of the device extends through the gate contact ( Fig. 9 The cross section shows a plurality of grooves 751. These grooves are all formed to the same depth. Fig.13 The trenches shown in FIG. 7 are used for different purposes. Each trench 751 is filled with polysilicon 753, and an insulator may be provided around the polysilicon. For the trenches that will form the conductive trenches connecting the first surface contact and the second surface contact, a conductive plug 757 is provided above the polysilicon 753. Fig.12 Shown in cross section is one of these conductive trenches.

[0102] The trench 759 forms a seal ring. This trench is formed towards the edge of the device. This is the outermost trench 759 and is also formed in the same manner as the conductive trench, with a polysilicon fill and a conductive plug 761 arranged to cover the polysilicon fill. In addition, the conductive plug is used to prevent the ingress of contaminants. In addition, the conductive trench also provides some defense against the ingress of contaminants, which is another advantage of providing a conductive trench.

[0103] The gate contact 750 is shown covering the gate structure. Here, a trench for contacting the gate is formed, the depth of which is also the same as the trench 751 used to form the conductive trench. Therefore, the trench for the gate and the conductive trench can be etched in the same manufacturing step. Polysilicon 765 is arranged in the trench. This will then form a polysilicon source surrounded by insulating material. A gate metal 767 is arranged above the insulating material. Above the gate metal, in the area where the gate 767 needs to be contacted, a conductive plug 769 is also arranged. It can be seen that these conductive plugs 769 then directly contact the gate metal 750.

[0104] In an embodiment, for ease of manufacturing, other trenches are also formed and these trenches are filled with polysilicon only and are shown as trench 763. These trenches are filled with polysilicon to prevent contaminants from entering the trenches.

[0105] The trenches may be etched to a depth range of 1 to 20 microns. Examples of possible etching chemistries are: SF6+O2; C4F8; HBr+He or Cl2.

[0106] It can be seen that the above system provides simplified manufacturing. All trenches can be etched together in the same step. In addition, polysilicon can be provided to all trenches in the same step. Further manufacturing steps are then performed on the trench that will contain the gate to allow the gate metal to be provided above the polysilicon. Then, in the trench to which the conductive plug is provided, the conductive plug can be provided to all trenches that require a conductive plug using the same manufacturing step.

[0107] The conductive plug may be formed of tungsten (W). In other examples, the plug may be formed of any one or a combination of Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, Ni, Pd, Pt, Cu, Ag, Au, or Zn.

[0108] The material of the plug is robust to etching techniques, such as dry and wet etching techniques using etchants such as AlCu etching acid (H3PO4 / HNO3, 50°C), and a conductive path can still be provided after the conductive plug has been exposed to subsequent processing steps. It has been found that tungsten plugs are particularly robust to further processing.

[0109] The use of a conductive trench to provide an electrical connection between the two source regions avoids the need for a surface connection such as AlCu power metal to connect the source contacts, providing a robust electrical connection without topography.

[0110] By using this method of connecting two source regions, the active area of ​​the chip can be extended. For example, Figure 7 The width of the metallization connecting the two source contacts in the example may be 60 μm, which results in an inactive area of ​​60 μm. However, using a method in which the source contacts are connected via a conductive trench Fig. 9 With the arrangement of the conductive trench, a much smaller area is required, for example 10 μm, which allows the width of the inactive area to be reduced by 50 μm and converted to an active area. In addition, by making the U-shape redundant, a physical separation of the two source regions is achieved, which is beneficial for mechanical robustness as described below.

[0111] In addition, a tungsten-filled moat contact is incorporated in the device's seal ring, rather than using AlCu. The exclusion of AlCu allows the seal ring to be ultra-compact without sacrificing its primary function of ion stopping.

[0112] Using the W-plug connector and decoupled source layout, approximately 50um of active area can be recovered on the left side of the chip, allowing this area to be converted to active area, achieving the active area increases listed in Table 1 for the largest dies in popular power packages.

[0113] Package Pin % Gain 12x 12mm 0.6％ 8x 8mm 0.8％ 5x 6mm 1.4％ 3x 3mm 4.0％

[0114] Table 1 Gain in the active area when adding 50um active area strips

[0115] The decoupling of the two source metals allows redesigning the source metal corners to set larger bending radius or 45° layout in extreme corners, which is more robust against cracking of the passivation layer.

[0116] The addition of an ultra-compact seal ring made entirely of W plugs maximizes the use of silicon die area while setting a robust ion entry barrier. Using a moat contact in the source trench around the entire perimeter of the device is superior to using only the source trench itself because the moat contact cuts off the main ion migration path, which is through the interlayer dielectric.

[0117] In the above arrangement, the conductive plug is completely retracted into the trench and its effective surface thickness t m Very low, effectively close to zero thickness. This enhances the thermomechanical figure of merit (FOM) S of the source contact made using a conductive plug that complies with equations (1) and (2):

[0118]

[0119] Based on stress theory, the parameter S in equation (1) is an indicator of the thermomechanical stability that is critical for controlling the initiation of crack formation during thermal cycling of the device. As long as S < 2, yielding and ratcheting of AlCu will not occur during TMCL, and the thermomechanical stress caused by TMCL will be borne by all materials constituting the bulk of the device, i.e., by the passivation layer, AlCu powder metal, and the bulk of the MOSFET crystal. It is therefore desirable to make the quantity σ M big.

[0120] The FOM quantity S can be optimized by careful engineering methods, such as the yield strength σ of the metal layer. M Yield strength σ M The enhancement can be obtained by:

[0121] (i) Reduce the material thickness t m , as shown in equation (2)

[0122] (ii) Appropriate selection of materials with higher inherent yield strength

[0123]

[0124] This embodiment proposes a method of obtaining an improved yield strength σ of the source-source connection by using the above two techniques. M method.

[0125] The use of an extremely thin tungsten layer as a source-source connector brings an improvement in the yield strength of the connection, especially when deployed in areas prone to high thermomechanical stresses during TMCL. Using tungsten instead of AlCu increases the Young's modulus of the connection by about 6 times. Therefore, the above-described embodiments bring a significant improvement in the yield strength of the connection material using a feasible method that is compatible with existing manufacturing technology.

[0126] The examples above mainly involve silicon split-gate MOSFETs. However, the above principles can be applied to any device that requires an electrical connection between two surface contacts.

[0127] Furthermore, the seal ring described above can be used in any semiconductor device. It can be used in combination with a conductive trench, or it can be used completely alone in a device that does not use the conductive trench described above.

[0128] Although the present disclosure has been described according to the preferred embodiments described above, it should be understood that these embodiments are illustrative only and the claims are not limited to those embodiments. In view of this disclosure, those skilled in the art will be able to make modifications and substitutions, which are considered to fall within the scope of the appended claims. Each feature disclosed or shown in this specification may be incorporated into the present disclosure, either alone or in any appropriate combination with any other features disclosed or shown herein.

[0129] Many other effective alternatives will occur to those skilled in the art.It should be understood that the present disclosure is not limited to the embodiments described, but covers all modifications coming within the scope of the appended claims.

Claims

1. A semiconductor device, comprising: a first surface contact disposed on a first surface of the semiconductor device; a second surface contact, the second surface contact being disposed on the first surface and physically separated from the first surface contact; a third surface contact disposed on the first surface between the first surface contact and the second surface contact; as well as a first trench disposed in the first surface and extending from the first surface into the device, and a conductive plug disposed in the trench, wherein the groove is located in a region of the first surface between an end of the third surface contact and an edge of the first surface, and wherein the first surface contact and the second surface contact cover the first groove, and wherein the conductive plug in the first groove sets a conductive path between the first and second surface contacts.

2. The semiconductor device according to claim 1, The device further comprises at least one further trench containing a gate or a source within the device, the first trench and the at least one further trench extending to the same depth into the device, the at least one further trench extending under the third surface contact. 3 . The semiconductor device according to claim 2 , wherein the first trench and the at least one further trench are provided with the same conductive plug.

4. A semiconductor device according to any preceding claim, wherein the semiconductor device is a plurality of transistor cells comprising a plurality of sources, gates and drains, the at least one further trench providing an electrical connection to a source or a gate. 5 . The semiconductor device of claim 4 , wherein a first plurality of sources are connected via the first surface contacts, and a second plurality of sources are connected via the second surface contacts.

6. The semiconductor of claim 5 , wherein the cells in the plurality of transistor cells are split gate transistor cells, each split gate transistor cell comprising a gate, a buried first source and a second source, the first surface contact connecting the buried first source, and the second surface contact connecting the plurality of second sources.

7. A semiconductor device according to claim 6, wherein the at least one additional trench is a plurality of additional trenches, each additional trench in the plurality of additional trenches comprises a gate and a buried first source, the buried first source is located in the additional trench further away from the first surface than the gate, wherein a contact metal is arranged in the additional trench to contact the gate, and the third surface contact covers the contact metal connected to the gate in the additional trench. 8 . The semiconductor device of claim 7 , wherein the buried first source is connected to the first surface contact via a conductive plug provided in the plurality of further trenches.

9. A semiconductor device according to any preceding claim, wherein the conductive plugs in the first trench and the at least one further trench are selected from one or more of W, Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, Ni, Pd, Pt, Cu, Ag, Au or Zn.

10. A semiconductor device as claimed in any preceding claim, wherein a first plurality of trenches provides electrical connections between the first and the second surface contacts.

11. A semiconductor device according to any preceding claim, further comprising a perimeter trench extending around the first, second and third surface contacts, the perimeter trench being arranged in the first surface and extending from the first surface into the device, the perimeter trench comprising a conductive plug in the trench that is identical to a conductive plug present in the first trench.

12. A semiconductor device according to any preceding claim, wherein corners of the first, the second and the third surface contacts are rounded or beveled at an angle less than 90°.

13. A semiconductor device comprising: a sealing ring disposed in a first surface of the device, the sealing ring comprising a first trench disposed in the first surface and extending from the first surface into the device, and a conductive plug disposed in the trench, The seal ring extends around an active area in the first surface of the device.

14. A semiconductor device, wherein the seal ring extends around the entire perimeter of the active area.

15. A method of forming a semiconductor device, the method comprising: providing a semiconductor substrate; etching a plurality of trenches in the first surface of the substrate; specifying a first subset of the plurality of grooves and a second subset of the plurality of grooves; providing a gate electrode in said first subset of said plurality of said trenches; disposing conductive plugs in said first and said second subsets of said plurality of trenches; A first, a second and a third surface contact are arranged on the first surface, wherein the third surface contact is arranged to contact a conductive plug in a groove in the first subset of the plurality of grooves, the first, the second and the third surface contacts are physically separated from each other on the first surface, and the first and the second surface contacts are arranged to cover the conductive plug in the second subset of the plurality of grooves, so that the first and the second surface contacts are electrically connected via the conductive plug in the second subset of the plurality of grooves.

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