Method of fabricating vertical field effect transistor structure and vertical field effect crystal structure

Abstract

Vertical field effect crystal structures and methods of making the same are disclosed. The semiconductor device is provided with: a semiconductor body having first and second connection regions of a first conductivity type; the first conduction type channel region or the second conduction type channel region complementary to the first conduction type channel region is arranged between the first connection region and the second connection region; a plurality of trenches extending to the body through the channel region from the second connection region to the first connection region and forming channel region and second connection region fins; a control electrode disposed in the trench adjacent to the channel region and insulated from the body; and a breakdown current path in the first and second connection regions and connected in parallel with the channel region, which has at least one pn junction and is configured to conduct when a threshold voltage acting on the first and second connection regions is reached. The body has a second conductivity type doped region in the first connection region under the first trench in the trenches and does not have the second conductivity type doped region in the first connection region under the second trench in the trenches. The fin has a second conductivity type body connection region extending to the drift region in electrical contact with the channel region and the second connection region.

Description

Technical Field

[0001] The invention relates to a method for manufacturing a vertical field effect transistor structure and a corresponding vertical field effect crystal structure. Background Art

[0002] Typically, a power MOSFET (TMOSFET) having a vertical channel region is used for applications of semiconductors having a wide bandgap, such as silicon carbide (SiC) or gallium nitride (GaN), in power electronic devices.

[0003] In the design of TMOSFET, the n+ type source region and the p type channel region in the semiconductor material are interrupted by a trench, which extends to the n type drift region. The gate electrode is located inside the trench, which is separated from the semiconductor material by a gate oxide and is used to control the channel region.

[0004] The on-resistance, threshold voltage, short-circuit resistance, oxide loading and breakdown voltage of this type of TMOSFET can be optimized by appropriate selection of geometry, epitaxial doping, channel doping and shielding doping.

[0005] Figure 3 A schematic perspective view of a vertical field effect transistor structure according to the prior art DE 102 24 201 B4 is shown as a starting point for the present invention.

[0006] exist Figure 3 The semiconductor structure element shown in embodies an n-conductive vertical trench MOSFET with a shielding structure arranged on the trench. Of course, the known structure can also be applied to a p-conductive MOSFET, wherein the doping explained below may then be exchanged.

[0007] The semiconductor structure element comprises a semiconductor body 100 with n-doped first connection regions 12, 14. The first connection regions 12, 14 are more strongly n-doped in the region of the back side of the semiconductor body 100 and form there the n+ drain region 12 of the MOSFET, while the weaker n-doped n-type drift region 14 adjoins the n+ drain region 12. In addition, the semiconductor body 100 comprises a p-type channel region or body region 20, which adjoins the n-type drift region 14 and is formed between the n-type drift region 14 and a strongly n-doped second n+ connection region 30 formed in the region of the front side. The second n+ connection region 30 forms the source region of the MOSFET.

[0008] A plurality of grooves 60 (in which a plurality of grooves are Figure 3Two are shown in FIG. 1 ) extending starting from the front side 101 of the semiconductor body 100 through the n + -type source region 30 , the p-type body region 20 and into the n-type drift zone 14 of the semiconductor body 100 .

[0009] Control electrodes 40 are arranged in the region of the side walls of the trenches 60, respectively, and the control electrodes are connected together to form the gate electrodes of the MOSFET. These gate electrodes 40 are insulated from the semiconductor body 100 by a gate insulating layer 50 and extend in a vertical direction of the semiconductor body from the n+ type source region 30 along the p-type body region 20 to the n-type drift region 14, so that when a suitable control potential is applied, a conductive channel is formed in the body region 20 along the side walls of the trench between the n+ type source region 30 and the n-type drift region 14.

[0010] The semiconductor structure element comprises a large number of transistor structures of the same type, so-called cells with corresponding n+ source regions 30, p-body regions 20 and gate electrodes 40, wherein, in the example, the n-type drift region 14 and the n+ drain region 12 are common to all cells. In this case, the n+ source regions 30 of all cells are electrically conductively connected to one another to form a common source region, and the gate electrodes 40 of all cells are electrically conductively connected to one another to form a common gate electrode.

[0011] exist Figure 3 The semiconductor structure element shown in comprises a shielding structure with an electrode 80, which is formed in the respective trench 60 and is insulated from the respective gate electrode 40 by means of a further insulating layer 70. The electrode 80 extends in a vertical direction over the entire length of the trench and contacts the semiconductor body 100 at the bottom of the trench 60 in the region of the drift zone 14. A p-type doping region 90 is arranged in this contact region between the electrode 80 and the drift zone 14, which is contacted by the electrode 80 and completely covers the electrode in this region. The p-type doping region 90 and the drift zone 14 or the drain zone 12 form a diode, the circuit symbol of which is shown in FIG. Figure 3 , and the diode is polarized in the source-drain direction in the forward direction or in the drain-source direction in the reverse direction in the n-conducting MOSFET shown. The breakdown voltage of the diode in the drain-source direction can be adjusted by doping the p-doped region 90. Thus, a JFET is formed on the p-doped region, which serves to limit the current through the channel region in the event of a short circuit.

[0012] The electrode 80 arranged in the trench 60 is short-circuited with the n+ source region 30. For this purpose, the electrode 80 is located in the region above the trench, directly adjacent to the side wall of the trench 60, and adjacent to the n+ source region 30. Therefore, the electrode 80 (which is preferably composed of metal or polysilicon, in particular n-doped or p-doped polysilicon) is simultaneously used as a connection contact for the n+ source region 30, so that in order to contact the n-type source region 30, it is possible to directly contact the electrode 80 above the trench 60, thereby eliminating the contact terminal arranged above the semiconductor region (so-called mesa region) between the trenches.

[0013] Furthermore, the semiconductor structure comprises a p+ type body connection region 22 which is strongly p-doped, such as Figure 3 As becomes apparent from the perspective view in FIG. 1 , the strongly p-doped p+ body connection region extends from the p-body region 20 between the segments of the n+ source region 30 to the front side of the semiconductor body 100 and makes contact with the electrode 80 in the region above the trench 60, so that the electrode 80 short-circuits the p-body region 20 and the n+ source region 30 via the p+ body connection region 22, in order to avoid parasitic bipolar effects in a known manner. In the semiconductor structure, a separate contact for short-circuiting the n+ source region 30 and the p-body region 20 in the semiconductor region formed between the trenches (the so-called mesa region) can be omitted.

[0014] In order to connect the p-type body region 20 to the electrode 80 for short-circuiting, a narrow p+ body connection region 22 is sufficient, so that the space required for this in the mesa region is small. The body diode between the source 30 and the drain 14 generated by the short-circuit between the n+ source region 30 and the p-type body region 20 corresponds to the diode polarization of the shielding structure.

[0015] The threshold voltage of the shielding structure is set so that it is less than the threshold voltage of the body diode. When a positive voltage is then applied in the source-drain direction, the majority of the current flows through the diode of the shielding structure which is polarized in the conducting direction, so that the cross section of the p+ body connection region 22, by means of which the p-type body region 20 and the n+ source region 30 are short-circuited, can be small and can therefore be realized in a space-saving manner. The size of the silicon region between the trenches 60 can thus be reduced relative to conventional semiconductor components, which contributes to reducing the specific on-resistance of the semiconductor component.

[0016] In the case of a positive drain-source voltage and a positive gate potential relative to the source potential, known semiconductor components such as conventional MOSFETs, whose circuit symbol is shown in Figure 3If the drain-source voltage in the blocked MOSFET exceeds the threshold voltage of the diode formed by the p-doped region 90 and the drift region 14, a reverse current flows from the drain terminal connected to the drain region 12 via the drift region 14, the p-doped region 90 and the electrode 80 to the source terminal connected to the electrode 80. When a voltage is applied in the reverse direction (that is, a positive voltage in the source-drain direction), this breakdown structure behaves like a body diode and takes over most of the current flowing at that time, so that the connection contact for the p-type body region 20 can be small and can be formed in a space-saving manner.

[0017] In accordance with Figure 3 In a TMOSFET, a short circuit may occur, for example, when switched on without the application of a gate voltage. In this case, a high drain voltage acts on the semiconductor component and, without appropriate countermeasures, very high short-circuit currents may flow, which may lead to damage to the component.

[0018] The limitation of the short-circuit current can be achieved by means of a JFET formed by the p-doped region 90, wherein the space charge regions starting from the p-doped region 90 are so close to each other that a pinch-off of the short-circuit current occurs. Thus, in the event of a short circuit, the p-doped region 90 acts as a p-type shielding region.

[0019] A common optimization problem in such TMOSFETs is that in the design of every power MOSFET a compromise must be found between small on-resistance (i.e., high current at small drain voltage) and small short-circuit current (i.e., small current at high drain voltage). Summary of the invention

[0020] The invention realizes a vertical field effect transistor structure and a method for manufacturing the vertical field effect transistor structure.

[0021] The vertical field effect transistor structure according to the present invention has:

[0022] a semiconductor body having a first connection region and a second connection region of a first conductivity type;

[0023] a channel region of the first conductivity type or of a second conductivity type complementary to the first conductivity type, arranged between the first and second connection regions;

[0024] a plurality of trenches extending into the semiconductor body, the trenches passing through the channel region from the second connection region until reaching the first connection region and forming fins of the channel region and the second connection region;

[0025] a control electrode arranged in the trench, the control electrode being adjacent to the channel region and being arranged insulated relative to the semiconductor body;

[0026] a reverse current path connected between the first and second connection regions and in parallel with the channel region, the reverse current path having at least one pn junction and being designed to conduct when a threshold voltage acting between the first and second connection regions is reached;

[0027] wherein the semiconductor body has a doped region of the second conductivity type in the first connection region below a first trench in the trenches, and the first connection region below a second trench in the trenches does not have a doped region of the second conductivity type;

[0028] wherein the fin has a main body connection region of the second conductivity type, the main body connection region being in electrical contact with the channel region and the second connection region; and

[0029] The second conductive type body connection region extends into the drift region.

[0030] The method for manufacturing a vertical field effect transistor structure according to the present invention comprises the following steps:

[0031] Providing a semiconductor body having a first and a second connection region of a first conductivity type and a channel region of the first conductivity type or of a second conductivity type complementary to the first conductivity type arranged between the first and the second connection region;

[0032] forming a plurality of trenches extending into the semiconductor body, the trenches passing through the channel region from the second connection region until reaching the first connection region and forming fins of the channel region and the second connection region;

[0033] forming a control electrode arranged in the trench, the control electrode being adjacent to the channel region and being arranged insulated relative to the semiconductor body;

[0034] a reverse current path formed between the first and second connection regions and connected in parallel to the channel region, the reverse current path having at least one pn junction and configured to be conductive when a threshold voltage acting between the first and second connection regions is reached;

[0035] forming a doped region of the second conductivity type in a first connection region below a first one of the trenches, while a first connection region below a second one of the trenches does not have a doped region of the second conductivity type;

[0036] forming a body connection region of the second conductivity type in the fin, the fin being in electrical contact with the channel region and the second connection region; and,

[0037] Therein, the body connection region of the second conductivity type is formed in such a way that it extends into the drift region.

[0038] The preferred expansion options are described below.

[0039] The idea underlying the invention is to implant a p-type screening implant, for example, only in every second trench in a vertical field effect transistor structure and nevertheless achieve a good compromise between low short-circuit current and low on-resistance.

[0040] The p-type body connection can be implemented deeper than the p-type body region, so that it extends into the n-type drift region. As a result, a PN junction is generated below the channel, which reduces the resistance at high drain voltages and thus helps to reduce the short-circuit current. That is, at high drain voltages, a depletion region is formed in the n-type drift region, which leads to an increase in the resistance of the component. In the event of a short circuit, the increase in resistance here precisely helps to limit the short-circuit current.

[0041] Since, in addition to the JFET formed below the fin between two p-type shielding implants, the short-circuit current is additionally limited by this PN junction, it is sufficient according to the invention to implant only in, for example, every second trench, so that a p-type shielding region is produced only below every second trench. In the absence of a p-type shielding region below the trench bottom, the gate electrode in the trench is not implemented in two halves, since there is no p-type shielding region below the trench to which contact must be made. In the presence of a p-type shielding region below the trench bottom, the gate electrode in the trench can alternatively be implemented in two halves (especially when the p-type body connection is not as in Figure 1c in order to reach the p-type shielding region in order to make contact therewith) or as undivided electrodes (especially when these regions are already Figure 2b When contact is made via a deep p-body connection).

[0042] The trenches are preferably widened by cyclic oxidation and oxide etching, so that the mesas between the trenches are narrowed into fins.

[0043] According to a preferred development, the reverse current path extends in the trench, wherein electrodes are correspondingly arranged in the trench, which are conductively connected to the second connection region and electrically insulated from the control electrode, and a first electrode of the electrodes contacts a doped region of the second conductivity type at a first trench bottom in the trench.

[0044] According to a further preferred embodiment, the body connection region of the second conductivity type is in electrical contact with the doped region of the second conductivity type, wherein the reverse current path runs via the body connection region of the second conductivity type and the doped region of the second conductivity type. This has the advantage that complex processing of the connection in the trench for producing the electrode can be omitted.

[0045] According to a further preferred development, the first connection region has a lower-doped drift region of the first conductivity type and a higher-doped drain region, a doped region of the second conductivity type is arranged in the drift region, and a body connection region of the second conductivity type extends into the drift region.

[0046] According to another preferred embodiment, a diffusion region of the first conductivity type is arranged between the first connection region and the channel region, which contributes to better current distribution.

[0047] According to a further preferred embodiment, the semiconductor body consists of silicon carbide or gallium nitride. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Subsequently, further features and advantages of the present invention are explained based on embodiments with reference to the attached drawings.

[0049] The accompanying drawings show:

[0050] Figure 1a )-1h) shows a schematic cross-sectional view for explaining a method for manufacturing a vertical field effect transistor structure and a corresponding vertical field effect crystal structure according to a first embodiment of the present invention;

[0051] Figure 2a ), 2b) shows a schematic cross-sectional view for explaining a method for manufacturing a vertical field effect transistor structure and a corresponding vertical field effect crystal structure according to a second embodiment of the present invention; and

[0052] Figure 3 A schematic perspective view of a vertical field effect transistor structure according to the prior art DE 102 24 201 B4 is shown as a starting point for the present invention.

[0053] In the figures, the same reference signs denote identical elements or elements having the same function. DETAILED DESCRIPTION

[0054] Figure 1a )-1h) show schematic cross-sectional views for explaining a method for manufacturing a vertical field effect transistor structure and a corresponding vertical field effect crystal structure according to an embodiment of the present invention.

[0055] Figure 1a) shows a semiconductor body 100, which has a strongly n-doped region 12 (later n+ drain region) in the region of the back side, a weaker n-doped n-type drift region 14 adjoining the n+ drain region 12, a p-doped region 20 (later main region) adjoining the n-type drift region 14, and a strongly n-doped region (later n+ source region 30) adjoining the main region 20 on the front side 101. Optionally, an n-type diffusion region 14a can be arranged between the n-type drift region 14 and the main region 20, which contributes to better current distribution during operation. If necessary, the diffusion region 14a can also be located deeper in the n-type drift region 14 or penetrate deeper into it. In particular, up to the p-type shielding region 90.

[0056] The method is achieved by providing the semiconductor body 100 in the form of a semiconductor wafer and subsequent epitaxy and implantation steps known per se. Figure 1a ). With the aid of the hard mask M, a trench 60 is etched into the front side 101 by a trench etching process and then a scattering oxide 120 is deposited on the walls of the trench 60. Optionally (not shown), an n-type implantation step for producing an n-type diffusion region in the n-type drift region 14 can also be performed.

[0057] according to Figure 1b ), followed by a p-type implantation I, so as to form a p-type doped region 90 (p-type shielding region) in the n-type drift region 14 below the trench 60. No p-type implantation is performed in other adjacent trenches. The p-type implantation can be performed at periodic intervals. For example, a p-type shielding region can be implanted below every second, third or fourth trench, while no p-type implantation is performed in the trench located in between. Other patterns of p-type shielding regions are also possible, for example, two mutually connected trenches with implanted p-type shielding regions are followed by a trench in which no p-type implantation is performed. The p-type implantation can also be performed only partially in the trench, by partially retaining the n-type drift region 14 in the trench.

[0058] Different from Figure 3 According to the known structure, when a p-type implantation I is performed through the corresponding openings in the hard mask M, contact can also be made with the p-type body region 20 in the third dimension through the p+ type doped region 22', and the p+ type doped region 22' is staggered with the n+ type source region 30 along the n+p fin FI.

[0059] In addition, the p+ doped region 22' may be Figure 3 In particular, the p+ doped region 22' in this embodiment may extend into the n-type drift region 14, such as in Figure 1b) is indicated by a dotted line and Figure 1c ) is illustrated in a three-dimensional abstract cross-sectional diagram.

[0060] The p-type doping region 90 and / or the p+-type doping region 22 ′ may be out-diffused and activated by the annealing step.

[0061] Further references Figure 1d ), remove the hard mask M and the scattering oxide 120.

[0062] Next, according to Figure 1e ), at least widen such a groove 60: in the groove, according to Figure 1b ), wherein the widened trench 60' is laterally bounded by a narrowed n+ / p-type terrace, also referred to as an n+ / p-type fin FI. This is done by means of cyclic oxidation and oxide etching of the n+ / p-type terrace. By this step, undesired p-type implanted regions are removed from the sidewalls of the n+ / p-type terrace, which may be caused by the formation of a fin according to the invention. Figure 1b ) is produced by injection step I.

[0063] Figure 1f ) shows the structure after the gate insulating layer 50 and the polysilicon layer 40' are deposited. Figure 1g ), a gate electrode 40 is manufactured from the polysilicon layer on the sidewalls of the widened trench 60'.

[0064] These gate electrodes 40 can be produced, for example, by means of a so-called polyspacer process. For this purpose, the polysilicon layer 40 is etched back, for example, by means of an anisotropic etching method. This is done until the polysilicon layer 40 is removed at the bottom of the trench 60 ′ and from the front side 101 of the semiconductor body 100 and partially from the side walls in the region above the widened trench 60 ′. The gate insulation layer 50 is likewise removed from the front side 101 .

[0065] Finally, an insulating layer 70, for example an oxide layer, is produced on the exposed regions of the gate electrode 60. For this purpose, the insulating layer 70 is either deposited onto the gate electrode 40 or the gate electrode 40 is subjected to an oxidation treatment. Subsequently, the insulating layer 70 is removed from the front side 101 of the semiconductor body 100 and in the bottom region of the widened trench 60'.

[0066] Next, as in Figure 1h), the widened trench 60' is filled with an electrode material (eg metal or polysilicon) to produce an electrode 80, thereby obtaining a vertical field effect transistor structure according to an embodiment of the present invention.

[0067] If the electrode consists of metal or n-doped silicon, then, advantageously, silicon is applied to the exposed front side 101 of the semiconductor body 100, at least in the region of the p-doped region, before the electrode 80 is produced, in order to obtain a good ohmic contact between the electrode 80 and the p-doped region 90, thereby preventing a pn junction or a Schottky contact at this transition. The contacting of the gate electrode 40 can be carried out in this way as in known trench transistors and is not shown here.

[0068] Here, the process sequence described above focuses only on the process in the cell area. Other processes such as edge closure and contact pad lead-out, etc., should also be considered outside the cell area. In addition, each step may contain multiple sub-steps that are not specifically mentioned.

[0069] Figure 2a ), 2b) are schematic cross-sectional views for explaining a method for manufacturing a vertical field effect transistor structure and a corresponding vertical field effect crystal structure according to a second embodiment of the present invention.

[0070] If you have already referred to Figure 1b ) is performed as described above, so as to form a p-type doped region 90a (p-type shielding region) in the n-type drift region 14 below the trench 60. The p-type implantation is performed only below one trench, and no p-type implantation is performed in another adjacent trench. The p-type implantation I can be performed as described above. Figure 1b ) as described.

[0071] Figure 2a ) shows a vertical field effect transistor structure similar to that completed according to the second embodiment. Figure 1f )’s process status.

[0072] Different from Figure 1f ) Figure 2a ), the p+ doped region 22" is implanted even deeper into the n-type drift region 14. This results in the p+ doped region 22" and the p-doped region 90a being in contact and thus electrically connected to each other. In this way, electrical connection of the p-doped region 90a (p-type shielding region) via the electrode 80 is unnecessary. This is advantageous because the laborious processing of the connection in the trench 60' for manufacturing the electrode 80 can now be omitted.

[0073] Therefore, according to Figure 2a) is only filled with an insulating layer I in order to obtain a planar front side 101. In addition, further layers can also be applied for filling and planarization. In particular, in the case of a region 22" (which contacts the p-doped region 90a) implanted deeply into the n-type floating region 14, the division of the electrode 40 into two halves can be omitted. In this case (not shown), the trench is completely filled with electrode material and insulated on the surface with an insulating layer I.

[0074] Figure 2b ) is a three-dimensional abstract cross-sectional diagram similar to Figure 1c ) for illustration, the p+ type doping region 22″ and the p type doping region 90a are in contact with each other.

[0075] Although the invention has been described according to preferred embodiments, it is not limited thereto. In particular, the materials and topologies mentioned are merely exemplary and are not limited to the examples explained. The geometric structures shown are also merely exemplary and can be arbitrarily modified as required.

[0076] Although in the embodiments described above the p + -doped region and the p-doped region are formed in a common implantation step, it is also possible to use two separate implantation steps for this purpose.

Claims

1. A vertical field effect transistor structure having: A semiconductor body (100) having a first connection region (12, 14) and a second connection region (30) of a first conductivity type (n); a channel region (20) of the first conductivity type (n) or of a second conductivity type (p) complementary to the first conductivity type, arranged between the first and second connection regions (12, 14; 30); a plurality of trenches (60') extending into the semiconductor body (100), the trenches extending from the second connection region (30) through the channel region (20) to the first connection region (12, 14) and forming fins (FI) of the channel region (20) and of the second connection region (30); a control electrode (40) arranged in the trench (60'), the control electrode being adjacent to the channel region (20) and being arranged insulated relative to the semiconductor body (100); a reverse current path connected between the first and second connection regions (12, 14; 30) and in parallel with the channel region (20), the reverse current path having at least one pn junction and being configured to conduct when a threshold voltage acting between the first and second connection regions (12, 14; 30) is reached; wherein the semiconductor body (100) has a doped region (90; 90a) of the second conductivity type (p) in the first connection region (12, 14) below a first trench in the trench (60'), while the first connection region (12, 14) below a second trench in the trench (60') does not have a doped region (90; 90a) of the second conductivity type (p); wherein the fin (FI) has a body connection region (22'; 22") of the second conductivity type (p), the body connection region being in electrical contact with the channel region (20) and the second connection region (30); and The main connecting region (22'; 22") of the second conductivity type (p) extends into the drift region (14).

2. The vertical field effect transistor structure according to claim 1, wherein: The reverse current path extends in the trench (60'), wherein a corresponding electrode (80) is arranged in the trench (60'), the electrode is conductively connected to the second connection area (30) and the electrode is electrically insulated relative to the control electrode (40), and a first electrode of the electrodes (80) is in contact with a doped area (90; 90a) of the second conductivity type (p) at the bottom of the first trench in the trench (60').

3. The vertical field effect transistor structure according to claim 1, wherein: The second conductivity type (p) body connection region (22") is in electrical contact with the second conductivity type (p) doped region (90a), wherein a breakdown current path extends through the second conductivity type (p) body connection region (22') and the second conductivity type (p) doped region (90a).

4. The vertical field effect transistor structure according to claim 1, 2 or 3, wherein: The first connection region (12, 14) has a lower doped drift region (14) of the first conductivity type (n) and a higher doped drain region (12), a doped region (90; 90a) of the second conductivity type (p) being arranged in the drift region (13), wherein the body connection region (22'; 22") of the second conductivity type (p) extends into the drift region (14).

5. The vertical field effect transistor structure according to any one of claims 1 to 4, wherein: A diffusion region (14a) of the first conductivity type (n) is arranged between the first connection region (12, 14) and the channel region (20).

6. The vertical field effect transistor structure according to any one of claims 1 to 5, wherein: The semiconductor body (100) is composed of silicon carbide (SiC) or gallium nitride (GaN).

7. A method for manufacturing a vertical field effect transistor structure, comprising the following steps: A semiconductor body (100) is provided, comprising a first connection region (12, 14) and a second connection region (30) of a first conductivity type (n) and a channel region (20) of the first conductivity type (n) or of a second conductivity type (p) complementary to the first conductivity type, arranged between the first and second connection regions (12, 14; 30); forming a plurality of trenches (60') extending into the semiconductor body (100), the trenches passing through the channel region (20) from the second connection region (30) until reaching the first connection region (12, 14) and forming fins (FI) of the channel region (20) and the second connection region (30); forming a control electrode (40) arranged in the trench (60'), the control electrode being adjacent to the channel region (20) and being arranged insulated relative to the semiconductor body (100); A reverse current path formed between the first and second connection regions (12, 14; 30) and connected in parallel to the channel region (20), the reverse current path having at least one pn junction and configured to be conductive when a threshold voltage acting between the first and second connection regions (12, 14; 30) is reached; A doped region (90; ... 90a), while the first connection region (12, 14) below the second trench in the trench (60') does not have a doping region (90; 90a) of the second conductivity type (p); forming a main body connection region (22'; 22") of the second conductivity type (p) in the fin (FI), the fin being in electrical contact with the channel region (20) and the second connection region (30); and, Therein, the body connection region (22'; 22") of the second conductivity type (p) is formed in such a way that it extends into the drift region (14).

8. The method according to claim 7, wherein: A doped region (90; 90a) of the second conductivity type (p) and a body connection region (22'; 22") of the second conductivity type (p) are formed in a common implantation step (I).

9. The method according to claim 7 or 8, wherein: The reverse current path extends in the groove (60'), wherein a corresponding electrode (80) is arranged in the groove (60'), the corresponding electrode (80) is conductively connected to the second connection area (30), and the corresponding electrode is electrically insulated relative to the control electrode (40), and a first electrode of the electrodes (80) contacts the doped area (90; 90a) of the second conductivity type (p) at the bottom of the first groove (60) in the groove (60').

10. The method according to claim 7 or 8, wherein: The main connection region (22") of the second conductivity type (p) is formed so that it is electrically contacted with the doped region (90a) of the second conductivity type (p), wherein a breakdown current path extends through the main connection region (22") of the second conductivity type (p) and the doped region (90a) of the second conductivity type (p).

11. The method according to any one of claims 7 to 10, wherein: The first connection region (12, 14) has a lower doped drift region (14) of the first conductivity type (n) and a higher doped drain region (12), a doped region (90; 90a) of the second conductivity type (p) being arranged in the drift region (13), wherein the body connection region (22'; 22") of the second conductivity type (p) extends into the drift region (14).

12. The method according to any one of claims 7 to 11, wherein: A diffusion region (14a) of the first conductivity type (n) is arranged between the first connection region (12, 14) and the channel region (20).

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