Power semiconductor device

Abstract

The invention relates to a power semiconductor device. The power semiconductor device comprises a cellular region and a non-cellular region, and the non-cellular region is adjacent to the cellular region; the cellular region comprises a junction field effect transistor region; the power semiconductor device further comprises a gate layer, the gate layer comprises a first rectangular region, and the first rectangular region is located above the junction field effect transistor region or located in the non-cellular region. The first rectangular area comprises a hollow area. According to the technical scheme provided by the invention, the input capacitance of the device and the grid internal resistance of the device can be reduced, the charge and discharge quantity of the driver can be reduced, the driving power is saved, the cost of the driving board is reduced, and the driving board is more miniaturized.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a power semiconductor device. Background Art

[0002] In the related art, the polysilicon gate layer is an indispensable and important component of the Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), and its main function is to transmit the gate signal to each cell, so that the normal opening and closing of the cell can be controlled by the gate signal. The structure of the polysilicon gate layer has a very significant impact on the electrical performance of the MOSFET device, but the structure of the polysilicon gate layer in the MOSFET device in the related art is rough and needs further improvement. Summary of the invention

[0003] The purpose of the present application is to provide a power semiconductor device that can reduce the input capacitance of the device and reduce the gate internal resistance of the device, while reducing the amount of charge and discharge of the drive and saving driving power, reducing the cost of the drive board, and making the drive board more miniaturized.

[0004] According to a first aspect of an embodiment of the present application, there is provided a power semiconductor device, comprising: a cell region and a non-cell region, wherein the non-cell region is adjacent to the cell region; the cell region comprises a junction field effect transistor region; The power semiconductor device further includes: a gate layer, the gate layer includes a first rectangular area, the first rectangular area is located above the junction field effect transistor area or in the non-cell area; the first rectangular area includes a hollow area.

[0005] In one embodiment, the power semiconductor device further includes: A substrate of a first conductivity type, the substrate comprising an epitaxial layer of the first conductivity type; A first well region and a second well region of a second conductivity type are located in the epitaxial layer; A first source region, located in the first well region; a second source region, located in the second well region; a first effective channel is formed between an edge of the first source region close to the second source region and an edge of the first well region close to the second well region, and a second effective channel is formed between an edge of the second source region close to the first source region and an edge of the second well region close to the first well region; and the junction field effect transistor region is located between the first effective channel and the second effective channel; When the first rectangular area is located above the junction field effect transistor area, the first rectangular area further includes a first gate bar and a second gate bar, and the hollow area is located between the first gate bar and the second gate bar; The first gate strip is located above the first effective channel, and a projection of the first effective channel on the substrate is located within a projection of the first gate strip on the substrate; The second gate strip is located above the second effective channel, and a projection of the second effective channel on the substrate is located within a projection of the second gate strip on the substrate.

[0006] In one embodiment, the distance between the edge of the first gate strip close to the second gate strip and the edge of the first well region close to the second well region is greater than or equal to the process margin; A distance between an edge of the second gate strip close to the first gate strip and an edge of the second well region close to the first well region is greater than or equal to a process margin.

[0007] In one embodiment, the power semiconductor device further includes a gate oxide layer, wherein the gate oxide layer is located between the epitaxial layer and the gate layer; A first micro groove is arranged on the surface of the junction field effect transistor region, and the first micro groove is located below the hollow region.

[0008] In one embodiment, the non-cell region is a gate pad region; The hollow area is rectangular, and the first rectangular area also includes a first annular area, and the first annular area surrounds the hollow area; The power semiconductor device also includes an insulating layer and a gate contact hole, the insulating layer is located above the first annular area, the gate contact hole penetrates the insulating layer and contacts the first annular area, and the width of the first annular area is greater than or equal to the minimum allowable line width and greater than or equal to the minimum size of the gate contact hole.

[0009] In one embodiment, the non-cell region is a gate pad region; The hollow area is annular, the first rectangular area further includes a second annular area and the second rectangular area, the hollow area surrounds the second rectangular area, and the second annular area surrounds the hollow area; The second rectangular area is floating.

[0010] In one embodiment, the non-cell region is a gate wiring region; The first rectangular area further includes a third rectangular area and a plurality of third grid bars, the first side of the third rectangular area is provided with the hollow areas and the third grid bars arranged alternately in sequence, the third grid bars are connected to the third rectangular area, the second side of the third rectangular area is provided with the hollow areas and the third grid bars arranged alternately in sequence, and the first side is opposite to the second side; The power semiconductor device also includes an insulating layer and a gate contact hole, the insulating layer is located above the third rectangular area, the gate contact hole penetrates the insulating layer and contacts the third rectangular area, the width of the third rectangular area is smaller than the width of the first rectangular area, the width of the third rectangular area is greater than or equal to the minimum allowable line width, and is greater than or equal to the minimum size of the gate contact hole.

[0011] In one embodiment, the non-cellular region is a terminal region; The first rectangular area further includes a fourth rectangular area and a plurality of fourth grid bars, the hollow area includes a plurality of first hollow portions and a second hollow portion; the fourth grid bars and the first hollow portions are located on a side of the fourth rectangular area close to the cell area and are arranged alternately, and the fourth grid bars are connected to the fourth rectangular area; the second hollow portion is located on a side of the fourth rectangular area away from the cell area, the fourth grid bars and the first hollow portions extend along the width direction of the fourth rectangular area, and the second hollow portions extend along the length direction of the fourth rectangular area; The power semiconductor device also includes an insulating layer and a gate contact hole, the insulating layer is located above the fourth rectangular area, the gate contact hole penetrates the insulating layer and contacts the fourth rectangular area, and the width of the fourth rectangular area is greater than or equal to the minimum allowable line width and greater than or equal to the minimum size of the gate contact hole.

[0012] In one embodiment, the gate layer is made of polysilicon.

[0013] In one embodiment, the substrate and the epitaxial layer are made of silicon carbide.

[0014] Compared with the prior art, the beneficial effect of the present application is that: since the gate layer includes a first rectangular area, the first rectangular area is located above the junction field effect transistor area or in the non-cell area, and the first rectangular area includes a hollow area, therefore, the area of ​​the gate layer can be reduced, thereby reducing the input capacitance of the device and reducing the gate internal resistance of the device, while reducing the amount of charge and discharge of the drive and saving the drive power, reducing the cost of the drive board, and making the drive board more miniaturized.

[0015] Since the width of the gate layer or the area of ​​the hollow region can be greatly adjusted according to demand, the purpose of adjusting parasitic parameters such as input capacitance and gate internal resistance over a large range can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a cross-sectional schematic diagram of a cell region of a MOSFET chip shown according to the related art.

[0017] Figure 2 FIG. 1 is a top view of a polysilicon gate layer in a cell region of a MOSFET chip according to the related art.

[0018] Figure 3 FIG. 1 is a top view of a polysilicon gate layer in a gate pad region of a MOSFET chip according to the related art.

[0019] Figure 4 It is a top view of a polysilicon gate layer in a gate wiring area of ​​a MOSFET chip according to the related art.

[0020] Figure 5 FIG. 1 is a top view of a polysilicon gate layer in a terminal region of a MOSFET chip according to the related art.

[0021] Figure 6 is a schematic cross-sectional view of a cell region of a power semiconductor device according to an exemplary embodiment.

[0022] Figure 7 yes Figure 6 Top view of the gate layer in FIG.

[0023] Figure 8 is a schematic cross-sectional view of a cell region of a power semiconductor device according to another exemplary embodiment.

[0024] Fig. 9 FIG. 4 is a top view of a gate layer in a gate pad region of a power semiconductor device according to another exemplary embodiment.

[0025] Fig.10 FIG. 4 is a top view of a gate layer in a gate pad region of a power semiconductor device according to yet another exemplary embodiment.

[0026] Fig.11 FIG. 1 is a top view of a gate layer in a gate wiring region of a power semiconductor device according to another exemplary embodiment.

[0027] Fig.12 FIG. 4 is a top view of a gate layer in a terminal region of a power semiconductor device according to another exemplary embodiment. DETAILED DESCRIPTION

[0028] Unless otherwise defined, the technical terms or scientific terms used in this specification and claims shall have the usual meanings understood by persons with ordinary skills in the technical field to which this application belongs. The specific implementation modes of this application will be described below in conjunction with the accompanying drawings. It should be noted that in the specific description of these implementation modes, in order to provide a concise description, this specification cannot provide a detailed description of all the features of the actual implementation modes. Without departing from the spirit and scope of this application, those skilled in the art may modify and replace the implementation modes of this application, and the resulting implementation modes are also within the scope of protection of this application.

[0029] In the related art, the polysilicon gate layer of the MOSFET chip is mainly distributed in four areas of the chip, namely the cell area, the gate pad area, the terminal area and the gate routing area (other gate buses are located in this area). In the related art, the existing structure of the polysilicon gate layer is relatively rough and the potential of the structure has not been fully explored. The existing structure of the polysilicon gate layer in each area is introduced below by region.

[0030] like Figure 1~Figure 2 As shown, the polysilicon gate layer 17 includes a fifth gate strip 171, which is located in the cell region and spans across the two P-type wells 12 and the JFET (Junction Field-Effect Transistor) region 111 between the two P-type wells 12. Figure 1 It is a cross-sectional diagram of the cell area of ​​MOSFET chip. Figure 2 It is a top view of the polysilicon gate layer in the cell area.

[0031] like Figure 1 As shown, the MOSFET chip includes an N-type substrate 11, two P-type wells 12, an N+ type source region 13, an N+ type source region 14, two P+ doped regions 15, a gate oxide layer 16, a polysilicon gate layer 17, a first interlayer dielectric layer 18, two conductive parts 19 and a first metal layer 110. The N-type substrate 11 includes an N-type epitaxial layer, two P-type wells 12 are located in the N-type epitaxial layer, and a JFET region 111 is between the two P-type wells 12.

[0032] like Figure 2 As shown, the first region 1711 of the fifth gate strip 171 located above the JFET region 111 is a gate strip with a relatively large width and a relatively rough structure.

[0033] like Figure 3 As shown, the second region 172 in the gate pad region of the gate layer 17 is a gate strip with a relatively large width and a relatively rough structure. The second region 172 is connected to the fifth gate strip 171 in the cell region.

[0034] like Figure 4 As shown, the third region 173 in the gate wiring area of ​​the gate layer 17 is a gate strip with a relatively large width and a relatively rough structure. The width of the third region 173 is greater than the width D1 of the first protrusion 161 in the gate oxide layer 16. The third region 173 is connected to the fifth gate strip 171 in the cell area.

[0035] like Figure 5 As shown, the fourth region 174 in the gate layer 17 located in the terminal region is a gate strip with a relatively large width and a relatively rough structure. The fourth region 174 is connected to the fifth gate strip 171 located in the cell region. The fourth region 174 is closer to the first boundary E1 of the cell region than the second protrusion 162 in the gate oxide layer 16 is closer to the second boundary E2 of the cell region and is farther away from the terminal region.

[0036] In order to solve the above technical problems, the present application proposes a power semiconductor device that can reduce the input capacitance of the device and reduce the gate internal resistance of the device, while reducing the amount of charge and discharge of the drive and saving driving power, reducing the cost of the driving board, and making the driving board more miniaturized.

[0037] An embodiment of the present application provides a power semiconductor device. The power semiconductor device may be a MOSFET with a planar gate and a silicon carbide substrate, but is not limited thereto. The power semiconductor device may include a cell region and a non-cell region, and the non-cell region is adjacent to the cell region.

[0038] In one embodiment, the non-cell region may include a cell region, a gate pad region, a terminal region, and a gate wiring region.

[0039] In one embodiment, Figure 6 As shown, the structure of the power semiconductor device in the cell area includes: a substrate 61 of a first conductivity type, a first well region 62 and a second well region 63 of a second conductivity type, a first source region 64 of a first conductivity type, a second source region 65 of a first conductivity type, a first doped region 66 and a second doped region 67 of a second conductivity type, a JFET region 111, a gate oxide layer 16, a gate layer 68, a source 69, a drain 610, an interlayer dielectric layer 18 and a second metal layer 611.

[0040] In one embodiment, the first conductivity type may be N type, and the second conductivity type may be P type, but is not limited thereto. The first source region 64 is an N+ type source region, and the second source region 65 is an N+ type source region. The first doping region 66 and the second doping region 67 are P+ type doping regions.

[0041] In one embodiment, the substrate 61 may include an epitaxial layer of the first conductivity type. Figure 6As shown, the first well region 62 and the second well region 63 are located in the epitaxial layer. The first source region 64 is located in the first well region 62, and the second source region 65 is located in the second well region 63. The first effective channel C1 is formed between the edge of the first source region 64 close to the second source region 65 and the edge of the first well region 62 close to the second well region 63, the second effective channel C2 is formed between the edge of the second source region 65 close to the first source region 64 and the edge of the second well region 63 close to the first well region 62, and the junction field effect transistor region 111 is located between the first effective channel C1 and the second effective channel C2.

[0042] In one embodiment, Figure 6 As shown, the first doping region 66 penetrates the first source region 64 and extends into the first well region 62 , and the second doping region 67 penetrates the second source region 65 and extends into the second well region 63 .

[0043] In one embodiment, Figure 6 As shown, the gate oxide layer 16 is located on the epitaxial layer. The material of the gate oxide layer 16 can be silicon oxide.

[0044] In one embodiment, Figure 6 As shown, the gate layer 68 is located on the gate oxide layer 16. A first through hole 612 and a second through hole 613 are provided on the gate oxide layer 16 and the gate layer 68. The first through hole 612 penetrates the gate oxide layer 16 and the gate layer 68 to expose a portion of the first source region 64. The second through hole 613 penetrates the gate oxide layer 16 and the gate layer 68 to expose a portion of the second source region 65.

[0045] In one embodiment, Figure 6 As shown, the interlayer dielectric layer 18 covers the gate layer 68. The interlayer dielectric layer 18 is provided with a source contact hole 615 and a drain contact hole 616. The source contact hole 615 penetrates the interlayer dielectric layer 18 to expose the first doped region 66. The drain contact hole 616 penetrates the interlayer dielectric layer 18 to expose the second doped region 67.

[0046] In one embodiment, Figure 6 As shown, the source electrode 69 is located in the source contact hole 615 and contacts the first doping region 66 . The drain electrode 610 is located in the drain contact hole 616 and contacts the second doping region 67 .

[0047] In one embodiment, Figure 6 As shown, the source 69 and the drain 610 are electrically connected to the second metal layer 611 .

[0048] In one embodiment, the material of the gate layer 68 is polysilicon.

[0049] In one embodiment, the materials of the substrate 61 and the epitaxial layer are both silicon carbide.

[0050] In one embodiment, Figure 6 and Figure 7 As shown, the gate layer 68 includes a first rectangular area 681, the first rectangular area 681 is located above the junction field effect transistor area 111, and the first rectangular area 681 includes a hollow area 6811, a first gate bar 6812, and a second gate bar 6813. The hollow area 6811 is located between the first gate bar 6812 and the second gate bar 6813. The projection of the hollow area 6811 on the substrate 61 is located within the projection of the junction field effect transistor area 111 on the substrate 61.

[0051] In one embodiment, Figure 6 As shown, the first gate strip 6812 is located above the first effective channel C1, and the projection of the first effective channel C1 on the substrate 61 is located within the projection of the first gate strip 6812 on the substrate 61. The second gate strip 6813 is located above the second effective channel C2, and the projection of the second effective channel C2 on the substrate 61 is located within the projection of the second gate strip 6813 on the substrate 61.

[0052] In one embodiment, the distance between the edge of the first gate strip 6812 close to the second gate strip 6813 and the edge of the first well region 62 close to the second well region 63 may be greater than the process margin or may be equal to the process margin.

[0053] In one embodiment, the distance between the edge of the second gate strip 6813 close to the first gate strip 6812 and the edge of the second well region 63 close to the first well region 62 may be greater than the process margin or may be equal to the process margin.

[0054] In one embodiment, the gate layer 68 can be implemented by a high-precision photolithography machine, a layout machine, and an etching machine.

[0055] In the embodiment of the present application, since the gate layer 68 includes the first rectangular area 681, the first rectangular area 681 is located above the junction field effect transistor area 111, and the first rectangular area 681 includes the hollow area 6811, the area of ​​the gate layer 68 can be reduced, and then the input capacitance of the device and the gate internal resistance of the device can be reduced. At the same time, the charging and discharging charge of the drive can be reduced, the driving power can be saved, the cost of the driving board can be reduced, and the driving board can be more miniaturized.

[0056] Another embodiment of the present application provides a power semiconductor device. Figure 8 As shown, in this embodiment, a first micro groove 614 is provided on the surface of the junction field effect transistor region 111 , and the first micro groove 614 is located below the hollow region 6811 .

[0057] In this embodiment, since the first micro-grooves 614 are provided on the surface of the junction field effect transistor region 111 , the surface width of the junction field effect transistor region 111 is reduced, the parasitic capacitance of the device can be reduced, and the gate oxide layer 16 can be protected.

[0058] In one embodiment, the first through hole 612, the second through hole 613 and the hollow area 6811 can be prepared by the same etching process. While the first micro groove 614 is formed on the surface of the junction field effect transistor area 111, the first through hole 612 extends to the first source area 64 and the second through hole 613 extends to the second source area 65, resulting in over-etching. However, over-etching at the positions of the first through hole 612 and the second through hole 613 has no effect on subsequent processes.

[0059] Another exemplary embodiment of the present application further provides a power semiconductor device. In this embodiment, the non-cell region is a gate pad region.

[0060] In this embodiment, if Fig. 9 As shown, in the gate layer 68 in the gate pad region, the first rectangular region 681 includes a first annular region 6814 and a hollow region 6811 .

[0061] like Fig. 9 As shown, the hollow area 6811 is rectangular, and the first annular area 6814 surrounds the hollow area 6811. The width of the first annular area 6814 is greater than or equal to the minimum allowable line width, which is 0.2 microns. For example, the width of the first annular area 6814 can be 0.2 microns or 3 microns.

[0062] The power semiconductor device further includes an insulating layer and a gate contact hole, the insulating layer is located above the first annular region 6814, and the gate contact hole penetrates the insulating layer and contacts the first annular region 6814. The width of the first annular region 6814 is greater than or equal to the minimum size of the gate contact hole.

[0063] In one embodiment, the material of the insulating layer is silicon oxide.

[0064] In this embodiment, if Fig. 9 As shown, the gate layer 68 includes a sixth gate bar 682 . The sixth gate bar 682 is located in the cell region and is connected to the first rectangular region 681 .

[0065] Since the gate layer 68 in the gate pad area includes the first rectangular area 681, and the first rectangular area 681 includes the hollow area 6811, the area of ​​the gate layer 68 can be reduced, thereby reducing the input capacitance of the device and reducing the gate internal resistance of the device. At the same time, it can reduce the amount of charge and discharge of the drive and save driving power, reduce the cost of the driving board, and make the driving board more miniaturized.

[0066] It should be noted that if Fig. 9 The embodiment shown is similar to Figure 6 The embodiments shown can be implemented independently or simultaneously. Fig. 9 The embodiment shown is similar to Figure 8 The embodiments shown can be implemented independently or simultaneously.

[0067] Another exemplary embodiment of the present application further provides a power semiconductor device. In this embodiment, the non-cell region is a gate pad region.

[0068] In this embodiment, if Fig.10 As shown, in the gate layer 68 in the gate pad region, the first rectangular region 681 includes a hollow region 6811 , a second annular region 6815 and a second rectangular region 6816 .

[0069] like Fig.10 As shown, the hollow area 6811 is annular, the hollow area 6811 surrounds the second rectangular area 6816, and the second annular area 6815 surrounds the hollow area 6811.

[0070] In one embodiment, the second rectangular area 6816 is floating and does not receive any electrical signals.

[0071] In one embodiment, Fig.10 As shown, the gate layer 68 includes a sixth gate bar 682 . The sixth gate bar 682 is located in the cell region and is connected to the first rectangular region 681 .

[0072] Since the gate layer 68 in the gate pad area includes the first rectangular area 681, and the first rectangular area 681 includes the hollow area 6811, the area of ​​the gate layer 68 can be reduced, thereby reducing the input capacitance of the device and reducing the gate internal resistance of the device. At the same time, it can reduce the amount of charge and discharge of the drive and save driving power, reduce the cost of the driving board, and make the driving board more miniaturized.

[0073] It should be noted that if Fig.10 The embodiment shown, Fig. 9 The embodiment shown is similar to Figure 6 The embodiments shown can be implemented independently or simultaneously. Fig.10 The embodiment shown, Fig. 9 The embodiment shown is similar to Figure 8 The embodiments shown can be implemented independently or simultaneously.

[0074] Another exemplary embodiment of the present application further provides a power semiconductor device. In this embodiment, the non-cell region is a gate wiring region.

[0075] In this embodiment, if Fig.11As shown, in the gate layer 68 of the gate wiring area, the first rectangular area 681 includes a plurality of hollow areas 6811 , a third rectangular area 6817 and a plurality of third gate strips 6818 .

[0076] like Fig.11 As shown, the first side of the third rectangular area 6817 is provided with hollow areas 6811 and third gate bars 6818 arranged alternately in sequence, the third gate bar 6818 is connected to the third rectangular area 6817, and the second side of the third rectangular area 6817 is provided with hollow areas 6811 and third gate bars 6818 arranged alternately in sequence, and the first side is opposite to the second side.

[0077] In one embodiment, the power semiconductor device further includes an insulating layer and a gate contact hole, the insulating layer is located above the third rectangular area, the gate contact hole penetrates the insulating layer and contacts the third rectangular area 6817, the width D2 of the third rectangular area 6817 is less than the width D3 of the first rectangular area 681, the width D3 of the third rectangular area 6817 may be greater than or equal to the minimum allowable line width, and greater than or equal to the minimum size of the gate contact hole. The minimum allowable line width is 0.2 microns. The minimum size of the gate contact hole is 0.2 microns. The width D3 of the third rectangular area 6817 may be 0.2 microns or 3 microns.

[0078] In one embodiment, Fig.11 As shown, the width D2 of the third rectangular area 6817 may also be smaller than the width D1 of the first protrusion 161 in the gate oxide layer 16 .

[0079] In one embodiment, Fig.11 As shown, the gate layer 68 includes a sixth gate bar 682 , which is located in the cell region and connected to the third gate bar 6818 .

[0080] Since the gate layer 68 in the gate wiring area includes the first rectangular area 681, and the first rectangular area 681 includes the hollow area 6811, the area of ​​the gate layer 68 can be reduced, thereby reducing the input capacitance of the device and the gate internal resistance of the device, while reducing the amount of charge and discharge of the drive and saving the drive power, thereby reducing the cost of the drive board and making the drive board more miniaturized.

[0081] It should be noted that if Fig.11 The embodiment shown, Fig.10 The embodiment shown, Fig. 9 The embodiment shown is similar to Figure 6 The embodiments shown can be implemented independently or simultaneously. Fig.11 The embodiment shown, Fig.10 The embodiment shown, Fig. 9 The embodiment shown is similar to Figure 8The embodiments shown can be implemented independently or simultaneously.

[0082] Another exemplary embodiment of the present application further provides a power semiconductor device. In this embodiment, the non-cell region is a terminal region.

[0083] In this embodiment, if Fig.12 As shown, in the gate layer 68 of the terminal region, the first rectangular region 681 includes a hollow region 6811 , a fourth rectangular region 6819 and a plurality of fourth gate strips 6810 .

[0084] like Fig.12 As shown, the hollow area 6811 includes a plurality of first hollow portions 8111 and second hollow portions 8112. The fourth gate bar 6810 and the first hollow portions 8111 are located on the side of the fourth rectangular area 6819 close to the cell area and are arranged alternately. The fourth gate bar 6810 is connected to the fourth rectangular area 6819. The second hollow portion 8112 is located on the side of the fourth rectangular area 6819 away from the cell area. The fourth gate bar 6810 and the first hollow portion 8111 extend along the width direction of the fourth rectangular area 6819, and the second hollow portion 8112 extends along the length direction of the fourth rectangular area 6819.

[0085] In one embodiment, the power semiconductor device further includes an insulating layer and a gate contact hole, the insulating layer is located above the fourth rectangular area, the gate contact hole penetrates the insulating layer and contacts the fourth rectangular area 6819, and the width of the fourth rectangular area 6819 is greater than or equal to the minimum allowed line width and greater than or equal to the minimum size of the gate contact hole. The width D3 of the fourth rectangular area 6819 can be 0.2 microns or 3 microns.

[0086] like Fig.12 As shown, the fourth rectangular region 6819 close to the third boundary E3 of the cell region is closer to the terminal region than the second protrusion 162 in the gate oxide layer 16 close to the second boundary E2 of the cell region.

[0087] In one embodiment, Fig.12 As shown, the gate layer 68 includes a sixth gate bar 682 . The sixth gate bar 682 is located in the cell region and is connected to the fourth gate bar 6810 .

[0088] Since the gate layer 68 in the terminal area includes the first rectangular area 681, and the first rectangular area 681 includes the hollow area 6811, the area of ​​the gate layer 68 can be reduced, thereby reducing the input capacitance of the device and reducing the gate internal resistance of the device. At the same time, it can reduce the amount of charge and discharge of the drive and save driving power, reduce the cost of the driving board, and make the driving board more miniaturized.

[0089] It should be noted that if Fig.12 The embodiment shown, Fig.11The embodiment shown, Fig.10 The embodiment shown, Fig. 9 The embodiment shown is similar to Figure 6 The embodiments shown can be implemented independently or simultaneously. Fig.12 The embodiment shown, Fig.11 The embodiment shown, Fig.10 The embodiment shown, Fig. 9 The embodiment shown is similar to Figure 8 The embodiments shown can be implemented independently or simultaneously.

[0090] The above-mentioned embodiments can be combined without conflict, and the width of the gate layer 68 or the area of ​​the hollow region 6811 can be greatly adjusted according to demand, so as to achieve the purpose of adjusting parasitic parameters such as input capacitance and gate internal resistance in a larger range.

[0091] The above description of the embodiments is to facilitate those of ordinary skill in the art to understand and apply the present application. It is obvious that those familiar with the art can easily make various modifications to these embodiments and apply the general principles described herein to other embodiments without having to pay creative labor. Therefore, the present application is not limited to the embodiments herein, and improvements and modifications made by those skilled in the art based on the contents disclosed in the present application without departing from the scope and spirit of the present application are within the scope of the present application.

Claims

1. A power semiconductor device, characterized in that: include: A cell region, the cell region including a junction field effect transistor region; The power semiconductor device further comprises: A gate layer, the gate layer comprising a first rectangular area, the first rectangular area is located above the junction field effect transistor area; the first rectangular area comprises a hollow area; A substrate of a first conductivity type, the substrate comprising an epitaxial layer of the first conductivity type; A first well region and a second well region of a second conductivity type are located in the epitaxial layer; A first source region, located in the first well region; a second source region, located in the second well region; a first effective channel is formed between an edge of the first source region close to the second source region and an edge of the first well region close to the second well region, and a second effective channel is formed between an edge of the second source region close to the first source region and an edge of the second well region close to the first well region; the junction field effect transistor region is located between the first effective channel and the second effective channel; the first rectangular region further includes a first gate bar and a second gate bar, and the hollow region is located between the first gate bar and the second gate bar; the first gate bar is located above the first effective channel, and a projection of the first effective channel on the substrate is located within a projection of the first gate bar on the substrate; the second gate bar is located above the second effective channel, and a projection of the second effective channel on the substrate is located within a projection of the second gate bar on the substrate; A gate oxide layer is located between the epitaxial layer and the gate layer; a first micro-groove is provided on the surface of the junction field effect transistor region, and the first micro-groove is located below the hollow region.

2. The power semiconductor device according to claim 1, characterized in that: The distance between the edge of the first gate strip close to the second gate strip and the edge of the first well region close to the second well region is greater than or equal to the process margin; A distance between an edge of the second gate strip close to the first gate strip and an edge of the second well region close to the first well region is greater than or equal to a process margin.

3. The power semiconductor device according to claim 1, characterized in that: It also includes a non-cellular area, which is adjacent to the cellular area. The non-cellular area is provided with the first rectangular area, and the first rectangular area includes a hollow area.

4. The power semiconductor device according to claim 3, characterized in that: The non-cell region is a gate pad region; The hollow area is rectangular, and the first rectangular area also includes a first annular area, and the first annular area surrounds the hollow area; The power semiconductor device also includes an insulating layer and a gate contact hole, the insulating layer is located above the first annular area, the gate contact hole penetrates the insulating layer and contacts the first annular area, and the width of the first annular area is greater than or equal to the minimum allowable line width and greater than or equal to the minimum size of the gate contact hole.

5. The power semiconductor device according to claim 3, characterized in that: The non-cell region is a gate pad region; The hollow area is annular, the first rectangular area further includes a second annular area and a second rectangular area, the hollow area surrounds the second rectangular area, and the second annular area surrounds the hollow area; The second rectangular area is floating.

6. The power semiconductor device according to claim 3, characterized in that: The non-cell area is a gate wiring area; The first rectangular area further includes a third rectangular area and a plurality of third grid bars, the first side of the third rectangular area is provided with the hollow areas and the third grid bars arranged alternately in sequence, the third grid bars are connected to the third rectangular area, the second side of the third rectangular area is provided with the hollow areas and the third grid bars arranged alternately in sequence, and the first side is opposite to the second side; The power semiconductor device also includes an insulating layer and a gate contact hole, the insulating layer is located above the third rectangular area, the gate contact hole penetrates the insulating layer and contacts the third rectangular area, the width of the third rectangular area is smaller than the width of the first rectangular area, the width of the third rectangular area is greater than or equal to the minimum allowable line width, and is greater than or equal to the minimum size of the gate contact hole.

7. The power semiconductor device according to claim 3, characterized in that: The non-cellular region is a terminal region; The first rectangular area further includes a fourth rectangular area and a plurality of fourth grid bars, the hollow area includes a plurality of first hollow portions and a second hollow portion; the fourth grid bars and the first hollow portions are located on a side of the fourth rectangular area close to the cell area and are arranged alternately, and the fourth grid bars are connected to the fourth rectangular area; the second hollow portion is located on a side of the fourth rectangular area away from the cell area, the fourth grid bars and the first hollow portions extend along the width direction of the fourth rectangular area, and the second hollow portions extend along the length direction of the fourth rectangular area; The power semiconductor device also includes an insulating layer and a gate contact hole, the insulating layer is located above the fourth rectangular area, the gate contact hole penetrates the insulating layer and contacts the fourth rectangular area, and the width of the fourth rectangular area is greater than or equal to the minimum allowable line width and greater than or equal to the minimum size of the gate contact hole.

8. The power semiconductor device according to claim 1, characterized in that: The material of the gate layer is polysilicon.

9. The power semiconductor device according to claim 1, characterized in that: The substrate and the epitaxial layer are made of silicon carbide.

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