Semiconductor device and method for manufacturing semiconductor device

Abstract

The invention provides a semiconductor device and a method for manufacturing the semiconductor device. The solder of the semiconductor device preferably does not reach a triple point formed by a first electrode, a protective film, and a plating layer. The semiconductor device includes: a semiconductor substrate having an upper surface; a first electrode provided above the upper surface of the semiconductor substrate; the protective film is arranged above the first electrode; a plating layer provided above the first electrode and having a non-overlapping portion that does not overlap the protective film in plan view; and a nitride film provided continuously from between the protective film and the first electrode to between the non-overlapping portion and the first electrode, the thickness of the plating layer located above the nitride film being greater than the thickness of the nitride film.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] Conventionally, there is known a semiconductor device in which an intermediate layer is provided between an aluminum electrode and an organic protective film (see Patent Document 1). Also, there is known a semiconductor device in which there is no triple point formed by overlapping ends of a protective film, a plating layer, and an emitter electrode (see Patent Document 2).

[0003] Patent Document 1: WO2017 / 103978 Patent Document 2: Japanese Patent Application Laid-Open No. 2017-168659 Summary of the invention

[0004] Technical issues It is preferable that the solder does not reach the triple point formed by the first electrode, the protective film, and the plating layer.

[0005] Technical Solution In order to solve the above-mentioned problems, in a first embodiment of the present invention, a semiconductor device having a semiconductor substrate with an upper surface is provided. The semiconductor device may include a first electrode disposed above the upper surface of the semiconductor substrate. Any of the semiconductor devices may include a protective film disposed above the first electrode. Any of the semiconductor devices may include a plating layer disposed above the first electrode and having a non-overlapping portion that does not overlap with the protective film when viewed from above. Any of the semiconductor devices may include a nitride film disposed continuously from between the protective film and the first electrode to between the non-overlapping portion and the first electrode. In any of the semiconductor devices, the thickness of the plating layer located above the nitride film may also be greater than the thickness of the nitride film.

[0006] In any of the above-mentioned semiconductor devices, the nitride film may be in contact with the plated layer.

[0007] In any of the above-mentioned semiconductor devices, the nitride film may be in contact with the first electrode.

[0008] In any of the above-mentioned semiconductor devices, the protective film may be in contact with the plated layer.

[0009] In any of the above-mentioned semiconductor devices, the protective film may be separated from the plating layer.

[0010] In a plan view of any of the above semiconductor devices, a first length of a portion where the nitride film overlaps the plating layer in a direction perpendicular to an edge of the plating layer is 1 μm or more.

[0011] When any of the above semiconductor devices is viewed from above, the first length may be greater than 2 μm.

[0012] When any of the above semiconductor devices is viewed from above, the first length may be less than 4 μm.

[0013] In any of the above-mentioned semiconductor devices, a portion of the nitride film that protrudes further toward the plating layer than the protective film may have a thickness of 3 μm or more and 7 μm or less.

[0014] In any of the above-mentioned semiconductor devices, the thickness of the plated layer may be greater than the thickness of the protective film.

[0015] Any of the semiconductor devices described above may further include a second plating layer, the second plating layer being provided between the protective film and the nitride film, and the density of the second plating layer being lower than the density of the plating layer. In any of the semiconductor devices described above, in a plane parallel to the upper surface of the semiconductor substrate, the length of the second plating layer in a direction connecting the protective film and the plating layer may be less than half of the thickness of the plating layer.

[0016] In a second aspect of the present invention, a method for manufacturing a semiconductor device having a semiconductor substrate having a first electrode above an upper surface is provided. In the above method for manufacturing a semiconductor device, a nitride film may be manufactured above a portion of the first electrode. In any of the above methods for manufacturing a semiconductor device, a protective film may be manufactured above a portion of the nitride film. In any of the above methods for manufacturing a semiconductor device, an annealing treatment may be performed on the nitride film and the protective film. In any of the above methods for manufacturing a semiconductor device, a plating layer may be manufactured above the first electrode not covered by the nitride film and above a portion of the nitride film after the annealing treatment.

[0017] In any of the above-mentioned methods for manufacturing a semiconductor device, the temperature of the annealing process may be 300° C. or higher and 400° C. or lower.

[0018] In any of the above methods for manufacturing a semiconductor device, the annealing treatment may last for 30 minutes or more and 1 hour or less. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 1 is a plan view showing an example of a semiconductor device 100 according to an embodiment of the present invention.

[0020] Figure 2A It is shown Figure 1 A diagram showing an example of the aa section in FIG.

[0021] Figure 2B It is shown Figure 1FIG. 1 is a diagram showing another example of the aa section in FIG.

[0022] Figure 3A This is a diagram showing an example of the aa cross section in the comparative example.

[0023] Figure 3B This is a diagram showing another example of the aa cross section in the comparative example.

[0024] Figure 4 It is shown Figure 1 FIG. 1 is a diagram showing another example of the aa section in FIG.

[0025] Figure 5 A diagram showing a part of the manufacturing process of the semiconductor device 100 .

[0026] Figure 6 It is shown Figure 1 FIG. 1 is a diagram showing another example of the aa section in FIG.

[0027] Explanation of symbols 10…semiconductor substrate, 12…emitter region, 14…base region, 15…contact region, 16…accumulation region, 18…drift region, 20…buffer region, 21…upper surface, 22…collector region, 23…lower surface, 24…collector electrode, 30…dummy trench portion, 32…dummy insulating film, 34…dummy conductive portion, 38…interlayer insulating film, 40…gate trench portion, 42…gate insulating film, 44…gate conductive portion, 52…emitter electrode, 54…contact hole, 56…contact plug, 60, 61…teras, 70…protective film, 72…plating layer, 73…plating layer, 74…non-overlapping portion, 75…end side, 76…nitride film, 77…nitride film, 78…second plating layer, 80…diode portion, 82…cathode region, 90…transistor portion, 100…semiconductor device, 102…end side. DETAILED DESCRIPTION

[0028] Hereinafter, the present invention will be described by way of the embodiments of the invention, but the following embodiments do not limit the invention involved in the claims. In addition, all combinations of features described in the embodiments are not necessarily essential to the technical means of the invention.

[0029] In this specification, one side in a direction parallel to the depth direction of the semiconductor substrate is referred to as "upper", and the other side is referred to as "lower". One of the two main surfaces of a substrate, layer, or other component is referred to as an upper surface, and the other is referred to as a lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction when the semiconductor device is actually installed.

[0030] In this specification, sometimes the orthogonal coordinate axes of the X-axis, Y-axis and Z-axis are used to explain technical matters. The orthogonal coordinate axes only determine the relative positions of the components and do not limit specific directions. For example, the Z-axis is not limited to the height direction relative to the ground. It should be noted that the +Z-axis direction and the -Z-axis direction are opposite directions to each other. When the positive and negative are not recorded but the Z-axis direction is recorded, it means the direction parallel to the +Z-axis and the -Z-axis.

[0031] In this specification, the orthogonal axes parallel to the upper surface and the lower surface of the semiconductor substrate are referred to as the X-axis and the Y-axis. In addition, the axis perpendicular to the upper surface and the lower surface of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis is sometimes referred to as the depth direction. In addition, in this specification, the direction including the X-axis and the Y-axis and parallel to the upper surface and the lower surface of the semiconductor substrate is sometimes referred to as the horizontal direction.

[0032] In this specification, when it is said that they are “same” or “equal”, it may include the case where there is an error due to manufacturing variation, etc. The error is within 10%, for example.

[0033] In this specification, the conductivity type of the doped region doped with impurities is described as P-type or N-type. In this specification, impurities sometimes refer to either N-type donors or P-type acceptors, and sometimes are described as dopants. In this specification, doping refers to introducing donors or acceptors into a semiconductor substrate to form a semiconductor showing N-type conductivity or a semiconductor showing P-type conductivity.

[0034] In this specification, when described as P+ type or N+ type, it means that the doping concentration is higher than the doping concentration of P type or N type, and when described as P- type or N- type, it means that the doping concentration is lower than the doping concentration of P type or N type.

[0035] Figure 1 1 is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. The semiconductor device 100 includes a semiconductor substrate 10, a protective film 70, a plating layer 72, and a nitride film 76. The semiconductor device 100 may further include a plating layer 73 and a nitride film 77. The semiconductor substrate 10 has an upper surface and a lower surface. Figure 1 The diagram shows the semiconductor device 100 as viewed from above the upper surface of the semiconductor substrate 10 , which is referred to as a plan view in this specification.

[0036] The semiconductor substrate 10 is a substrate formed of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. When viewed from above, the semiconductor substrate 10 has an edge 102. The semiconductor substrate 10 of this example has two sets of edge 102 that are opposite to each other when viewed from above. Figure 1In the embodiment, the X-axis and the Y-axis are parallel to one of the end sides 102. In addition, the Z-axis is perpendicular to the upper surface of the semiconductor substrate 10.

[0037] At least one of the transistor unit and the diode unit described later is provided on the semiconductor substrate 10. A first electrode described later is provided above the upper surface of the semiconductor substrate 10. As an example, the first electrode may be an alloy of Al-Si. The first electrode is an electrode such as an emitter electrode or a source electrode through which a main current flows. The protective film 70, the plating layer 72, and the nitride film 76 of this example are provided above the first electrode. Solder is provided above the protective film 70, the plating layer 72, and the nitride film 76, and is connected to an external power source, etc., for example, via a lead frame joined to the solder, but Figure 1 Omitted in.

[0038] A control electrode such as a gate pad may be provided above the upper surface of the semiconductor substrate 10. The protective film 70 of this example is also provided above the control electrode. The plating layer 73 and the nitride film 77 are provided above the control electrode. The configuration and structure of the protective film 70, the plating layer 73 and the nitride film 77 above the control electrode are the same as the configuration and structure of the protective film 70, the plating layer 72 and the nitride film 76 above the first electrode. In this specification, the configuration and structure of the protective film 70, the plating layer 72 and the nitride film 76 above the first electrode are described, and the description of the configuration and structure of the protective film 70, the plating layer 73 and the nitride film 77 above the control electrode is omitted. The nitride film 77 may be connected to the nitride film 76. That is, the nitride film 77 may be a part of the nitride film 76.

[0039] Electrodes other than the first electrode and the control electrode may be further provided above the semiconductor substrate 10. The same structures as the protective film 70, the plating layer 72, and the nitride film 76 may be provided for each electrode above the semiconductor substrate 10.

[0040] The protective film 70 is provided from the edge 102 of the semiconductor substrate 10 toward the inner side of the semiconductor substrate 10 in a plan view. Figure 1 In the figure, the portion where the protective film 70 is provided is shaded. The protective film 70 is an insulating organic film, and is polyimide as an example. An opening is provided inside the protective film 70 above the first electrode. A plating layer 72 and a nitride film 76 are provided above the first electrode at the opening, and are exposed upward from the opening of the protective film 70.

[0041] The plating layer 72 is provided at a position closer to the inner side of the semiconductor substrate 10 than the protective film 70. That is, the plating layer 72 is provided at the opening of the protective film 70. However, the protective film 70 and the plating layer 72 may overlap. The portion that does not overlap with the protective film 70 when viewed from above is referred to as a non-overlapping portion. That is, the plating layer 72 has a non-overlapping portion. The plating layer 72 is electrically connected to the first electrode. The plating layer 72 may be nickel, or may be a structure in which gold for anti-oxidation is stacked on nickel.

[0042] The nitride film 76 is continuously provided from between the protective film 70 and the first electrode to between the non-overlapping portion of the plating layer 72 and the first electrode. The nitride film 76 may overlap the entire protective film 70. The nitride film 76 of this example has a portion that does not overlap with the protective film 70. The nitride film 76 may be provided in a wider range than the protective film 70 when viewed from above. Since the protective film 70 of this example does not overlap with the plating layer 72, the nitride film 76 is exposed upward from between the protective film 70 and the plating layer 72. The nitride film 76 may be silicon nitride having good adhesion to Al-Si.

[0043] Figure 2A It is shown Figure 1 1 is a diagram of an example of the aa section in FIG. The aa section of this example is an XZ section passing through the semiconductor substrate 10, the emitter electrode 52, the collector electrode 24, the interlayer insulating film 38, the protective film 70, the plating layer 72, and the nitride film 76. The semiconductor device 100 of this example has the semiconductor substrate 10, the interlayer insulating film 38, the emitter electrode 52, the collector electrode 24, the protective film 70, the plating layer 72, and the nitride film 76 in this cross section.

[0044] The semiconductor substrate 10 has an upper surface 21 and a lower surface 23. The semiconductor substrate 10 of this example is described as an RC-IGBT having a transistor portion 90 and a diode portion 80, but is not limited thereto. The transistor portion 90 may be a MOSFET. The semiconductor substrate 10 may have only the transistor portion 90 or only the diode portion 80. In addition, the aa cross section may be a cross section of a pad portion such as a gate pad for applying a gate voltage to a gate trench portion described later.

[0045] The interlayer insulating film 38 is provided on the upper surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 is a film including at least one of an insulating film such as silicate glass to which impurities such as boron or phosphorus are added, a thermal oxide film, and other insulating films. A contact hole 54 is provided in the interlayer insulating film 38. The contact hole 54 is filled with a contact plug 56 made of tungsten or the like.

[0046] The emitter electrode 52 is provided above the interlayer insulating film 38. The emitter electrode 52 is in contact with the upper surface 21 of the semiconductor substrate 10 via the contact plug 56. The emitter electrode 52 is an example of a first electrode. The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 (Z-axis direction) is referred to as the depth direction.

[0047] The semiconductor substrate 10 has an N-type drift region 18. The drift region 18 is provided in each of the transistor portion 90 and the diode portion 80.

[0048] The transistor section 90 and the diode section 80 each have a plurality of groove sections arranged in the arrangement direction (X-axis direction). In the transistor section 90 of this example, one or more gate groove sections 40 and one or more dummy groove sections 30 are alternately arranged along the arrangement direction. In the diode section 80 of this example, a plurality of dummy groove sections 30 are arranged along the arrangement direction. In the diode section 80 of this example, no gate groove section 40 is provided.

[0049] In the arrangement direction, a mesa portion is provided between each groove portion. The mesa portion refers to an area clamped by the groove portion inside the semiconductor substrate 10. As an example, the upper end of the mesa portion is the upper surface 21 of the semiconductor substrate 10. The depth position of the lower end of the mesa portion is the same as the depth position of the lower end of the groove portion. The mesa portion of this example is provided in the upper surface 21 of the semiconductor substrate 10 along the groove portion in the extension direction (Y-axis direction). In this example, a mesa portion 60 is provided in the transistor portion 90, and a mesa portion 61 is provided in the diode portion 80. When referred to as the mesa portion in this specification, it refers to the mesa portion 60 and the mesa portion 61 respectively.

[0050] In the mesa portion 60 of the transistor portion 90, an N+ type emitter region 12, a P+ type contact region 15, and a P type base region 14 are provided on the upper surface 21 side of the semiconductor substrate 10. An N type drift region 18 is provided below the base region 14. An N+ type accumulation region 16 is provided in the mesa portion 60. The accumulation region 16 is arranged between the base region 14 and the drift region 18.

[0051] The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10 and is provided in contact with the gate trench portion 40. The emitter region 12 may be in contact with the trench portions on both sides of the mesa portion 60. The doping concentration of the emitter region 12 is higher than the doping concentration of the drift region 18.

[0052] The contact region 15 is exposed on the upper surface 21 of the semiconductor substrate 10 at a position closer to the center of the mesa portion 60 than the emitter region 12. The contact region 15 may be provided at a position deeper than the emitter region 12.

[0053] The base region 14 is provided below the emitter region 12 and the contact region 15. The base region 14 is provided in contact with the emitter region 12 and the contact region 15. The base region 14 may be in contact with the groove portions on both sides of the mesa portion 60.

[0054] The accumulation region 16 is provided below the base region 14. The accumulation region 16 is an N+ type region having a higher doping concentration than the drift region 18. By providing a high-concentration accumulation region 16 between the drift region 18 and the base region 14, the carrier injection promotion effect (IE effect) can be improved and the on-state voltage can be reduced. The accumulation region 16 can be provided in a manner covering the entire lower surface of the base region 14 in each mesa portion 60.

[0055] In the mesa portion 61 of the diode portion 80, a P-type base region 14 is provided in contact with the upper surface 21 of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. In the mesa portion 61, an accumulation region 16 may be provided below the base region 14.

[0056] In the transistor portion 90 and the diode portion 80, an N+ type buffer region 20 may be provided below the drift region 18. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower end of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82.

[0057] In the transistor portion 90, a P+ type collector region 22 is provided below the buffer region 20. The acceptor concentration of the collector region 22 is higher than the acceptor concentration of the base region 14. The collector region 22 may contain the same acceptor as the base region 14 or may contain an acceptor different from the base region 14. The acceptor of the collector region 22 is, for example, boron.

[0058] In the diode portion 80, an N+ type cathode region 82 is provided below the buffer region 20. The donor concentration of the cathode region 82 is higher than the donor concentration of the drift region 18. The donor of the cathode region 82 is, for example, hydrogen or phosphorus. It should be noted that the elements that become the donors and acceptors of each region are not limited to the above examples. The collector region 22 and the cathode region 82 are exposed on the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24. The collector electrode 24 can be in contact with the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum. In this example, the boundary between the diode portion 80 and the transistor portion 90 in the X-axis direction is the boundary between the cathode region 82 and the collector region 22.

[0059] Each groove portion penetrates the base region 14 from the upper surface 21 of the semiconductor substrate 10 and reaches the drift region 18. In the region where at least any one of the emitter region 12, the contact region 15, and the accumulation region 16 is provided, each groove portion also penetrates these doped regions and reaches the drift region 18. The groove portion penetrating the doped region is not limited to the order of forming the groove portion after the doped region is formed. The case where the groove portion penetrates the doped region after the groove portion is formed is also included in the case where the groove portion penetrates the doped region.

[0060] The gate trench portion 40 includes a gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided in a manner covering the inner wall of the gate trench. The gate insulating film 42 can be formed by oxidizing or nitriding the semiconductor of the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench at a position closer to the inner side than the gate insulating film 42. That is, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0061] The gate conductive portion 44 can be set longer than the base region 14 in the depth direction. The gate groove portion 40 at this cross section is covered by the interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring in other cross sections. If a predetermined gate voltage is applied to the gate conductive portion 44, a channel formed by an inversion layer of electrons is formed in the surface layer of the interface in the base region 14 that is connected to the gate groove portion 40.

[0062] The dummy groove portion 30 may have the same structure as the gate groove portion 40 in this cross section. The dummy groove portion 30 includes a dummy groove provided on the upper surface 21 of the semiconductor substrate 10, a dummy insulating film 32 and a dummy conductive portion 34. The dummy conductive portion 34 may be electrically connected to the emitter electrode 52 in other cross sections. The dummy insulating film 32 is provided in a manner covering the inner wall of the dummy groove. The dummy conductive portion 34 is provided inside the dummy groove and is provided at a position closer to the inner side than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction.

[0063] The gate trench 40 and the dummy trench 30 of this example are covered by the interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The bottoms of the dummy trench 30 and the gate trench 40 may be curved surfaces convex downward (curved in cross section).

[0064] A protective film 70, a plating layer 72, and a nitride film 76 are provided above the emitter electrode 52. Although solder is formed above the plating layer 72, Figure 2A The solder may also be formed on the protective film 70 and the nitride film 76. The plating layer 72 has a non-overlapping portion 74 that does not overlap with the protective film 70 in the depth direction (Z-axis direction). Since the protective film 70 of this example is separated from the plating layer 72, the entire plating layer 72 becomes the non-overlapping portion 74.

[0065] The nitride film 76 is provided between the protective film 70 and the emitter electrode 52. The nitride film 76 of this example is in contact with the emitter electrode 52. The nitride film 76 is provided continuously from between the protective film 70 and the emitter electrode 52 to between the non-overlapping portion 74 of the plating layer 72 and the emitter electrode 52. By providing the nitride film 76, it is possible to prevent solder from reaching the triple point of the emitter electrode 52, the protective film 70, and the plating layer 72 described later.

[0066] The thickness of the nitride film 76 in the depth direction is set to t1. The thickness t1 of the nitride film 76 may be the average value of the thickness of the entire nitride film 76, or the average value of the thickness of the portion of the nitride film 76 that overlaps with the protective film 70. In the depth direction, the thickness of the plating layer 72 located above the nitride film 76 is set to t2. The thickness t2 may be greater than the thickness t1. By relatively reducing the thickness t1, the unevenness of the plating layer 72 caused by the provision of the nitride film 76 can be reduced. The thickness t2 may be more than 1.5 times the thickness t1, more than 2 times, more than 3 times, or more than 5 times. The thickness t2 may be less than 10 times the thickness t1. The plating layer 72 located above the nitride film 76 also includes a portion that does not overlap with the nitride film 76 in the depth direction. In this case, the thickness t2 may be the thickness of the plating layer 72 located above the position obtained by extending the upper end of the nitride film 76 in a plane parallel to the upper surface 21. The thickness t2 may be a value at the center of the plating layer 72, an average value of the thickness of the entire plating layer 72 may be used, or an average value or maximum value of the thickness of the portion overlapping the nitride film 76 may be used.

[0067] The nitride film 76 may be in contact with the plated layer 72. The nitride film 76 may overlap the plated layer 72. In a plan view, the length of the portion where the nitride film 76 overlaps the plated layer 72 in a direction perpendicular to the edge 75 of the plated layer 72 is denoted as t3. Figure 2A The end edge 75 shown extends in the Y-axis direction. Figure 2A In the embodiment, the length t3 is the length in the X-axis direction, but in the portion where the end of the plated layer 72 extends in the X-axis direction, the length t3 is the length in the Y-axis direction. The length t3 may be 1 μm or more. This prevents the solder from reaching the emitter electrode 52.

[0068] When solder is formed on the plating layer 72, there is a case where the plating layer 72 reacts with the solder about 2 μm from the surface, that is, so-called solder corrosion occurs. Therefore, the length t3 may be greater than 2 μm, or greater than 2.5 μm. Thus, the solder can be prevented from reaching the emitter electrode 52. The length t3 may be less than 5 μm, or less than 4 μm, or less than 3.5 μm. In addition, the length t3 may be less than the thickness t6 of the plating layer 72, or may be equal to the thickness t6 of the plating layer 72.

[0069] The length of the portion of the nitride film 76 that protrudes toward the plating layer 72 from the protective film 70 is t4. Figure 2A In the figure, the length t4 is the length in the X-axis direction, but in the portion where the end edge of the protective film 70 extends in the X-axis direction, the length t4 is the length in the Y-axis direction. The length t4 may be the length in the direction perpendicular to the end edge of the protective film 70 when viewed from above. The length t4 may be greater than 3 μm, or greater than 4 μm. The length t4 may be less than 5 μm, or less than 7 μm.

[0070] Figure 2B It is shown Figure 1 The configuration of the protective film 70 and the plating layer 72 in the aa section of this example is similar to Figure 2A The aa section shown is different. Other parts are the same Figure 2A The same, therefore the description is omitted.

[0071] The protective film 70 of this example is in contact with the plated layer 72. The end of the plated layer 72 can be arranged above the end of the protective film 70. As described later, since the adhesion between the protective film 70 and the plated layer 72 is not high, the solder may penetrate between the protective film 70 and the plated layer 72. In this example, since the nitride film 76 is provided, it is possible to prevent the solder that penetrates between the protective film 70 and the plated layer 72 from reaching the emitter electrode 52 (that is, the triple point).

[0072] Figure 3A 1 is a diagram showing an example of aa cross section in a comparative example. The semiconductor device 100 of this example does not include the nitride film 76. Figure 2AThe same, so the description is omitted. Residues of organic matter generated during patterning and etching of the protective film 70 are likely to remain near the end edge of the opening of the protective film 70. If a plating process is performed to form the plating layer 72 in this state, it is difficult for the plating layer to grow near the end edge of the opening of the protective film 70, and sometimes the plating layer 72 cannot be formed. Therefore, a triple point of the emitter electrode 52, the protective film 70, and the plating layer 72 is formed and exposed at the top. In this specification, the triple point is a position where the emitter electrode 52, the protective film 70, and the plating layer 72 coexist. If the subsequent process is entered in this state and solder is formed, the solder will reach the above-mentioned triple point.

[0073] When the semiconductor device 100 is used for a long time in a state where the solder has reached the triple point, cracks develop in the order of the emitter electrode 52 and the semiconductor substrate 10. Due to the development of the cracks, the reliability of the semiconductor device 100 against failures etc. is reduced. The development of the cracks gradually develops due to long-term use, and therefore it is difficult to detect in the inspection before shipment.

[0074] like Figure 2A and Figure 2B As shown, the semiconductor device 100 of this embodiment has the nitride film 76 continuously provided from between the protective film 70 and the emitter electrode 52 to between the non-overlapping portion 74 of the plating layer 72 and the emitter electrode 52, so that the above-mentioned triple point is not formed. In addition, the solder can also be prevented from reaching the emitter electrode 52.

[0075] Figure 3B 1 is a diagram showing another example of the aa cross section in the comparative example. The semiconductor device 100 of this example also does not include the nitride film 76. Figure 2A The same, so the description is omitted. This example shows a situation where no organic residue remains near the end edge of the opening of the protective film 70, and the plating layer still grows near the end edge of the opening of the protective film 70. In this case, although a triple point is formed, it is not exposed at the top. However, since the adhesion between the protective film 70 and the plating layer 72 is not high, there is a concern that the solder penetrates between the protective film 70 and the plating layer 72 and reaches the triple point. For the semiconductor device 100 of this embodiment, since the nitride film 76 is used and the triple point is not formed, even if the plating layer is grown near the end edge of the opening of the protective film 70, the reduction in the reliability of the semiconductor device 100 can be suppressed.

[0076] Figure 4 It is shown Figure 1 The thickness of the protective film 70 and the plating layer 72 in the aa section of this example is Figure 2A The thickness of the protective film 70 and the plating layer 72 in the cross section aa shown in FIG. Figure 2AThe same, therefore the description is omitted.

[0077] The thickness of the protective film 70 in the depth direction is t5. The thickness of the plating layer 72 in the depth direction is t6. In the semiconductor device 100 of this example, the thickness t6 is greater than the thickness t5. By thickening the plating layer 72, the unevenness of the plating layer 72 caused by the provision of the nitride film 76 can be reduced. However, if Figure 2A As shown in FIG. 1 , the thickness t5 may be greater than the thickness t6. Figure 2B As shown, the protective film 70 and the plated layer 72 are in contact with each other.

[0078] Figure 5 1 is a diagram showing a part of the manufacturing process of the semiconductor device 100. The manufacturing process of this example includes a first electrode film forming step S1000, a first electrode patterning etching step S1002, a nitride film forming step S1004, a nitride film patterning etching step S1006, a protective film coating step S1008, a protective film patterning etching step S1010, an annealing treatment step S1012, and a plating layer film forming step S1014.

[0079] In the first electrode film forming step S1000, a first electrode is formed on the upper surface 21 of the semiconductor substrate 10. As an example, a first electrode is formed on the semiconductor substrate 10. Figure 2A As an example, the first electrode is the emitter electrode 52, which may be an Al-Si alloy. In the first electrode patterning and etching step S1002, the manufactured first electrode is patterned and etched into a desired shape.

[0080] In the nitride film forming step S1004, a nitride film 76 is formed on a portion of the first electrode. As an example, the nitride film 76 is silicon nitride and is produced by sputtering, etc. In the nitride film patterning and etching step S1006, the produced nitride film 76 is patterned and etched to form an opening.

[0081] In the protective film coating step S1008, a protective film 70 is formed on a portion of the nitride film 76. The protective film 70 may be an insulating organic film, such as polyimide. In the protective film patterning and etching step S1010, the protective film 70 is patterned and etched to form an opening. At this time, the opening of the protective film 70 is made larger than the opening of the nitride film 76, so that Figure 2A As shown in FIG. 1 and FIG. 2 , the nitride film 76 can be continuously provided until between the non-overlapping portion 74 of the plating layer 72 to be formed later and the first electrode.

[0082] In the annealing step S1012, the nitride film 76 and the protective film 70 are annealed. As a result, the adhesion between the protective film 70 and the nitride film 76 is improved, and the growth of the second plating layer described later can be suppressed. As an example, the temperature of the annealing is 300° C. or more and 400° C. or less. As an example, the time of the annealing is 30 minutes or more and 1 hour or less. The time of the annealing can be 40 minutes or more, or 50 minutes or less.

[0083] In the plating layer film forming step S1014, after the annealing step S1012, the plating layer 72 is formed on the first electrode not covered by the nitride film 76 and on a part of the nitride film 76. The plating layer 72 can be nickel and is formed by a method such as electroless plating. Gold for oxidation resistance can also be produced on nickel. After that, solder is formed on the protective film 70, the nitride film 76 and the plating layer 72.

[0084] Figure 6 It is shown Figure 1 Another example of the aa section in FIG. The aa section in this example is different from Figure 2A The difference between the cross section aa shown is that a second plating layer 78 is formed between the protective film 70 and the nitride film 76. Figure 2A The same, therefore the description is omitted.

[0085] The semiconductor device 100 of this example further includes a second plating layer 78, which is provided between the protective film 70 and the nitride film 76, and the density of the second plating layer 78 is lower than that of the plating layer 72. Density is the weight per unit volume. Figure 6 In the plating layer film forming step S1014 , if the adhesion between the protective film 70 and the nitride film 76 is low, the plating solution will penetrate between the protective film 70 and the nitride film 76 to form the second plating layer 78 having a lower density than the plating layer 72 .

[0086] By performing annealing in the annealing step S1012, the adhesion between the protective film 70 and the nitride film 76 is improved, and since the penetration of the plating solution is reduced, the growth of the second plating layer 78 can be suppressed. The longer the plating treatment time in the plating layer film forming step S1014, the greater the thickness t6 of the plating layer 72, and similarly, it is considered that the second plating layer 78 is also grown. Therefore, as the degree of growth inhibition, the ratio of the thickness of the plating layer 72 to the length of the second plating layer 78 can be used. That is, the length of the second plating layer 78 in the direction of connecting the protective film 70 and the plating layer 72 in the plane parallel to the upper surface 21 of the semiconductor substrate 10 (in the X-axis direction in the aa section) is set to t7. The thickness t7 can be less than half of the thickness t6. The thickness t7 can be less than 30% of the thickness t6, or less than 20%, or less than 10%.

[0087] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. According to the description of the claims, the method to which such changes or improvements are made can also be included in the technical scope of the present invention.

[0088] It should be noted that the execution order of each process such as actions, sequences, steps and stages in the devices, systems, programs and methods shown in the claims, specifications and drawings can be implemented in any order unless it is specifically stated that "earlier than" or "in advance", etc., and that the previous processing results are not used in the subsequent processing. Even if the action flow in the claims, specifications and drawings is described using "first" or "next" for convenience, it does not mean that it must be implemented in this order.

Claims

1. A semiconductor device, characterized in that: have: a semiconductor substrate having an upper surface; a first electrode disposed above the upper surface of the semiconductor substrate; A protective film, disposed above the first electrode; a plating layer disposed above the first electrode and having a non-overlapping portion that does not overlap with the protective film when viewed from above; as well as a nitride film provided continuously from between the protective film and the first electrode to between the non-overlapping portion and the first electrode, The thickness of the plating layer at a position above the nitride film is greater than the thickness of the nitride film.

2. The semiconductor device according to claim 1, wherein: The nitride film is in contact with the plating layer.

3. The semiconductor device according to claim 1, wherein: The nitride film is in contact with the first electrode.

4. The semiconductor device according to claim 1, wherein: The protective film is in contact with the plating layer.

5. The semiconductor device according to claim 1, wherein: The protection film is separated from the plating layer.

6. The semiconductor device according to claim 1, wherein: In a plan view, a first length of a portion where the nitride film overlaps the plating layer in a direction perpendicular to an end side of the plating layer is 1 μm or more.

7. The semiconductor device according to claim 6, wherein: The first length is greater than or equal to 2 μm in a plan view.

8. The semiconductor device according to claim 7, wherein: The first length is less than or equal to 4 μm in a plan view.

9. The semiconductor device according to claim 1, wherein: A portion of the nitride film that protrudes toward the plating layer side beyond the protective film is 3 μm or more and 7 μm or less.

10. The semiconductor device according to claim 1, wherein: The thickness of the plating layer is greater than the thickness of the protective film.

11. The semiconductor device according to any one of claims 1 to 10, characterized in that The semiconductor device further includes a second plating layer, the second plating layer is provided between the protective film and the nitride film, and the density of the second plating layer is lower than the density of the plating layer. In a plane parallel to the upper surface of the semiconductor substrate, a length of the second plating layer in a direction connecting the protective film and the plating layer is less than or equal to half of a thickness of the plating layer.

12. A method for manufacturing a semiconductor device, characterized in that: The semiconductor device includes a semiconductor substrate having a first electrode above an upper surface. The method for manufacturing a semiconductor device comprises: forming a nitride film over a portion of the first electrode; forming a protective film over a portion of the nitride film; performing an annealing process on the nitride film and the protective film; and After the annealing process, a plating layer is produced on the first electrode not covered by the nitride film and on a portion of the nitride film.

13. The method for manufacturing a semiconductor device according to claim 12, wherein: The annealing treatment is performed at a temperature of 300° C. or higher and 400° C. or lower.

14. The method for manufacturing a semiconductor device according to claim 12, wherein: The annealing treatment time is 30 minutes or more and 1 hour or less.

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