Semiconductor structure and manufacturing method thereof

Abstract

The invention discloses a semiconductor structure and a manufacturing method thereof, and the semiconductor structure comprises a silicon-coated insulating substrate which comprises an element layer and a buried oxide layer adjacent to the element layer; at least one transistor disposed on the device layer; a dielectric layer surrounding the at least one transistor; an interconnect structure disposed on the dielectric layer and electrically connected to a gate of the at least one transistor; a charge trapping layer adjacent to the buried oxide layer; an upper cover layer adjacent to the charge trapping layer; and a conductive via penetrating the cap layer, the charge trapping layer, the buried oxide layer, the device layer and the dielectric layer, in which the conductive via is electrically connected to the interconnect structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an improved semiconductor structure and a manufacturing method thereof. Background Art

[0002] As is known, silicon-on-insulator (SOI) technology is often applied in the field of high-frequency technology, for example, radio frequency (RF) communication circuits, and three-dimensional integrated circuit (3D IC) chip fields.

[0003] The SOI device structure generally includes a base layer, an insulating layer and an active layer. The base layer is generally composed of a semiconductor material, such as silicon. The insulating layer is composed of a dielectric material layer. When the base layer is, for example, silicon, the insulating layer is generally composed of silicon dioxide formed by oxidation of the base layer. The active layer includes a device layer and a metal layer or a metal interconnect layer. The circuit formed may include metal lines (for example, formed in the metal interconnect layer); passive components, such as resistors, capacitors or inductors; and active components, such as transistors (for example, formed in the active device layer).

[0004] In the application of 3D integrated circuit chips, the breakdown voltage (BVD) of the top wafer with the input-output NMOS (IO-NMOS) circuit is equivalent to that of the bottom wafer before wafer bonding. However, the results of wafer reliability (WAT) analysis show that the breakdown voltage of the top wafer has a shift of about 0.8V after wafer bonding. Summary of the invention

[0005] The main purpose of the present invention is to provide an improved semiconductor structure and a manufacturing method thereof to solve the above-mentioned deficiencies or shortcomings of the prior art.

[0006] On one hand, the present invention provides a semiconductor structure, comprising: a silicon-on-insulator substrate, comprising a device layer and a buried oxide layer adjacent to the device layer; at least one transistor, arranged on the device layer; a dielectric layer, surrounding the at least one transistor; an internal wiring structure, arranged on the dielectric layer and electrically connected to the gate of the at least one transistor; a charge trapping layer, adjacent to the buried oxide layer; a cap layer, adjacent to the charge trapping layer; and a conductive via, penetrating the cap layer, the charge trapping layer, the buried oxide layer, the device layer and the dielectric layer, wherein the conductive via is electrically connected to the internal wiring structure and electrically connected to the at least one transistor via the internal wiring structure.

[0007] According to an embodiment of the present invention, the at least one transistor is a fully-depleted MOS-on-Si transistor.

[0008] According to an embodiment of the present invention, the charge trapping layer includes a phosphosilicate glass layer or a borosilicate glass layer.

[0009] According to an embodiment of the present invention, the charge trapping layer has a thickness of 80 to 120 angstroms.

[0010] According to an embodiment of the present invention, the upper cover layer includes a silicon nitride layer.

[0011] According to an embodiment of the present invention, the conductive via comprises copper.

[0012] According to an embodiment of the present invention, the dielectric layer includes an undoped silicate glass layer.

[0013] According to an embodiment of the present invention, the semiconductor structure further includes: an insulating layer adjacent to the upper cover layer; a passivation layer adjacent to the insulating layer; and a metal circuit layer disposed in the insulating layer and the passivation layer.

[0014] According to an embodiment of the present invention, the insulating layer includes a silicon oxide layer, and the passivation layer includes a silicon nitride layer.

[0015] According to an embodiment of the present invention, the metal circuit layer is an aluminum circuit layer.

[0016] On the other hand, the present invention provides a method for forming a semiconductor structure, comprising: providing a silicon-coated insulating substrate, comprising a device layer and a buried oxide layer adjacent to the device layer; forming at least one transistor on the device layer; forming a dielectric layer surrounding the at least one transistor; forming an internal connection structure on the dielectric layer, wherein the internal connection structure is electrically connected to the gate of the at least one transistor; forming a charge trapping layer adjacent to the buried oxide layer; forming a cap layer adjacent to the charge trapping layer; and forming a conductive via penetrating the cap layer, the charge trapping layer, the buried oxide layer, the device layer and the dielectric layer, wherein the conductive via is electrically connected to the internal connection structure and electrically connected to the at least one transistor via the internal connection structure.

[0017] According to an embodiment of the present invention, the at least one transistor is a fully depleted MOS-on-insulator transistor.

[0018] According to an embodiment of the present invention, the charge trapping layer includes a phosphosilicate glass layer or a borosilicate glass layer.

[0019] According to an embodiment of the present invention, the charge trapping layer has a thickness of 80 to 120 angstroms.

[0020] According to an embodiment of the present invention, the upper cover layer includes a silicon nitride layer.

[0021] According to an embodiment of the present invention, the conductive via comprises copper.

[0022] According to an embodiment of the present invention, the dielectric layer includes an undoped silicate glass layer.

[0023] According to an embodiment of the present invention, the method further comprises: forming an insulating layer adjacent to the upper cover layer; forming a passivation layer adjacent to the insulating layer; and forming a metal circuit layer in the insulating layer and the passivation layer.

[0024] According to an embodiment of the present invention, the insulating layer includes a silicon oxide layer, and the passivation layer includes a silicon nitride layer.

[0025] According to an embodiment of the present invention, the metal circuit layer is an aluminum circuit layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figures 1 to 4 The diagram is a schematic diagram of a method for forming a semiconductor structure according to an embodiment of the present invention.

[0027] Explanation of symbols

[0028] 1 Semiconductor structure

[0029] 10 First Wafer

[0030] 100 Silicon-on-insulator substrate

[0031] 101 Basal Layer

[0032] 102 Buried Oxide Layer

[0033] 103 Component Layer

[0034] 110 Dielectric layer

[0035] 120 Internal connection structure

[0036] 20 Second Wafer

[0037] 200 Silicon-coated insulating substrate

[0038] 201 Basal layer

[0039] 202a Rich trap layer

[0040] 202b Buried oxide layer

[0041] 203 Component Layer

[0042] 210 Dielectric layer

[0043] 220 Internal connection structure

[0044] 310 Charge Trapping Layer

[0045] 320 Upper cover

[0046] 410 Insulation layer

[0047] 420 Passivation layer

[0048] 430 Metal Circuit Layer

[0049] BL Bonding Layer

[0050] BV Bonding Via

[0051] BD Bonding Dielectric Layer

[0052] M1-M3 metal conductor layer

[0053] V1-V2 via layer

[0054] IMD Intermetal Dielectric

[0055] T, TB transistor

[0056] G, GB gate

[0057] GOX gate oxide

[0058] S, SB source doping region

[0059] D. DB drain doping region

[0060] ST, STB shallow trench insulation structure

[0061] P Plug

[0062] S1 Surface

[0063] DV conductive via DETAILED DESCRIPTION

[0064] In the following, the details will be described with reference to the accompanying drawings, which also constitute part of the detailed description of the specification and are illustrated in a specific way that the embodiment can be implemented. The following embodiments have been described in sufficient detail to enable a person skilled in the art to implement them.

[0065] Of course, other embodiments may be adopted, or any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the following detailed description should not be considered as limiting, but rather, the embodiments included therein will be defined by the appended claims.

[0066] See also Figures 1 to 4 , which is a schematic diagram of a method for forming a semiconductor structure 1 according to an embodiment of the present invention. Figure 1As shown, a first wafer 10 and a second wafer 20 are provided. The bonding layers BL of the first wafer 10 and the second wafer 20 may be bonded to each other via, for example, plasma activated bonding (PAB) technology. According to an embodiment of the present invention, for example, the bonding layer BL may include a bonding via BV and a bonding dielectric layer BD, but is not limited thereto. According to an embodiment of the present invention, for example, the bonding via BV may include a copper via, and the bonding dielectric layer BD may include silicon dioxide or silicon nitride, but is not limited thereto.

[0067] According to an embodiment of the present invention, the first wafer 10 may include a silicon-on-insulator (SOI) substrate 100. For example, the silicon-on-insulator substrate 100 may include a substrate layer 101, a buried oxide layer 102 adjacent to the substrate layer 101, and a device layer 103 adjacent to the buried oxide layer 102. A dielectric layer 110 may be formed on the device layer 103. According to an embodiment of the present invention, the dielectric layer 110 may include an undoped silicate glass (USG) layer, but is not limited thereto. According to an embodiment of the present invention, an internal connection structure 120 may be formed on the dielectric layer 110. For example, the internal connection structure 120 may include metal wire layers M1-M3, via layers V1, V2, and an intermetallic dielectric layer IMD.

[0068] According to an embodiment of the present invention, a circuit element, for example, a transistor T may be formed in the element layer 103 and the dielectric layer 110. For example, the transistor T may be a MOS transistor in an input / output NMOS circuit. According to an embodiment of the present invention, for example, the transistor T may include a gate G formed on the element layer 103 and surrounded by the dielectric layer 110, a gate oxide layer GOX below the gate G, a source doped region S formed in the element layer 103, and a drain doped region D formed in the element layer 103. According to an embodiment of the present invention, for example, the gate G may be a polysilicon gate or a metal gate. The transistor T may be electrically isolated by a shallow trench insulation structure ST formed in the element layer 103.

[0069] According to an embodiment of the present invention, for example, the transistor T may be an NMOS transistor, and the source doping region S and the drain doping region D may be N + According to an embodiment of the present invention, the transistor T may be a fully-depleted silicon-on-insulated metal oxide semiconductor transistor. According to an embodiment of the present invention, the gate G of the transistor T may be electrically connected to the metal wire layer M1 of the interconnect structure 120 through a plug P formed in the dielectric layer 110, such as a tungsten plug.

[0070] According to an embodiment of the present invention, the second wafer 20 may also include a silicon-on-insulator (SOI) substrate 200. For example, the silicon-on-insulator substrate 200 may include a substrate layer 201, a trap rich layer 202a adjacent to the substrate layer 201, a buried oxide layer 202b adjacent to the trap rich layer 202a, and a device layer 203 adjacent to the buried oxide layer 202b. According to an embodiment of the present invention, for example, the trap rich layer 202a may include amorphous silicon or polycrystalline silicon. A dielectric layer 210 may be formed on the device layer 203. According to an embodiment of the present invention, the dielectric layer 210 may also include an undoped silicate glass (USG) layer, but is not limited thereto. According to an embodiment of the present invention, an internal connection structure 220 may also be formed on the dielectric layer 210. For example, the internal connection structure 220 may also include a plurality of metal wire layers, a guide hole layer, and a metal interlayer dielectric layer.

[0071] According to an embodiment of the present invention, a circuit element, for example, a transistor TB may be formed in the element layer 203 and the dielectric layer 210. According to an embodiment of the present invention, for example, the transistor TB may include a gate GB formed on the element layer 203 and surrounded by the dielectric layer 210, a source doping region SB formed in the element layer 203, and a drain doping region DB formed in the element layer 203. According to an embodiment of the present invention, for example, the gate GB may be a polysilicon gate or a metal gate. The transistor TB may be electrically isolated by a shallow trench insulation structure STB formed in the element layer 203. According to an embodiment of the present invention, the transistor TB may be a fully depleted silicon-covered insulated metal oxide semiconductor transistor.

[0072] like Figure 2 As shown, then, the base layer 101 of the first wafer 10 is removed by a grinding process or a tetramethylammonium hydroxide (TMAH) etching process to expose the surface S1 of the buried oxide layer 102 .

[0073] like Figure 3 As shown, a chemical vapor deposition process may be performed to form a charge trapping layer 310 adjacent to the buried oxide layer 102. According to an embodiment of the present invention, the charge trapping layer 310 comprises a phosphosilicate glass layer or a borosilicate glass layer. According to an embodiment of the present invention, the thickness of the charge trapping layer 310 is about 80 to 120 angstroms. A chemical vapor deposition process may be performed to form an upper cover layer 320 adjacent to the charge trapping layer 310. According to an embodiment of the present invention, for example, the upper cover layer 320 may comprise a silicon nitride layer.

[0074] like Figure 4As shown, then, a metallization process is performed to form a conductive via DV penetrating the upper cover layer 320, the charge trapping layer 310, the buried oxide layer 102, the device layer 103 and the dielectric layer 110, wherein the conductive via DV is electrically connected to the metal wire layer M1 of the interconnect structure 120, and can be electrically connected to the transistor T through the metal wire layer M1, for example, electrically connected to the gate G of the transistor T. According to an embodiment of the present invention, the conductive via DV may include copper. Then, a chemical vapor deposition process may be performed, for example, a plasma enhanced chemical vapor deposition (PECVD) process, to form an insulating layer 410 adjacent to the upper cover layer 320. Then, a passivation layer 420 adjacent to the insulating layer 410 is formed. According to an embodiment of the present invention, the insulating layer 410 may include a silicon oxide layer, and the passivation layer 420 may include a silicon nitride layer. Finally, a metallization process is performed to form a metal line layer 430 in the insulating layer 410 and the passivation layer 420. According to an embodiment of the present invention, the metal circuit layer 430 may be an aluminum circuit layer.

[0075] The advantage of the present invention is that the charge trapping layer 310 formed on the buried oxide layer 102 is used to trap the charges in the buried oxide layer 102 so that the charges will not be damaged along the conductive via DV and the interconnect structure 120, thereby effectively preventing the breakdown voltage deviation problem of the top wafer after wafer bonding.

[0076] Structurally, such as Figure 4 As shown, the semiconductor structure 1 of the present invention comprises a silicon-on-insulator substrate 100 , which comprises a device layer 103 and a buried oxide layer 102 adjacent to the device layer 103 .

[0077] The semiconductor structure 1 of the present invention further comprises at least one transistor T disposed on the device layer 103. According to an embodiment of the present invention, the at least one transistor T is a fully-depleted silicon-on-insulator metal oxide semiconductor transistor.

[0078] The semiconductor structure 1 of the present invention further comprises a dielectric layer 110 surrounding at least one transistor T. According to an embodiment of the present invention, the dielectric layer comprises an undoped silicate glass layer.

[0079] The semiconductor structure 1 of the present invention further includes an interconnect structure 120 disposed on the dielectric layer 110 and electrically connected to the gate G of at least one transistor T.

[0080] The semiconductor structure 1 of the present invention further comprises a charge trapping layer 310 adjacent to the buried oxide layer 102. The buried oxide layer 102 is sandwiched between the device layer 103 and the charge trapping layer 310. According to an embodiment of the present invention, the charge trapping layer 310 comprises a phosphosilicate glass layer or a borosilicate glass layer. According to an embodiment of the present invention, the thickness of the charge trapping layer 310 is 80 to 120 angstroms.

[0081] The semiconductor structure 1 of the present invention further comprises an upper cap layer 320 adjacent to the charge trapping layer 310. According to an embodiment of the present invention, the upper cap layer 320 comprises a silicon nitride layer.

[0082] The semiconductor structure 1 of the present invention further comprises a conductive via DV penetrating the upper cover layer 320, the charge trapping layer 310, the buried oxide layer 102, the device layer 103 and the dielectric layer 110. According to an embodiment of the present invention, the conductive via DV is electrically connected to the metal wire layer M1 of the interconnect structure 120. According to an embodiment of the present invention, the conductive via DV comprises copper.

[0083] The semiconductor structure 1 of the present invention further comprises an insulating layer 410 adjacent to the upper cover layer 320; a passivation layer 420 adjacent to the insulating layer 410; and a metal circuit layer 430 disposed between the insulating layer 410 and the passivation layer 420. According to an embodiment of the present invention, the insulating layer 410 comprises a silicon oxide layer, and the passivation layer 420 comprises a silicon nitride layer. According to an embodiment of the present invention, the metal circuit layer 430 is an aluminum circuit layer.

[0084] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A semiconductor structure comprising: A silicon-covered insulating substrate comprising a component layer and a buried oxide layer adjacent to the component layer; At least one transistor is disposed on the device layer; a dielectric layer surrounding the at least one transistor; an interconnect structure disposed on the dielectric layer and electrically connected to a gate of the at least one transistor; a charge trapping layer adjacent to the buried oxide layer; an upper cap layer adjacent to the charge trapping layer; as well as A conductive via penetrates the cap layer, the charge trapping layer, the buried oxide layer, the device layer and the dielectric layer, wherein the conductive via is electrically connected to the internal connection structure and is electrically connected to the at least one transistor via the internal connection structure.

2. The semiconductor structure according to claim 1, wherein: The at least one transistor is a fully depleted silicon-on-insulator metal-oxide-semiconductor transistor.

3. The semiconductor structure according to claim 1, wherein: The charge trapping layer includes a phosphosilicate glass layer or a borosilicate glass layer.

4. The semiconductor structure according to claim 1, wherein: The charge trapping layer has a thickness of 80 to 120 angstroms.

5. The semiconductor structure according to claim 1, wherein: The upper cover layer includes a silicon nitride layer.

6. The semiconductor structure of claim 1, wherein: The conductive via comprises copper.

7. The semiconductor structure of claim 1, wherein: The dielectric layer includes an undoped silicate glass layer.

8. The semiconductor structure of claim 1, wherein: Also includes: an insulating layer adjacent to the upper cover layer; a passivation layer adjacent to the insulating layer; as well as The metal circuit layer is arranged in the insulating layer and the passivation layer.

9. The semiconductor structure of claim 8, wherein: The insulating layer includes a silicon oxide layer, and the passivation layer includes a silicon nitride layer.

10. The semiconductor structure of claim 8, wherein: The metal circuit layer is an aluminum circuit layer.

11. A method of forming a semiconductor structure, comprising: Providing a silicon-covered insulating substrate, comprising a device layer and a buried oxide layer adjacent to the device layer; forming at least one transistor on the device layer; forming a dielectric layer surrounding the at least one transistor; forming an interconnect structure on the dielectric layer, wherein the interconnect structure is electrically connected to a gate of the at least one transistor; forming a charge trapping layer adjacent to the buried oxide layer; forming a cap layer adjacent to the charge trapping layer; and A conductive via is formed through the cap layer, the charge trapping layer, the buried oxide layer, the device layer and the dielectric layer, wherein the conductive via is electrically connected to the interconnect structure and electrically connected to the at least one transistor via the interconnect structure.

12. The method of claim 11, wherein: The at least one transistor is a fully depleted silicon-on-insulator metal-oxide-semiconductor transistor.

13. The method of claim 11, wherein: The charge trapping layer includes a phosphosilicate glass layer or a borosilicate glass layer.

14. The method of claim 11, wherein: The charge trapping layer has a thickness of 80 to 120 angstroms.

15. The method of claim 11, wherein: The upper cover layer includes a silicon nitride layer.

16. The method of claim 11, wherein: The conductive via comprises copper.

17. The method of claim 11, wherein: The dielectric layer includes an undoped silicate glass layer.

18. The method of claim 11, wherein: Also includes: forming an insulating layer adjacent to the upper cover layer; forming a passivation layer adjacent to the insulating layer; and A metal circuit layer is formed in the insulating layer and the passivation layer.

19. The method of claim 18, wherein: The insulating layer includes a silicon oxide layer, and the passivation layer includes a silicon nitride layer.

20. The method of claim 18, wherein: The metal circuit layer is an aluminum circuit layer.

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