Preparation method of SOI (Silicon On Insulator) substrate
By forming an oxide layer on the device substrate and support substrate surface of the SOI material, injecting bubble ions and modified Ar ions, and performing bonding and annealing treatment, the problem of difficult suppression of the size of the suspended area around the SOI material is solved, and the quality of the SOI crystal is improved.
Patent Information
- Application Number
- CN202411890717.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-20
- Publication Date
- 2025-05-02
AI Technical Summary
In the prior art, after bonding, the SOI material will produce suspended areas around the perimeter due to the chamfer of the wafer itself, resulting in poor crystal quality and it is difficult to suppress the size of the suspended areas.
By forming an oxide layer on the surface of the device substrate and the support substrate, bubble ions are injected into the device substrate, and modified Ar ions are implanted above the bubble ion implantation area, and the device substrate is then bonded and reinforced at high temperatures, and finally peeling the device substrate by annealing to form an SOI substrate.
By implanting Ar ions to expand the effective bonding area, the size of the suspended part of the edge of the device layer is relatively reduced, the risk of subsequent edge collapse and fragmentation is reduced, and the quality of the SOI crystal is improved.
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Figure CN119922975A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of semiconductor technology, and in particular to a method for preparing an SOI substrate. Background Art
[0002] With the development of semiconductor manufacturing technology, integrated circuits have been widely used in many fields. Among them, devices based on silicon-on-insulator (SOI) technology have the characteristics of high temperature resistance and radiation resistance, which are suitable for traditional fields such as aerospace. At the same time, their advantages such as low power consumption, high speed and high integration are the basis for the design and preparation of high-speed and low-power integrated circuits, which can be applied to emerging fields such as autonomous driving and the Internet of Things.
[0003] The bonding process is one of the most important preparation methods in the prior art to prepare SOI materials. After bonding, due to the chamfering of the wafer itself, an overhanging area will be generated around it. How to suppress the size of this area is one of the key factors in improving the quality of SOI crystals. Summary of the invention
[0004] The technical problem to be solved by the present invention is to provide a method for preparing an SOI substrate, which can suppress the size of the peripheral suspended area.
[0005] In order to solve the above problems, the present invention provides a method for preparing an SOI substrate, comprising: providing a device substrate and a support substrate; forming an oxide layer on the surface of at least one of the device substrate and the support substrate; injecting bubbling ions into the device substrate; injecting modified ions above the bubbling ion injection region of the device substrate, wherein the modified ions are Ar ions; bonding the device substrate and the support substrate; and annealing to peel off the device substrate at the position where the bubbling ions are injected to form an SOI substrate.
[0006] Optionally, the energy range of the Ar ion implantation is 50-150 KeV, and the dose range is 1E14-1E16 cm -2 .
[0007] Optionally, the bubbling ions are selected from one or a combination of H ions and He ions.
[0008] Optionally, the device substrate is a single crystal silicon substrate.
[0009] Optionally, a high temperature reinforcement process is performed after the bonding to enhance the bonding strength.
[0010] The present invention uses Ar ions as modified ions to be injected into the device layer, which can expand the effective bonding area between the device substrate and the support substrate, relatively reduce the size of the suspended portion of the edge of the device layer, and thus reduce the risk of subsequent edge collapse and fragmentation. BRIEF DESCRIPTION OF THE DRAWINGS
[0011] AttachedFigure 1 Shown is a schematic diagram of the implementation steps of a method for preparing an SOI substrate according to a specific embodiment of the present invention.
[0012] Attached Figure 2A To Attachment Figure 2E Shown is a process flow chart of a method for preparing an SOI substrate according to a specific embodiment of the present invention.
[0013] Attached Figure 3 Shown is a top view of a wafer obtained by the method for preparing an SOI substrate according to a specific embodiment of the present invention.
[0014] Attached Figure 4 Shown are the comparative results of the edge overhang size test of the wafer obtained by the method for preparing the SOI substrate according to a specific embodiment of the present invention. DETAILED DESCRIPTION
[0015] The specific implementation of the method for preparing the SOI substrate provided by the present invention is described in detail below with reference to the accompanying drawings.
[0016] Attached Figure 1 The figure shows a schematic diagram of the implementation steps of the method for preparing the SOI substrate according to a specific embodiment of the present invention, including: step S10, providing a device substrate and a support substrate; step S11, forming an oxide layer on the surface of at least one of the device substrate and the support substrate; step S12, injecting bubbling ions into the device substrate; step S13, injecting modified ions above the bubbling ion injection region of the device substrate, wherein the modified ions are Ar ions; step S14, bonding the device substrate and the support substrate; step S15, annealing to peel off the device substrate at the position where the bubbling ions are injected to form an SOI substrate.
[0017] Attached Figure 2A To Attachment Figure 2E Shown is a process flow chart of a method for preparing an SOI substrate according to a specific embodiment of the present invention.
[0018] Attached Figure 2A As shown, referring to step S10, a device substrate 10 and a support substrate 20 are provided. The device substrate 10 and the support substrate 20 can be wafers of any common semiconductor material including silicon, germanium, silicon carbide, GaAs, and GaN. In this specific embodiment, the device substrate 10 and the support substrate 20 are single crystal silicon substrates.
[0019] Attached Figure 2BAs shown, referring to step S11, an oxide layer is formed on the surface of at least one of the device substrate 10 and the support substrate 20. The purpose of generating the oxide layer is to form a buried oxide of the SOI structure later. In this specific embodiment, oxide layers 11 and 21 are formed on both the device substrate 10 and the support substrate 20. The method of forming the oxide layer can be epitaxy or thermal oxidation. In this specific embodiment, the device substrate 10 and the support substrate 20 are single crystal silicon substrates, so the oxide layer can be formed by thermal oxidation, including dry oxygen and wet oxygen.
[0020] Attached Figure 2C As shown, referring to step S12, bubbling ions are injected into the device substrate 10. The bubbling ion implantation region 12 formed by the implantation is used for subsequent stripping operations. The bubbling ions are selected from one or a combination of H ions and He ions, and a suitable energy and dose range are selected according to the implantation depth. The surface portion of the implantation region 12 will be retained after stripping as the device layer of the final SOI substrate.
[0021] Step S13, injecting modified ions above the bubble ion implantation area 12 of the device substrate 10, wherein the modified ions are Ar ions. The area above the bubble ion implantation area 12 of the device substrate 10 is used as the device layer of the final SOI substrate. Ar ions are used as modified ions, which is beneficial to reduce the size of the suspended portion of the edge of the top device layer after the subsequent stripping process is completed. In this specific embodiment, the energy range of the Ar ion implantation is 50-150KeV, and the dose range is 1E14-1E16 cm -2 .
[0022] Attached Figure 2D As shown, referring to step S14, the device substrate 10 and the support substrate 20 are bonded. The bonding can be performed by any common bonding process such as normal pressure bonding and vacuum bonding, and the bonding surface is treated by plasma activation or the like before bonding to improve the quality of the bonding process. After bonding, a high temperature reinforcement process or the like can also be performed to enhance the bonding strength.
[0023] Attached Figure 2E As shown, step S15, annealing is performed to peel off the device substrate 10 at the position where the bubbling ions are injected to form an SOI substrate. The SOI substrate formed after peeling includes a support substrate 20, an oxide buried layer 30 formed by the oxide layers 11 and 21 on the surface of the support substrate, and a device layer 40 retained after peeling. Since the wafers all have an inward chamfered structure at the edge, the edge of the device layer 40 of the bonded SOI wafer is suspended, that is, Figure 2E The virtual frame parts on the left and right sides. This part is a ring shape in the three-dimensional structure of the wafer. Figure 3The above-mentioned suspended portion is shown in the circular ring shape in the top view of the wafer. The suspended portion will affect the subsequent process and cause the device layer 40 to collapse or even break. In step S13, Ar ions are injected into the device layer 40 as modified ions, which can expand the effective bonding area between the device substrate 10 and the support substrate 20, and relatively reduce the size of the suspended portion at the edge of the device layer 40, thereby reducing the risk of subsequent collapse and breakage.
[0024] Attached Figure 4 The figure shows the test results after adopting the solution described in the above specific implementation mode. Obviously, the size of the suspended part of the edge of the device layer 40 is significantly reduced.
[0025] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.
Claims
1. A method for preparing an SOI substrate, characterized in that: include: Providing a device substrate and a supporting substrate; forming an oxide layer on a surface of at least one of the device substrate and the support substrate; implanting bubbling ions into the device substrate; Implanting modified ions above the bubble ion implantation region of the device substrate, wherein the modified ions are Ar ions; bonding the device substrate to the support substrate; Annealing is performed to peel off the device substrate at the position where the bubble ions are implanted to form an SOI substrate.
2. The method according to claim 1, characterized in that The energy range of Ar ion implantation is 50-150 KeV, and the dose range is 1E14-1E16 cm -2 .
3. The method according to claim 1, characterized in that The foaming ions are selected from one or a combination of H ions and He ions.
4. The method according to claim 1, characterized in that: The device substrate is a single crystal silicon substrate.
5. The method according to claim 1, characterized in that: A high temperature reinforcement process is implemented after bonding to enhance the bonding strength.
Citation Information
Cited By
Method for preparing SOI substrate
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