Semiconductor structure, preparation method of semiconductor structure and electronic equipment

Abstract

The embodiment of the invention provides a semiconductor structure, a preparation method of the semiconductor structure and electronic equipment, and aims to solve the problem of poor performance of an MOS (Metal Oxide Semiconductor) tube in related technologies. The semiconductor structure includes a gate layer, a source portion, a drain portion, and a channel layer. The source electrode part comprises a source electrode layer and a source electrode contact layer which are arranged in a stacked mode, the source electrode contact layer is located between the source electrode layer and the grid electrode layer, the drain electrode part comprises a drain electrode layer and a drain electrode contact layer which are arranged in a stacked mode, and the drain electrode contact layer is located between the drain electrode layer and the grid electrode layer. The channel layer is located on one side of the gate layer, and at least part of the channel layer is located between the source electrode part and the drain electrode part. Wherein in the direction perpendicular to the grid electrode layer, first doping ions are evenly distributed in the source electrode contact layer, and / or second doping ions are evenly distributed in the drain electrode contact layer. Through the arrangement, the linear resistance of the source electrode contact layer and the drain electrode contact layer can be reduced, and the performance of the MOS tube can be improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a semiconductor structure, a method for preparing the semiconductor structure, and an electronic device. Background Art

[0002] Semiconductor structures are usually provided on electronic devices such as memories and controllers. MOS tubes (Metal Oxide Semiconductor Field Effect Transistors) are provided in the semiconductor structures. MOS tubes are used to realize functions such as switching and amplification. MOS tubes include a gate, a source, and a drain formed on a substrate. There is a channel structure between the source and the drain. By applying voltage to the gate and the source, an electric field effect is generated to control the switching of the conductive channel. However, the related art still has the problem of low performance of MOS tubes. Summary of the invention

[0003] The purpose of the embodiments of the present application is to provide a semiconductor structure, a method for preparing the semiconductor structure, and an electronic device, which are used to improve the problem of low performance of MOS tubes in semiconductor structures in related technologies.

[0004] To achieve the above purpose, the present application provides the following solution:

[0005] On the one hand, a semiconductor structure is provided, comprising: a gate layer, a source portion, a drain portion and a channel layer. The source portion and the drain portion are located on the first side of the gate layer, and the source portion and the drain portion are arranged at intervals, the source portion includes a source electrode layer and a source contact layer arranged in a stacked manner, the source contact layer is located between the source electrode layer and the gate layer, and the drain portion includes a drain electrode layer and a drain contact layer arranged in a stacked manner, and the drain contact layer is located between the drain electrode layer and the gate layer. The channel layer is located on the first side of the gate layer, and at least part of the channel layer is located between the source portion and the drain portion. Wherein, in a direction perpendicular to the gate layer, the source contact layer is uniformly distributed with a first doping ion, and / or, the drain contact layer is uniformly distributed with a second doping ion. Here, "uniform distribution" includes the described situation and a situation similar to the described situation, the range of which is within an acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement being discussed and the error associated with the measurement of a specific quantity (i.e., the limitations of the measurement system). For example, "uniform" includes absolute uniformity and approximate uniformity, wherein the acceptable deviation range of approximate uniformity may be, for example, a deviation within 5%. Through the above arrangement, since the first doping ions are uniformly distributed in the source contact layer in the direction perpendicular to the gate layer, it is beneficial to reduce the linear resistance of the source contact layer, thereby facilitating the improvement of the on-state current and effective mobility of the transistor. Similarly, since the second doping ions are uniformly distributed in the drain contact layer in the direction perpendicular to the gate layer, it is beneficial to reduce the linear resistance of the drain contact layer, thereby facilitating the improvement of the on-state current (Ion), effective mobility (mobility), on / off ratio, hysteresis and other characteristics of the MOS tube, thereby facilitating the improvement of the performance of the MOS tube.

[0006] In some embodiments, the channel layer includes a first portion and a second portion, the first portion and the second portion are connected, the first portion is located between the source contact layer and the drain contact layer, and the second portion is located on the side of the source contact layer and the drain contact layer away from the gate dielectric layer. Through the above arrangement, part of the first portion can contact the side wall of the source contact layer, and part of the second portion can contact the side of the source contact layer away from the gate layer, which is beneficial to increase the contact area between the channel layer and the source portion, and improve the contact reliability between the channel layer and the source portion. Similarly, part of the first portion can contact the side wall of the drain contact layer, which is beneficial to increase the contact area between the channel layer and the drain portion, and improve the contact reliability between the channel layer and the drain portion.

[0007] In some embodiments, the channel layer further includes a third portion, the third portion is connected to the second portion, and the third portion is located on a side of the source contact layer away from the drain contact layer, and on a side of the drain contact layer away from the source contact layer. It can be understood that the source portion and the drain portion are spaced relatively small along the second direction, and the first portion and the second portion of the channel layer are located between the source portion and the drain portion, and the first portion and the second portion of the channel layer are also relatively small in size in the second direction. By providing the third portion, it is helpful to increase the size of the channel layer in the second direction, thereby helping to reduce the difficulty of preparing the channel layer.

[0008] In some embodiments, the material of the channel layer includes crystalline silicon. Among them, the crystalline silicon can be formed, for example, by metal induced crystallization (MIC) technology. Metal induced crystallization silicon technology also has a lower processing cost, which is beneficial to reduce the manufacturing cost of semiconductor structures. Moreover, the channel material formed by this technology has better performance and reliability than solid phase crystallization (SPC). Furthermore, Metal Induced Lateral Crystallization (MILC) technology is a type of metal induced crystallization silicon technology. Crystalline silicon can also be formed by metal induced lateral crystallization technology. Metal induced lateral crystallization technology is beneficial to further improve the number of grains and defects in crystalline silicon.

[0009] In some embodiments, the orthographic projection of the source electrode layer on the gate layer is located within the orthographic projection of the source contact layer on the gate layer, and / or, the orthographic projection of the drain electrode layer on the gate layer is located within the orthographic projection of the drain contact layer on the gate layer. Since the source electrode layer is farther away from the substrate than the source contact layer, the above arrangement is conducive to improving the structural stability of the source portion. Similarly, since the drain electrode layer is farther away from the substrate than the drain contact layer, the above arrangement is conducive to improving the structural stability of the drain portion.

[0010] In some embodiments, the gate layer includes a gate electrode layer and a gate dielectric layer that are stacked, and the gate electrode layer is located on a side of the gate dielectric layer that is away from the source portion and the drain portion. Through the above arrangement, the gate electrode layer is located on a side of the gate dielectric layer that is away from the source portion and the drain portion, that is, the MOS tube in the embodiment of the present application is a bottom gate structure, which is conducive to avoiding leakage of the gate dielectric layer, thereby improving the reliability of the MOS tube.

[0011] On the other hand, a method for preparing a semiconductor structure is provided, comprising: providing a gate layer. Forming a source contact layer and a drain contact layer. Forming a channel layer. Forming a source electrode layer and a drain electrode layer. Wherein, the source electrode layer and the source contact layer constitute a source portion, the drain electrode layer and the drain contact layer constitute a drain portion, the source portion and the drain portion are located on one side of the gate layer, and the source portion and the drain portion are arranged at intervals, the source contact layer is located between the source electrode layer and the gate layer, and the drain contact layer is located between the drain electrode layer and the gate layer; the channel layer is located on one side of the gate layer, and at least part of the channel layer is located between the source portion and the drain portion; in a direction perpendicular to the gate layer, the source contact layer is uniformly distributed with first doped ions, and / or the drain contact layer is uniformly distributed with second doped ions. The method for preparing a semiconductor structure provided in an embodiment of the present application can prepare a semiconductor structure as described above, and therefore has all the above-mentioned beneficial effects, which will not be repeated here.

[0012] In some embodiments, forming a source contact layer and a drain contact layer includes: forming an intermediate contact layer by a thin film deposition process; removing a portion of the intermediate contact layer to form a source contact layer and a drain contact layer. In the intermediate contact layer formed by the thin film deposition process, the concentration distribution of the doped ions in the intermediate contact layer is uniform in the direction perpendicular to the gate layer. Among them, the doped ions located in the source contact layer are the first doped ions, and the doped ions located in the drain contact layer are the second doped ions. Through the above arrangement, in the direction perpendicular to the gate layer, the first doped ions are uniformly distributed in the source contact layer, which is beneficial to reducing the linear resistance of the source contact layer, and thus is beneficial to improving the on-state current and effective mobility of the transistor. Similarly, since the second doped ions are uniformly distributed in the drain contact layer in the direction perpendicular to the gate layer, it is beneficial to reduce the linear resistance of the drain contact layer, and thus is beneficial to improving the on-state current (Ion) and effective mobility (mobility) of the transistor.

[0013] In some embodiments, forming the channel layer includes: forming an intermediate channel layer, the intermediate channel layer being located on a side of the source contact layer, the drain contact layer, and the gate dielectric layer away from the substrate; and inducing the intermediate channel layer into the channel layer using a metal induced lateral crystallization process. Through the above arrangement, the metal induced lateral crystallization technology is conducive to further improving the number of grains and defects of crystalline silicon, thereby improving the performance of the channel layer.

[0014] In some embodiments, providing a gate layer includes: providing a gate electrode layer; forming a gate dielectric layer, wherein the gate dielectric layer is located on a side of the gate electrode layer close to the source portion and the drain portion. Through the above arrangement, the substrate and the gate electrode layer are the same film layer, and since the gate dielectric layer is located on a side of the substrate close to the source portion and the drain portion, the MOS tube is a bottom gate structure.

[0015] On the other hand, an electronic device is also provided, comprising a circuit board and a semiconductor structure as in any of the above embodiments, wherein the semiconductor structure and the circuit board are electrically connected. The electronic device provided in the embodiment of the present application comprises the semiconductor structure as described above, and thus has all the above beneficial effects, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A structural block diagram of an electronic device provided in an embodiment of the present application;

[0017] Figure 2 A structural diagram of a semiconductor structure provided for some embodiments;

[0018] Figure 3 A structural diagram of a semiconductor structure provided in an embodiment of the present application;

[0019] Figure 4 for Figure 3 Schematic diagram of the cross section of the semiconductor structure under a scanning electron microscope;

[0020] Figure 5 A top view of a semiconductor structure provided in an embodiment of the present application;

[0021] Figure 6 for Figure 3 Electron backscatter diffraction pattern of the channel layer of the semiconductor structure in FIG.

[0022] Figure 7 Schematic diagram of the preparation process of the top gate structure in some embodiments;

[0023] Figure 8 The electrical property curve diagram of the top gate structure in some embodiments;

[0024] Fig. 9 Schematic diagram of the preparation process of the bottom gate structure in some embodiments;

[0025] Fig.10 is a graph of diffusion simulation of nickel in a gate dielectric layer in a bottom gate structure in some embodiments;

[0026] Fig.11 is an electrical property curve diagram of a bottom gate structure in some embodiments;

[0027] Fig.12 A flowchart of the steps of the method for preparing a semiconductor structure in an embodiment of the present application;

[0028] Fig.13 A structural diagram after providing a substrate in the method for preparing a semiconductor structure in an embodiment of the present application;

[0029] Fig.14This is a structural diagram after a gate dielectric layer is formed in the method for preparing a semiconductor structure in an embodiment of the present application;

[0030] Fig.15 This is a structural diagram after the intermediate contact layer is formed in the method for preparing the semiconductor structure in the embodiment of the present application;

[0031] Fig.16 This is a structural diagram after a source contact layer and a drain contact layer are formed in the method for preparing a semiconductor structure in an embodiment of the present application;

[0032] Fig.17 This is a structural diagram after depositing a channel material in the method for preparing a semiconductor structure in an embodiment of the present application;

[0033] Fig.18 This is a structural diagram after an intermediate channel layer is formed in the method for preparing a semiconductor structure in an embodiment of the present application;

[0034] Fig.19 This is a structural diagram after a metal block is formed in the method for preparing a semiconductor structure in an embodiment of the present application;

[0035] Fig. 20 This is a structural diagram after a channel layer is formed in the method for preparing a semiconductor structure in an embodiment of the present application;

[0036] Fig.21 A structural diagram after forming a first opening and a second opening in the method for preparing a semiconductor structure in an embodiment of the present application;

[0037] Fig. 22 This is a structural diagram after a source electrode layer and a drain electrode layer are formed in the method for preparing a semiconductor structure in an embodiment of the present application;

[0038] Fig.23 This is a structural diagram after a conductive plug is formed in the method for preparing a semiconductor structure in an embodiment of the present application. DETAILED DESCRIPTION

[0039] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0040] In the following, the terms "first", "second", etc. are used only for convenience of description and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0041] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0042] When describing some embodiments, the expression "connected" and its derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components have direct physical or electrical contact with each other.

[0043] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0044] In the context of this application, the meaning of "on", "above", and "over" should be interpreted in the broadest manner, so that "on" not only means "directly on something", but also includes the meaning of "on something" with intervening features or layers in between, and "above" or "over" not only means "above" or "over" something, but also includes the meaning of "above" or "over" something without intervening features or layers in between (i.e., directly on something).

[0045] In the context of this application, "same-layer setting" refers to using the same film-forming process to form a film layer used to form a specific pattern, and then using the same mask template to form a layer structure through a single composition process. A single composition process may include multiple exposure, development or etching processes, and the material of the specific pattern in the formed layer structure is the same.

[0046] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0047] Figure 1 This is a structural block diagram of an electronic device provided in an embodiment of the present application. Figure 1As shown, an embodiment of the present application provides an electronic device 001, which includes a circuit board 2 and a semiconductor structure 1, wherein the semiconductor structure 1 can be the semiconductor structure 1 in any of the embodiments below, and the semiconductor structure 1 is electrically connected to the circuit board 2.

[0048] The electronic device 001 can be, for example, a mobile phone, a tablet computer (pad), a personal digital assistant (PDA), a television, a smart wearable product (e.g., a smart watch, a smart bracelet), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a rechargeable small household appliance (e.g., a soymilk machine, a sweeping robot), a drone, a radar, an aerospace equipment, a vehicle-mounted device, and other different types of user equipment or terminal equipment; the electronic device 001 can also be a network device such as a base station. The electronic device 001 can also be a radio frequency power amplifier, an analog driver, a discrete device, and other devices used in the above-mentioned electronic device 001. The embodiment of the present application does not impose any special restrictions on the specific form of the electronic device 001.

[0049] The circuit board 2 may be a printed circuit board (PCB), and of course the circuit board 2 may also be a flexible printed circuit (FPC), etc. This embodiment does not limit the circuit board 2. The semiconductor structure 1 may be packaged as a chip, and the circuit board 2 is connected to the semiconductor structure 1 through the pins of the chip. Furthermore, the electronic device 001 may also include a packaging substrate, which is fixed to the printed circuit board through solder balls, and the chip is fixed to the packaging substrate through solder balls.

[0050] The semiconductor structure 1 includes a MOS tube (Metal Oxide Semiconductor Field Effect Transistor). Figure 2 FIG. 1 is a structural diagram of a semiconductor structure 1' provided in some embodiments. Figure 2 As shown, the MOS transistor includes a gate electrode layer 11', a source electrode layer 31' and a drain electrode layer 32'. Further, the MOS transistor also includes a semiconductor layer 20' and a gate dielectric layer 12', and the semiconductor layer 20', the gate dielectric layer 12' and the gate electrode layer 11' are stacked. Exemplarily, the semiconductor layer 20' may include a source region 21', a drain region 22' and a channel region 23' sandwiched between the source region 21' and the drain region 22'. Among them, the source region 21' is in contact with the source electrode layer 31', and the drain region 22' is in contact with the drain electrode layer 32'.

[0051] It is understandable that MOS transistors can be divided into top gate structures and bottom gate structures. Figure 2 The MOS transistor in the semiconductor structure 1 shown may be a bottom gate structure. The semiconductor structure 1 may further include a substrate 101', the MOS transistor is located on one side of the substrate 101', the gate electrode layer 11' is located on the side of the gate dielectric layer 12' close to the substrate 101', and the source electrode layer 31' and the drain electrode layer 32' are located on the side of the semiconductor layer 20' away from the substrate 101'.

[0052] In some embodiments, to prepare the semiconductor structure 1, it is usually necessary to form a source region 21' and a drain region 22' at corresponding positions by an ion implantation process after forming the semiconductor layer 20'. However, the source region 21' or the drain region 22' formed by the ion implantation process has an uneven concentration distribution of doped ions in a direction perpendicular to the substrate 101, which increases the linear resistance of the source region 21' and the drain region 22', reduces the on-state current and effective mobility of the MOS tube, and causes the performance of the MOS tube to be reduced.

[0053] Furthermore, since the gate dielectric layer 12' is located on the side of the semiconductor layer 20' close to the substrate 101', when ion implantation is performed into the corresponding position of the semiconductor layer 20', the gate dielectric layer 12' may be damaged during the implantation process, causing leakage of the gate dielectric layer 12', thereby reducing the reliability of the MOS tube.

[0054] In view of this, an embodiment of the present application provides a semiconductor structure 1. Figure 3 A structural diagram of a semiconductor structure 1 provided in an embodiment of the present application; Figure 4 for Figure 3 The cross-sectional view of the semiconductor structure 1 in FIG. 1 under a scanning electron microscope (SEM) is shown. Figure 3 and Figure 4 As shown, the semiconductor structure 1 includes a gate layer 10 , a source portion 210 and a drain portion 220 .

[0055] The source portion 210 and the drain portion 220 are located on the first side M1 of the gate layer 10, and the source portion 210 and the drain portion 220 are arranged at intervals. The source portion 210 includes a source electrode layer 23 and a source contact layer 21 which are stacked, and the source contact layer 21 is located between the drain electrode layer 24 and the gate layer 10. The drain portion 220 includes a drain electrode layer 24 and a drain contact layer 22 which are stacked, and the drain contact layer 22 is located between the drain electrode layer 24 and the gate layer 10. For the convenience of explanation below, the direction parallel to the gate layer 10 is referred to as the first direction X and the second direction Y, and the first direction X and the second direction Y intersect (for example, the first direction X may be perpendicular to the second direction Y), and the direction perpendicular to the gate layer 10 is referred to as the third direction Z.

[0056] In some embodiments, the materials of the source electrode layer 23 and the drain electrode layer 24 may be the same. For example, the materials of the source electrode layer 23 and the drain electrode layer 24 may include a combination of one or more metals such as Pt, Ti, W, and Co. Further, the source electrode layer 23 and the drain electrode layer 24 may be arranged in the same layer, which is beneficial to improving the preparation efficiency of the semiconductor structure 1. Of course, in some other embodiments, the materials of the source electrode layer 23 and the drain electrode layer 24 may also be different, and this application does not specifically limit this.

[0057] Similarly, in some embodiments, the materials of the source contact layer 21 and the drain contact layer 22 may also be the same, for example, the materials of the source contact layer 21 and the drain contact layer 22 may include doped silicon. Further, the source contact layer 21 and the drain contact layer 22 may be provided in the same layer, which is beneficial to improving the preparation efficiency of the semiconductor structure 1. Of course, in some other embodiments, the materials of the source contact layer 21 and the drain contact layer 22 may also be different, and this application does not specifically limit this.

[0058] The semiconductor structure 1 further includes a channel layer 40, which is located on the first side M1 of the gate layer 10, and at least a portion of the channel layer 40 is located between the source portion 210 and the drain portion 220. In some embodiments, the channel layer 40 may be entirely located between the source portion 210 and the drain portion 220, and one end of the channel layer 40 is in contact with the source portion 210, and the other end of the channel layer 40 is in contact with the drain portion 220. By providing the channel layer 40, when a voltage is applied to the gate layer 10, current may be conducted between the source portion 210 and the drain portion 220 through the channel layer 40, so that the MOS tube is turned on.

[0059] The embodiment of the present application does not specifically limit the structural shapes of the source portion 210 , the drain portion 220 and the channel layer 40 in the semiconductor structure 1 . Figure 5 A top view of a semiconductor structure 1 provided in an embodiment of the present application. In some embodiments, Figure 5As shown, the source portion 210, the drain portion 220 and the channel layer 40 may be, for example, in a strip-shaped structure. Exemplarily, the source portion 210 and the drain portion 220 may be arranged at intervals along the first direction X, and the source portion 210 and the drain portion 220 may extend along the second direction Y; the channel layer 40 may extend along the second direction Y, and the channel layer 40 is in contact with the source portion 210 and the drain portion 220, respectively. The first direction X and the second direction Y are both parallel to the gate layer 10, and the first direction X and the second direction Y intersect. For example, the first direction X may be perpendicular to the second direction Y.

[0060] In which, in the direction perpendicular to the gate layer 10 (i.e., the third direction Z), the first doping ions are uniformly distributed in the source contact layer 21, and / or, the second doping ions are uniformly distributed in the drain contact layer 22. In some embodiments, a deposition process may be used to form the source contact layer 21 having the first doping ions, so that in the direction perpendicular to the gate layer 10 (i.e., the third direction Z), the concentration distribution of the first doping ions in the source contact layer 21 is uniform. Similarly, in some embodiments, a deposition process may be used to form the drain contact layer 22 having the second doping ions, so that in the direction perpendicular to the gate layer 10 (i.e., the third direction Z), the concentration distribution of the second doping ions in the drain contact layer 22 is uniform. Exemplarily, the deposition process may include, for example, an atomic layer deposition (ALD) process.

[0061] Here, "uniform distribution" includes the described situation and the situation similar to the described situation, and the range of the similar situation is within the acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the error associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "uniform" includes absolutely uniform and approximately uniform, wherein the acceptable deviation range of approximately uniform can be, for example, a deviation within 5%.

[0062] Through the above arrangement, since the first doping ions are uniformly distributed in the source contact layer 21 in the direction perpendicular to the gate layer 10 (i.e., the third direction Z), it is beneficial to reduce the linear resistance of the source contact layer 21, thereby facilitating the improvement of the on-state current and effective mobility of the transistor. Similarly, since the second doping ions are uniformly distributed in the drain contact layer 22 in the direction perpendicular to the gate layer 10 (i.e., the third direction Z), it is beneficial to reduce the linear resistance of the drain contact layer 22, thereby facilitating the improvement of the on-state current (Ion), effective mobility (mobility), on / off ratio, hysteresis and other characteristics of the MOS tube, thereby facilitating the improvement of the performance of the MOS tube.

[0063] Exemplarily, the gate layer 10 may include a gate electrode layer 11 and a gate dielectric layer 12 which are stacked, and the gate electrode layer 11 is located on the side of the gate dielectric layer 12 away from the source portion 210 and the drain portion 220. In some embodiments, the material of the gate dielectric layer 12 may include SiO2 (silicon dioxide). In some other embodiments, the material of the gate dielectric layer 12 may also include one or more high-K dielectric materials such as HfO2 (hafnium oxide) and Al2O3 (aluminum oxide). The present embodiment of the application does not specifically limit the structure of the gate layer 10. For example, the gate layer 10 may be as follows: Figure 5 Alternatively, the gate layer 10 may also be a local gate.

[0064] Based on the above structure, the semiconductor structure 1 also includes a substrate 101, at least a portion of which is a gate electrode layer 11. Exemplarily, the gate electrode layer 11 may be a silicon substrate 101, that is, the gate electrode layer 11 and the substrate 101 are the same film layer. Alternatively, the portion of the substrate 101 facing the gate dielectric layer 12 may be the gate electrode layer 11. Since the gate electrode layer 11 is located on the side of the gate dielectric layer 12 away from the source portion 210 and the drain portion 220, the substrate 101 is also located on the side of the gate dielectric layer 12 away from the source portion 210 and the drain portion 220, that is, the MOS tube in the embodiment of the present application is a bottom gate structure. Further, continue to refer to Figure 4 The semiconductor structure 1 may further include a protective layer 50, which may be located on the side of the source electrode layer 23 and the drain electrode layer 24 away from the substrate 101, wherein the material of the protective layer 50 may include silicon dioxide, and may be formed, for example, by an atomic layer deposition process. By providing the protective layer 50, the MOS tube can be isolated from water and air, which is beneficial to improving the stability of the MOS tube.

[0065] In some embodiments, the material of the channel layer 40 may include crystalline silicon. Among them, crystalline silicon can be formed, for example, by metal induced crystallization (MIC) technology. Metal induced crystalline silicon technology is a technology that transforms amorphous silicon into crystalline silicon by depositing metal and heat treatment. Metal induced crystalline silicon technology has a low thermal budget, and crystalline silicon grains larger than micron level can be obtained below 600°C. Metal induced crystalline silicon technology also has a low processing cost, which is conducive to reducing the manufacturing cost of the semiconductor structure 1. In addition, the channel material formed by this technology has good performance and reliability. Further, Metal Induced Lateral Crystallization (MILC) technology is a type of metal induced crystalline silicon technology. Crystalline silicon can also be formed by metal induced lateral crystallization technology. Metal induced lateral crystallization technology is a technology that transforms patterned amorphous silicon into crystalline silicon by locally depositing metal. This technology is conducive to further improving the number of grains and defects in crystalline silicon.

[0066] It is understandable that in the metal-induced lateral crystallization technology, the size of the crystal nucleus during the crystallization process can be controlled to obtain quasi-single-crystalline silicon with higher performance. Quasi-single-crystalline silicon has higher electron mobility and hole mobility. Figure 6 for Figure 3 The electron backscattered diffraction (EBSD) diagram of the channel layer 40 of the semiconductor structure 1 is shown in FIG. Figure 6 As shown, the colors of IPF X in the figure are consistent, which shows that the crystalline silicon has a good single crystal state. In summary, the crystalline silicon produced by the metal induced lateral crystallization technology can have a higher electron mobility and hole mobility, which is beneficial to improving the performance of the channel layer 40.

[0067] When crystalline silicon is formed by metal-induced crystalline silicon technology, metal impurities (such as Ni) are contained in the crystal lattice of the crystalline silicon. Figure 7 Schematic diagram of the preparation process of the top gate structure in some embodiments. Figure 7 When the MOS transistor is a top gate structure, the gate dielectric layer 12 is located on the side of the channel layer 40 away from the substrate 101, that is, the gate dielectric layer 12 is formed first, and then the gate dielectric layer 12 is formed. When the material of the gate dielectric layer 12 includes SiO2, the film layer needs to be thermally oxidized during the formation process, and metal impurities (such as Ni nickel) will remain in the gate dielectric layer 12 during the oxidation process. Figure 8 Graphs showing electrical properties of top gate structures in some embodiments. Figure 8As shown, due to the metal impurities in the gate dielectric layer 12, the gate dielectric layer 12 is more likely to form a conductive channel (trap assisted tunneling). When the gate voltage Vg applied to the gate increases to A, the gate dielectric layer 12 is broken down and the leakage current Ig increases significantly. That is, when the metal impurities remain in the gate dielectric layer 12, the gate dielectric layer 12 may leak electricity, resulting in reduced reliability of the transistor.

[0068] In the embodiment of the present application, since the MOS tube is a bottom gate structure, the gate dielectric layer 12 is formed first, and then the channel layer 40 is formed. Fig. 9 Schematic diagram of the preparation process of the bottom gate structure in some embodiments. Fig. 9 , the metal impurities (such as Ni nickel) in the crystalline silicon diffuse less in the gate dielectric layer 12 and have less impact on the gate dielectric layer 12 . Fig.10 FIG. 4 is a graph of a diffusion simulation of nickel in the gate dielectric layer 12 in a bottom gate structure in some embodiments. Fig.10 As shown, as the diffusion time of nickel increases, the concentration of nickel in the gate dielectric layer 12 does not increase significantly, which shows that the metal impurities in the crystalline silicon diffuse less in the gate dielectric layer 12 . Fig.11 2 is an electrical property curve diagram of the bottom gate structure in some embodiments. Figure 8 and Fig.10 , it can be seen that the leakage current Ig' of the bottom gate structure is lower than the leakage current Ig of the top gate structure. When the gate voltage Vg' applied to the gate increases, the gate dielectric layer 12 is not broken down. It can be seen that the breakdown voltage of the bottom gate structure is greater than the breakdown voltage of the top gate structure. In summary, when the channel layer 40 is formed by the metal-induced crystallized silicon technology, setting the MOS transistor to a bottom gate structure is beneficial to avoid leakage of the gate dielectric layer 12, thereby improving the reliability of the MOS transistor.

[0069] In some embodiments, the gate electrode layer 11 may have a third doping ion. When the third doping ion is a P-type ion, the first doping ion and the second doping ion are both N-type ions. When the third doping ion is an N-type ion, the first doping ion and the second doping ion are both P-type ions. Among them, the material of the p-type ion can be at least one of boron (B), aluminum (Al), gallium (Ga), indium (In), or a combination thereof. The material of the N-type ion can be at least one of phosphorus (P), PHx+ and / or P2Hx+ (x=1, 2, 3...) or a combination thereof.

[0070] In some embodiments, the channel layer 40 may include a first portion 41 and a second portion 42, the first portion 41 and the second portion 42 are connected, the first portion 41 is located between the source contact layer 21 and the drain contact layer 22, and the second portion 42 is located on the side of the source contact layer 21 and the drain contact layer 22 away from the gate dielectric layer 12. Exemplarily, the source contact layer 21 includes a first sidewall 211 and a second sidewall 212 arranged opposite to each other along the second direction Y, wherein the second sidewall 212 of the source contact layer 21 is a sidewall facing the drain contact layer 22, and the first sidewall 211 of the source contact layer 21 is a sidewall away from the drain contact layer 22. The drain contact layer 22 includes a third sidewall 221 and a fourth sidewall 222 arranged opposite to each other along the second direction Y, wherein the third sidewall 221 of the drain contact layer 22 is a sidewall facing the source contact layer 21, and the fourth sidewall 222 of the drain contact layer 22 is a sidewall away from the source contact layer 21. The first portion 41 may cover the gate dielectric layer 12 between the second sidewall 212 and the third sidewall 221, and the first portion 41 may also cover the second sidewall 212 and the third sidewall 221. The second portion 42 may include a first sub-portion 421 and a second sub-portion 422, wherein the first sub-portion 421 is located on the side of the source contact layer 21 away from the gate layer 10 and in contact with the source contact layer 21; the second sub-portion 422 is located on the side of the drain contact layer 22 away from the gate layer 10 and in contact with the drain contact layer 22. The first sub-portion 421 is connected to the first portion 41 covering the second sidewall 212, and the second sub-portion 422 is connected to the first portion 41 covering the third sidewall 221, so that the first portion 41 and the second portion 42 are connected.

[0071] Through the above-mentioned arrangement, part of the first part 41 can contact the side wall of the source contact layer 21, and part of the second part 42 can contact the side of the source contact layer 21 away from the gate layer 10, which is beneficial to increase the contact area between the channel layer 40 and the source portion 210, and improve the contact reliability between the channel layer 40 and the source portion 210. Similarly, part of the first part 41 can contact the side wall of the drain contact layer 22, which is beneficial to increase the contact area between the channel layer 40 and the drain portion 220, and improve the contact reliability between the channel layer 40 and the drain portion 220.

[0072] Continue to refer to Figure 3In some embodiments, the orthographic projection of the source electrode layer 23 on the gate layer 10 may be located within the orthographic projection of the source contact layer 21 on the gate layer 10. Since the source electrode layer 23 is farther from the substrate 101 than the source contact layer 21, the above arrangement is conducive to improving the structural stability of the source portion 210. Similarly, in some embodiments, the orthographic projection of the drain electrode layer 24 on the gate layer 10 may be located within the orthographic projection of the drain contact layer 22 on the gate layer 10. Since the drain electrode layer 24 is farther from the substrate 101 than the drain contact layer 22, the above arrangement is conducive to improving the structural stability of the drain portion 220.

[0073] Continue to refer to Figure 3 , the channel layer 40 may further include a third portion 43, the third portion 43 is connected to the second portion 42, and the third portion 43 is located on the side of the source contact layer 21 away from the drain contact layer 22, and on the side of the drain contact layer 22 away from the source contact layer 21. Exemplarily, the third portion 43 may include a third sub-portion 431 and a fourth sub-portion 432, wherein the third sub-portion 431 is located on the side of the source contact layer 21 away from the drain contact layer 22, and the fourth sub-portion 432 is located on the side of the drain contact layer 22 away from the source contact layer 21. It can be understood that the spacing between the source portion 210 and the drain portion 220 along the second direction Y is small, and the first portion 41 and the second portion 42 of the channel layer 40 are located between the source portion 210 and the drain portion 220, and the size of the first portion 41 and the second portion 42 of the channel layer 40 in the second direction Y is also small. The third portion 43 is provided to increase the size of the channel layer 40 in the second direction Y, thereby reducing the difficulty of preparing the channel layer 40 .

[0074] Further, in the embodiment where the material of the channel layer 40 is crystalline silicon, when the crystalline silicon is formed by the metal-induced crystalline silicon technology, an induction metal needs to be formed on the channel layer 40 so that the induction metal induces the amorphous silicon material to be a crystalline silicon material. Through the above arrangement, since the size of the channel layer 40 in the second direction Y increases, it is convenient to achieve the contact between the induction metal and the channel layer 40, which is conducive to further reducing the difficulty of preparing the channel layer 40.

[0075] Of course, in some other embodiments, the material of the channel layer 40 may also include amorphous silicon and polycrystalline silicon, or a combination of more than one thereof, which is not limited in the embodiments of the present application.

[0076] The embodiment of the present application further provides a method for preparing a semiconductor structure 1 , and the method is used to prepare the semiconductor structure 1 in any of the above embodiments. Fig.12 1 is a flowchart of the steps of the method for preparing the semiconductor structure 1 in the embodiment of the present application. Fig.12 , the method for preparing the semiconductor structure 1 may include steps S1-S4.

[0077] S1. Provide a gate layer.

[0078] Fig.13 This is a structural diagram after providing a substrate 101 in the method for preparing the semiconductor structure 1 in the embodiment of the present application. Fig.13 , the step of providing the gate layer 10 may include: providing a substrate 101, at least a portion of the substrate 101 being a gate electrode layer 11. Exemplarily, the material of the substrate 101 may include polysilicon doped with doping ions, and the substrate 101 is used as the gate electrode layer 11. Through the above arrangement, the substrate 101 and the gate electrode layer 11 are the same film layer. Of course, in some other embodiments, a silicon substrate 101 may also be provided, and a portion of the silicon substrate 101 may be doped so that the doped portion of the substrate 101 is the gate electrode layer 11.

[0079] Fig.14 FIG. 1 is a structural diagram of a semiconductor structure 1 after a gate dielectric layer 12 is formed in a method for preparing the semiconductor structure 1 in an embodiment of the present application. Fig.14 After providing the substrate 101, the step of providing the gate layer 10 may further include: forming a gate dielectric layer 12, the gate dielectric layer 12 being located on one side of the substrate 101. Exemplarily, in an embodiment where the material of the substrate 101 includes polycrystalline silicon, the substrate 101 may be subjected to thermal oxidation treatment to form thermally oxidized silicon, and the thermally oxidized silicon is the gate dielectric layer 12. Alternatively, in some other embodiments, other deposition processes may be used to form the gate dielectric layer 12 on the gate electrode layer 11, and the deposition process may be, for example, one of chemical vapor deposition (CVD), physical vapor deposition (physical vapor deposition, PVD), atomic layer deposition (atomic layer deposition, ALD), high-density plasma chemical vapor deposition (HDPCVD), metal organic chemical vapor deposition (metal organic chemical vapor deposition, MOCVD) and plasma enhanced chemical vapor deposition (plasma enhanced chemical vapor deposition, PECVD).

[0080] In summary, the gate electrode layer 11 and the gate dielectric layer 12 formed by the above steps can together constitute the gate layer 10. In the embodiment of the present application, after providing the gate layer 10, the method for preparing the semiconductor structure 1 further includes step S2.

[0081] S2. Forming a source contact layer and a drain contact layer.

[0082] Fig.15FIG. 2 is a structural diagram of a semiconductor structure 1 after forming an intermediate contact layer 203 in the method for preparing the semiconductor structure 1 according to an embodiment of the present application. Fig.15 , the step of forming the source contact layer 21 and the drain contact layer 22 may include: forming the intermediate contact layer 203 by a thin film deposition process. Exemplarily, the material of the intermediate contact layer 203 may include silicon doped with doping ions (e.g., amorphous silicon, polycrystalline silicon, or a combination of amorphous silicon and polycrystalline silicon). Wherein, when the doping ions in the substrate 101 are P-type ions, the doping ions in the intermediate contact layer 203 are N-type ions; when the doping ions in the substrate 101 are N-type ions, the doping ions in the intermediate contact layer 203 are P-type ions. In the intermediate contact layer 203 formed by the thin film deposition process, the concentration distribution of the doping ions in the intermediate contact layer 203 is uniform in the direction perpendicular to the gate layer 10 (i.e., the third direction Z). As described in the above embodiments, "uniform distribution" includes the described situation and the situation similar to the described situation, and the range of the similar situation is within the acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement being discussed and the error associated with the measurement of a specific quantity (i.e., the limitations of the measurement system). For example, “uniform” includes absolutely uniform and approximately uniform, wherein the acceptable deviation range of approximately uniform may be, for example, a deviation within 5%.

[0083] Fig.16 FIG. 1 is a structural diagram after forming a source contact layer 21 and a drain contact layer 22 in the method for preparing the semiconductor structure 1 in the embodiment of the present application. Fig.16 , after forming the intermediate contact layer 203, the step of forming the source contact layer 21 and the drain contact layer 22 may further include: removing part of the intermediate contact layer 203 to form the source contact layer 21 and the drain contact layer 22. Among them, the intermediate contact layer 203 can be patterned by a patterning process to form the source contact layer 21 and the drain contact layer 22. The patterning process includes a photolithography process and an etching process. The photolithography process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, developing photoresist, rinsing and drying (e.g., hard baking). The etching process includes a dry etching process or a wet etching process. The dry etching process includes using an etching gas such as carbon tetrafluoride (CF4), argon (Ar), nitrogen trifluoride (NF3), chlorine (Cl2), helium (He), hydrogen bromide (HBr), oxygen (O2), nitrogen (N2), fluoromethane (CH3F), methane (CH4), difluoromethane (CH2F2) or a combination thereof.

[0084] Among them, the doping ions located in the source contact layer 21 are the first doping ions, and the doping ions located in the drain contact layer 22 are the second doping ions. Through the above-mentioned arrangement, in the direction perpendicular to the gate layer 10 (that is, the third direction Z), the first doping ions are uniformly distributed in the source contact layer 21, which is beneficial to reducing the linear resistance of the source contact layer 21, thereby facilitating the improvement of the on-state current and effective mobility of the transistor. Similarly, since in the direction perpendicular to the gate layer 10 (that is, the third direction Z), the second doping ions are uniformly distributed in the drain contact layer 22, which is beneficial to reducing the linear resistance of the drain contact layer 22, thereby facilitating the improvement of the on-state current (Ion) and effective mobility (mobility) of the MOS tube.

[0085] In the embodiment of the present application, after the source contact layer 21 and the drain contact layer 22 are formed, step S3 may be further included.

[0086] S3. Forming a channel layer.

[0087] Fig.17 FIG. 5 is a structural diagram of a semiconductor structure 1 after a channel material 500 is deposited in a method for preparing the semiconductor structure 1 according to an embodiment of the present application. Fig.17 The step of forming the channel layer 40 may include: forming an intermediate channel layer 400, the intermediate channel layer 400 being located on the side of the source contact layer 21, the drain contact layer 22 and the gate dielectric layer 12 away from the substrate 101. Exemplarily, the channel material 500 may be deposited by a thin film deposition process, and the thin film deposition process may be one of the above-mentioned embodiments, which will not be described in detail herein. The channel material 500 may be amorphous silicon. Fig.18 FIG. 4 is a structural diagram after forming an intermediate channel layer 400 in the method for preparing the semiconductor structure 1 in the embodiment of the present application. Fig.18 After the channel material 500 is deposited, it can be patterned by a patterning process to form the middle channel layer 400. The middle channel layer 400 can be a stripe structure, and the middle channel layer 400 extends along the second direction Y.

[0088] As described in the above embodiment, the source contact layer 21 includes a first side wall 211 and a second side wall 212 that are oppositely arranged along the second direction Y, and the drain contact layer 22 includes a third side wall 221 and a fourth side wall 222 that are oppositely arranged along the second direction Y. The intermediate channel layer 400 may include a first middle portion 401, a second middle portion 402, and a third middle portion 403. The first middle portion 401 is located between the second side wall 212 and the third side wall 221, and is in contact with the second side wall 212 and the third side wall 221. The second middle portion 402 is located on the side of the source contact layer 21 that is away from the gate layer 10, and on the side of the drain contact layer 22 that is away from the gate layer 10. The third middle portion 403 is located on the side of the source contact layer 21 that is away from the drain contact layer 22, and on the side of the drain contact layer 22 that is away from the source contact layer 21, and the third middle portion 403 is also in contact with the first side wall 211 and the fourth side wall 222.

[0089] After forming the middle channel layer 400 , the step of forming the channel layer 40 may further include: inducing the middle channel layer 400 to be the channel layer 40 by using a metal induced lateral crystallization process.

[0090] Fig.19 FIG. 1 is a structural diagram of a semiconductor structure 1 after a metal block 60 is formed in a method for preparing the semiconductor structure 1 according to an embodiment of the present application. Fig.19 , the step of inducing the intermediate channel layer to be the channel layer may include: forming a metal block 60, the metal block 60 being in contact with the intermediate channel layer 400. Exemplarily, the metal block 60 may be formed on the third intermediate portion 403. Specifically, the metal block 60 may be formed by an evaporation process. The material of the metal block 60 may be at least one of Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Mo, Tr, Ru, Rh, Cd, Pt, etc. or any combination thereof. Fig.19 FIG. 1 is a structural diagram of the semiconductor structure 1 after the metal block 60 is peeled off in the method for preparing the semiconductor structure 1 in the embodiment of the present application. Fig.19 After the metal block 60 is formed, the metal block 60 needs to be peeled off to avoid affecting the subsequent process.

[0091] Fig. 20 FIG. 4 is a structural diagram after forming a channel layer 40 in the method for preparing the semiconductor structure 1 according to an embodiment of the present application. Fig. 20, the step of inducing the intermediate channel layer to be the channel layer may further include: heat treating the intermediate channel layer 400 so that the intermediate channel layer 400 forms the channel layer 40. Exemplarily, the amorphous silicon can be crystallized into quasi-single-crystal silicon under the induction of the metal block 60 by a heat treatment process, so that the intermediate channel layer 400 is induced into the channel layer 40. The above-mentioned process technology for forming the channel layer 40 is also the metal-induced lateral crystallization technology, which is beneficial to further improve the number of grains and defects of crystalline silicon. As described in the above embodiment, the channel layer 40 may include a first portion 41, a second portion 42, and a third portion 43, wherein the first intermediate portion 401 of the intermediate channel layer 400 may be induced into the first portion 41 of the channel layer 40, the second intermediate portion 402 of the intermediate channel layer 400 may be induced into the second portion 42 of the channel layer 40, and the third intermediate portion 403 of the intermediate channel layer 400 may be induced into the third portion 43 of the channel layer 40.

[0092] In the embodiment of the present application, after forming the channel layer 40, the method for preparing the semiconductor structure 1 further includes:

[0093] S4. Form a source electrode layer and a drain electrode layer; wherein the source electrode layer and the source contact layer constitute a source portion, the drain electrode layer and the drain contact layer constitute a drain portion, the source portion and the drain portion are located on one side of the gate layer, and the source portion and the drain portion are spaced apart, the source contact layer is located between the source electrode layer and the gate layer, and the drain contact layer is located between the drain electrode layer and the gate layer; the channel layer is located on one side of the gate layer, and at least part of the channel layer is located between the source portion and the drain portion; in a direction perpendicular to the gate layer, the source contact layer is uniformly distributed with first doped ions, and / or the drain contact layer is uniformly distributed with second doped ions.

[0094] Fig.21 FIG. 8 is a structural diagram after forming a first opening 81 and a second opening 82 in the method for preparing the semiconductor structure 1 according to an embodiment of the present application. Fig.21 , after forming the channel layer 40 and before forming the source electrode layer 23 and the drain electrode layer 24, further comprising: forming a photoresist layer 80, wherein the photoresist layer 80 has a first opening 81 and a second opening 82. Exemplarily, the photoresist layer 80 may be patterned by a patterning process to form the first opening 81 and the second opening 82, wherein the first opening 81 exposes at least a portion of the first sub-portion 421, and the second opening 82 exposes at least a portion of the second sub-portion 422.

[0095] Fig. 22 FIG. 2 is a structural diagram after forming a source electrode layer 23 and a drain electrode layer 24 in the method for preparing the semiconductor structure 1 in the embodiment of the present application. Fig. 22The step of forming the source electrode layer 23 and the drain electrode layer 24 may include: depositing a conductive material in the first opening 81 and the second opening 82, wherein the conductive material in the first opening 81 constitutes the source electrode layer 23, and the conductive material in the second opening 82 constitutes the drain electrode layer 24. Through the above arrangement, the material of the source electrode layer 23 and the drain electrode layer 24 are the same, for example, the material of the source electrode layer 23 and the drain electrode layer 24 may include a combination of one or more metals such as Pt, Ti, W, and Co. In addition, the source electrode layer 23 and the drain electrode layer 24 may be arranged in the same layer, which is beneficial to improving the preparation efficiency of the semiconductor structure 1.

[0096] In summary, the source electrode layer 23 and the source contact layer 21 constitute the source portion 210, the drain electrode layer 24 and the drain contact layer 22 constitute the drain portion 220, and the source portion 210 and the drain portion 220 are located on one side of the gate layer 10. Based on the above structure, the step of providing the gate layer 10 may further include: forming a gate dielectric layer 12, and the gate dielectric layer 12 is located on one side of the gate electrode layer 11 close to the source portion 210 and the drain portion 220.

[0097] Fig.23 FIG. 1 is a structural diagram of a semiconductor structure 1 after a conductive plug 70 is formed in the method for preparing the semiconductor structure 1 according to an embodiment of the present application. Fig.23 Further, after forming the source electrode layer 23 and the drain electrode layer 24, a corresponding conductive plug 70 may be formed. For example, the conductive plug 70 may include a gate plug 73, a source plug 71, and a drain plug 72. Exemplarily, the gate plug 73 may contact the gate electrode layer 11, the source plug 71 may contact the source electrode layer 23, and the drain plug 72 may contact the drain electrode layer 24.

[0098] In an embodiment of the present application, after forming the source electrode layer 23 and the drain electrode layer 24, the preparation method of the semiconductor structure 1 may further include: performing a heat treatment process so that the portion of the source contact layer 21 close to the source electrode layer 23 forms a metal silicide, and the portion of the drain contact layer 22 close to the drain electrode layer 24 also forms a metal silicide.

[0099] Another embodiment of the present application also provides a non-transitory computer-readable storage medium for use with a computer, the computer having software for creating and manufacturing the above-mentioned chip stacking structure, and one or more computer-readable data structures are stored on the computer-readable storage medium, and the one or more computer-readable data structures have control data for manufacturing the semiconductor stacking structure provided in any one of the diagrams provided above, such as mask layer data.

[0100] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that: include: Gate layer; A source portion and a drain portion, located on a first side of the gate layer, and the source portion and the drain portion are spaced apart, the source portion includes a source electrode layer and a source contact layer stacked, the source contact layer is located between the source electrode layer and the gate layer, the drain portion includes a drain electrode layer and a drain contact layer stacked, the drain contact layer is located between the drain electrode layer and the gate layer; A channel layer, located on a first side of the gate layer, and at least a portion of the channel layer is located between the source portion and the drain portion; Wherein, in a direction perpendicular to the gate layer, the first doping ions are uniformly distributed in the source contact layer, and / or the second doping ions are uniformly distributed in the drain contact layer.

2. The semiconductor structure according to claim 1, characterized in that: The channel layer includes a first part and a second part, the first part and the second part are connected, the first part is located between the source contact layer and the drain contact layer, and the second part is located on a side of the source contact layer and the drain contact layer away from the gate dielectric layer.

3. The semiconductor structure according to claim 2, characterized in that: The channel layer further includes a third portion connected to the second portion, and the third portion is located on a side of the source contact layer facing away from the drain contact layer and on a side of the drain contact layer facing away from the source contact layer.

4. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The material of the channel layer includes crystalline silicon.

5. The semiconductor structure according to any one of claims 1 to 4, characterized in that: The orthographic projection of the source electrode layer on the gate layer is located within the orthographic projection of the source contact layer on the gate layer, and / or the orthographic projection of the drain electrode layer on the gate layer is located within the orthographic projection of the drain contact layer on the gate layer.

6. The semiconductor structure according to any one of claims 1 to 5, characterized in that: The gate layer includes a gate electrode layer and a gate dielectric layer which are stacked, and the gate electrode layer is located on a side of the gate dielectric layer away from the source portion and the drain portion.

7. A method for preparing a semiconductor structure, characterized in that: include: providing a gate layer; forming a source contact layer and a drain contact layer; forming a channel layer; forming a source electrode layer and a drain electrode layer; The source electrode layer and the source contact layer constitute a source portion, the drain electrode layer and the drain contact layer constitute the drain portion, the source portion and the drain portion are located on one side of the gate layer, and the source portion and the drain portion are spaced apart, the source contact layer is located between the source electrode layer and the gate layer, and the drain contact layer is located between the drain electrode layer and the gate layer; the channel layer is located on one side of the gate layer, and at least part of the channel layer is located between the source portion and the drain portion; in a direction perpendicular to the gate layer, the source contact layer is uniformly distributed with first doped ions, and / or the drain contact layer is uniformly distributed with second doped ions.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that: The forming of the source contact layer and the drain contact layer comprises: A thin film deposition process is used to form an intermediate contact layer; A portion of the intermediate contact layer is removed to form the source contact layer and the drain contact layer.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that: The forming of the channel layer comprises: forming an intermediate channel layer, wherein the intermediate channel layer is located on a side of the source contact layer, the drain contact layer and the gate dielectric layer away from the substrate; The intermediate channel layer is induced to become the channel layer by using a metal induced lateral crystallization process.

10. The method for preparing a semiconductor structure according to any one of claims 7 to 9, characterized in that: The providing of the gate layer comprises: providing a gate electrode layer; A gate dielectric layer is formed, wherein the gate dielectric layer is located on a side of the gate electrode layer close to the source portion and the drain portion.

11. An electronic device, characterized in that: The invention comprises a circuit board and a semiconductor structure as claimed in any one of claims 1 to 6, wherein the semiconductor structure and the circuit board are electrically connected.

Images