Array substrate and display panel

Abstract

The invention discloses an array substrate and a display panel, the array substrate comprises a substrate, a first metal layer, a common electrode layer and a capacitance compensation block, and the first metal layer is arranged on one side of the substrate and comprises a first scanning line and a second scanning line; the common electrode layer is arranged on the side, away from the substrate, of the first metal layer, the common electrode layer comprises a plurality of region blocks arranged at intervals, the region blocks are reused as touch electrodes, and each region block comprises a plurality of common electrode rows arranged in the column direction and connecting parts for connecting every two adjacent common electrode rows; the capacitance compensation block is electrically connected to a region block; in a plane view of the array substrate, each first scanning line is located between every two adjacent common electrode rows of the same area block and partially overlaps with the corresponding connecting part; the second scanning lines are located between the two adjacent area blocks, and the capacitance compensation blocks and the second scanning lines are at least partially overlapped. The display effect can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] In-cell flat panel display technology with high resolution and excellent image quality is one of the key technologies in the industry. The touch screen reporting is achieved by graphicizing the common electrode layer into multiple area blocks. The pen / hand causes the capacitance change of the local area block. The adjacent area blocks are disconnected. One area block corresponds to multiple scan lines. The overlapping area between the area block and the corresponding scan line will affect the load of the corresponding scan line.

[0003] Among the multiple scan lines corresponding to a region block, the overlap area between the scan lines corresponding to the center of the region block and the region block is larger, while the overlap area between the scan lines corresponding to the edge of the region block and the region block is smaller. Therefore, the load of the scan lines corresponding to the center of the region block is greater than the load of the scan lines corresponding to the edge of the region block, causing horizontal stripes to appear on the display screen, affecting the display effect.

[0004] Therefore, it is necessary to propose a new technical solution to solve the above technical problems. Summary of the invention

[0005] The purpose of the present application is to provide an array substrate and a display panel to improve the display effect.

[0006] To solve the above problems, the technical solution of this application is as follows:

[0007] In a first aspect, the present application proposes an array substrate, comprising:

[0008] substrate;

[0009] A first metal layer, disposed on one side of the substrate, includes a first scanning line and a second scanning line;

[0010] a common electrode layer, disposed on a side of the first metal layer away from the substrate, the common electrode layer comprising a plurality of spaced-apart area blocks, the area blocks being reused as touch electrodes, the area blocks comprising a plurality of common electrode rows arranged along a column direction and a connecting portion connecting two adjacent common electrode rows; and

[0011] A capacitance compensation block, electrically connected to one of the area blocks;

[0012] In a plan view of the array substrate, the first scanning line is located between two adjacent common electrode rows in the same area block and partially overlaps with the connecting portion;

[0013] The second scan line is located between two adjacent area blocks, and the capacitance compensation block at least partially overlaps with the second scan line.

[0014] In an embodiment of the present application, the capacitance compensation block is disposed in the same layer as the area block, and is connected to an edge of one area block close to another area block.

[0015] In an embodiment of the present application, the capacitance compensation block and the common electrode row located at the edge of the area block are formed in one piece.

[0016] In an embodiment of the present application, the plurality of area blocks include a first area block and a second area block arranged at intervals along the column direction;

[0017] The first area block includes a first common electrode row, a second common electrode row and a first connecting portion, the second common electrode row is located on a side of the first common electrode row close to the second area block, and the first connecting portion connects the first common electrode row and the second common electrode row;

[0018] The second area block includes a third common electrode row, a fourth common electrode row, and a second connection portion, the fourth common electrode row is located on a side of the third common electrode row close to the first area block, and the second connection portion connects the third common electrode row and the third common electrode row;

[0019] In a plan view of the array substrate, one of the first scanning lines is located between the first common electrode row and the second common electrode row, and overlaps with the first connecting portion;

[0020] One of the first scanning lines is located between the third common electrode row and the fourth common electrode row, and partially overlaps with the second connecting portion;

[0021] A second scanning line is located between the second common electrode row and the fourth common electrode row, and at least partially overlaps with the capacitance compensation block;

[0022] Wherein, between two adjacent first area blocks and the second area blocks, the capacitance compensation block includes a first compensation block;

[0023] In the first area block, a side of the second common electrode row close to the fourth common electrode row is a first side;

[0024] In the second area block, a side of the fourth common electrode row close to the second common electrode row is a second side, and the first compensation block is connected to one of the first side and the second side;

[0025] In a plan view of the array substrate, the first compensation block at least partially overlaps with the second scan line.

[0026] In one embodiment of the present application, between two adjacent first area blocks and second area blocks, the capacitance compensation block further includes a second compensation block, the second compensation block is connected to the other side of the first side and the second side, and the second compensation block is spaced apart from the first compensation block;

[0027] In a plan view of the array substrate, the second compensation block at least partially overlaps with the second scan line.

[0028] In one embodiment of the present application, the second common electrode row includes a plurality of first sub-electrodes arranged along the row direction, and a side of each of the first sub-electrodes close to the fourth common electrode row is connected to the first compensation block;

[0029] The fourth common electrode row includes a plurality of second sub-electrodes arranged along the row direction, and a side of each second sub-electrode close to the second common electrode row is connected to the second compensation block.

[0030] In one embodiment of the present application, in a plan view of the array substrate, an overlapping area between the first compensation block and the second scan line is a first overlapping area, an overlapping area between the second compensation block and the second scan line is a second overlapping area, and the first overlapping area is equal to the second overlapping area.

[0031] In one embodiment of the present application, in a plan view of the array substrate, the second scan line is located on one side of the second common electrode row, the second scan line is spaced apart from the fourth common electrode row, and an area of ​​the first compensation block is smaller than an area of ​​the second compensation block.

[0032] In one embodiment of the present application, the common electrode row includes a plurality of sub-electrodes arranged along a row direction;

[0033] The array substrate further includes:

[0034] A plurality of pixel electrodes, wherein one pixel electrode is arranged corresponding to one sub-electrode;

[0035] a second metal layer, the second metal layer being disposed between the first metal layer and the common electrode layer, the second metal layer comprising a plurality of data lines, the data lines extending along the column direction, and the plurality of data lines being arranged along the row direction;

[0036] In the planar view of the array substrate, a column of pixel electrodes is provided between two adjacent data lines; in a column of pixel electrodes, the pixel electrodes in odd rows are electrically connected to one of the two adjacent data lines, and the pixel electrodes in even rows are electrically connected to the other of the two adjacent data lines.

[0037] In one embodiment of the present application, the first metal layer further includes:

[0038] A first gate connected to the first scanning line, wherein the first gate is correspondingly provided with one of the pixel electrodes;

[0039] a third compensation block connected to the first scanning line and located at one side of the first gate;

[0040] A second gate connected to the second scanning line, the second gate being provided with one of the pixel electrodes corresponding thereto; and

[0041] a fourth compensation block connected to the second scan line and located at one side of the second gate;

[0042] In the same area block, the connecting portion and the adjacent third compensation block form a first capacitor, and the capacitor compensation block and the adjacent fourth compensation block form a second capacitor.

[0043] In one embodiment of the present application, the second metal layer further includes:

[0044] a first drain electrode, arranged corresponding to the first gate electrode, the first drain electrode being electrically connected to the pixel electrode corresponding to the first gate electrode;

[0045] a second drain electrode, arranged corresponding to the second gate electrode, the second drain electrode being electrically connected to the pixel electrode corresponding to the second gate electrode;

[0046] In a plan view of the array substrate, the third compensation block, the first drain, and the pixel electrode corresponding to the first drain overlap, and the fourth compensation block, the second drain, and the pixel electrode corresponding to the second drain overlap.

[0047] In one embodiment of the present application, the common electrode row includes a plurality of sub-electrodes arranged along a row direction;

[0048] The array substrate further includes:

[0049] A plurality of pixel electrodes, wherein one pixel electrode is arranged corresponding to one sub-electrode;

[0050] a second metal layer, the second metal layer being disposed between the first metal layer and the common electrode layer, the second metal layer comprising a plurality of data lines, the data lines extending along the column direction, and the plurality of data lines being arranged along the row direction;

[0051] In a plan view of the array substrate, one data line is correspondingly arranged at one side of a plurality of pixel electrodes in a same column, and the plurality of pixel electrodes in a same column are electrically connected to the corresponding data line.

[0052] In the second aspect, the present application proposes a display panel, including an array substrate, the array substrate including a substrate, a first metal layer, a common electrode layer and a capacitor compensation block, the first metal layer is arranged on one side of the substrate, including a first scan line and a second scan line; the common electrode layer is arranged on a side of the first metal layer away from the substrate, the common electrode layer includes a plurality of spaced-apart area blocks, the area blocks are reused as touch electrodes, the area blocks include a plurality of common electrode rows arranged along a column direction and a connecting portion connecting two adjacent common electrode rows; the capacitor compensation block is electrically connected to one of the area blocks; in a plan view of the array substrate, the first scan line is located between two adjacent common electrode rows in the same area block and partially overlaps with the connecting portion; the second scan line is located between two adjacent area blocks, and the capacitor compensation block at least partially overlaps with the second scan line.

[0053] In the present application, a capacitor compensation block is arranged between two adjacent area blocks, and the capacitor compensation block is overlapped with at least part of the second scan line. Since the load of the second scan line increases after the second scan line overlaps with the capacitor compensation block, the difference between the load of the first scan line corresponding to the center of the area block and the load of the second scan line corresponding to the edge of the area block in the same area block is reduced, and the influence of the horizontal stripes on the display effect is weakened, thereby improving the display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 is a plan view of the array substrate of the present application;

[0055] Figure 2 yes Figure 1 The enlarged view of point A in the middle;

[0056] Figure 3 yes Figure 2 The enlarged view of point B in the middle;

[0057] Figure 4 is a schematic diagram of an array substrate of a column inversion architecture of the present application;

[0058] Figure 5 is a schematic diagram of an array substrate of a dot inversion structure of the present application;

[0059] Figure 6 is a schematic diagram of an embodiment of a first scan line and a common electrode row of a dot inversion structure of the present application;

[0060] Figure 7 It is a schematic diagram of an embodiment of a second scan line and a common electrode row of the dot inversion structure of the present application;

[0061] Figure 8 yes Figure 2 An enlarged view of an embodiment at C in the middle;

[0062] Fig. 9 yes Figure 2 An enlarged view of another embodiment at C in the middle;

[0063] Fig.10 yes Figure 2 An enlarged view of another embodiment at C in the middle. DETAILED DESCRIPTION

[0064] The meanings of the terms used in this specification and claims correspond to the meanings commonly understood by those of ordinary skill in the art to which this application belongs. The terms used in this specification and claims are only for the purpose of facilitating the description and understanding of this application, and are not intended to limit this application to the narrow interpretation of the specific terms used in the specification and claims.

[0065] The present application proposes a display panel, which can be applied to tablet computers, e-readers, electronic display screens, laptop computers, mobile phones, augmented reality (AR) and virtual reality (VR) devices, media players, wearable devices, digital cameras, car navigation systems, etc.

[0066] Optionally, the display panel is a liquid crystal display panel (LCD). The embodiment of the present application is described by taking a liquid crystal display panel as an example, and the display panel includes an array substrate 100 .

[0067] See also Figure 1The present application proposes an array substrate 100, comprising a substrate 10, a first metal layer 20, a common electrode layer 30 and a capacitance compensation block 40. The first metal layer 20 is disposed on one side of the substrate 10, and comprises a first scan line 21 and a second scan line 22. The common electrode layer 30 is disposed on a side of the first metal layer 20 away from the substrate 10. The common electrode layer 30 comprises a plurality of spaced-apart area blocks 31. The area blocks 31 are reused as touch electrodes. The area blocks 31 comprise a plurality of common electrode rows 32 arranged along a column direction and a connecting portion 33 connecting two adjacent common electrode rows 32. The capacitance compensation block 40 is electrically connected to an area block 31.

[0068] See also Figure 2 In the plan view of the array substrate 100, the first scan line 21 is located between two adjacent common electrode rows 32 of the same area block 31 and partially overlaps with the connecting portion 33. The second scan line 22 is located between two adjacent area blocks 31. The capacitance compensation block 40 at least partially overlaps with the second scan line 22.

[0069] In the present application, a capacitor compensation block 40 is arranged between two adjacent area blocks 31, and the capacitor compensation block 40 overlaps at least part of the second scan line 22. Since the second scan line 22 overlaps with the capacitor compensation block 40, the load of the second scan line 22 increases, thereby reducing the difference between the load of the first scan line 21 corresponding to the center of the area block 31 and the load of the second scan line 22 corresponding to the edge of the area block 31 in the same area block 31, reducing the influence of the horizontal stripes on the display effect, thereby improving the display effect.

[0070] Optionally, the substrate 10 is a flexible substrate 10, and the material of the substrate 10 is polyimide.

[0071] Optionally, the substrate 10 is a hard substrate 10, and the material of the substrate 10 is glass.

[0072] Optionally, the array substrate 100 further includes a plurality of touch lines 62. One touch line 62 is electrically connected to one area block 31, and the touch line 62 is electrically connected to a chip disposed in the non-display area. The touch line 62 may be disposed between the substrate 10 and the first metal layer 20, or the touch line 62 may be disposed in the same layer as the second metal layer 60, and the location of the touch line 62 is not limited here.

[0073] Optionally, the capacitor compensation block 40 is arranged in a different layer from the regional block 31. Optionally, the capacitor compensation block 40 is arranged between the common electrode layer 30 and the first metal layer 20, which can further increase the capacitance formed by the capacitor compensation block 40 and the second scan line 22, thereby increasing the load of the second scan line 22, and further reducing the load difference between the first scan line 21 and the second scan line 22, further reducing the influence of the horizontal stripes on the display effect, thereby improving the display effect.

[0074] See also Figure 3 Optionally, the capacitor compensation block 40 and the regional block 31 are arranged in the same layer, and connected to the edge of one regional block 31 near the other regional block 31. Compared with the embodiment in which the capacitor compensation block 40 and the regional block 31 are arranged in different layers, this embodiment can reduce a step of forming the film layer where the capacitor compensation block 40 is located separately, and the capacitor compensation block 40 and the regional block 31 are formed by a one-step process, thereby improving production efficiency and reducing production costs.

[0075] See also Figure 3 Optionally, the capacitor compensation block 40 is integrally formed with the common electrode row 32 located at the edge of the regional block 31. In this embodiment, the material of the capacitor compensation block 40 is the same as that of the regional block 31. In the process of patterning the regional block 31, the capacitor compensation block 40 can be formed simultaneously, thereby further improving production efficiency and reducing production costs.

[0076] Optionally, the common electrode row 32 includes a plurality of sub-electrodes 34 arranged along the row direction.

[0077] See also Figure 4 Optionally, the array substrate 100 is an array substrate 100 of a stripe structure. The array substrate 100 of the stripe structure further includes a plurality of pixel electrodes 50 and a second metal layer 60. One pixel electrode 50 is arranged corresponding to one sub-electrode 34. The second metal layer 60 is arranged between the first metal layer 20 and the common electrode layer 30. The second metal layer 60 includes a plurality of data lines 61. The data lines 61 extend in the column direction. The plurality of data lines 61 are arranged in the row direction.

[0078] In a plan view of the array substrate 100 with a column inversion structure, a data line 61 is correspondingly disposed at one side of a plurality of pixel electrodes 50 in the same column, and the plurality of pixel electrodes 50 in the same column are electrically connected to the corresponding data line 61 .

[0079] In the array substrate 100 of the column inversion architecture, a plurality of sub-pixels are included. A sub-pixel includes a sub-electrode 34 and a pixel electrode 50 arranged corresponding to the sub-electrode 34. In the column inversion architecture, the pixels are arranged in a column-inverted manner, that is, the sub-pixels of adjacent columns will alternately display different colors when displayed to reduce visual afterimages and improve display quality. In the column inversion architecture, the pixels are arranged in columns, which means that the pixels in the same column share the same data line 61. This arrangement helps to reduce the number of data lines 61, thereby reducing cost and complexity. Since the data lines 61 are shared in columns, the pixels in the same column are driven at the same time. This driving method can increase the refresh rate because only the data of one column of pixels needs to be processed at the same time. The capacitor compensation block 40 is provided in the column inversion architecture, which can reduce the load difference between the first scanning line 21 and the second scanning line 22 corresponding to the single area block 31, reduce the influence of the horizontal stripes on the display effect, and thus improve the display effect.

[0080] See also Figure 5 Optionally, the array substrate 100 is an array substrate 100 of a dot flip architecture. The array substrate 100 of the dot flip architecture further includes a plurality of pixel electrodes 50 and a second metal layer 60. One pixel electrode 50 is arranged corresponding to one sub-electrode 34. The second metal layer 60 is arranged between the first metal layer 20 and the common electrode layer 30. The second metal layer 60 includes a plurality of data lines 61. The data lines 61 extend in the column direction. The plurality of data lines 61 are arranged in the row direction.

[0081] In the plan view of the array substrate 100 of the dot inversion architecture, a column of the pixel electrodes 50 is disposed between two adjacent data lines 61. In a column of the pixel electrodes 50, the pixel electrodes 50 in odd-numbered rows are electrically connected to one of the two adjacent data lines 61, and the pixel electrodes 50 in even-numbered rows are electrically connected to the other of the two adjacent data lines 61.

[0082] In the array substrate 100 of the dot inversion architecture, a plurality of sub-pixels are included. A sub-pixel includes a sub-electrode 34 and a pixel electrode 50 arranged corresponding to the sub-electrode 34. In the array substrate 100 of the dot inversion architecture, the pixels are arranged in a dot inversion manner, which means that each pixel point has a different color from its adjacent pixel points, thereby reducing visual afterimages and improving display quality. In the array substrate 100 of the dot inversion architecture, a data line 61 can simultaneously drive pixels of two colors in two adjacent columns, and this design helps to simplify the driving circuit.

[0083] Optionally, in the array substrate 100 of the dot inversion architecture, the first metal layer 20 further includes a first gate 23, a third compensation block 24, a second gate 25 and a fourth compensation block 26. The first gate 23 is connected to the first scan line 21. A pixel electrode 50 is provided corresponding to the first gate 23. The third compensation block 24 is connected to the first scan line 21 and is located on one side of the first gate 23. The second gate 25 is connected to the second scan line 22. A pixel electrode 50 is provided corresponding to the second gate 25. The fourth compensation block 26 is connected to the second scan line 22 and is located on one side of the second gate 25. In the same area block 31, the connecting portion 33 forms a first capacitor with the adjacent third compensation block 24, and the capacitor compensation block 40 forms a second capacitor with the adjacent fourth compensation block 26.

[0084] In a conventional array substrate of a dot inversion structure, since the conventional array substrate of a dot inversion structure has the characteristic of non-repetitive design of adjacent odd-numbered sub-pixels and even-numbered sub-pixels, in the manufacturing process of the conventional array substrate of a dot inversion structure, when the second metal layer 60 is offset relative to the first metal layer 20, the compensation capacitance of the even-numbered sub-pixels and the odd-numbered sub-pixels will be different. To solve this problem, please refer to Figure 6 , the third compensation block 24 is connected to the first scan line 21, and the fourth compensation block 26 is connected to the second scan line 22. When the second metal layer 60 is offset relative to the first metal layer 20, the difference in compensation capacitance between the even-numbered sub-pixels and the odd-numbered sub-pixels can be reduced. However, since the third compensation block 24 is provided on the first scan line 21, the third compensation block 24 forms a first capacitor with the connecting portion 33. While the fourth compensation block 26 is provided on the second scan line 22, the second scan line 22 cannot form a capacitor with the connecting portion 33, resulting in a further increase in the load difference between the first scan line 21 in the center of the area block 31 and the second scan line 22 in the edge of the area block 31.

[0085] See also Figure 7 In this embodiment, a capacitor compensation block 40 is provided at the edge of the area block 31, and the capacitor compensation block 40 and the fourth compensation block 26 form a second capacitor. Due to the formation of the second capacitor, the load difference between the first scan line 21 and the second scan line 22 can be reduced, and the influence of the horizontal stripes on the display effect can be weakened, thereby improving the display effect.

[0086] Optionally, the capacitance value of the second capacitor is greater than the capacitance value of the first capacitor, thereby further reducing the load difference between the first scan line 21 and the second scan line 22, weakening the influence of the horizontal stripes on the display effect, and thus improving the display effect.

[0087] Optionally, in the array substrate 100 of the dot inversion architecture, the second metal layer 60 further includes a first drain electrode 63 and a second drain electrode 64. The first drain electrode 63 is arranged corresponding to the first gate electrode 23. The first drain electrode 63 is electrically connected to the pixel electrode 50 corresponding to the first gate electrode 23. The second drain electrode 64 is arranged corresponding to the second gate electrode 25. The second drain electrode 64 is electrically connected to the pixel electrode 50 corresponding to the second gate electrode 25.

[0088] In the plan view of the array substrate 100 of the dot inversion structure, the third compensation block 24, the first drain 63 and the pixel electrode 50 corresponding to the first drain 63 overlap. The fourth compensation block 26, the second drain 64 and the pixel electrode 50 corresponding to the second drain 64 overlap.

[0089] In a conventional array substrate of a dot inversion structure, when the second metal layer 60 is offset relative to the first metal layer 20, the compensation capacitance of the even-numbered sub-pixels and the odd-numbered sub-pixels will be different. In this embodiment, by providing a third compensation block 24 and a fourth compensation block 26, and making the third compensation block 24 overlap with the first drain 63 and the pixel electrode 50, and the fourth compensation block 26 overlap with the second drain 64 and the pixel electrode 50, the difference in compensation capacitance between the even-numbered sub-pixels and the odd-numbered sub-pixels is reduced, thereby improving the display effect of the array substrate 100 of the dot inversion structure.

[0090] Optionally, in the array substrate 100 of the dot inversion architecture, the array substrate 100 further includes a semiconductor layer, and the semiconductor layer is located between the second metal layer 60 and the first metal layer 20. The semiconductor layer includes a first active layer 71 and a second active layer 72. The first active layer 71 overlaps with the first gate electrode 23, a portion of the first drain electrode 63 overlaps with the first active layer 71, a portion of the data line 61 corresponding to the first drain electrode 63 overlaps with the first active layer 71, and the portion of the data line 61 is reused as a source electrode. The second active layer 72 overlaps with the second gate electrode 25, a portion of the second drain electrode 64 overlaps with the second active layer 72, a portion of the data line 61 corresponding to the second drain electrode 64 overlaps with the second active layer 72, and the portion of the data line 61 is reused as a source electrode.

[0091] See also Figure 8 , in the first embodiment of the present application:

[0092] Optionally, the plurality of region blocks 31 include first region blocks 31 a and second region blocks 31 b that are spaced apart along a column direction.

[0093] The first area block 31a includes a first common electrode row, a second common electrode row 32a and a first connection portion 33. The second common electrode row 32a is located on a side of the first common electrode row close to the second area block 31b. The first connection portion 33 connects the first common electrode row and the second common electrode row 32a.

[0094] The second area block 31b includes a third common electrode row, a fourth common electrode row 32b and a second connection portion 33. The fourth common electrode row 32b is located on a side of the third common electrode row close to the first area block 31a. The second connection portion 33 connects the third common electrode row and the third common electrode row.

[0095] In a plan view of the array substrate 100 , a first scan line 21 is located between the first common electrode row and the second common electrode row 32 a and overlaps with the first connection portion 33 .

[0096] A first scan line 21 is located between the third common electrode row and the fourth common electrode row 32 b and partially overlaps with the second connection portion 33 .

[0097] A second scan line 22 is located between the second common electrode row 32 a and the fourth common electrode row 32 b and at least partially overlaps with the capacitance compensation block 40 .

[0098] The capacitance compensation block 40 includes a first compensation block 41 between two adjacent first area blocks 31 a and second area blocks 31 b .

[0099] In the first area block 31 a , a side of the second common electrode row 32 a close to the fourth common electrode row 32 b is a first side.

[0100] In the second area block 31b, a side of the fourth common electrode row 32b close to the second common electrode row 32a is the second side. The first compensation block 41 is connected to the first side.

[0101] In a plan view of the array substrate 100 , the first compensation block 41 at least partially overlaps with the second scan line 22 .

[0102] In the first embodiment of the present application, between two adjacent first area blocks 31a and second area blocks 31b, the first compensation block 41 is connected to the side of the second common electrode row 32a close to the fourth common electrode row 32b, and the first compensation block 41 at least partially overlaps with the second scan line 22, which can increase the load of the second scan line 22, thereby reducing the load difference between the first scan line 21 and the second scan line 22 caused by the overlap of the first scan line 21 with the connecting portion 33, weakening the influence of the horizontal stripes on the display effect, thereby improving the display effect.

[0103] See also Fig. 9 , in the second embodiment of the present application:

[0104] In order to avoid redundancy, the second embodiment of the present application will describe parts different from the first embodiment of the present application.

[0105] The second embodiment of the present application is different from the first embodiment of the present application in that:

[0106] Optionally, the first compensation block 41 is connected to the second side.

[0107] In the second embodiment of the present application, between two adjacent first area blocks 31a and second area blocks 31b, the first compensation block 41 is connected to the side of the fourth common electrode row 32b close to the second common electrode row 32a, and the first compensation block 41 at least partially overlaps with the second scan line 22, which can increase the load of the second scan line 22, thereby reducing the load difference between the first scan line 21 and the second scan line 22 caused by the overlap of the first scan line 21 with the connecting portion 33, weakening the influence of the horizontal stripes on the display effect, thereby improving the display effect.

[0108] See also Fig.10 , in the third embodiment of the present application:

[0109] In order to avoid redundancy, the third embodiment of the present application will describe parts different from those of the first embodiment of the present application.

[0110] The third embodiment of the present application is different from the first embodiment of the present application in that:

[0111] Optionally, between two adjacent first area blocks 31a and second area blocks 31b, the capacitance compensation block 40 further includes a second compensation block 42. The second compensation block 42 is connected to the other side of the first side and the second side, and is spaced apart from the first compensation block 41.

[0112] In a plan view of the array substrate 100 , the second compensation block 42 at least partially overlaps with the second scan line 22 .

[0113] In the third embodiment of the present application, between two adjacent first area blocks 31a and second area blocks 31b, the second compensation block 42 is connected to the side of the fourth common electrode row 32b close to the second common electrode row 32a, and the second compensation block 42 at least partially overlaps with the second scan line 22. On the basis of the first embodiment, the load of the second scan line 22 can be further increased, thereby further reducing the load difference between the first scan line 21 and the second scan line 22 caused by the overlap of the first scan line 21 with the connecting portion 33, further weakening the influence of the horizontal stripes on the display effect, thereby further improving the display effect.

[0114] Optionally, between two adjacent first area blocks 31 a and second area blocks 31 b , a first compensation block 41 connected to the first area block 31 a is insulated from a second compensation block 42 connected to the second area block 31 b .

[0115] Optionally, the second common electrode row 32a includes a plurality of first sub-electrodes 34a arranged along the row direction. A first compensation block 41 is connected to a side of each first sub-electrode 34a close to the fourth common electrode row 32b.

[0116] The fourth common electrode row 32b includes a plurality of second sub-electrodes 34b arranged along the row direction. A second compensation block 42 is connected to a side of each second sub-electrode 34b close to the second common electrode row 32a.

[0117] In this embodiment, in the first area block 31a, the first common electrode row includes a plurality of sub-electrodes 34 arranged along the row direction, wherein the sub-electrodes 34 of the first common electrode row are connected to the first sub-electrodes 34a of the second common electrode row 32a adjacent to the first common electrode row 32a along the column direction via a connecting portion 33. Therefore, a first scanning line 21 located between the first common electrode row and the second common electrode row 32a overlaps with the plurality of connecting portions 33, resulting in the formation of capacitance between the first scanning line 21 and the plurality of connecting portions 33, so that the load of the first scanning line 21 is relatively large. In this embodiment, a first compensation block 41 is connected to a side of each first sub-electrode 34a close to the fourth common electrode row 32b, so that a plurality of first compensation blocks 41 are connected to a side of the second common electrode row 32a close to the fourth common electrode row 32b, so that a second scan line 22 located between the second common electrode row 32a and the fourth common electrode row 32b overlaps with the plurality of first compensation blocks 41, and the plurality of first compensation blocks 41 form a capacitor with the second scan line 22, thereby increasing the load of the second scan line 22 and reducing the load difference between the first scan line 21 and the second scan line 22, thereby weakening the influence of the horizontal stripes on the display effect, thereby improving the display effect.

[0118] Similarly, in the second area block 31b, the third common electrode row includes a plurality of sub-electrodes 34 arranged along the row direction, wherein the sub-electrodes 34 of the third common electrode row are connected to the second sub-electrodes 34b of the fourth common electrode row 32b adjacent to the third common electrode row 32b along the column direction via a connecting portion 33. Therefore, a first scan line 21 located between the third common electrode row and the fourth common electrode row 32b overlaps with the plurality of connecting portions 33, resulting in the formation of capacitance between the first scan line 21 and the plurality of connecting portions 33, so that the load of the first scan line 21 is relatively large. In this embodiment, a second compensation block 42 is connected to a side of each second sub-electrode 34b close to the second common electrode row 32a, so that a plurality of second compensation blocks 42 are connected to a side of the fourth common electrode row 32b close to the second common electrode row 32a, so that a second scan line 22 located between the second common electrode row 32a and the fourth common electrode row 32b overlaps with the plurality of second compensation blocks 42, and the plurality of second compensation blocks 42 form a capacitor with the second scan line 22, thereby further increasing the load of the second scan line 22, and further reducing the load difference between the first scan line 21 and the second scan line 22, further weakening the influence of the horizontal stripes on the display effect, thereby further improving the display effect.

[0119] Optionally, in the plan view of the array substrate 100, the overlapping area between the first compensation block 41 and the second scan line 22 is the first overlapping area, the overlapping area between the second compensation block 42 and the second scan line 22 is the second overlapping area, and the first overlapping area is equal to the second overlapping area.

[0120] In this embodiment, since the first overlapping area is equal to the second overlapping area, the capacitance formed by the first compensation block 41 and the second scan line 22 can be made the same as the capacitance formed by the second compensation block 42 and the second scan line 22, thereby avoiding the capacitance difference between adjacent area blocks 31, resulting in a difference in the recovery time of the area block 31 after the touch ends, causing display abnormality, and improving the display effect.

[0121] Optionally, in the plan view of the array substrate 100 , the second scan line 22 is located at one side of the second common electrode row 32 a . The second scan line 22 is spaced apart from the fourth common electrode row 32 b . The area of ​​the first compensation block 41 is smaller than that of the second compensation block 42 .

[0122] In this embodiment, in the plan view of the array substrate 100, since the second scan line 22 is located on one side of the second common electrode row 32a, the first compensation block 41 connected to the second common electrode row 32a near the fourth common electrode row 32b can directly overlap with the second scan line 22 and have a first overlapping area. Since the second scan line 22 and the fourth common electrode row 32b are arranged at intervals, the second compensation block 42 needs to extend a distance along the column direction and cross the interval between the second scan line 22 and the fourth common electrode row 32b before overlapping with the second scan line 22 and forming a second overlapping area. Since the second compensation block 42 needs to cross the interval between the second scan line 22 and the fourth common electrode row 32b, the effective area of ​​the second compensation block 42 needs to be larger than the effective area of ​​the first compensation block 41.

[0123] The above is a detailed description of the specific implementation of the present application. The above implementation disclosed in the present application is only the preferred implementation of the present application. For ordinary technicians in this field, many modifications and improvements can be made without departing from the concept of the present application. These modifications and improvements all fall within the scope of protection defined by the claims of the present application.

Claims

1. An array substrate, characterized in that: include: substrate; A first metal layer, disposed on one side of the substrate, includes a first scanning line and a second scanning line; a common electrode layer, disposed on a side of the first metal layer away from the substrate, the common electrode layer comprising a plurality of spaced-apart area blocks, the area blocks being reused as touch electrodes, the area blocks comprising a plurality of common electrode rows arranged along a column direction and a connecting portion connecting two adjacent common electrode rows; and A capacitance compensation block, electrically connected to one of the area blocks; In a plan view of the array substrate, the first scanning line is located between two adjacent common electrode rows in the same area block and partially overlaps with the connecting portion; The second scan line is located between two adjacent area blocks, and the capacitance compensation block at least partially overlaps with the second scan line.

2. The array substrate according to claim 1, characterized in that: The capacitance compensation block is arranged in the same layer as the area block, and is connected to an edge of one area block close to another area block.

3. The array substrate according to claim 2, characterized in that: The capacitance compensation block is formed integrally with the common electrode row located at the edge of the area block.

4. The array substrate according to claim 2, characterized in that: The plurality of area blocks include a first area block and a second area block arranged at intervals along the column direction; The first area block includes a first common electrode row, a second common electrode row and a first connecting portion, the second common electrode row is located on a side of the first common electrode row close to the second area block, and the first connecting portion connects the first common electrode row and the second common electrode row; The second area block includes a third common electrode row, a fourth common electrode row, and a second connection portion, the fourth common electrode row is located on a side of the third common electrode row close to the first area block, and the second connection portion connects the third common electrode row and the third common electrode row; In a plan view of the array substrate, one of the first scanning lines is located between the first common electrode row and the second common electrode row, and overlaps with the first connecting portion; One of the first scanning lines is located between the third common electrode row and the fourth common electrode row, and partially overlaps with the second connecting portion; A second scanning line is located between the second common electrode row and the fourth common electrode row, and at least partially overlaps with the capacitance compensation block; Wherein, between two adjacent first area blocks and the second area blocks, the capacitance compensation block includes a first compensation block; In the first area block, a side of the second common electrode row close to the fourth common electrode row is a first side; In the second area block, a side of the fourth common electrode row close to the second common electrode row is a second side, and the first compensation block is connected to one of the first side and the second side; In a plan view of the array substrate, the first compensation block at least partially overlaps with the second scan line.

5. The array substrate according to claim 4, characterized in that: Between two adjacent first area blocks and second area blocks, the capacitance compensation block further includes a second compensation block, the second compensation block is connected to the other side of the first side and the second side, and the second compensation block is spaced apart from the first compensation block; In a plan view of the array substrate, the second compensation block at least partially overlaps with the second scan line.

6. The array substrate according to claim 5, characterized in that: The second common electrode row includes a plurality of first sub-electrodes arranged along the row direction, and a side of each of the first sub-electrodes close to the fourth common electrode row is connected to the first compensation block; The fourth common electrode row includes a plurality of second sub-electrodes arranged along the row direction, and a side of each second sub-electrode close to the second common electrode row is connected to the second compensation block.

7. The array substrate according to claim 6, characterized in that: In a plan view of the array substrate, an overlapping area between the first compensation block and the second scan line is a first overlapping area, an overlapping area between the second compensation block and the second scan line is a second overlapping area, and the first overlapping area is equal to the second overlapping area.

8. The array substrate according to claim 7, characterized in that: In a plan view of the array substrate, the second scan line is located at one side of the second common electrode row, the second scan line is spaced apart from the fourth common electrode row, and an area of ​​the first compensation block is smaller than an area of ​​the second compensation block.

9. The array substrate according to claim 1, wherein: The common electrode row includes a plurality of sub-electrodes arranged along the row direction; The array substrate further includes: A plurality of pixel electrodes, wherein one pixel electrode is arranged corresponding to one sub-electrode; a second metal layer, the second metal layer being disposed between the first metal layer and the common electrode layer, the second metal layer comprising a plurality of data lines, the data lines extending along the column direction, and the plurality of data lines being arranged along the row direction; In the planar view of the array substrate, a column of pixel electrodes is provided between two adjacent data lines; in a column of pixel electrodes, the pixel electrodes in odd rows are electrically connected to one of the two adjacent data lines, and the pixel electrodes in even rows are electrically connected to the other of the two adjacent data lines.

10. The array substrate according to claim 9, characterized in that: The first metal layer further comprises: A first gate connected to the first scanning line, wherein the first gate is correspondingly provided with one of the pixel electrodes; a third compensation block connected to the first scanning line and located at one side of the first gate; A second gate connected to the second scanning line, the second gate being provided with one of the pixel electrodes corresponding thereto; and a fourth compensation block connected to the second scan line and located at one side of the second gate; In the same area block, the connecting portion and the adjacent third compensation block form a first capacitor, and the capacitor compensation block and the adjacent fourth compensation block form a second capacitor.

11. The array substrate according to claim 10, characterized in that: The second metal layer further includes: a first drain electrode, arranged corresponding to the first gate electrode, the first drain electrode being electrically connected to the pixel electrode corresponding to the first gate electrode; a second drain electrode, arranged corresponding to the second gate electrode, the second drain electrode being electrically connected to the pixel electrode corresponding to the second gate electrode; In a plan view of the array substrate, the third compensation block, the first drain, and the pixel electrode corresponding to the first drain overlap, and the fourth compensation block, the second drain, and the pixel electrode corresponding to the second drain overlap.

12. The array substrate according to claim 1, wherein: The common electrode row includes a plurality of sub-electrodes arranged along the row direction; The array substrate further includes: A plurality of pixel electrodes, wherein one pixel electrode is arranged corresponding to one sub-electrode; a second metal layer, the second metal layer being disposed between the first metal layer and the common electrode layer, the second metal layer comprising a plurality of data lines, the data lines extending along the column direction, and the plurality of data lines being arranged along the row direction; In a plan view of the array substrate, one data line is correspondingly arranged at one side of a plurality of pixel electrodes in a same column, and the plurality of pixel electrodes in a same column are electrically connected to the corresponding data line.

13. A display panel, characterized in that: It comprises an array substrate as described in any one of claims 1 to 12.

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