Solar cell and photovoltaic module

Abstract

The invention discloses a solar cell, comprising a substrate having a first surface and a second surface arranged oppositely; first doped regions are arranged in the substrate and are regions close to the first surface, second semiconductor material layers are stacked on the first surface of the substrate, and the first doped regions and the second semiconductor material layers are alternately arranged; a spacer region is arranged between the second semiconductor material layer and the first doped region; the doping type of the second semiconductor material layer is opposite to that of the first doped region; the second semiconductor material layer comprises an ultrathin material layer and a second silicon-containing doped layer which are stacked in sequence; the surface of one side, far away from the second silicon-containing doping layer, of the ultrathin material layer is laminated with the substrate; the first doped region comprises a co-doped region; the co-doped region is connected with a partial region of the second silicon-containing doped layer; the first electrode is in contact and electric connection with the first doped region; and the second electrode is in contact and electrical connection with the second silicon-containing doping layer.

Description

Technical Field

[0001] The present application relates to the technical field of solar cells, and in particular to a solar cell and a photovoltaic module. Background Art

[0002] Improving photoelectric conversion efficiency and reducing production costs are the eternal goals of solar cell mass production, aiming to reduce the cost per kilowatt-hour of photovoltaic power generation. At present, conventional back-contact cells usually use multi-busbar technology or improved busbar-free technology. In order to prevent the hot spot phenomenon from affecting the overall efficiency of the battery module, the p-region and n-region are often overlapped in local areas of the battery structure, but the overlap area is more serious and the manufacturing cost is high. In addition, there is a large gap between the properties of P-poly and N-poly, and the requirements for metallization are more stringent. It is often necessary to use metal paste with a high silver content, which further increases the cost of battery manufacturing. Summary of the invention

[0003] In response to the above problems, the present application proposes a solar cell. Since the solar cell has a co-doped region between the first doped region and the second doped region, the first doped region is connected to a partial area of ​​the second silicon-containing doped layer, thereby forming a channel with a large forward resistance and a small reverse resistance, thereby separating the reverse current and achieving the effect of preventing hot spots. At the same time, the forward resistance is large and the efficiency loss of the battery is small.

[0004] The present application provides a solar cell, comprising a substrate, wherein the substrate has a first surface and a second surface arranged opposite to each other;

[0005] A first doped region is provided in the substrate and is a region close to the first surface,

[0006] A second semiconductor material layer is stacked on the first surface of the substrate, the first doped regions and the second semiconductor material layer are arranged alternately; and a spacing region is provided between the second semiconductor material layer and the first doped regions;

[0007] The doping type of the second semiconductor material layer is opposite to the doping type of the first doping region;

[0008] The second semiconductor material layer comprises an ultra-thin material layer and a second silicon-containing doped layer stacked in sequence; a surface of the ultra-thin material layer away from the second silicon-containing doped layer is stacked with the substrate;

[0009] The first doped region includes a co-doped region; the co-doped region is connected to a portion of the second silicon-containing doped layer;

[0010] A first electrode, the first electrode is in contact and electrically connected with the first doping region; and

[0011] A second electrode is in contact and electrically connected with the second silicon-containing doped layer.

[0012] Furthermore, in the first doping region, the co-doping region is located in a region close to a side of the second silicon-containing doping layer.

[0013] Along the direction in which the first doped regions and the second silicon-containing doped layers alternate, a width L1 of the co-doped regions is 0.02 μm-1 μm; or

[0014] Along the extending direction of the first doping region, the length L2 of the co-doping region is 10 μm-500 μm.

[0015] Furthermore, the first surface of the substrate corresponding to the first doped region is higher than the first surface of the substrate corresponding to the second silicon-containing doped layer, and the height difference between the first surface of the substrate corresponding to the first doped region and the first surface of the substrate corresponding to the second silicon-containing doped layer is 0.1-8μm.

[0016] Further, a sidewall of the substrate on a side of the first doped region facing the second semiconductor material layer is a first sidewall, and the co-doped layer includes at least a partial region of the first sidewall.

[0017] Furthermore, an oxide layer and a second silicon-containing doped layer are sequentially stacked on a partial area of ​​the first surface of the substrate corresponding to the first doped region.

[0018] A partial area of ​​the oxide layer covers the co-doped region.

[0019] Furthermore, the second silicon-doped layer has an overlapping portion.

[0020] The overlapping portion of the second silicon-containing doped layer extends from the first sidewall of the substrate to the top of the oxide layer; or

[0021] The overlapping portion of the second silicon-containing doped layer extends from the first side wall of the substrate to the top of the oxide layer and the side surface thereof until it directly contacts the first doped region.

[0022] Furthermore, the second silicon-doped layer has an overlapping portion, and a portion where the second silicon-doped layer is connected to the first side wall of the substrate is the overlapping portion of the second silicon-doped layer.

[0023] A surface of a side of the overlapping portion of the second silicon-containing doped layer away from the substrate is higher than a first surface corresponding to the first doped region; or

[0024] A surface of a side of the overlapping portion of the second silicon-containing doped layer away from the substrate is flush with a first surface corresponding to the first doped region.

[0025] Further, the ultra-thin material layer extends from a first surface of the substrate corresponding to the second silicon-containing doped layer to a surface of a first side wall of the substrate;

[0026] The overlapping portion of the second silicon-containing doped layer overlaps the side wall of the entire co-doped region.

[0027] Further, the portion where the second silicon-containing doped layer is in contact with the first side wall of the substrate is an overlapping portion of the second silicon-containing doped layer;

[0028] A surface of a side of the overlapping portion of the second silicon-containing doped layer away from the substrate is lower than a first surface corresponding to the first doped region.

[0029] Furthermore, a height difference between a first surface of the substrate corresponding to the co-doped region and a surface of a side of the overlapping portion of the second silicon-containing doped layer away from the substrate is less than or equal to 1 μm; or

[0030] The ratio between the height difference between the first surface of the substrate corresponding to the co-doped region and the surface of the side of the overlapping portion of the second silicon-containing doped layer away from the substrate and the junction depth of the first doped region is less than or equal to 90%.

[0031] Further, in the thickness direction, a doping concentration of the doping element in a portion of the co-doped region that is in contact with the second silicon-containing doped layer is lower than a doping concentration of the doping element in a portion of the co-doped region that is not in contact with the second silicon-containing doped layer.

[0032] Furthermore, on the first doping region, along its extension direction, there are a plurality of co-doping regions arranged in compartments, and the first doping region between two adjacent co-doping regions is a non-overlapping portion of the first doping region;

[0033] The spacing region is located between a non-overlapping portion of the first doped region and the second silicon-containing doped layer adjacent thereto.

[0034] Furthermore, the co-doped region contains the doping elements in the first doping region and the doping elements in the second doping layer.

[0035] The present application also provides a photovoltaic assembly, which includes the aforementioned solar cell.

[0036] The solar cell provided in the present application has a co-doped region between the first doped region and the second doped region, and the first doped region is connected to a partial area of ​​the second silicon-containing doped layer, thereby forming a channel with a large forward resistance and a small reverse resistance, thereby being able to separate the reverse current and play an anti-hot spot effect. At the same time, the forward resistance is large and the efficiency loss of the battery is small. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The accompanying drawings are used to better understand the present application and do not constitute an improper limitation on the present application.

[0038] Figure 1A This is the first bonding method for solar cells provided in this application.

[0039] Figure 1B This is a variation of the first bonding method for solar cells provided in the present application.

[0040] Figure 2 This is the second bonding method for solar cells provided in this application.

[0041] Figure 3 This is the third bonding method for solar cells provided in this application.

[0042] Figure 4 A schematic diagram of a portion of the structure of the solar cell provided in this application.

[0043] Figure 5 A top view of the second overlapping method of the solar cell provided in the present application.

[0044] Description of Reference Numerals

[0045] 1-substrate, 2-first doping region, 3-second silicon-containing doping layer, 4-ultra-thin material layer, 5-co-doping region, 6-oxide layer, 7-spacer region. DETAILED DESCRIPTION

[0046] The following is a description of exemplary embodiments of the present application, including various details of the embodiments of the present application to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present application. Similarly, for clarity and conciseness, the description of well-known functions and structures is omitted in the following description. In the present application, the upper and lower positions are determined according to the incident direction of the light, and the place where the light is incident is the upper part.

[0047] The present application provides a solar cell, comprising a substrate 1, wherein the substrate 1 has a first surface and a second surface arranged opposite to each other;

[0048] The substrate 1 has a first doping region 2, which is a region close to the first surface.

[0049] A second semiconductor material layer is stacked on the first surface of the substrate 1; the second semiconductor material layer and the first doping region 2 are arranged alternately; and a spacing region 7 is provided between the second semiconductor material layer and the first doping region 2;

[0050] The doping type of the second semiconductor material layer is opposite to the doping type of the first doping region 2;

[0051] The ultra-thin material layer 4 is stacked on the substrate 1 on a surface of one side away from the second silicon-doped layer 3;

[0052] The first doping region 2 includes a co-doping region 5;

[0053] The co-doped region 5 is connected to a portion of the second silicon-containing doped layer 3;

[0054] In this article, contact includes direct contact and indirect contact. There is an ultra-thin material layer 4 between the two parts of indirect contact. The ultra-thin material layer 4 does not affect the electrical contact between the second silicon-containing doped layer 3 and the co-doped region 5. For example, the ultra-thin material layer 4 can be a tunneling layer or an amorphous silicon layer. The thickness of the tunneling layer can be 1-5nm, and the thickness of the amorphous silicon layer can be 2-10nm. The ultra-thin material layer can be a uniform film layer or a non-uniform film layer. For example, the film layer can have a through hole, and the co-doped region 5 can be in direct contact with the second silicon-containing doped layer 3 through the through hole.

[0055] A first electrode, the first electrode is in contact and electrically connected with the first doping region 2; and,

[0056] A second electrode is in contact and electrically connected with the second silicon-containing doped layer 3 .

[0057] Herein, the first surface of the substrate 1 is the backlight surface, and the second surface is the light-facing surface. The substrate 1 may be a silicon substrate 1, for example, a p-type single crystal silicon substrate 1 or an n-type single crystal silicon substrate 1, or other types of semiconductor substrates 1.

[0058] The first surface of the substrate 1 corresponding to the first doping region 2 may be a suede structure or a polished surface.

[0059] In the first doping region 2 , in a direction from close to the first surface to the inside of the substrate 1 , the doping concentration of the doping element increases first and then decreases.

[0060] The junction depth of the first doped region 2 is 1-2.5 μm, for example, 1 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.4 μm, 1.5 μm, 1.8 μm, 2 μm, 2.2 μm, 2.5 μm, etc.

[0061] The concentration of the doping element in the first doping region 2 is 1E18-1E19 at 0μm-0.2μm from the first surface; the doping concentration of the doping element is 5E18-3E19 at 0.2μm-1μm from the first surface; and the doping concentration of the doping element is 1E17-5E18 at 1-2.5μm from the first surface. Since the first doping region 2 is a low-concentration silicon diffusion layer of the substrate 1 compared to the second silicon-containing doping layer 3, the first doping region 2 is connected to a part of the second silicon-containing doping layer 3, thereby forming a channel with a large forward resistance and a small reverse resistance, thereby separating the reverse current and enhancing the effect of preventing hot spots.

[0062] Those skilled in the art can understand that the doping concentration of the doping element in the first doping region 2 can refer to the concentration of the doping element at any site on the surface of the first doping region 2 or in the first doping region 2, and of course, it can also be the average value of the doping element at multiple locations. Those skilled in the art can select the above-mentioned arbitrary sites for detection based on the actual situation based on the detection conditions and the instruments used, or calculate the average value of multiple sites after detecting multiple sites as the concentration of the doping element. In a specific embodiment, the concentration of the doping element refers to the average value detected on the thickness of the doping element. For example, the concentration of the doping element in the first doping region 2 is detected in a thickness direction using the SIMS method, and the average value in this thickness direction is calculated.

[0063] There is a height difference between the first surface of the substrate 1 corresponding to the first doping region 2 and the first surface of the substrate 1 corresponding to the second silicon-containing doping layer 3, and the height difference is 0.1-8μm, for example, it can be 0.1μm, 0.5μm, 1μm, 1.5μm, 2μm, 2.5μm, 3μm, 3.5μm, 4μm, 4.5μm, 5μm, 5.5μm, 6μm, 6.5μm, 7μm, 7.5μm, 8μm, etc.

[0064] Furthermore, a first surface of the substrate 1 corresponding to the first doping region 2 is higher than a first surface of the substrate 1 corresponding to the second silicon-containing doping layer 3 .

[0065] The doping element in the first doping region 2 is a Group IIIA element or a Group VA element, for example, boron.

[0066] The square resistance of the first doped region 2 is 200 ohm-500 ohm, for example, 200 ohm, 250 ohm, 300 ohm, 350 ohm, 400 ohm, 450 ohm, 500 ohm, etc.

[0067] Sheet resistance, also known as film resistance, is a measurement value used to indirectly characterize the thermal infrared performance of vacuum coatings on samples such as thin film layers and glass coating layers. The value can be directly converted into thermal infrared emissivity. The size of the sheet resistance is independent of the sample size. Its unit is Siements / sq, and the ohm / sq representation method is added later. The unit is directly translated into sheet resistance or surface resistance. It is also called film layer resistance when used for film layer measurement.

[0068] The composite current density of the first doping region 2 is 3-15 fA.

[0069] The first surface of the substrate 1 corresponding to the second silicon-containing doped layer 3 may be a suede structure or a polished surface.

[0070] In some embodiments, the first surface corresponding to the first doping region 2 is a suede structure, and the first surface of the substrate 1 corresponding to the second silicon-containing doping layer 3 is a polished surface.

[0071] In some embodiments, the first surface corresponding to the first doped region 2 and the first surface of the substrate 1 corresponding to the second silicon-containing doped layer 3 are both polished surfaces.

[0072] The doping element in the second silicon-containing doped layer 3 may be a Group IIIA element or a Group VA element, for example, phosphorus.

[0073] The second silicon-containing doped layer 3 may be one of an n-type doped polycrystalline silicon layer, an n-type doped amorphous silicon layer, an n-type doped microcrystalline silicon layer, and an n-type doped silicon carbide layer, including but not limited to these.

[0074] The thickness of the second silicon-containing doped layer 3 is 50nm-300nm, for example, it can be 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, 160nm, 170nm, 180nm, 190nm, 200nm, 210nm, 220nm, 230nm, 240nm, 250nm, 260nm, 270nm, 280nm, 290nm or 300nm, etc.

[0075] The composite current density of the second silicon-doped layer 3 is 1-5 fA.

[0076] The co-doped region 5 is located in a region of the first doped region 2 close to a side of the second silicon-containing doped layer 3 .

[0077] Along the direction of alternation between the first doping region 2 and the second silicon-containing doping layer 3 (width direction), the width L1 of the co-doped region 5 is 0.02μm-1μm, for example, it can be 0.02μm, 0.05μm, 0.1μm, 0.15μm, 0.2μm, 0.3μm, 0.4μm, 0.5μm, 0.6μm, 0.7μm, 0.8μm, 0.9μm, 1μm, etc.

[0078] Along the extending direction of the first doping region 2, i.e., in the direction perpendicular to the alternating direction of the second silicon-containing doping layer 3 and the first doping region 2, the length L2 of the co-doping region 5 is 10-500 μm, i.e., 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, 120 μm, 140 μm, 160 μm, 180 μm, 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, 500 μm, etc.

[0079] The co-doped region 5 contains both the doping elements in the first doping region 2 and the doping elements in the second doping layer.

[0080] The co-doped region 5 is a diffusion layer of the substrate 1 that has both the doping elements in the first doping region 2 and the doping elements in the second doping layer.

[0081] The first surface of the substrate 1 corresponding to the first doping region 2 is higher than the first surface of the substrate 1 corresponding to the second silicon-containing doping layer 3, and the height difference between the first surface of the substrate 1 corresponding to the first doping region 2 and the first surface of the substrate 1 corresponding to the second silicon-containing doping layer 3 is 0.1-8μm, for example, it can be 0.1μm, 0.5μm, 1μm, 1.5μm, 2μm, 2.5μm, 3μm, 3.5μm, 4μm, 4.5μm, 5μm, 5.5μm, 6μm, 6.5μm, 7μm, 7.5μm, 8μm, etc.

[0082] In the present application, the sidewall of the substrate 1 on the side of the first doping region 2 facing the second semiconductor material layer is the first sidewall, and the co-doped layer includes at least a portion of the first sidewall. The first sidewall of the substrate 1 overlaps with the sidewall of the co-doped region 5.

[0083] In the present application, there are three overlapping modes for the co-doped region 5 to connect with a partial region of the second silicon-containing doped layer 3, which are specifically as follows:

[0084] The first type of lap joint, such as Figure 1AAs shown, the second silicon-containing doped layer 3 includes a main body portion and an overlapping portion, the main body portion is located directly above the first surface of the substrate 1 , and the overlapping portion of the second silicon-containing doped layer 3 overlaps the co-doped region 5 .

[0085] The solar cell may further include an oxide layer 6, which is located on the first surface of the substrate 1 corresponding to the first doping region 2, and a partial area of ​​the oxide layer 6 covers the co-doping region 5, and a partial area of ​​the overlapping portion of the second silicon-containing doping layer 3 is stacked on the surface of the oxide layer 6 on the side away from the substrate 1. That is, the oxide layer 6 and the overlapping portion of the second silicon-containing doping layer 3 are sequentially stacked on the partial area of ​​the first surface of the substrate 1 corresponding to the first doping region 2, and a partial area of ​​the oxide layer 6 covers the co-doping region 5. Since the co-doping region 5 includes the region with a higher doping concentration of the first doping region 2, the overlapping effect of the PN region can be improved, and the performance of anti-hot spot can be improved.

[0086] Furthermore, if Figure 1B As shown, the overlapping portion of the second silicon-containing doped layer 3 extends from the oxide layer 6 to the surface of the first doped region 2 and directly contacts the surface of the first doped region 2, that is, the overlapping portion of the second silicon-containing doped layer 3 extends from the top of the oxide layer 6 to its side surface, and continues to extend until it directly contacts the first doped region 2. This improves the overlapping effect of the pn region.

[0087] Further, the ultra-thin material layer 4 is a tunneling layer, and the tunneling layer includes a portion between the first side wall of the substrate 1 and the overlapping portion of the second silicon-containing doped layer 3, a portion between the oxide layer 6 and the overlapping portion of the second silicon-containing doped layer 3, and a portion between the main body of the second silicon-containing doped layer 3 and the substrate 1. That is, the tunneling layer extends from the first surface of the substrate 1 corresponding to the main body of the second silicon-containing doped layer 3 to the surface of the first side wall, and then continues to extend until the oxide layer 6 is away from the side surface of the substrate 1.

[0088] The thickness of the oxide layer 6 is 10-120 mm, for example, 10 mm, 20 mm, 30 mm, 40 mm, 50 mm, 60 mm, 70 mm, 80 mm, 90 mm, 100 mm, 110 mm, 120 mm, etc.

[0089] In the second overlapping manner, the second silicon-containing doped layer 3 has an overlapping portion, and a portion where the second silicon-containing doped layer 3 is connected to the first side wall of the substrate 1 is the overlapping portion of the second silicon-containing doped layer 3 .

[0090] The side wall of the substrate 1 on the side of the first doping region 2 facing the second semiconductor material layer is the first side wall, and the co-doped layer includes at least a portion of the first side wall. That is, at least a portion of the first side wall of the substrate 1 forms the side wall of the co-doped region 5 (the portion of the first side wall close to the first surface is the side wall of the co-doped region 5).

[0091] The second silicon-containing doped layer 3 is only connected to the side wall of the co-doped region 5. The second silicon-containing doped layer 3 is only connected to the side wall of the co-doped region 5, which can reduce the complex stacking structure in the battery structure and improve the transmittance of light, thereby utilizing more light to improve battery efficiency.

[0092] like Figure 2 As shown, the portion where the second silicon-containing doped layer 3 is connected to the side wall of the co-doped region 5 is the overlapped portion of the second silicon-containing doped layer 3, and the surface of the side away from the substrate 1 is higher than the first surface corresponding to the first doped region 2; or the surface of the overlapped portion of the second silicon-containing doped layer 3 is away from the substrate 1 and is flush with the first surface corresponding to the first doped region 2. The overlapped portion of the second silicon-containing doped layer 3 is connected to the side wall of the entire co-doped region 5; such a design can effectively utilize the first side wall to achieve butt conduction of the pn region.

[0093] In some embodiments, a surface of a side of the overlapping portion of the second silicon-containing doped layer 3 away from the substrate 1 is higher than a first surface corresponding to the first doped region 2, and a height difference thereof is 10 nm-50 nm, for example, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, etc.

[0094] In some embodiments, a surface of a side of the overlapping portion of the second silicon-containing doped layer 3 away from the substrate 1 is flush with a first surface corresponding to the first doped region 2 , which is beneficial to the quality of a subsequent passivation anti-reflection film layer.

[0095] Furthermore, the ultra-thin material layer 4 is a tunneling layer, which includes a portion located between the second silicon-containing doped layer 3 and the first side wall, and also includes a portion between the second silicon-containing doped layer 3 and the substrate 1, that is, the tunneling layer extends from the first surface of the substrate 1 corresponding to the second silicon-containing doped layer 3 to the surface of the first side wall.

[0096] Furthermore, the second silicon-containing doped layer 3 also includes a portion directly in contact with the sidewall of the co-doped region 5, and the portion is close to the top surface of the co-doped region 5. That is, the overlapping portion of the second silicon-containing doped layer 3 is in direct contact with the co-doped region 5 at a side away from the substrate 1.

[0097] The third lap method, such as Figure 3As shown, the difference between the second overlapping mode and the second overlapping mode is that the top surface of the second silicon-doped layer 3 is lower than the top surface of the co-doped region 5, that is, the side surface of the overlapping portion of the second silicon-doped layer 3 away from the substrate 1 is lower than the first surface corresponding to the first doped region 2. The overlapping portion of the second silicon-doped layer 3 is connected to a partial area of ​​the co-doped region 5. Further, the overlapping portion of the second silicon-doped layer 3 is connected to a portion of the co-doped region 5 away from the first surface. In the thickness direction, the doping concentration of the doping element in the portion of the co-doped region 5 connected to the second silicon-doped layer 3 is lower than the doping concentration of the doping element in the portion not connected to the second silicon-doped layer 3. Such a design can reasonably adjust the leakage degree of the pn region and improve the design window. Preferably, the height difference S between the first surface of the substrate 1 corresponding to the co-doped region 5 and the surface of the side of the overlapping portion of the second silicon-containing doped layer 3 away from the substrate 1 is less than or equal to 1 μm, for example, it can be 1 μm, 0.95 μm, 0.9 μm, 0.85 μm, 0.8 μm, 0.75 μm, 0.7 μm, 0.65 μm, 0.5 μm, 0.55 μm, 0.45 μm, 0.4 μm, 0.35 μm, 0.3 μm, 0.25 μm, 0.2 μm, 0. In some embodiments, S may be any value between 0.1 μm and 0.9 μm, excluding 0; in some embodiments, S may be 0.1-1 μm; in some embodiments, S may be 0.1-0.9 μm; in some embodiments, S may be 0.1-0.8 μm; in some embodiments, S may be 0.1-0.7 μm; in some embodiments, S may be 0.1-0.6 μm; in some embodiments, S may be 0.1-0.5 μm. The ratio M between the height difference S between the first surface of the substrate 1 corresponding to the co-doped region 5 and the side surface of the overlapped portion of the second silicon-containing doped layer 3 away from the substrate 1 and the junction depth of the first doped region 2 is less than or equal to 90%. In some embodiments, M may be 1%-80%, in some embodiments, M may be 5%-70%, in some embodiments, M may be 5%-60%, in some embodiments, M may be 5%-50%, in some embodiments, M may be 5%-40%, in some embodiments, M may be 5%-30%, in some embodiments, M may be 5%-20%, in some embodiments, M may be 5%-10%. Specifically, M may be any value between 1%, 5%, 10%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%, 90%.

[0098] By adjusting the height difference S between the first surface of the substrate 1 corresponding to the co-doped region 5 and the surface of the side of the overlapping portion of the second silicon-containing doped layer 3 away from the substrate 1, the function of channel separation of reverse current can be achieved. Because the reverse resistance should be as small as possible, there is a window for achieving the optimal reverse resistance within a certain range of the height difference S.

[0099] Furthermore, the ultra-thin material layer 4 is a tunneling layer, which includes a portion located between the second silicon-containing doped layer 3 and the first side wall, and also includes a portion between the second silicon-containing doped layer 3 and the substrate 1, that is, the tunneling layer extends from the first surface of the substrate 1 corresponding to the second silicon-containing doped layer 3 to a partial surface of the first side wall.

[0100] In this article, the solar cell may include any one of the three overlapping modes mentioned above.

[0101] like Figure 4 as well as Figure 5 As shown, on each of the first doping regions 2, in the extension direction thereof, there are a plurality of co-doping regions 5 arranged in compartments, and the first doping region 2 between two adjacent co-doping regions 5 is a non-overlapping portion of the first doping region 2. There is the spacing region 7 between the non-overlapping portion of the first doping region 2 and the adjacent second silicon-containing doping layer 3, and the non-overlapping portion of the first doping region 2 and the adjacent second silicon-containing doping layer 3 are not overlapped.

[0102] In some embodiments, on each of the first doping regions 2 , a plurality of co-doping regions 5 are arranged at equal intervals in the extending direction thereof.

[0103] In the present application, a first electrode is disposed on a surface of the first doping region 2 that is away from the interior of the substrate 1 , and a portion of the first electrode extends into the first doping region 2 .

[0104] A second electrode is disposed on a surface of the second silicon-containing doped layer 3 away from the substrate 1 , and a portion of the second electrode extends into the second silicon-containing doped layer 3 .

[0105] Specifically, a second passivation anti-reflection layer is stacked on the second surface of the substrate 1, a first passivation anti-reflection layer covering the second silicon-containing doped layer 3 and the first doped region 2 is stacked on the surface of the second silicon-containing doped layer 3 facing away from the substrate 1, and the first electrode penetrates the first passivation anti-reflection layer and extends into the first doped region 2, and the second electrode penetrates the first passivation anti-reflection layer and contacts the second silicon-containing doped layer 3.

[0106] The first passivation anti-reflection layer includes one or more layers of silicon oxide, silicon nitride, aluminum oxide, and silicon oxynitride. For example, the first passivation anti-reflection layer includes an aluminum oxide layer (AlOx, x is an arbitrary value) and a silicon nitride layer (SiNx, x can be an arbitrary value) stacked in sequence, wherein the surface of the aluminum oxide layer away from the silicon nitride layer is stacked together with the first surface of the substrate 1 corresponding to the second silicon-containing doped layer 3 not stacked thereon and the second silicon-containing doped layer 3.

[0107] The thickness of the silicon nitride layer is 50nm-130nm, and the thickness of the aluminum oxide layer is 2nm-15nm.

[0108] The second passivation anti-reflection layer includes one or more layers of silicon oxide, silicon nitride, aluminum oxide, and silicon oxynitride. For example, the second passivation anti-reflection layer includes a silicon nitride layer (SiNx, x can be any value) and a silicon oxynitride layer stacked in sequence, wherein a surface of the silicon nitride layer away from the silicon oxynitride layer is stacked with the second surface of the substrate 1.

[0109] The thickness of the silicon nitride layer is 30nm-130nm, and the thickness of the silicon oxynitride layer is 10nm-100nm.

[0110] The first electrode and the second electrode may be made of silver, copper, aluminum or alloys thereof. The first electrode and the second electrode may be the same or different.

[0111] The method for preparing a solar cell provided by the present application comprises the following steps:

[0112] Step 1: providing a substrate 1; the substrate 1 has a first surface and a second surface opposite to each other;

[0113] Step 2: polish or texturize the first surface (backlight surface) of the substrate 1 to diffuse the doping elements, thereby forming an initial first doping region 2 , and forming a BSG layer on the top of the initial first doping region 2 .

[0114] Step 3: first patterning to form a patterned first doping region 2.

[0115] The first patterning is performed by a conventional method, which is not specifically limited, such as laser grooving or masking.

[0116] When laser grooving is used for imaging, the unit energy density of the laser can be adjusted specifically. By adjusting the power, frequency, speed, and type of light source of the laser, the energy density can be adjusted to 0.3J / m 3 -2 J / m 3The reflectivity of the light in the laser band on this kind of battery structure is adjusted. The reflectivity on the velvet surface is 1%-5%, and the reflectivity on the polished surface is 5%-25%. At this time, the best film removal effect and low damage effect are achieved. The judgment standard is PL test. The PL measurement after laser drops to 1%-5%.

[0117] When the mask method is used, the mask is an oxide with a thickness of 5nm-100nm, the main component of which is silicon oxide, and the proportion of boron in the oxide is 0-20%, or it is matched with other masking films, such as commonly used wax printing or offset printing, etc. The main advantage is that the masking film of this component can be completely removed in less than 120S under low concentration HF (1%-5%), or completely removed in 240S under low concentration alkali NaOH or KOH (2%-10%), without using additives and introducing other impurities.

[0118] After the first patterning is completed, a plurality of first doped regions 2+BSG layers are provided at intervals on the first surface of the substrate 1 , and the exposed substrate 1 forms a polished surface.

[0119] Step 4: An entire ultra-thin material layer 4 and a second silicon-containing doped layer 3 are formed on the surface of the BSG layer away from the substrate 1 and the exposed substrate 1, and the doping elements in the second silicon-containing doped layer 3 enter the first doping region 2 through the ultra-thin material layer 4, thereby forming a co-doped region 5 in the area of ​​the first doping region 2 close to the second silicon-containing doped layer 3 on one side.

[0120] The preparation processes of the ultra-thin material layer 4 and the second silicon-doped layer 3 are conventional and are not further limited here. For example, the ultra-thin material layer 4 can be formed by POLY, and the second silicon-doped layer 3 can be formed by LPCVD.

[0121] Step 5: Second patterning: forming a patterned ultra-thin material layer 4 and a second silicon-doped layer 3 .

[0122] The second patterning is performed by a conventional method, which is not specific and limited, such as laser grooving + cleaning or masking.

[0123] When the first lap joint method is used,

[0124] During the second patterning process, most of the BSG layer, the ultra-thin material layer 4 and the second silicon-containing doped layer 3 located on the first doped region 2 are removed, and the portion of the first doped region 2 close to the second doped region is retained without being patterned, thereby forming an oxide layer 6, an ultra-thin material layer 4 and a second silicon-containing doped layer 3 stacked in sequence on the first surface of the substrate 1 corresponding to the area of ​​the first doped region 2 close to the second silicon-containing doped layer 3.

[0125] When the second lap joint method is used,

[0126] In the second patterning process, the BSG layer, the ultra-thin material layer 4 and the second silicon-containing doped layer 3 located on the first doped region 2 are all removed.

[0127] When the third lap method is used,

[0128] During the second patterning process, the BSG layer, the ultra-thin material layer 4 and the second silicon-containing doped layer 3 located on the first doped region 2 are all removed, and part of the ultra-thin material layer 4 and the second silicon-containing doped layer 3 on the side wall of the first doped region 2 close to the second silicon-containing doped layer 3 are removed.

[0129] Step 6: A passivation anti-reflection layer is formed on the second surface (light-facing surface) of the substrate 1 and the surface of the second silicon-doped layer 3 away from the substrate 1. The passivation anti-reflection layer on the light-facing surface of the substrate 1 is the second passivation anti-reflection layer, and the passivation anti-reflection layer on the first doping region 2 and the second silicon-doped layer 3 is the first passivation anti-reflection layer. The preparation process of the passivation anti-reflection layer is conventional and is not further limited here. For example, the passivation anti-reflection layer can be formed by a pecvd method.

[0130] Step 7: Form a first electrode and a second electrode.

[0131] First, a first electrode precursor is formed on a surface of the first passivation anti-reflection layer away from the first doping region 2 by a screen printing process, and a second electrode is formed on a surface of the first passivation anti-reflection layer away from the second doping region; then, the first electrode and the first doping region 2 are processed by a LECO process, so as to form a first electrode and a second electrode penetrating the first passivation anti-reflection layer on the first passivation anti-reflection layer, wherein the first electrode penetrates the first passivation anti-reflection layer and partially extends into the first doping region 2, and the second electrode penetrates the first passivation anti-reflection layer and contacts the second silicon-containing doping layer 3.

[0132] The laser in the LECO process is green light or infrared light, the reverse bias voltage is between 2V and 15V, and the scanning mode is front scanning or back scanning.

[0133] The present application also provides a photovoltaic assembly, which includes the aforementioned solar cell.

[0134] Example

[0135] The experimental methods used in the following examples are all conventional methods unless otherwise specified.

[0136] Unless otherwise specified, the materials and reagents used in the following examples can be obtained from commercial sources.

[0137] Example 1

[0138] This embodiment is the first overlapping method. Figure 1A The solar cell is prepared as follows:

[0139] Step 1: providing a silicon substrate; the silicon substrate has a first surface and a second surface arranged opposite to each other;

[0140] The single crystal silicon wafer is an N-type silicon wafer, and a texturing and cleaning procedure is performed on both sides of the N-type silicon wafer so that the first surface has a pyramid-shaped texture structure, and the height of the pyramid-shaped texture structure is 1-3 μm.

[0141] Step 2: Boron is used to diffuse doping elements on the first surface (backlight side) of the silicon substrate, thereby forming a first doping region, and a BSG layer is formed on the top of the first doping region. In the first doping region, the doping concentration of the boron element increases first and then decreases from the first surface to the substrate, and the difference between the maximum doping concentration of the boron element and the doping concentration at the first surface is 3E18; the junction depth of the first doping region is 0.8μm; the square resistance of the first doping region is 200ohm.

[0142] Step 3: Patterning for the first time to form a patterned first doping region.

[0143] When laser grooving is used for imaging, the first laser is used to irradiate the first surface except for the first doped region + BSG layer to be retained, and the first doped region + BSG layer in other regions except the first doped region + BSG layer to be retained is etched away, thereby exposing the silicon substrate. The first laser is a picosecond laser with an energy density of 200MJ / m 2 After the first patterning is completed, a plurality of first doped regions + BSG layers are provided at intervals on the first surface of the silicon substrate. The width of the first doped region is 250 μm, the exposed silicon substrate is a polished surface, and the height difference between the first surface of the silicon substrate corresponding to the first doped region and the exposed silicon substrate is 3 μm.

[0144] Step 4: A tunneling layer and a second silicon-containing doped layer 3 are formed on the surface of the BSG layer away from the silicon substrate, and the doping elements in the second silicon-containing doped layer 3 enter the first doped region through the tunneling layer, thereby forming a co-doped region 5, the length L2 of the co-doped region 5 is 100μm and the width L1 is 0.5μm. The tunneling layer can be formed by POLY, and the second silicon-containing doped layer 3 is formed by POLY.

[0145] The layer 3 can be formed by LPCVD. The tunneling layer is a silicon oxide layer with a thickness of 2 nm. The second silicon-doped layer 3 is a phosphorus-doped polysilicon layer with a thickness of 100 nm.

[0146] Step 5: Second patterning: forming a patterned tunneling layer and a second silicon-containing doped layer 3 .

[0147] A second laser is used to irradiate a partial area directly above the first doped region, and the part of the first doped region close to the second doped region does not need to be irradiated by the second laser. The instantaneous high temperature of the laser has a film-opening effect, and then the second silicon-containing doped layer 3 and the tunneling layer directly above the first doped region are etched away, thereby forming a sequentially stacked oxide layer 6, an ultra-thin material layer 4 and a second silicon-containing doped layer 3 on the first surface of the substrate corresponding to the area of ​​the first doped region close to the second silicon-containing doped layer 3.

[0148] The second laser is a picosecond laser with an energy density of 200MJ / m 2 .

[0149] In the length direction, the length of the second silicon-containing doped layer 3 and the tunneling layer is 250 μm.

[0150] Step 6: A passivation anti-reflection layer is formed on the second surface (light-facing surface) of the silicon substrate and the surface of the second silicon-containing doped layer 3 away from the silicon substrate. The passivation anti-reflection layer located on the light-facing surface of the silicon substrate is the second passivation anti-reflection layer, and the passivation layer located on the first doped region and the second silicon-containing doped layer 3 is the first passivation anti-reflection layer. The passivation anti-reflection layer can be formed by PECVD. The first passivation anti-reflection layer is a stack of a silicon nitride layer and an aluminum oxide layer, the thickness of the silicon nitride layer is 100nm, and the thickness of the aluminum oxide layer is 5nm. In the first passivation anti-reflection layer, the aluminum oxide layer is stacked together with the first doped region and the second silicon-containing doped layer 3. The second passivation anti-reflection layer is a stack of a silicon nitride layer and a silicon oxynitride layer, and the silicon nitride layer is stacked together with the second surface of the silicon substrate.

[0151] Step 7: Form a first electrode and a second electrode.

[0152] First, a first electrode precursor is formed on a surface of the first passivation anti-reflection layer away from the first doping region by a screen printing process, and a second electrode is formed on a surface of the first passivation anti-reflection layer away from the second doping region; then, the first electrode and the first doping region are processed by a LECO process to form a first electrode and a second electrode, wherein the first electrode penetrates the first passivation anti-reflection layer and partially extends into the first doping region, and the second electrode penetrates the first passivation anti-reflection layer and is connected to the second silicon-containing doping layer 3. The first electrode is silver paste, and the second electrode is silver paste.

[0153] The laser in the LECO process is green light, the reverse bias voltage is 15V, the reverse current is 8A, the scanning mode is front scanning or back scanning, and the diameter of the laser spot used is the distance between the two spires in the pyramid-shaped velvet structure. The performance of the solar cell of this embodiment is shown in Table 1.

[0154] Example 2

[0155] This embodiment is a solar cell of the second overlapping mode, and the difference between its preparation method and the preparation method of embodiment 1 lies in step 5. Step 5 of this embodiment is as follows: in the second patterning process, the BSG layer, the ultra-thin material layer 4 and the second silicon-containing doped layer located on the first doped region are all removed, and the surface of the side of the overlapping portion of the second silicon-containing doped layer away from the silicon substrate is flush with the first surface corresponding to the first doped region.

[0156] The performance of the solar cell of this embodiment is shown in Table 1.

[0157] Example 3

[0158] This embodiment is a solar cell with a third overlapping method, and the difference between its preparation method and the preparation method of embodiment 1 lies in step five. Step five of this embodiment is as follows: in the second patterning process, the BSG layer, the ultra-thin material layer 4 and the second silicon-containing doped layer located on the first doped region are completely removed, and part of the ultra-thin material layer 4 and the second silicon-containing doped layer on the side wall of the first doped region close to the second silicon-containing doped layer are removed at the same time. The height difference between the first surface of the substrate corresponding to the co-doped region 5 and the surface of the side of the overlapping portion of the second silicon-containing doped layer away from the substrate is 0.3μm.

[0159] The performance of the solar cell of this embodiment is shown in Table 1.

[0160] Table 1 shows the parameters in each embodiment.

[0161]

[0162] In this article, the forward resistance and the reverse resistance are obtained by the IV test method.

[0163] Summary: From the above table, we can see that the above three connection schemes can all achieve the effect of large forward resistance and small reverse resistance. The difference lies in that the maximum and minimum values ​​of the forward and reverse resistances of different connection methods are different. The larger the forward resistance value, the smaller the battery failure, and the smaller the reverse resistance, the better the effect of separating the reverse current.

[0164] Although the embodiments of the present application are described above in conjunction with the accompanying drawings, the present application is not limited to the above specific embodiments and application fields, and the above specific embodiments are merely illustrative and instructive, rather than restrictive. A person of ordinary skill in the art can also make many forms under the guidance of this specification and without departing from the scope of protection of the claims of the present application, all of which belong to the protection of the present application.

Claims

1. A solar cell, wherein: comprising a substrate having a first surface and a second surface disposed opposite to each other; A first doped region is provided in the substrate and is a region close to the first surface, A second semiconductor material layer is stacked on the first surface of the substrate, the first doped regions and the second semiconductor material layer are arranged alternately; and a spacing region is provided between the second semiconductor material layer and the first doped regions; The doping type of the second semiconductor material layer is opposite to the doping type of the first doping region; The second semiconductor material layer comprises an ultra-thin material layer and a second silicon-containing doped layer stacked in sequence; a surface of the ultra-thin material layer away from the second silicon-containing doped layer is stacked with the substrate; The first doped region includes a co-doped region; The co-doped region is connected to a portion of the second silicon-containing doped layer; a first electrode, the first electrode being in contact and electrically connected with the first doping region; as well as, A second electrode is in contact and electrically connected with the second silicon-containing doped layer.

2. The solar cell according to claim 1, wherein: In the first doping region, the co-doping region is located in a region close to a side of the second silicon-containing doping layer. Along the direction in which the first doped regions and the second silicon-containing doped layers alternate, a width L1 of the co-doped regions is 0.02 μm-1 μm; or Along the extending direction of the first doping region, the length L2 of the co-doping region is 10 μm-500 μm.

3. The solar cell according to claim 2, wherein: The first surface of the substrate corresponding to the first doped region is higher than the first surface of the substrate corresponding to the second silicon-containing doped layer, and the height difference between the first surface of the substrate corresponding to the first doped region and the first surface of the substrate corresponding to the second silicon-containing doped layer is 0.1-8μm.

4. The solar cell according to claim 1, wherein: A sidewall of the substrate on a side of the first doped region facing the second semiconductor material layer is a first sidewall, and the co-doped layer includes at least a portion of the first sidewall.

5. The solar cell according to any one of claims 1 to 4, wherein: An oxide layer and a second silicon-containing doped layer are sequentially stacked on a partial area of ​​the first surface of the substrate corresponding to the first doped area. A partial area of ​​the oxide layer covers the co-doped region.

6. The solar cell according to claim 5, wherein: The second silicon-doped layer has an overlapping portion, The overlapping portion of the second silicon-containing doped layer extends from the first sidewall of the substrate to the top of the oxide layer; or The overlapping portion of the second silicon-containing doped layer extends from the first side wall of the substrate to the top of the oxide layer and the side surface thereof until it directly contacts the first doped region.

7. The solar cell according to any one of claims 1 to 4, wherein: The second silicon-doped layer has an overlapping portion, and a portion where the second silicon-doped layer is in contact with the first side wall of the substrate is the overlapping portion of the second silicon-doped layer. A surface of a side of the overlapping portion of the second silicon-containing doped layer away from the substrate is higher than a first surface corresponding to the first doped region; or A surface of a side of the overlapping portion of the second silicon-containing doped layer away from the substrate is flush with a first surface corresponding to the first doped region.

8. The solar cell according to claim 7, wherein: The ultra-thin material layer extends from the first surface of the substrate corresponding to the second silicon-containing doped layer to the surface of the first side wall of the substrate; The overlapping portion of the second silicon-containing doped layer overlaps the side wall of the entire co-doped region.

9. The solar cell according to any one of claims 1 to 4, wherein: The portion where the second silicon-containing doped layer is in contact with the first side wall of the substrate is an overlapping portion of the second silicon-containing doped layer; A surface of a side of the overlapping portion of the second silicon-containing doped layer away from the substrate is lower than a first surface corresponding to the first doped region.

10. The solar cell according to claim 9, wherein: A height difference between the first surface of the substrate corresponding to the co-doped region and a surface of a side of the overlapping portion of the second silicon-containing doped layer away from the substrate is less than or equal to 1 μm; or The ratio between the height difference between the first surface of the substrate corresponding to the co-doped region and the surface of the side of the overlapping portion of the second silicon-containing doped layer away from the substrate and the junction depth of the first doped region is less than or equal to 90%.

11. The solar cell according to claim 9, wherein: In the thickness direction, a doping concentration of the doping element in a portion of the co-doped region that is in contact with the second silicon-containing doped layer is lower than a doping concentration of the doping element in a portion of the co-doped region that is not in contact with the second silicon-containing doped layer.

12. The solar cell according to claim 1, wherein: On the first doping region, along its extension direction, there are a plurality of co-doping regions arranged in compartments, and the first doping region between two adjacent co-doping regions is a non-overlapping portion of the first doping region; The spacing region is located between a non-overlapping portion of the first doped region and the second silicon-containing doped layer adjacent thereto.

13. The solar cell according to any one of claims 1 to 3, wherein: The co-doped region has the doping elements in the first doping region and the doping elements in the second doping layer.

14. A photovoltaic module, wherein: A solar cell comprising the solar cell according to any one of claims 1 to 13.

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