Method of manufacturing display device

Abstract

A method for manufacturing a display device includes: manufacturing an epitaxial wafer including an epitaxial thin film; dividing the epitaxial wafer into wafer grains, wherein the wafer grains have a size corresponding to the area of each unit region of the backplane substrate including the unit regions; transferring the wafer crystal grains to a carrier substrate; forming a conductive bonding layer on the epitaxial crystal grains of the wafer crystal grains; disposing the carrier substrate on the backplane substrate such that the epitaxial die is disposed in each cell region of the backplane substrate, and bonding the epitaxial die to the backplane substrate; removing the carrier substrate from the epitaxial grains; and etching the epitaxial die to form a respective light emitting element in an emission region included in each unit region of the backplane substrate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0144880 filed in the Korean Intellectual Property Office on October 26, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a method for manufacturing a display device. Background Art

[0004] With the development of multimedia, the importance of display devices has gradually increased. Therefore, various display devices such as liquid crystal display devices and light-emitting display devices have been developed. Among them, the light-emitting display device includes a display panel including a light-emitting element, and has been applied to various types of electronic devices including virtual reality (VR) devices or augmented reality (AR) devices, as well as portable electronic devices or televisions.

[0005] It should be understood that this background technology section is intended, in part, to provide a useful background for understanding the technology. However, this background technology section may also include ideas, concepts or realizations that were not known or understood as part of the subject matter disclosed herein by a person skilled in the relevant art before the corresponding effective filing date. Summary of the invention

[0006] Aspects of the present disclosure provide a method of manufacturing a display device capable of increasing manufacturing efficiency of a display panel including a light emitting element.

[0007] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0008] According to aspects of the present disclosure, a method for manufacturing a display device is provided, the method may include: manufacturing an epitaxial wafer including an epitaxial thin film; dividing the epitaxial wafer into wafer dies, the wafer dies having a size corresponding to the area of ​​each unit region of a backplane substrate including a plurality of unit regions; transferring the wafer dies to a carrier substrate; forming a conductive bonding layer on the epitaxial grains of the wafer dies; disposing the carrier substrate on the backplane substrate so that the epitaxial grains are disposed in each unit region of the backplane substrate and the epitaxial grains are bonded to the backplane substrate; removing the carrier substrate from the epitaxial grains; and etching the epitaxial grains to form respective light-emitting elements in an emission region included in each unit region of the backplane substrate.

[0009] In an embodiment, the carrier substrate may have a size corresponding to an area of ​​the backplane substrate, and include a plurality of unit regions corresponding to the plurality of unit regions of the backplane substrate.

[0010] In an embodiment, transferring the wafer dies to the carrier substrate may include aligning the wafer dies with respective unit regions of the carrier substrate.

[0011] In an embodiment, the wafer dies may include respective wafer substrates and respective epitaxial dies divided from the epitaxial thin film.

[0012] In an embodiment, the method for manufacturing a display device may further include: filling the gaps between the wafer grains by applying a filler to the carrier substrate on which the wafer grains are arranged, and after transferring the wafer grains to the carrier substrate and before forming the conductive bonding layer, flattening the upper surface of the carrier substrate on which the wafer grains and the filler are arranged.

[0013] In an embodiment, in the planarizing of the upper surface of the carrier substrate, the epitaxial grains may be exposed by removing the respective wafer substrates from the wafer grains, and the conductive bonding layer may be formed by applying a conductive bonding material to the upper surface of the carrier substrate on which the epitaxial grains are exposed.

[0014] In an embodiment, the method for manufacturing a display device may further include: before the transferring of the wafer dies to the carrier substrate, selecting a product by evaluating the wafer dies, and the wafer dies selected as the product may be transferred to the carrier substrate.

[0015] In an embodiment, the backplane substrate may include a pixel electrode individually disposed in the emission region of each unit region of the backplane substrate.

[0016] In an embodiment, in the etching of the epitaxial grains, the respective light emitting elements may be formed on the pixel electrodes.

[0017] In an embodiment, the backplane substrate may further include a first bonding electrode disposed on the pixel electrode.

[0018] In an embodiment, in bonding the epitaxial grain to the backplane substrate, the epitaxial grain may be bonded to the first bonding electrode by a transient liquid phase (TLP) bonding method or a thermal compression (TC) bonding method.

[0019] In an embodiment, the method for manufacturing a display device may further include: forming a second bonding electrode between the first bonding electrode and the light emitting element by etching the conductive bonding layer.

[0020] In an embodiment, in the removing the carrier substrate, the carrier substrate may be removed from the epitaxial die by a laser lift off (LLO) method.

[0021] In an embodiment, the method for manufacturing a display device may further include: forming a common electrode on the light emitting element in each unit area of ​​the backplane substrate.

[0022] In an embodiment, the method for manufacturing a display device may further include: forming a lens type optical structure on a light emitting element layer including the light emitting element and the common electrode.

[0023] In an embodiment, the method for manufacturing a display device may further include: separating respective cells corresponding to the unit regions into separate display panels by cutting the backplane substrate based on the unit regions of the backplane substrate.

[0024] According to aspects of the present disclosure, a method for manufacturing a display device is provided, the method may include: preparing a backplane substrate, the backplane substrate including a plurality of unit areas and a pixel electrode, the pixel electrode being individually arranged in an emission area arranged in each of the plurality of unit areas; manufacturing wafer grains, the wafer grains having a size corresponding to an area of ​​each of the plurality of unit areas and including respective epitaxial grains; preparing a carrier substrate, the carrier substrate having a size corresponding to the backplane substrate and including a plurality of unit areas corresponding to the plurality of unit areas of the backplane substrate; transferring the wafer grains to the carrier substrate; flattening the upper surface of the carrier substrate so that the epitaxial grains of the wafer grains are exposed, and forming a conductive bonding layer on the epitaxial grains; bonding the epitaxial grains to the pixel electrodes using the conductive bonding layer; and forming respective light-emitting elements on the pixel electrodes by etching the epitaxial grains.

[0025] In an embodiment, the transferring the wafer dies to the carrier substrate may include aligning the wafer dies with the respective unit regions of the carrier substrate.

[0026] In an embodiment, the backplane substrate may further include a first bonding electrode disposed on the pixel electrode, and the epitaxial grain may be bonded to the first bonding electrode by a TLP bonding method or a TC bonding method.

[0027] In an embodiment, the method for manufacturing a display device may further include: forming a second bonding electrode between the first bonding electrode and the light emitting element by etching the conductive bonding layer.

[0028] According to an embodiment, the epitaxial wafer may be divided into sizes corresponding to the area of ​​each unit region of the backplane substrate and transferred to a carrier substrate, and the epitaxial grains may be bonded to each unit region of the backplane substrate and etched to form a light-emitting element of a pixel.

[0029] By the method for manufacturing a display device according to the embodiment, the use efficiency of the wafer substrate for the growth of the epitaxial thin film can be increased, and the manufacturing cost of the display panel can be reduced. The manufacturing process of the display panel can be facilitated and / or simplified, and the alignment error related to the position where the light-emitting element is formed can be prevented or reduced. Therefore, the manufacturing efficiency of the display panel including the light-emitting element and the display device including the display panel can be increased, and the output of the display panel and the display device can be improved.

[0030] However, the effects according to the present disclosure are not limited to the effects described above, and various other effects are incorporated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0032] Figure 1 is a schematic perspective view showing a display device according to an embodiment;

[0033] Figure 2 It is shown Figure 1 A schematic plan view of an example of a region A;

[0034] Figure 3 is a diagram showing the display panel along Figure 2 A schematic cross-sectional view of an example of a cross section taken along line X1-X1' in FIG.

[0035] Figure 4 is a schematic cross-sectional view showing a light emitting element according to an embodiment;

[0036] Figure 5 is a schematic cross-sectional view showing a light emitting element according to an embodiment;

[0037] Figure 6 is a schematic cross-sectional view showing a light emitting element according to an embodiment;

[0038] Figure 7 is a flowchart showing a method of manufacturing a display device according to an embodiment;

[0039] Figures 8 to 22 is a view for describing a method for manufacturing a display panel according to an embodiment;

[0040] Fig.23 is a schematic diagram showing a virtual reality device including a display device according to an embodiment;

[0041] Fig.24 is a schematic diagram showing a smart device including a display device according to an embodiment;

[0042] Fig.25 is a schematic diagram showing an instrument panel and a center instrument panel of a vehicle including a display device according to an embodiment; and

[0043] Fig.26 is a schematic diagram showing a transparent display device including the display device according to the embodiment. DETAILED DESCRIPTION

[0044] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments are shown. However, the present disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the scope of the present disclosure to those skilled in the art.

[0045] In the drawings, the size, thickness, ratio and magnitude of elements may be exaggerated for convenience of description and clarity. The same reference numerals refer to the same elements throughout.

[0046] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0047] In the specification and claims, for the purpose of its meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in a conjunction or disjunction sense and may be understood to be equivalent to "and / or".

[0048] In the specification and claims, for the purpose of its meaning and interpretation, the phrase "at least one of" is intended to include the meaning of "at least one selected from the group of". For example, "at least one of A and B" can be understood to mean "A, B, or A and B".

[0049] It should be understood that although the terms first, second, etc. can be used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the present disclosure, the first element can be referred to as the second element, and similarly, the second element can be referred to as the first element.

[0050] It will also be understood that when an element or layer is referred to as being “on” another element or layer, it can be directly on the other element or layer, or intervening layers may also be present. Throughout the specification, the same reference numerals refer to the same components.

[0051] The term "overlap" or "overlapped" means that the first object can be above or below the second object or on one side of the second object, or vice versa. In addition, the term "overlap" or "overlapped" may include stacking, stacking, facing or facing, extending over, covering or partially covering, or any other suitable term as will be appreciated and understood by those of ordinary skill in the art.

[0052] The terms "facing" and "facing" indicate that a first element may be directly or indirectly opposed to a second element. In the case where a third element is interposed between the first and second elements, the first and second elements may be understood to be indirectly opposed to each other, although still facing each other.

[0053] When an element is described as “not overlapping or to not overlap” another element, this may include the elements being spaced apart, offset or separated from each other, or any other suitable terminology as would be appreciated and understood by one of ordinary skill in the art.

[0054] When used in this specification, the terms “comprises, comprising, includes and / or including,” “has, have and / or having” and variations thereof indicate the presence of stated features, integers, steps, operations, elements, components and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0055] As used herein, "about" or "approximately" includes the stated value and means within the range of acceptable deviations for the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0056] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It should also be understood that, unless so explicitly defined herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense.

[0057] It should be understood that when an element (or region, layer or part, etc.) is referred to as being "on" another element, "connected to" or "coupled to" another element in this specification, the element can be directly set on the other element, directly connected to or coupled to the other element, or an intermediate element can be set between the element and the other element.

[0058] It should be understood that the term "connected to" or "coupled to" may include a physical connection or an electrical connection or a physical coupling or an electrical coupling.

[0059] The features of each of the various embodiments may be partially or completely combined with each other and may interact with each other technically differently, and the respective embodiments may be implemented independently of each other or may be implemented together in association with each other.

[0060] Figure 1is a schematic perspective view showing a display device 10 according to the embodiment. Figure 2 It is shown Figure 1 A schematic plan view of an example of area A. Figure 3 is a diagram showing the display panel 100 along Figure 2 Schematic cross-sectional view of an example of a cross section taken along line X1 - X1 ′ in FIG.

[0061] Figures 1 to 3 An embodiment in which the display device 10 is a light emitting diode on silicon (LEDoS) is shown, in which a light emitting diode as a light emitting element LE is arranged on a semiconductor circuit board formed by a semiconductor process using a silicon wafer (for example, a backplane substrate 110 formed based on a silicon wafer such as a pixel circuit PXC on the display panel 100). However, the device including the light emitting element LE according to the embodiment is not limited thereto. For example, the light emitting element LE manufactured according to the embodiment can be applied to display devices of other types and / or structures, or to devices of other types and / or structures (such as lighting devices). As an example, refer to Figures 4 to 19 The described embodiments may also be applied to the manufacture of devices including other types and / or structures of light emitting elements LE.

[0062] exist Figures 1 to 3 , the first direction DR1 may refer to a transverse direction of the display panel 100, and the second direction DR2 may refer to a longitudinal direction of the display panel 100. The third direction DR3 may refer to a thickness direction of the display panel 100.

[0063] First, refer to Figure 1 and Figure 2 , the display device 10 according to the embodiment may include a display panel 100 including a display area DA and a non-display area NDA.

[0064] In a plan view, the display panel 100 may have a rectangular shape having long sides in the first direction DR1 and short sides in the second direction DR2. However, the shape of the display panel 100 in a plan view is not limited thereto, and the display panel 100 may also have other shapes. For example, in a plan view, the display panel 100 may have other polygonal shapes, a circular shape, an elliptical shape, or an irregular shape other than a rectangular shape.

[0065] The display area DA may be an area in which an image is displayed, and the non-display area NDA may be an area in which an image is not displayed. In an embodiment, the shape of the display area DA in a plan view may follow the shape of the display panel 100 in a plan view. Figure 11 has shown that the shape of the display area DA in the plan view is a rectangular shape. The display area DA may be disposed in the central area of ​​the display panel 100. The non-display area NDA may be disposed around the display area DA. As an example, the non-display area NDA may surround the display area DA.

[0066] The display area DA may include pixels PX. Each pixel PX may include at least two light emitting elements LE.

[0067] In an embodiment, each pixel PX may include three light emitting elements LE. For example, each pixel PX may include a first light emitting element LE1, a second light emitting element LE2, and a third light emitting element LE3. The number and / or type of light emitting elements LE provided to each of the plurality of pixels PX may be variously changed according to the embodiment.

[0068] In an embodiment, each pixel PX may include a light emitting element LE that emits light of different colors. As an example, the first light emitting element LE1, the second light emitting element LE2, and the third light emitting element LE3 may emit light of different colors.

[0069] The first light emitting element LE1 may emit a first light. The first light may be red light. For example, a main peak wavelength (R-peak) of the first light may be in a range of about 600 nm to about 750 nm, but the embodiment is not limited thereto.

[0070] The second light emitting element LE2 may emit a second light. The second light may be green light. For example, a main peak wavelength (G-peak) of the second light may be in the range of about 480 nm to about 560 nm, but the embodiment is not limited thereto.

[0071] The third light emitting element LE3 may emit a third light. The third light may be blue light. For example, a main peak wavelength (B-peak) of the third light may be in the range of about 370 nm to about 460 nm, but the embodiment is not limited thereto.

[0072] In an embodiment, the first light emitting element LE1, the second light emitting element LE2, and the third light emitting element LE3 may emit light of the same color. On at least one of the first light emitting element LE1, the second light emitting element LE2, and the third light emitting element LE3, a light conversion layer may be provided, the light conversion layer including a light conversion element (e.g., quantum dots) for converting the color of light emitted from the at least one light emitting element LE (or a wavelength band corresponding to the color) into light of another color (or a wavelength band corresponding to another color).

[0073] In an embodiment, the first light emitting element LE1, the second light emitting element LE2, and the third light emitting element LE3 of each pixel PX may be sequentially arranged in the first direction DR1. In an embodiment, the first light emitting element LE1 may be arranged (or arranged) in the second direction DR2. The second light emitting element LE2 may be arranged in the second direction DR2. The third light emitting element LE3 may be arranged in the second direction DR2. For example, in each pixel column extending along the second direction DR2, the first light emitting element LE1, the second light emitting element LE2, or the third light emitting element LE3 may be arranged. The arrangement structure of the pixel PX and the arrangement structure of the light emitting element LE provided in the pixel PX may be changed differently according to the embodiment.

[0074] In the embodiment, the light emitting elements LE may be arranged at substantially equal intervals in the display area DA, but the embodiment is not limited thereto. For example, the positions and / or arrangement intervals of the light emitting elements LE may be variously changed according to the embodiment.

[0075] In an embodiment, the sizes (e.g., areas) of the light emitting elements LE may be substantially the same as each other. For example, the first light emitting element LE1, the second light emitting element LE2, and the third light emitting element LE3 may have substantially the same size. However, the embodiment is not limited thereto, and the size of each of the plurality of light emitting elements LE, and the area of ​​the emission region corresponding to the light emitting element LE, etc. may be changed differently according to the embodiment.

[0076] In the embodiment, the light emitting element LE may have a circular shape in a plan view, but the embodiment is not limited thereto. For example, the light emitting element LE may have a rectangular shape or other polygonal shape, an elliptical shape, or an irregular shape. The light emitting element LE may have substantially the same shape in a plan view, or may have different shapes for each group in a plan view.

[0077] The non-display area NDA may include a first common voltage supply area CVA1, a second common voltage supply area CVA2, a first pad area PDA1, a second pad area PDA2, and a peripheral area PHA.

[0078] The first common voltage supply area CVA1 may be disposed between the first pad area PDA1 and the display area DA. The second common voltage supply area CVA2 may be disposed between the second pad area PDA2 and the display area DA. Each of the first common voltage supply area CVA1 and the second common voltage supply area CVA2 may include a common electrode (e.g., Figure 3The common electrode CME of the display area DA may be connected to a common electrode connection portion CVS. For example, the common electrode may extend from the display area DA to the first common voltage supply area CVA1 and the second common voltage supply area CVA2 and may be electrically connected to the common electrode connection portion CVS. The common voltage may be supplied to the common electrode through the common electrode connection portion CVS.

[0079] The common electrode connection portions CVS may be disposed in a common voltage supply area (eg, first common voltage supply area CVA1 and / or second common voltage supply area CVA2 ) of the non-display area NDA. The common electrode connection portions CVS may each include a conductive material (eg, a metal material such as aluminum (Al)). Figure 1 and Figure 2 The display device 10 in which the common electrode connection portion CVS is located in the non-display area NDA is shown, but the embodiment is not limited thereto. For example, the common electrode connection portion CVS may also be located in the display area DA. As an example, the common electrode connection portion CVS may be located in a pixel area or between pixel areas.

[0080] The common electrode connection portion CVS of the first common voltage supply area CVA1 may be electrically connected to any one of the plurality of first pads PD1 of the first pad area PDA1. For example, the common electrode connection portion CVS of the first common voltage supply area CVA1 may receive a common voltage from any one of the plurality of first pads PD1 of the first pad area PDA1.

[0081] The first pads PD1 may be disposed in the first pad area PDA1. The first pads PD1 may be connected to a circuit board (not shown) through a conductive connection member. For example, the first pads PD1 may be electrically connected to a circuit pad provided on the circuit board through wiring.

[0082] The common electrode connection portion CVS of the second common voltage supply area CVA2 may be electrically connected to any one of the plurality of second pads of the second pad area PDA2. For example, the common electrode connection portion CVS of the second common voltage supply area CVA2 may receive a common voltage from any one of the plurality of second pads of the second pad area PDA2. In an embodiment, the display panel 100 may not include the second common voltage supply area CVA2.

[0083] The first pad area PDA1 may be disposed at one side (eg, an upper side) of the display panel 100. The first pad area PDA1 may include first pads PD1 connected to an external circuit board.

[0084] The second pad area PDA2 may be disposed on the other side (eg, lower side) of the display panel 100. The second pad area PDA2 may include a second pad connected to an external circuit board. In an embodiment, the display panel 100 may not include the second pad area PDA2.

[0085] The second pad may be disposed in the second pad area PDA2 of the non-display area NDA. The second pad may be connected to a circuit board (not shown) through a conductive connection member. For example, the second pad may be electrically connected to a circuit pad provided on the circuit board through wiring.

[0086] The peripheral area PHA may be a remaining area of ​​the non-display area NDA except for the first common voltage supply area CVA1, the second common voltage supply area CVA2, the first pad area PDA1, and the second pad area PDA2. The peripheral area PHA may surround the first common voltage supply area CVA1, the second common voltage supply area CVA2, the first pad area PDA1, and the second pad area PDA2, and the display area DA.

[0087] Reference Figure 3 as well as Figure 1 and Figure 2 , the display panel 100 may include a backplane substrate 110 and a light emitting element layer 120. In an embodiment, the display panel 100 may further include an optical structure (or light emitting structure) provided on the light emitting element layer 120, for example, a lens type optical structure LS.

[0088] According to an embodiment, the display panel 100 may further include additional components. As an example, within the spirit and scope of the present disclosure, the display panel 100 may further include a light conversion layer for converting the color and / or wavelength of light emitted from at least some of the light emitting elements LE, and a color filter layer for controlling each emission area EA to emit light of a selectable color, etc.

[0089] The display panel 100 may include an emission area EA located in the display area DA. Each of the plurality of emission areas EA may include at least one light emitting element LE. For example, the emission area EA may include a first emission area EA1 in which at least one first light emitting element LE1 is provided, a second emission area EA2 in which at least one second light emitting element LE2 is provided, and a third emission area EA3 in which at least one third light emitting element LE3 is provided. In an embodiment, the first light, the second light, and the third light may be emitted from the first emission area EA1, the second emission area EA2, and the third emission area EA3, respectively.

[0090] The backplane substrate 110 may include a display area DA including an emission area EA. In an embodiment, the backplane substrate 110 may be a semiconductor circuit board formed by a semiconductor process using a silicon wafer. For example, a silicon wafer may be used as a base member for forming the display panel 100.

[0091] The backplane substrate 110 may include a pixel circuit PXC and a pixel electrode PXE provided in the display area DA. For example, at least one light emitting element LE may be provided in each emission area EA of the display panel 100, and the backplane substrate 110 may include a pixel circuit PXC and a pixel electrode PXE connected (e.g., electrically connected) to the respective light emitting elements LE provided in the respective emission areas EA.

[0092] In an embodiment, the backplane substrate 110 may further include a first bonding electrode BOE1 (also referred to as a "first contact electrode" or a "first connection electrode") disposed on each pixel electrode PXE. In an embodiment, the backplane substrate 110 may further include a first insulating layer INS1 disposed around the pixel electrode PXE and / or a second insulating layer INS2 disposed around the first bonding electrode BOE1.

[0093] The pixel circuit PXC may be provided in the display area DA so as to correspond to a region in which a corresponding pixel PX and / or emission area EA is formed. In an embodiment, each of the plurality of pixel circuits PXC may include a complementary metal oxide semiconductor (CMOS) circuit formed using a semiconductor process.

[0094] Each of the plurality of pixel circuits PXC may include at least one transistor formed by a semiconductor process. Each of the plurality of pixel circuits PXC may also include at least one capacitor formed by a semiconductor process.

[0095] The pixel circuits PXC may be electrically connected to respective pixel electrodes PXE. For example, the pixel circuits PXC and the pixel electrodes PXE may be connected to each other so as to correspond to each other in a one-to-one manner. Each of the plurality of pixel circuits PXC may apply a pixel voltage to the pixel electrode PXE connected thereto.

[0096] The pixel electrodes PXE may be connected to respective pixel circuits PXC. The pixel electrodes PXE may be provided individually in respective emission areas EA and electrically connected to the light emitting elements LE located in the respective emission areas EA. Therefore, the light emitting elements LE provided in the respective emission areas EA may be individually and / or independently controlled.

[0097] Each of the plurality of pixel electrodes PXE may be disposed on a pixel circuit PXC corresponding thereto. In an embodiment, each of the plurality of pixel electrodes PXE may be an electrode integrated with the pixel circuit PXC and exposed from the pixel circuit PXC. For example, each of the plurality of pixel electrodes PXE may protrude from the upper surface of the pixel circuit PXC. Each of the plurality of pixel electrodes PXE may receive a pixel voltage supplied from the pixel circuit PXC. The pixel electrodes PXE may each include a conductive material (e.g., a metal material such as aluminum (Al)).

[0098] In an embodiment, the first insulating layer INS1 may be disposed around the pixel electrode PXE. The first insulating layer INS1 may be provided on an upper surface of a semiconductor circuit board on which the pixel circuit PXC is formed. In an embodiment, the first insulating layer INS1 may be disposed between the pixel electrodes PXE in a form in which it surrounds the pixel electrode PXE.

[0099] The first insulating layer INS1 may expose at least a portion of each of the plurality of pixel electrodes PXE. For example, the first insulating layer INS1 may include an opening corresponding to the pixel electrode PXE and expose the upper surface of the pixel electrode PXE. The first insulating layer INS1 may include a silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al x O y ) or inorganic insulating materials such as aluminum nitride (AlN) or other insulating materials.

[0100] The first bonding electrode BOE1 may be provided separately in the respective emission areas EA so as to be located on the respective pixel electrodes PXE. The first bonding electrode BOE1 may be electrically connected to the respective pixel electrodes PXE. The first bonding electrode BOE1 may be electrically connected to the light emitting elements LE located in the respective emission areas EA. The light emitting elements LE may be connected to the respective pixel circuits PXC through the first bonding electrode BOE1.

[0101] The first bonding electrodes BOE1 may each include a conductive bonding material suitable for bonding or adhering the light emitting element LE to the pixel electrode PXE. As an example, each of the plurality of first bonding electrodes BOE1 may be a single-layer electrode or a multi-layer electrode including gold (Au), copper (Cu), aluminum (Al), tin (Sn) or other metal materials (e.g., bonding metals). In an embodiment, in the case where the backplane substrate 110 does not include the first bonding electrode BOE1 and the light emitting element LE is directly bonded or adhered to the pixel electrode PXE, the pixel electrode PXE may each include a conductive material (e.g., a metal material suitable for use as a bonding metal) that can be appropriately connected to the light emitting element LE by a bonding process or an adhesion process, etc. within the spirit and scope of the present disclosure.

[0102] In an embodiment, the second insulating layer INS2 may be disposed around the first bonding electrode BOE1. The second insulating layer INS2 may be provided on the upper surface of the semiconductor circuit board on which the pixel circuit PXC, the pixel electrode PXE and / or the first insulating layer INS1 are formed. In an embodiment, the second insulating layer INS2 may be disposed between the first bonding electrodes BOE1 in a form in which it surrounds the first bonding electrode BOE1.

[0103] The second insulating layer INS2 may expose at least a portion of each of the plurality of first bonding electrodes BOE1. For example, the second insulating layer INS2 may include an opening corresponding to the first bonding electrode BOE1 and expose the upper surface of the first bonding electrode BOE1. The second insulating layer INS2 may include a silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al x O y ) or inorganic insulating materials such as aluminum nitride (AlN) or other insulating materials.

[0104] The backplane substrate 110 may also include Figure 1 and Figure 2 In the embodiment, the backplane substrate 110 may further include a common electrode connection portion CVS, a first pad PD1, a second pad PD1, and the like in the non-display area NDA.

[0105] The light emitting element layer 120 may include a second bonding electrode BOE2, a light emitting element LE, and a common electrode CME. In an embodiment, the light emitting element layer 120 may further include an organic film ORL disposed around the light emitting element LE and / or a third insulating layer INS3 disposed on the common electrode CME.

[0106] In an embodiment, the light emitting element layer 120 may further include additional components. For example, the light emitting element layer 120 may further include a reflective layer and a light blocking layer provided between the light emitting elements LE and / or on the side surfaces of the light emitting elements LE.

[0107] The second bonding electrode BOE2 may be provided at a position corresponding to the respective pixel electrode PXE and electrically connected to the respective pixel electrode PXE. For example, the second bonding electrode BOE2 may be provided on the first bonding electrode BOE1 provided on the respective pixel electrode PXE. The second bonding electrode BOE2 may be individually patterned in a form corresponding to the respective pixel electrode PXE and / or the first bonding electrode BOE1. For example, the second bonding electrode BOE2 may be patterned to have a size and / or shape corresponding to the respective pixel electrode PXE and / or the first bonding electrode BOE1 and be separated from each other, and may be provided on the respective first bonding electrode BOE1.

[0108] The second bonding electrodes BOE2 may each include a conductive bonding material suitable for bonding or adhering the light emitting element LE to the first bonding electrode BOE1 (or the pixel electrode PXE). As an example, each of the plurality of second bonding electrodes BOE2 may be a single-layer electrode or a multi-layer electrode including gold (Au), copper (Cu), aluminum (Al), tin (Sn) or other metal materials (e.g., bonding metals).

[0109] The light emitting elements LE may be disposed on the respective second bonding electrodes BOE2. The light emitting elements LE may be electrically connected between the respective pixel electrodes PXE and the common electrode CME.

[0110] The light emitting element LE may include a semiconductor layer grown on a semiconductor substrate (e.g., a wafer substrate) by epitaxial growth. For example, the light emitting element LE may include a first semiconductor layer doped with a first conductivity type, a second semiconductor layer doped with a second conductivity type, and an active layer disposed between the first semiconductor layer and the second semiconductor layer.

[0111] The light emitting element LE may be formed of an epitaxial thin film of a wafer die divided from an epitaxial wafer, and may be patterned in a unit region corresponding to each display panel 100 and formed in a respective emission area EA. A detailed description of the structure and manufacturing method of the light emitting element LE according to the embodiment will be provided later.

[0112] The organic film ORL may be provided around the light emitting element LE. As an example, the organic film ORL may be provided between the emission areas EA so as to surround the emission area EA in which the light emitting element LE is provided, and may surround the light emitting element LE and the second bonding electrode BOE2. In an embodiment, the organic film ORL may be a filler filling a gap between the light emitting elements LE. The organic film ORL may expose a portion (e.g., an upper surface) of the light emitting element LE.

[0113] The organic film ORL may include an insulating material. For example, the organic film ORL may be a single-layer organic insulating film or a multi-layer organic insulating film including acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or other organic insulating materials.

[0114] The common electrode CME may be disposed on an upper portion of the light emitting element LE that is not covered by the organic film ORL. In an embodiment, within the spirit and scope of the present disclosure, the common electrode CME may be completely disposed in the display area DA so as to cover the light emitting element LE and the organic film ORL, etc. The common electrode CME may be a common layer that is commonly formed in the light emitting element LE of the display area DA and the pixel PX including the light emitting element LE and / or connected to the light emitting element LE of the display area DA and the pixel PX including the light emitting element LE.

[0115] The common electrode CME can be electrically connected to a Figure 1 and Figure 2 The common electrode CME may receive the common voltage supplied through the common electrode connection portion CVS in the first common voltage supply area CVA1 and / or the second common voltage supply area CVA2. Therefore, the common electrode CME may receive the common voltage supplied through the common electrode connection portion CVS.

[0116] The common electrode CME may include a transparent conductive material through which light can be transmitted. For example, the common electrode CME may be made of indium tin oxide (ITO), indium zinc oxide (IZO), or other transparent conductive materials. In an embodiment, the common electrode CME may be used as a cathode electrode (or anode electrode) of each of the plurality of light emitting elements LE.

[0117] The third insulating layer INS3 may be disposed on the common electrode CME. For example, the third insulating layer INS3 may be a coating layer completely disposed in the display area DA so as to cover the common electrode CME. The third insulating layer INS3 may include a silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al x O y) or inorganic insulating materials such as aluminum nitride (AlN) or other insulating materials.

[0118] In an embodiment, the display panel 100 may include a lens type optical structure LS provided over the light emitting element layer 120. The display panel 100 may further include a protection layer PSV covering the lens type optical structure LS.

[0119] The lens type optical structure LS may be disposed in the respective emission areas EA so as to overlap with the light emitting element LE. In an embodiment, the lens type optical structure LS may be a convex lens type optical structure provided above the light emitting element LE, but the type and / or shape of the optical structure is not limited thereto. By disposing the lens type optical structure LS above the light emitting element LE, the light emission characteristics of the pixel PX may be adjusted and / or improved.

[0120] The lens-type optical structures LS may each be made of a transparent material so that light incident from the light emitting element LE may be transmitted therethrough. As an example, the lens-type optical structures LS may each be made of glass, plastic, ceramic or other materials, and may be made of an optical material having a high refractive index.

[0121] The protective layer PSV may be disposed on the lens-type optical structure LS so as to cover the lens-type optical structure LS. The protective layer PSV may be made of a transparent and durable material (e.g., plastic or organic glass, optical glass, ceramic, etc.), and the material of the protective layer PSV is not particularly limited as long as it is suitable for protecting the lens-type optical structure LS, etc. within the spirit and scope of the present disclosure. Figure 3 An embodiment in which the protective layer PSV has a bend corresponding to the shape of the lens type optical structure LS has been disclosed, but the embodiment is not limited thereto. For example, the protective layer PSV may be formed in a shape in which the protective layer PSV may flatten the upper surface of the display panel 100 on which the lens type optical structure LS and the like are formed.

[0122] Figure 4 is a schematic cross-sectional view showing a light emitting element LE according to the embodiment. Figure 5 is a schematic cross-sectional view showing a light emitting element LE according to the embodiment. Figure 6 is a schematic cross-sectional view showing a light emitting element LE according to an embodiment. For example, Figure 5 Shown with Figure 4 The embodiments are different regarding the shape of the light emitting element LE, and Figure 6 Shown with Figure 4 The embodiments are different regarding the arrangement direction of the light emitting elements LE.

[0123] Reference Figures 4 to 6, the light emitting element LE may include a first semiconductor layer SEM1, an active layer MQW, and a second semiconductor layer SEM2 sequentially arranged and / or stacked along a third direction DR3. In an embodiment, the light emitting element LE may further include a contact electrode CTE provided at one end or one end thereof. For example, the light emitting element LE may further include a contact electrode CTE provided at one end or one end thereof where the first semiconductor layer SEM1 is located.

[0124] According to an embodiment, the light emitting element LE may further include additional layers. As an example, within the spirit and scope of the present disclosure, the light emitting element LE may further include an electron blocking layer disposed between the first semiconductor layer SEM1 and the active layer MQW, and a superlattice layer disposed between the active layer MQW and the second semiconductor layer SEM2.

[0125] In an embodiment, the light emitting element LE may be an inorganic light emitting element made of an inorganic material. For example, the light emitting element LE may be an inorganic light emitting diode made of a nitride semiconductor material such as GaN, AlGaN, InGaN, AlInGaN, AlN or InN, a phosphide semiconductor material such as GaP, GaInP, AlGaP, AlGaP, AlGaInP, AlP or InP, or other inorganic materials.

[0126] The contact electrode CTE may be provided and / or formed at one end or one end of the light emitting element LE where the first semiconductor layer SEM1 is provided. For example, the contact electrode CTE may be provided and / or formed at one surface or one surface of the first semiconductor layer SEM1. Within the spirit and scope of the present disclosure, the contact electrode CTE may be an electrode for protecting the first semiconductor layer SEM1 and smoothly connecting the first semiconductor layer SEM1 to at least one circuit element, electrode, wiring, conductive layer, etc. The contact electrode CTE may include metal, metal oxide, or other conductive materials.

[0127] The first semiconductor layer SEM1 may be disposed on the contact electrode CTE. In an embodiment, the first semiconductor layer SEM1 may include a nitride semiconductor material or a phosphide semiconductor material. For example, the first semiconductor layer SEM1 may include a nitride semiconductor material including at least one of GaN, AlGaN, InGaN, AlInGaN, AlN, and InN, or a phosphide semiconductor material including at least one of GaP, GaInP, AlGaP, AlGaInP, AlP, and InP. The first semiconductor layer SEM1 may also include other materials.

[0128] The first semiconductor layer SEM1 may include a semiconductor material doped with a first conductive type dopant. As an example, the first semiconductor layer SEM1 may be made of GaN (eg, p-GaN) doped with a first conductive type dopant (eg, p-type dopant) such as Mg, Zn, Ca, or Ba.

[0129] The active layer MQW may be disposed on the first semiconductor layer SEM1. The active layer MQW may emit light by recombination of electron-hole pairs according to an electrical signal applied via the first and second semiconductor layers SEM1 and SEM2. For example, the active layer MQW may be a light emitting layer of the light emitting element LE.

[0130] The active layer MQW may include a material having a single quantum well structure or a multi-quantum well structure. In the case where the active layer MQW may include a material having a multi-quantum well structure, the active layer MQW may have a structure in which a plurality of well layers and barrier layers are alternately stacked with each other. Depending on the wavelength band of the emitted light, the active layer MQW may also include other group III semiconductor materials to group V semiconductor materials.

[0131] In an embodiment, the active layer MQW may include a nitride semiconductor material or a phosphide semiconductor material. For example, the active layer MQW may include a nitride semiconductor material including at least one of GaN, AlGaN, InGaN, InGaAlN, AlN, InN and AlInN, or a phosphide semiconductor material including at least one of GaP, GaInP, AlGaP, AlGaInP, AlP and InP. As an example, the well layer may be made of InGaN, and the barrier layer may be made of GaN or AlGaN, but the embodiment is not limited thereto. In the case where the active layer MQW may include InGaN, the color of the light emitted from the light emitting element LE may be controlled by adjusting the content of indium (In). The active layer MQW may also include other materials.

[0132] In an embodiment, Figure 2 and Figure 3 The active layers MQW of the first light emitting element LE1, the second light emitting element LE2, and the third light emitting element LE3 shown in the figure may emit light of the same color (e.g., blue light). In an embodiment, the active layers MQW of the first light emitting element LE1, the second light emitting element LE2, and the third light emitting element LE3 may emit light of different colors (e.g., red light, green light, and blue light).

[0133] The second semiconductor layer SEM2 may be disposed on the active layer MQW. In an embodiment, the second semiconductor layer SEM2 may include a nitride semiconductor material or a phosphide semiconductor material. For example, the second semiconductor layer SEM2 may include a nitride semiconductor material including at least one of GaN, AlGaN, InGaN, AlInGaN, AlN, and InN, or a phosphide semiconductor material including at least one of GaP, GaInP, AlGaP, AlGaInP, AlP, and InP. The second semiconductor layer SEM2 may also include other materials.

[0134] The second semiconductor layer SEM2 may include a semiconductor material doped with a second conductive type dopant. As an example, the second semiconductor layer SEM2 may be made of GaN (eg, n-GaN) doped with a second conductive type dopant (eg, n-type dopant) such as Si, Ge, Se, or Sn.

[0135] In an embodiment, the first semiconductor layer SEM1 and the second semiconductor layer SEM2 may have different thicknesses in the thickness direction (e.g., the third direction DR3) of the light emitting element LE. As an example, in the thickness direction of the light emitting element LE, the second semiconductor layer SEM2 may have a greater thickness than the first semiconductor layer SEM1. Therefore, the active layer MQW may be located closer to the first end (e.g., p-type end) of the light emitting element LE provided with the first semiconductor layer SEM1, etc. than the second end (e.g., n-type end) of the light emitting element LE provided with the second semiconductor layer SEM2.

[0136] In an embodiment, the light emitting element LE may be a vertical micro light emitting diode (LED) extending and / or stacked in the third direction DR3. For example, the light emitting element LE may be a micro LED, each of which has a length in the first direction DR1, a length in the second direction DR2, and a length in the third direction DR3 of several micrometers (μm) to several hundred micrometers (μm). In an embodiment, each of the length of the light emitting element LE in the first direction DR1, the length of the light emitting element LE in the second direction DR2, and the length of the light emitting element LE in the third direction DR3 may be about 100 μm or less.

[0137] In an embodiment, the light emitting element LE may include Figure 4 For example, the light emitting element LE may be patterned by vertical etching and may have a rectangular or square cross-sectional shape, with the width of the upper surface and the width of the lower surface being substantially the same as each other.

[0138] According to the embodiment, the shape of the light emitting element LE may be variously changed. For example, the light emitting element LE may also have a cross-sectional shape in which the width of the upper surface and the width of the lower surface thereof are different from each other.

[0139] In an embodiment, the light emitting element LE may have Figure 5 For example, the light emitting element LE may also have an inverse trapezoidal cross-sectional shape in which the width of the upper surface is greater than the width of the lower surface.

[0140] In an embodiment, the light emitting element LE may be disposed on the backplane substrate 110 (see Figure 3 ), so that the first semiconductor layer SEM1 is located below the active layer MQW, and the second semiconductor layer SEM2 is located above the active layer MQW, as shown in FIG. Figure 4 For example, a light emitting element LE may be disposed in each emission area EA (see Figure 3 ), so that the contact electrode CTE (or the first semiconductor layer SEM1) and Figure 3 The second bonding electrode BOE2 of the semiconductor layer 100 is in contact with the second bonding electrode BOE2, and the second semiconductor layer SEM2 (or another contact electrode provided on the semiconductor layer SEM2) is in contact with the common electrode CME. In this case, the common electrode CME may be a cathode electrode.

[0141] In an embodiment, the light emitting element LE may be disposed on the backplane substrate 110 such that the second semiconductor layer SEM2 is located below the active layer MQW, and the first semiconductor layer SEM1 is located above the active layer MQW, as shown in FIG. Figure 6 For example, the light emitting element LE may be disposed in each emission area EA so that the second semiconductor layer SEM2 (or another contact electrode provided on the semiconductor layer SEM2) is in contact with the Figure 3 The second bonding electrode BOE2 of the semiconductor layer 100 is in contact with the contact electrode CTE (or the first semiconductor layer SEM1 ), and the contact electrode CTE (or the first semiconductor layer SEM1 ) is in contact with the common electrode CME. In this case, the common electrode CME may be an anode electrode.

[0142] In an embodiment, the arrangement direction of the light emitting element LE disposed on the second bonding electrode BOE2 can be adjusted by adjusting the direction in which each wafer grain (or epitaxial grain) used to form the light emitting element LE is transferred to the carrier substrate. As an example, the surface on which the bonding material is to be formed can be selected by a process of transferring the wafer grain (or epitaxial grain) to the carrier substrate once or twice or more.

[0143] The structure, material, size, shape, etc. of the light emitting element LE are not limited to the above-mentioned embodiments. For example, the structure, material, size, shape, etc. of the light emitting element LE may be variously changed according to the embodiments.

[0144] Figure 7 is a diagram showing the manufacture of a display device 10 (see FIG. Figure 1 ) is a flowchart of a method. For example, Figure 7 FIG. 1 is a diagram showing a method for manufacturing a display panel 100 (see FIG. 1 ) for manufacturing a display device 10 according to an embodiment. Figure 1 ) is a flow chart of a method. Figures 8 to 22 is used to describe a method for manufacturing a display panel 100 (see Figure 1 ) method. For example, Figures 8 to 22 Given steps for forming the display panel 100 are each shown in the form of a schematic perspective view, a schematic cross-sectional view, or a schematic plan view.

[0145] Reference Figures 7 to 9 and Figures 1 to 6 , can manufacture epitaxial wafer EWF (including epitaxial thin film EPIL Figure 7 , or step S110 in the above process.

[0146] For example, Figure 8 As shown in , a wafer substrate WAF (or another type of substrate suitable for epitaxial growth) may be prepared, and an epitaxial thin film EPIL may be formed on the wafer substrate WAF. Figure 8 is a schematic perspective view showing a schematic shape of an epitaxial wafer EWF.

[0147] The wafer substrate WAF may be a semiconductor substrate suitable for epitaxial growth of a semiconductor. For example, the wafer substrate WAF may be a substrate including a material such as silicon (Si), sapphire, SiC, GaN, GaAs, or ZnO. The type, material, shape, etc. of the wafer substrate WAF are not particularly limited as long as epitaxial growth for manufacturing the light emitting element LE can be smoothly performed.

[0148] like Fig. 9 As shown in FIG, the epitaxial thin film EPIL may include a second semiconductor layer SEM2, an active layer MQW, and a first semiconductor layer SEM1 sequentially disposed on a wafer substrate WAF. Fig. 9 is a schematic cross-sectional view showing a cross section of a portion of an epitaxial wafer EWF according to an embodiment.

[0149] For example, the second semiconductor layer SEM2, the active layer MQW and the first semiconductor layer SEM1 may be sequentially formed on the wafer substrate WAF by epitaxial growth. In an embodiment, the second semiconductor layer SEM2, the active layer MQW and the first semiconductor layer SEM1 may be formed by epitaxial growth using a process technology such as metal organic chemical vapor deposition (MOCVD), metal organic vapor phase epitaxy (MOVPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE) or vapor phase epitaxy (VPE).

[0150] The second semiconductor layer SEM2 may be made of the aforementioned material of the second semiconductor layer SEM2. For example, the second semiconductor layer SEM2 may be made of at least one nitride semiconductor material or a phosphide semiconductor material, and may be formed as a single semiconductor layer or a multi-layer semiconductor layer. The second semiconductor layer SEM2 may be doped to include a second conductive type dopant (e.g., an n-type dopant).

[0151] The active layer MQW may be made of the aforementioned material of the active layer MQW. For example, the active layer MQW may be made of at least one nitride semiconductor material or a phosphide semiconductor material. In an embodiment, the active layer MQW having a multi-quantum well structure may be formed by alternately and / or repeatedly forming a barrier layer and a quantum well layer on the second semiconductor layer SEM2.

[0152] The first semiconductor layer SEM1 may be made of the aforementioned material of the first semiconductor layer SEM1. For example, the first semiconductor layer SEM1 may be made of at least one nitride semiconductor material or a phosphide semiconductor material, and may be formed as a single semiconductor layer or a multi-layer semiconductor layer. The first semiconductor layer SEM1 may be doped to include a first conductive type dopant (e.g., a p-type dopant).

[0153] In an embodiment, in Figures 4 to 6 In the case of manufacturing the light emitting element LE including the contact electrode CTE in the embodiment of the present invention, a process of forming the contact electrode CTE (or a conductive layer for forming the contact electrode CTE) on the epitaxial thin film EPIL may be additionally performed. For example, the epitaxial wafer EWF may further include the contact electrode CTE formed on the first semiconductor layer SEM1, such as Fig. 9 as shown in .

[0154] The contact electrode CTE may be made of the materials of the contact electrode CTE described above. The contact electrode CTE may be formed by a process such as applying (eg, depositing) a conductive material onto the epitaxial thin film EPIL, and the method for forming the contact electrode CTE is not particularly limited.

[0155] Reference Fig.10 and Figures 1 to 9 , the epitaxial wafer EWF can be divided into wafer dies EWFD (also called "epitaxial wafer dies") ( Figure 7 As an example, a plurality of wafer dies EWFD may be manufactured by cutting the epitaxial wafer EWF. Fig.10 is a schematic perspective view showing a schematic shape of a wafer die EWFD.

[0156] The wafer die EWFD is a smaller size piece divided from the epitaxial wafer EWF, and the structure of the cross section of the wafer die EWFD may be substantially the same as the structure of the cross section of the epitaxial wafer EWF. For example, each of the plurality of wafer die EWFDs may include a wafer substrate (e.g., Fig.12 The wafer substrate WAF') (or a piece of wafer substrate WAF) and the epitaxial thin film EPIL divided into smaller sizes. Hereinafter, a piece of divided epitaxial thin film EPIL is referred to as an "epitaxial grain". For example, the wafer grain EWFD may include respective wafer substrates WAF' and respective epitaxial grains divided from the epitaxial thin film EPIL.

[0157] According to an embodiment, each of the plurality of wafer dies EWFD may or may not include a contact electrode CTE. Figures 12 to 19 The illustration of the contact electrode CTE will be omitted.

[0158] In an embodiment, each of the plurality of wafer die EWFDs may have a size corresponding to the area of ​​each unit region (e.g., an area corresponding to the area of ​​each unit region) of a backplane substrate (e.g., a backplane mother substrate to be divided into a backplane substrate 110 of each display panel 100), the backplane substrate including a plurality of unit regions for forming a plurality of display panels 100. For example, by dividing the epitaxial wafer EWF into a size corresponding to the area of ​​each unit region of a backplane substrate including a plurality of unit regions, a wafer die EWFD having a size corresponding to the area of ​​each unit region may be manufactured. In an embodiment, each of the plurality of wafer die EWFDs may have a size greater than or equal to the area of ​​a display area DA located in each unit region.

[0159] In an embodiment, after the epitaxial wafer EWF is divided into wafer dies EWFD, good products can be selected by performing evaluation (e.g., quality test) on each of the plurality of wafer dies EWFD. The wafer dies EWFD selected as good products can be used to form light emitting elements LE in each unit area through subsequent processes.

[0160] Reference Fig.11 and Figures 1 to 10 , the carrier substrate CWAF ( Figure 7 , or step S130 in the above procedure.

[0161] The carrier substrate CWAF may have a structure similar to that of a backplane substrate including a plurality of unit regions (eg, a backplane substrate 110 to be divided into each display panel 100). Figures 15 to 22The carrier substrate CWAF may have a size and / or shape corresponding to the backplane substrate 110' and is also referred to as a "backplane mother substrate"). For example, the carrier substrate CWAF may be a wafer substrate having a size corresponding to the area of ​​the backplane substrate (e.g., an area corresponding to the area of ​​the backplane substrate) and having a shape corresponding to the shape of the backplane substrate, so that the wafer die EWFD can be arranged on a unit area of ​​the backplane substrate for simultaneously manufacturing a plurality of display panels 100. In an embodiment, in a case where a pixel process for a display panel 100 or the like is to be performed on the backplane substrate (the backplane substrate is formed as a circular semiconductor substrate having a diameter of 12 inches and includes a plurality of unit areas of the backplane substrate 110 to be divided into each display panel 100), a circular carrier substrate CWAF having a diameter of approximately 12 inches may be prepared. The carrier substrate CWAF may include a unit area CELAc corresponding to a unit area of ​​the backplane substrate.

[0162] In an embodiment, an adhesive layer ADH may be provided and / or formed on one surface or surfaces of the carrier substrate CWAF. The adhesive layer ADH may be used to adhere the wafer die EWFD and the carrier substrate CWAF to each other in a subsequent process.

[0163] In an embodiment, the adhesive layer ADH may be formed of a layer suitable for being applied to an epitaxial die EWFD (or an epitaxial die EPID (see Fig.12 )) is made of a material that can be used for a process method of separation process between the epitaxial grain EPID and the carrier substrate CWAF. For example, in the case where the epitaxial grain EPID is to be separated from the carrier substrate CWAF by a laser lift-off (LLO) method, the adhesive layer ADH can be made of a material that can easily separate the epitaxial grain EPID from the carrier substrate CWAF by the LLO method. As an example, in the case where the adhesive layer ADH is made of a material whose bonding strength may be weakened due to sensitive reaction to the laser beam, such as a thermoplastic adhesive, a thermally decomposable adhesive, or an incompletely cured adhesive, the epitaxial grain EPID and the carrier substrate CWAF can be easily separated from each other by the LLO method. The separation method between the epitaxial grain EPID and the carrier substrate CWAF is not limited to the LLO method, and the adhesive layer ADH can be made of a material suitable for the selected separation method.

[0164] In an embodiment, within the spirit and scope of the present disclosure, the wafer grain EWFD (or epitaxial grain EPID) may be first manufactured to a size corresponding to the size of the unit area CELAc and transferred to the carrier substrate CWAF, the epitaxial grain EPID of the wafer grain EWFD may be bonded to the backplane substrate, and the respective epitaxial grain EPID may be patterned into a light-emitting element LE having a finer size by an etching process, etc. Therefore, restrictions on process methods that can be used for each process for adhering and separating the epitaxial grain EPID and the carrier substrate CWAF from each other or materials (e.g., adhesive) used in each process may be reduced, and the range of selection of process methods and materials may be broadened. Therefore, the adhesive layer ADH may be formed using various materials.

[0165] Reference Fig.12 and Figures 1 to 11 , the wafer die EWFD can be transferred to the carrier substrate CWAF ( Figure 7 , or step S140 in the above procedure.

[0166] The wafer die EWFD may be transferred to the carrier substrate CWAF at positions and / or intervals corresponding to the unit regions of the backplane substrate. Fig.12 As shown in , the wafer die EWFD may be aligned on one surface or one surface of the carrier substrate CWAF so as to be located in each unit area CELAc of the carrier substrate CWAF. In an embodiment, the wafer die EWFD may be adhered to the carrier substrate CWAF by an adhesive layer ADH. In an embodiment, the wafer die EWFD may be subjected to an evaluation step before being transferred to the carrier substrate CWAF, and only the wafer die EWFD selected as a good product may be transferred to the carrier substrate CWAF.

[0167] Reference Fig.13 and Figures 1 to 12 After the wafer die EWFD is transferred to the carrier substrate CWAF, a process of applying a filler FIL and a planarization process may be performed ( Figure 7 , or step S150 in the above process.

[0168] For example, the gaps between the wafer dies EWFD may be filled by applying a filler FIL onto the carrier substrate CWAF on which the wafer dies EWFD are provided, and the upper surface of the carrier substrate CWAF on which the wafer dies EWFD and the filler FIL are provided may be planarized. In an embodiment, the planarization process may be performed by a polishing process such as a chemical mechanical polishing (CMP) process, but the method for planarizing the upper surface of the carrier substrate CWAF is not limited thereto. For example, within the spirit and scope of the present disclosure, the upper surface of the carrier substrate CWAF may also be planarized by an etching process, etc.

[0169] In the process of planarizing the upper surface of the carrier substrate CWAF, the respective wafer substrates WAF' may be removed from the wafer grains EWFD. Thus, the epitaxial grains EPID may be exposed. For example, the upper surface of the epitaxial grains EPID may be exposed by performing a planarization process on the carrier substrate CWAF on which the wafer grains EWFD are provided. The filler FIL may remain on one surface or one surface of the carrier substrate CWAF in the form of filling the gaps between the epitaxial grains EPID.

[0170] In an embodiment, compared to the planarization process according to the comparative example performed in a state where the wafer grain EWFD (or epitaxial grain EPID) is etched into a fine size corresponding to the light emitting element LE, by transferring the wafer grain EWFD having a size corresponding to the size of the unit area CELAc to the carrier substrate CWAF and planarizing the upper surface of the carrier substrate CWAF, the planarization process can be facilitated and / or simplified, and defects that may occur in the manufacturing process of the light emitting element LE can be prevented or minimized.

[0171] Reference Fig.14 and Figures 1 to 13 , the bonding material can be applied to the epitaxial grain EPID ( Figure 7 , or step S160 in the above procedure.

[0172] For example, by completely applying a conductive bonding material to the upper surface of the carrier substrate CWAF on which the epitaxial grain EPID is exposed, the conductive bonding layer BDL can be formed on the epitaxial grain EPID and the filler FIL. As an example, the conductive bonding layer BDL can be formed by completely applying (e.g., depositing) gold (Au), copper (Cu), aluminum (Al), tin (Sn) or other bonding metals to the upper surface of the carrier substrate CWAF.

[0173] Reference Fig.15 and Fig.16 And further refer to Figures 1 to 14 , a backplane substrate 110 ′ ( Figure 7 , or step S170 in the above procedure. Fig.15 is a schematic cross-sectional view showing a schematic shape of a backplane substrate 110', and Fig.16 is a schematic cross-sectional view showing each unit area CELA of the backplane substrate 110 ′.

[0174] Each of the unit areas CELA of the plurality of backplane substrates 110' may include an emission area EA in which a light emitting element LE is to be formed. The backplane substrate 110' may include a pixel electrode PXE provided in the emission area EA located in each of the plurality of unit areas CELA, and the like. For example, the backplane substrate 110' may include a pixel electrode PXE provided individually in the emission area EA of each unit area CELA, a pixel circuit PXC connected to the respective pixel electrodes PXE, a first bonding electrode BOE1 disposed on the respective pixel electrodes PXE, a first insulating layer INS1 disposed around the pixel electrode PXE, and / or a second insulating layer INS2 disposed around the bonding electrode BOE1. The unit area CELA of the backplane substrate 110' may be divided into the backplane substrate 110 of the display panel 100 later.

[0175] The step of preparing the backplane substrate 110' can be performed independently of the step of manufacturing the wafer die EWFD and / or the step of preparing the carrier substrate CWAF. For example, the step of preparing the backplane substrate 110' can be performed simultaneously with the step of manufacturing the wafer die EWFD and / or the step of preparing the carrier substrate CWAF, or can be performed before or after the step of manufacturing the wafer die EWFD and / or the step of preparing the carrier substrate CWAF.

[0176] Reference Fig.17 and Figures 1 to 16 , the epitaxial grain EPID can be bonded to the backplane substrate 110' ( Figure 7 , or step S180 in the above procedure.

[0177] For example, the carrier substrate CWAF can be set on the backplane substrate 110' in a state where the epitaxial grain EPID is aligned to be positioned in each unit area CELA of the backplane substrate 110', and the carrier substrate CWAF and the backplane substrate 110' can be bonded to each other using a conductive bonding layer BDL. Therefore, the epitaxial grain EPID can be bonded to each unit area CELA of the backplane substrate 110'. The epitaxial grain EPID can be bonded to the pixel electrode PXE and the first bonding electrode BOE1 located in the emission area EA of each unit area CELA.

[0178] In an embodiment, alignment keys may be provided on the backplane substrate 110' and the carrier substrate CWAF, respectively. Therefore, the backplane substrate 110' and the carrier substrate CWAF may be easily and / or appropriately aligned and bonded to each other. For example, the epitaxial grain EPID of the carrier substrate CWAF may be aligned with the display area DA defined in the cell area CELA of the backplane substrate 110' and bonded to the backplane substrate 110'.

[0179] In an embodiment, the epitaxial grain EPID can be bonded to the first bonding electrode BOE1 of the backplane substrate 110' by a bonding process using a transient liquid phase (TLP) bonding method or a thermal compression (TC) bonding method between the backplane substrate 110' and the carrier substrate CWAF. In the case of bonding the epitaxial grain EPID to the backplane substrate 110' using the TLP bonding method or the TC bonding method, the resistance between the epitaxial grain EPID and the backplane substrate 110' (for example, the first bonding electrode BOE1 of the backplane substrate 110') can be reduced or minimized, and the performance and stability of the light-emitting element LE formed by the epitaxial grain EPID in subsequent processes can be ensured. The bonding (or adhesion) method between the backplane substrate 110' and the carrier substrate CWAF is not limited thereto, and the backplane substrate 110' and the carrier substrate CWAF can also be bonded to each other by other methods.

[0180] Reference Fig.18 and Fig.19 as well as Figures 1 to 17 , the carrier substrate CWAF can be removed from the epitaxial die EPID ( Figure 7 , or step S190 in the above procedure.

[0181] For example, the carrier substrate CWAF and the adhesive layer ADH can be removed from the epitaxial grain EPID bonded to the first bonding electrode BOE1 (or pixel electrode PXE) on the backplane substrate 110'. In an embodiment, the carrier substrate CWAF can be easily and / or appropriately removed from the epitaxial grain EPID by a laser lift-off (LLO) method. In the case of separating the carrier substrate CWAF using the LLO method, damage to the epitaxial grain EPID can be prevented or minimized, and the reliability of the light-emitting element LE formed by the epitaxial grain EPID in subsequent processes can be ensured.

[0182] However, the removal method or separation method of the carrier substrate CWAF is not limited thereto, and the carrier substrate CWAF may also be removed by other methods. For example, within the spirit and scope of the present disclosure, the carrier substrate CWAF may also be removed by a polishing process such as a CMP process or an etching process.

[0183] Reference Fig. 20 and Figures 1 to 19 , a light emitting element LE ( Figure 7 , or step S200 in the above procedure.

[0184] For example, by etching the epitaxial grains EPID, respective light emitting elements LE may be formed in the emission areas EA included in each cell area CELA. The light emitting elements LE may be formed on the pixel electrodes PXE and the first bonding electrodes BOE1 located in the respective emission areas EA.

[0185] By etching the conductive bonding layer BDL, the second bonding electrode BOE2 may be formed between the first bonding electrode BOE1 and the light emitting element LE. In an embodiment, the light emitting element LE and the second bonding electrode BOE2 may be formed to have a size and / or shape corresponding to the pixel electrode PXE and / or the first bonding electrode BOE1. For example, the light emitting element LE and the second bonding electrode BOE2 may be formed to each have an area corresponding to the area of ​​the pixel electrode PXE and the first bonding electrode BOE1, and each have a shape that follows the shape of the pixel electrode PXE and the first bonding electrode BOE1 in a plan view. However, the embodiment is not limited thereto, and the size and shape of the light emitting element LE and the second bonding electrode BOE2 may be changed differently according to the embodiment.

[0186] Reference Fig.21 and Fig. 22 as well as Figures 1 to 20 , a subsequent process for forming the light emitting element layer 120 (the subsequent process includes a process for forming a common electrode CME) may be performed ( Figure 7 , or step S210 in the above procedure.

[0187] For example, Fig.21 As shown in FIG. 1 , the organic film ORL may be formed between the light emitting elements LE in each unit area CELA. As an example, the organic film ORL may be filled between the light emitting elements LE at least in the display area DA. Thereafter, as shown in FIG. Fig. 22 As shown in , the common electrode CME and the third insulating layer INS3 may be sequentially formed on the light emitting element LE in each cell area CELA.

[0188] In an embodiment, when a display panel 100 including a light conversion layer and / or a color filter layer is to be manufactured, a process of forming the light conversion layer and / or the color filter layer over or inside the light emitting element layer 120 may be additionally performed.

[0189] In an embodiment, in order to manufacture a Figure 3 In the case of the display panel 100 having the lens type optical structure LS shown in , a process of attaching and / or forming the lens type optical structure LS and the protective layer PSV, etc., onto the light emitting element layer 120 may be additionally performed.

[0190] When the substantial manufacturing process of the display panel 100 is completed, a cell separation process ( Figure 7 , or step S220 in the above procedure.

[0191] For example, the display panels 100 formed based on one backplane substrate 110 ′ may be individually separated by cell separation. As an example, by cutting the backplane substrate 110 ′ based on the cell area CELA, the respective cells located in the cell area CELA may be separated into individual display panels 100 .

[0192] Thereafter, within the spirit and scope of the present disclosure, the display device 10 including each display panel 100 may be manufactured by additionally performing a module process or the like.

[0193] As described above, in an embodiment, the epitaxial wafer EWF may be divided in unit units (e.g., in a size corresponding to each unit region CELA or each unit) and transferred to the carrier substrate CWAF, and the epitaxial grain EPID may be bonded to each unit region CELA of the backplane substrate 110' and etched in each unit region CELA to be patterned into individual light emitting elements LE. Therefore, a light emitting element LE having a fine size may be effectively formed in the emission area EA included in each unit region CELA.

[0194] According to such an embodiment, the limitation on the size of the wafer substrate WAF used for the growth of the epitaxial thin film EPIL can be substantially eliminated, and the use efficiency of the wafer substrate WAF can be increased. For example, the epitaxial wafer EWF can be divided into a size corresponding to the size (e.g., area) of the display area DA included in each unit area CELA (e.g., the epitaxial wafer EWF can be divided into a size greater than or equal to the area of ​​the display area DA to the extent including process errors), and is used to manufacture the light-emitting element LE. Therefore, the size of the wafer substrate WAF does not need to be adjusted to the size (e.g., area) of the backplane substrate 110', so that the range of choices for the wafer substrate WAF can be widened, and the use area of ​​the wafer substrate WAF can be increased or maximized to reduce costs. As an example, by manufacturing a wafer die EWFD using a wafer substrate WAF having a size of 4 inches or 8 inches and transferring the wafer die EWFD to a carrier substrate CWAF having a size of 12 inches, the light-emitting element LE can be formed on a backplane substrate 110' having a size of 12 inches. For example, the light emitting element LE may be formed by manufacturing a wafer die EWFD using a wafer substrate WAF having substantially the same size as the backplane substrate 110 ′ (eg, a size of 12 inches) and using an epitaxial die EPID of the wafer die EWFD.

[0195] By aligning and bonding the respective epitaxial grains EPID to the respective unit areas CELA of the backplane substrate 110' in unit units, and patterning the epitaxial grains EPID into light-emitting elements LE, the difficulty of the panel process for manufacturing the display panel 100 can be reduced, and alignment errors can be prevented or reduced. For example, high-precision alignment according to the pixels PX and / or emission areas EA with fine sizes in the bonding process may become unnecessary, and after the epitaxial grains EPID are bonded to the backplane substrate 110', the respective light-emitting elements LE are formed in the emission areas EA by etching processes, etc., and therefore, the light-emitting elements LE can be easily and / or stably formed at appropriate locations. Therefore, the process efficiency of the display panel 100 and the display device 10 including the display panel 100 can be increased, and the yield of the display panel 100 and the display device 10 can be improved.

[0196] Fig.23 is a schematic diagram showing a virtual reality device 1 including a display device 10_1 according to an embodiment.

[0197] Reference Fig.23 The virtual reality device 1 according to the embodiment may be a glasses type device. The virtual reality device 1 according to the embodiment may include a display device 10_1, a left eye lens 10a, a right eye lens 10b, a support frame 20, glasses frame legs 30a and 30b, a reflective member 40, and a display device housing portion 50.

[0198] exist Fig.23 , the virtual reality device 1 including the glasses frame legs 30a and 30b has been shown, but the virtual reality device 1 according to the embodiment can also be applied to a head mounted display including a head strap that can be mounted on the user's head instead of the glasses frame legs 30a and 30b. For example, the virtual reality device 1 according to the embodiment is not limited to Fig.23 The present invention is in the form shown in , and can be applied to various other electronic devices in various forms.

[0199] The display device housing portion 50 can accommodate the display device 10_1 and the reflective member 40. The image displayed in the display device 10_1 can be reflected by the reflective member 40 and provided to the right eye of the user through the right eye lens 10b. Therefore, the user can observe the virtual reality image displayed in the display device 10_1 through his / her right eye.

[0200] exist Fig.231 has shown that the display device housing portion 50 is disposed at the right end of the supporting frame 20, but the embodiment is not limited thereto. For example, the display device housing portion 50 may be disposed at the left end of the supporting frame 20. In this case, the image displayed in the display device 10_1 may be reflected by the reflective member 40 and provided to the user's left eye through the left eye lens 10a. Therefore, the user can observe the virtual reality image displayed in the display device 10_1 through his / her left eye. For example, the display device housing portion 50 may be disposed at both the left and right ends of the supporting frame 20. In this case, the user can observe the virtual reality image displayed in the display device 10_1 through his / her left eye and right eye.

[0201] Fig.24 10_2 is a schematic diagram showing a smart device including a display device 10_2 according to an embodiment.

[0202] Reference Fig.24 , the display device 10_2 according to the embodiment can be applied to a smart watch 2, which is one of the smart devices. The shape of the watch display unit of the smart watch 2 in a plan view may follow the shape of the display device 10_2 in a plan view. For example, in a case where the display device 10_2 according to the embodiment has a circular shape or an elliptical shape in a plan view, the watch display unit of the smart watch 2 may have a circular shape or an elliptical shape in a plan view. For example, in a case where the display device 10_2 according to the embodiment has a rectangular shape in a plan view, the watch display unit of the smart watch 2 may have a rectangular shape in a plan view. However, the embodiment is not limited thereto, and the shape of the watch display unit of the smart watch 2 in a plan view may not follow the shape of the display device 10_2 in a plan view.

[0203] Fig.25 1 is a schematic diagram showing an instrument panel and a center instrument panel of a vehicle including the display devices 10_a, 10_b, 10_c, 10_d, and 10_e according to the embodiment. Fig.25 2 shows a vehicle to which the display devices 10_a, 10_b, 10_c, 10_d, and 10_e according to the embodiment are applied.

[0204] Reference Fig.25 The display devices 10_a, 10_b and 10_c according to the embodiments can be applied to a dashboard of a vehicle, to a central dashboard of a vehicle, or to a central information display (CID) provided on a dashboard of a vehicle. For example, the display devices 10_d and 10_e according to the embodiments can be applied to an interior mirror display of a vehicle that replaces a side mirror.

[0205] Fig.2610_3 is a schematic diagram showing a transparent display device including the display device 10_3 according to the embodiment.

[0206] Reference Fig.26 , the display device 10_3 according to the embodiment can be applied to a transparent display device. The transparent display device can transmit light therethrough while displaying an image IM. Therefore, a user located at the front surface of the transparent display device can not only observe the image IM displayed in the display device 10_3, but also can see an object RS or a background located at the rear surface of the transparent display device. In the case where the display device 10_3 is applied to a transparent display device, the display panel 100 (see Figure 1 ) may be formed on a base member including a light transmitting portion through which light can be transmitted or made of a material through which light can be transmitted.

[0207] In summarizing the detailed description, those skilled in the art will appreciate that many changes and modifications may be made to the embodiments without departing substantially from the principles of the present disclosure. Therefore, the disclosed embodiments are intended to be general and descriptive only and not for purposes of limitation.

Claims

1. A method for manufacturing a display device, wherein: The method comprises: manufacturing epitaxial wafers including epitaxial thin films; dividing the epitaxial wafer into wafer dies, the wafer dies having a size corresponding to an area of ​​each unit region of a backplane substrate including a plurality of unit regions; transferring the wafer die to a carrier substrate; forming a conductive bonding layer on the epitaxial grains of the wafer grains; Disposing the carrier substrate on the backplane substrate so that the epitaxial grains are disposed in each unit region of the backplane substrate, and bonding the epitaxial grains to the backplane substrate; removing the carrier substrate from the epitaxial die; and The epitaxial grains are etched to form respective light emitting elements in an emission region included in each unit region of the backplane substrate.

2. The method for manufacturing a display device according to claim 1, wherein: The carrier substrate has a size corresponding to an area of ​​the backplane substrate, and includes a plurality of unit regions corresponding to the plurality of unit regions of the backplane substrate.

3. The method for manufacturing a display device according to claim 2, wherein: The transferring the wafer dies to the carrier substrate includes aligning the wafer dies with respective unit areas of the carrier substrate.

4. The method for manufacturing a display device according to claim 1, wherein: The wafer dies include respective wafer substrates and respective epitaxial grains divided from the epitaxial thin film.

5. The method for manufacturing a display device according to claim 4, wherein: The method further comprises: The gaps between the wafer dies are filled by applying a filler onto the carrier substrate on which the wafer dies are disposed, and after transferring the wafer dies onto the carrier substrate and before forming the conductive bonding layer, the upper surface of the carrier substrate on which the wafer dies and the filler are disposed is flattened.

6. The method for manufacturing a display device according to claim 5, wherein: In planarizing the upper surface of the carrier substrate, the epitaxial dies are exposed by removing the respective wafer substrates from the wafer dies, and The conductive bonding layer is formed by applying a conductive bonding material to the upper surface of the carrier substrate on which the epitaxial grains are exposed.

7. The method for manufacturing a display device according to claim 1, wherein: The method further comprises: selecting products by evaluating said wafer dies prior to said transferring said wafer dies to said carrier substrate, The wafer dies selected as the products are transferred to the carrier substrate.

8. The method for manufacturing a display device according to claim 1, wherein: The backplane substrate includes a pixel electrode individually disposed in the emission region of each unit region of the backplane substrate.

9. The method for manufacturing a display device according to claim 8, wherein: In the etching of the epitaxial grains, the respective light emitting elements are formed on the pixel electrodes.

10. The method for manufacturing a display device according to claim 8, wherein: The backplane substrate further includes a first bonding electrode disposed on the pixel electrode.

11. The method for manufacturing a display device according to claim 10, wherein: In the step of bonding the epitaxial grain to the backplane substrate, the epitaxial grain is bonded to the first bonding electrode by a transient liquid phase bonding method or a thermal compression bonding method.

12. The method for manufacturing a display device according to claim 10, wherein: The method further comprises: By etching the conductive bonding layer, a second bonding electrode is formed between the first bonding electrode and the light emitting element.

13. The method for manufacturing a display device according to claim 1, wherein: In the removing the carrier substrate, the carrier substrate is removed from the epitaxial die by a laser lift-off method.

14. The method for manufacturing a display device according to claim 1, wherein: The method further comprises: A common electrode is formed on the light emitting element in each unit area of ​​the backplane substrate.

15. The method for manufacturing a display device according to claim 14, wherein: The method further comprises: A lens-type optical structure is formed on the light emitting element layer including the light emitting element and the common electrode.

16. The method for manufacturing a display device according to claim 1, wherein: The method further comprises: By cutting the backplane substrate based on the unit regions of the backplane substrate, respective cells corresponding to the unit regions are separated into individual display panels.

17. A method for manufacturing a display device, wherein: The method comprises: preparing a backplane substrate, the backplane substrate comprising a plurality of unit regions and a pixel electrode, the pixel electrode being individually disposed in an emission region disposed in each of the plurality of unit regions; manufacturing a wafer die having a size corresponding to an area of ​​each of the plurality of unit regions and including respective epitaxial grains; preparing a carrier substrate having a size corresponding to that of the backplane substrate and including a plurality of unit regions corresponding to the plurality of unit regions of the backplane substrate; transferring the wafer die to the carrier substrate; planarizing the upper surface of the carrier substrate so that the epitaxial grains of the wafer grains are exposed, and forming a conductive bonding layer on the epitaxial grains; bonding the epitaxial grain to the pixel electrode using the conductive bonding layer; and Respective light emitting elements are formed on the pixel electrodes by etching the epitaxial grains.

18. The method for manufacturing a display device according to claim 17, wherein: The transferring the wafer dies to the carrier substrate includes aligning the wafer dies with the respective unit regions of the carrier substrate.

19. The method for manufacturing a display device according to claim 17, wherein: The backplane substrate further includes a first bonding electrode disposed on the pixel electrode, and The epitaxial grain is bonded to the first bonding electrode by a transient liquid phase bonding method or a thermal compression bonding method.

20. The method for manufacturing a display device according to claim 19, wherein: The method further comprises: By etching the conductive bonding layer, a second bonding electrode is formed between the first bonding electrode and the light emitting element.

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