Display panel, preparation method of display panel and electronic equipment

Abstract

The embodiment of the invention provides a display panel, a preparation method of the display panel and electronic equipment, and relates to the technical field of display, and the display panel comprises an array substrate, a first electrode layer, an insulating layer, a peep-proof isolation wall, a light-emitting layer and a second electrode layer. The first electrode layer is located on one side of the array substrate, and the first electrode layer comprises a plurality of first electrodes arranged at intervals; the insulating layer is positioned on one side, far away from the array substrate, of the first electrode; the peep-proof isolation wall is located on the side, away from the array substrate, of the pixel defining layer. The orthographic projection of the peep-proof isolation wall on the array substrate is located in the orthographic projection of the first electrode on the array substrate; the light-emitting layer and the second electrode layer are located in the pixel opening and are sequentially arranged in a stacked mode. According to the display panel, the peep-proof effect of the display panel can be improved, and then the peep-proof requirement of a user can be met more easily.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular, to a display panel, a method for preparing a display panel, and an electronic device. Background Art

[0002] If you are not careful when using a mobile phone, you may be seen by people around you. The car screen will cause a reflection on the windshield, affecting driving safety. In order to protect personal privacy and improve safety, anti-peeping technology has become increasingly desired by the public. Therefore, it is necessary to make the display panel have an anti-peeping function.

[0003] However, the anti-peeping effect of the display panel in the prior art is not good enough, and thus cannot meet the higher anti-peeping requirements of users. Summary of the invention

[0004] In order to overcome the technical problems mentioned in the above technical background, an embodiment of the present application provides a display panel, wherein the display panel includes:

[0005] An array substrate;

[0006] A first electrode layer located at one side of the array substrate, the first electrode layer comprising a plurality of first electrodes arranged at intervals;

[0007] an insulating layer located on a side of the first electrode away from the array substrate; an orthographic projection of the insulating layer on the array substrate being located within an orthographic projection of the first electrode on the array substrate;

[0008] an anti-peeping isolation wall located on a side of the insulating layer away from the array substrate; the orthographic projection of the anti-peeping isolation wall on the array substrate is located within the orthographic projection of the first electrode on the array substrate;

[0009] A light emitting layer is located on a side of the first electrode away from the array substrate, and a second electrode layer is located on a side of the light emitting layer away from the array substrate.

[0010] In a possible implementation, the display panel further includes a pixel defining layer located on a side of the first electrode layer away from the array substrate, the pixel defining layer includes a pixel opening exposing at least a portion of the first electrode, and the light emitting layer and the second electrode layer are at least partially located in the pixel opening;

[0011] Preferably, the insulating layer and the pixel defining layer are arranged in the same layer.

[0012] In a possible implementation, the display panel further includes a partition structure located on a side of the pixel defining layer away from the array substrate, the partition structure encloses to form a partition opening, the partition opening is connected to the pixel opening, and the second electrode layer overlaps a side wall of the partition structure;

[0013] Preferably, the orthographic projection of the anti-peeping isolation wall on the array substrate is located within the orthographic projection range of the isolation opening on the array substrate;

[0014] Preferably, the orthographic projection of the partition structure on the array substrate is located between the orthographic projections of two adjacent pixel openings on the array substrate, and at least a portion of the second electrode layer extends from the pixel opening to a side of the pixel defining layer away from the array substrate and is in electrical contact with the partition structure;

[0015] Preferably, the second electrode layer is also overlapped with the side wall of the anti-peep isolation wall;

[0016] Preferably, the partition structure is arranged at the same level as the anti-peep isolation wall;

[0017] Preferably, the width of the orthographic projection of the anti-peeping isolation wall on the array substrate is smaller than the width of the orthographic projection of the partition structure on the array substrate;

[0018] Preferably, the distance from the side of the partition structure away from the array substrate to the array substrate is equal to or smaller than the distance from the side of the anti-peeping isolation wall away from the array substrate to the array substrate;

[0019] Preferably, along the direction in which the privacy-prevention isolation wall extends, there is a gap between the orthographic projection of the first end and / or the second end of the privacy-prevention isolation wall on the array substrate and the orthographic projection of the partition structure on the array substrate;

[0020] Preferably, the orthographic projection of the anti-peeping isolation wall on the array substrate passes through the orthographic projection of the first electrode on the array substrate;

[0021] Preferably, the orthographic projection shape of the anti-peep isolation wall on the array substrate is a rectangle;

[0022] Preferably, along a direction perpendicular to the array substrate, the cross-sectional shape of the anti-peeping isolation wall is a regular trapezoid or a column;

[0023] Preferably, along a direction perpendicular to the array substrate, the cross-sectional shape of the anti-peeping isolation wall is an inverted trapezoid;

[0024] Preferably, along the direction away from the array substrate, the privacy protection isolation wall comprises a first sub-layer and a second sub-layer which are stacked, and the orthographic projection of the first sub-layer on the array substrate is located within the orthographic projection range of the second sub-layer on the array substrate;

[0025] Preferably, the material of the anti-peep isolation wall includes a light-shielding and reflective metal material;

[0026] Preferably, the anti-peep isolation wall includes an aluminum metal layer located on the side of the insulating layer away from the array substrate, and a titanium metal layer located on the side of the aluminum metal layer away from the array substrate; or the anti-peep isolation wall includes a molybdenum metal layer located on the side of the insulating layer away from the array substrate, an aluminum metal layer located on the side of the molybdenum metal layer away from the array substrate, and a titanium metal layer located on the side of the aluminum metal layer away from the array substrate.

[0027] In a possible implementation, along the direction away from the array substrate, a light-emitting material layer and a second electrode material layer are sequentially provided on a side of the anti-peeping isolation wall away from the array substrate.

[0028] In a possible implementation, the display panel further includes an encapsulation layer located on a side of the second electrode layer away from the array substrate, and the encapsulation layer further extends to a side of the anti-peep isolation wall and the partition structure away from the array substrate.

[0029] In a possible implementation manner, within the same pixel opening, the number of the privacy protection isolation wall is one;

[0030] Preferably, the width of the orthographic projection of the anti-peeping isolation wall on the array substrate is in the range of 2 μm to 25 μm.

[0031] Preferably, along the extending direction of the anti-peeping isolation wall, a center line of an orthographic projection of the anti-peeping isolation wall on the array substrate coincides with a center line of an orthographic projection of the first electrode on the array substrate.

[0032] In a possible implementation manner, within the same pixel opening, there are multiple privacy-prevention isolation walls;

[0033] Preferably, the orthographic projections of the plurality of anti-peep isolation walls on the array substrate are parallel to each other;

[0034] Preferably, within the same pixel opening, the spacing between the orthographic projections of adjacent privacy protection walls on the array substrate is in the range of 2um-20um.

[0035] In a possible implementation, along a direction away from the array substrate, the partition structure includes a first portion and a second portion that are stacked, and an orthographic projection of the first portion on the array substrate is located within a projection range of the second portion on the array substrate;

[0036] Preferably, the first portion and / or the second portion comprises a conductive material;

[0037] Preferably, the first portion comprises an aluminum metal layer;

[0038] Preferably, the second portion comprises a titanium metal layer;

[0039] Preferably, a third portion is further provided on a side of the first portion facing the array substrate, and the third portion comprises a conductive material;

[0040] Preferably, the third portion comprises a molybdenum metal layer;

[0041] Preferably, the orthographic projection of the partition structure on the array substrate surrounds the orthographic projection of the light-emitting layer on the array substrate.

[0042] In a possible implementation, the present application further provides a method for preparing a display panel, the method comprising:

[0043] Providing an array substrate;

[0044] forming a first electrode layer on one side of the array substrate, wherein the first electrode layer includes a plurality of first electrodes arranged at intervals;

[0045] An insulating layer is formed on a side of the first electrode away from the array substrate; an orthographic projection of the insulating layer on the array substrate is located within an orthographic projection of the first electrode on the array substrate;

[0046] An anti-peeping isolation wall is formed on a side of the insulating layer away from the array substrate; the orthographic projection of the anti-peeping isolation wall on the array substrate is located within the orthographic projection of the first electrode on the array substrate;

[0047] forming a light-emitting layer on a side of the first electrode away from the array substrate, and forming a second electrode layer on a side of the light-emitting layer away from the array substrate;

[0048] Preferably, the step of forming an anti-peeping isolation wall on a side of the insulating layer away from the array substrate comprises:

[0049] forming a pixel defining layer on a side of the first electrode layer away from the array substrate, wherein the pixel defining layer comprises a pixel opening exposing at least a portion of the first electrode;

[0050] An anti-peep isolation wall and a partition structure are formed on the same layer on the side of the pixel defining layer away from the array substrate; the orthographic projection of the partition structure on the array substrate is located between the orthographic projections of two adjacent pixel openings on the array substrate, and at least a portion of the second electrode layer extends from the pixel opening to the side of the pixel defining layer away from the array substrate and is in electrical contact with the partition structure.

[0051] In a possible implementation, the present application further provides an electronic device, which includes the display panel described in the present application.

[0052] Compared with the prior art, this application has the following beneficial effects:

[0053] The present application provides a display panel, a method for preparing a display panel, and an electronic device. By setting an anti-peeping isolation wall on the side of the first electrode away from the array substrate, the display panel can have more anti-peeping angles, thereby improving the anti-peeping effect of the display panel, and making it easier to meet the anti-peeping needs of users. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0055] Figure 1 A schematic cross-sectional view of a display panel provided in an embodiment of the present application;

[0056] Figure 2 A schematic cross-sectional view of a display panel in which the insulating layer provided in an embodiment of the present application includes a pixel defining layer;

[0057] Figure 3 The partition structure and the anti-peeping isolation wall provided in the embodiment of the present application both include a cross-sectional view of a display panel with two film layers;

[0058] Figure 4 The partition structure and the anti-peeping isolation wall provided in the embodiment of the present application both include a cross-sectional view of a display panel with three film layers;

[0059] Figure 5 One of the top view schematic diagrams of a privacy-prevention isolation wall provided in the same pixel opening provided in the embodiment of the present application;

[0060] Figure 6 A second top view schematic diagram of a privacy-prevention isolation wall provided in the same pixel opening provided in an embodiment of the present application;

[0061] Figure 7 A schematic cross-sectional view of a display panel with a plurality of privacy-prevention walls disposed in a pixel opening according to an embodiment of the present application;

[0062] Figure 8 A schematic top view of a plurality of anti-peeping walls provided in the same pixel opening according to an embodiment of the present application;

[0063] Fig. 9 A cross-sectional schematic diagram showing that a light-emitting layer and a second electrode layer are sequentially arranged on a side of the anti-peeping isolation wall away from the array substrate provided in an embodiment of the present application;

[0064] Fig.10 The display panel provided in the embodiment of the present application further includes a cross-sectional schematic diagram of an encapsulation layer;

[0065] Fig.11 A schematic diagram of a process for preparing a display panel provided in an embodiment of the present application;

[0066] Fig.12 A schematic diagram of a specific execution direction flow chart of step S13 provided in an embodiment of the present application;

[0067] Fig.13 A cross-sectional schematic diagram of providing a first electrode and a pixel defining layer on one side of an array substrate provided in an embodiment of the present application;

[0068] Fig.14 A cross-sectional schematic diagram of an embodiment of the present application showing that a partition structure and an anti-peeping isolation wall are simultaneously provided on a side of a pixel defining layer away from an array substrate.

[0069] Figure numerals: 1. array substrate; 2. first electrode; 3. insulating layer; 4. light-emitting layer; 5. second electrode layer; 6. anti-peep isolation wall; 61. first sublayer; 62. second sublayer; 63. third sublayer; 7. pixel defining layer; 71. pixel opening; 8. partition structure; 81. first part; 82. second part; 83. third part; 9. encapsulation layer; 91. first inorganic encapsulation layer; 911. encapsulation unit; 92. organic encapsulation layer; 93. second inorganic encapsulation layer; 10. light-emitting material layer; 11. second electrode material layer. DETAILED DESCRIPTION

[0070] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0071] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0072] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0073] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "vertical", "horizontal", "inner", "outer", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, or the positions or positional relationships in which the inventive product is usually placed when in use. They are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0074] It should be noted that, in the absence of conflict, different features in the embodiments of the present application may be combined with each other.

[0075] In the related art, the anti-peeping technology mainly controls the liquid crystal layer to change the polarization direction or uses polarizers, vinyl and microlens arrays to increase the absorption of large-angle light, thereby realizing the anti-peeping of the side view of the display panel. However, the accuracy of the anti-peeping angle of the anti-peeping technology in the related art is not high enough, which affects the anti-peeping effect of the display panel in the related art, and thus cannot meet the user's anti-peeping requirements for the display panel. In addition, the process of setting the anti-peeping technology of the display panel in the related art is relatively complicated, thereby increasing the production cost of the display panel.

[0076] In view of this, the present embodiment provides a solution that can improve the anti-peeping effect of the display panel. The solution provided by the present embodiment is described in detail below.

[0077] See also Figure 1 This embodiment provides a display panel, which includes an array substrate 1, a first electrode layer, an insulating layer 3, an anti-peeping isolation wall 6, a light-emitting layer 4 and a second electrode layer 5.

[0078] The array substrate 1 may include a plurality of drive units, each of which may include one or more semiconductor switch devices. The semiconductor switch device may be formed by the cooperation of a plurality of film layers in the array substrate 1, for example, the semiconductor switch device may be a thin film transistor (TFT) formed by the cooperation of a plurality of film layers.

[0079] The first electrode layer is located on one side of the array substrate 1 , and includes a plurality of first electrodes 2 that are spaced apart from each other.

[0080] The insulating layer 3 is located on the side of the first electrode 2 away from the array substrate 1; the orthographic projection of the insulating layer 3 on the array substrate 1 is located within the orthographic projection of the first electrode 2 on the array substrate 1, and the insulating layer 3 only covers part of the first electrode 2. The insulating layer 3 can prevent the first electrode 2 from being connected to the second electrode layer 5 through the anti-peep isolation wall 6 to form a short circuit.

[0081] The anti-peeping isolation wall 6 is located on the side of the insulating layer 3 away from the array substrate 1; the orthographic projection of the anti-peeping isolation wall 6 on the array substrate 1 is located within the orthographic projection of the first electrode 2 on the array substrate 1; the light-emitting layer 4 is located on the side of the first electrode 2 away from the array substrate 1, and the second electrode layer 5 is located on the side of the light-emitting layer 4 away from the array substrate 1.

[0082] In this embodiment, the first electrode 2 is used as an anode and the second electrode layer 5 is used as a cathode layer. The first electrode 2, the light-emitting layer 4 and the second electrode form corresponding pixels. The array substrate 1 applies voltage to the first electrode 2 and the second electrode layer 5 to drive the pixels to emit light. The anti-peeping isolation wall 6 can divide the corresponding pixels and block the lateral light emitted by the pixels, thereby playing an anti-peeping role for the side view of the display panel.

[0083] Through the above solution, the anti-peeping accuracy of the display panel is higher, and the anti-peeping isolation wall 6 of corresponding width can be set according to the anti-peeping angle requirements, so that more viewing angles of the display panel can be protected from peeping.

[0084] Based on the above design, in this embodiment, by setting an anti-peeping isolation wall 6 on the side of the first electrode 2 away from the array substrate 1, the display panel can have more anti-peeping angles, thereby improving the anti-peeping effect of the display panel, and making it easier to meet the user's anti-peeping needs.

[0085] In one possible implementation, see Figure 2 The display panel also includes a pixel defining layer 7 located on a side of the first electrode layer away from the array substrate 1, the pixel defining layer 7 includes a pixel opening 71 exposing at least a portion of the first electrode 2, the light-emitting layer 4 and the second electrode layer 5 are at least partially located in the pixel opening 71, and the insulating layer 3 is arranged on the same layer as the pixel defining layer 7, that is, the insulating layer 3 and the pixel defining layer 7 are formed by the same process, without adding additional preparation steps, thereby reducing manufacturing costs.

[0086] The pixel defining layer 7 may have a plurality of pixel openings 71 , one pixel opening 71 corresponds to one pixel, and adjacent first electrodes 2 are isolated from each other by the pixel defining layer 7 .

[0087] The anti-peeping isolation wall 6 is located in the pixel opening 71 , and the anti-peeping isolation wall 6 can divide the corresponding pixels and block the lateral light emitted by the pixels, thereby playing an anti-peeping role for the side view of the display panel.

[0088] The anti-peep isolation wall 6 is formed based on the insulating layer 3 in the pixel opening 71. The insulating layer 3 is formed while the pixel defining layer 7 is formed. Therefore, there is no need to form the insulating layer 3 separately, thereby reducing the process of the display panel and further reducing the production cost of the display panel.

[0089] In one possible implementation, see Figure 3 The display panel also includes a partition structure 8 located on a side of the pixel defining layer 7 away from the array substrate 1 and arranged on the same layer as the anti-peeping isolation wall 6; the partition structure 8 encloses a partition opening, the partition opening is connected to the pixel opening 71, and the second electrode layer overlaps the side wall of the partition structure 8; the orthographic projection of the anti-peeping isolation wall 6 on the array substrate 1 is located within the orthographic projection range of the isolation opening on the array substrate 1; the orthographic projection of the partition structure 8 on the array substrate 1 is located between the orthographic projections of two adjacent pixel openings 71 on the array substrate 1, at least part of the second electrode layer 5 extends from the pixel opening 71 to the side of the pixel defining layer 7 away from the array substrate 1 and is in electrical contact with the partition structure 8, and the second electrode layer also overlaps the side wall of the anti-peeping isolation wall 6.

[0090] When forming the light-emitting layer 4 and the second electrode layer 5, the partition structure 8 can disconnect the light-emitting layer 4 and the second electrode layer 5 of the adjacent light-emitting device, and make at least part of the second electrode layer 5 extend from the pixel opening 71 to the side of the pixel defining layer 7 away from the array substrate 1 to be in electrical contact with the partition structure 8, and the partition structure 8 can connect the adjacent second electrode layer 5 or connect the second electrode layer 5 to other circuits. In this way, the patterning design of the light-emitting layer 4 and the second electrode layer 5 can be realized without using a precise mask, thereby reducing the manufacturing difficulty of the display panel.

[0091] In one embodiment of the present application, the cross-sectional shape of the privacy barrier 6 is a regular trapezoid or a column along a direction perpendicular to the array substrate 1. In this way, the privacy barrier 6 can be more conducive to shielding the light emitted by the corresponding pixel, thereby being more conducive to improving the privacy barrier effect of the display panel.

[0092] In other embodiments of the present application, the cross-sectional shape of the anti-peeping isolation wall 6 may also be an inverted trapezoidal shape along the direction perpendicular to the array substrate 1. In this way, the top surface of the anti-peeping isolation wall 6 is an eaves structure, which has a better blocking effect on the light emitted by the light-emitting layer 4, thereby improving the anti-peeping effect of the display panel.

[0093] Preferably, the distance from the side of the partition structure 8 away from the array substrate 1 to the array substrate 1 is equal to or smaller than the distance from the side of the anti-peeping isolation wall 6 away from the array substrate 1 to the array substrate 1 .

[0094] Since the insulating layer 3 is formed in the pixel opening 71 while the pixel defining layer 7 is formed, and the anti-peeping isolation wall 6 is formed on the side of the insulating layer 3 away from the array substrate 1 while the partition structure 8 is formed. Therefore, the height of the partition structure 8 and the anti-peeping isolation wall 6 are the same or the height of the partition structure 8 is less than the height of the anti-peeping isolation wall 6, and the partition structure 8 and the anti-peeping isolation wall 6 are formed by the same process. In this way, the anti-peeping technology does not need to add new process steps, does not increase process difficulty, and reduces material waste, and can achieve higher-end applications of new technologies.

[0095] Preferably, see again Figure 3 , along the direction away from the array substrate 1, the anti-peeping isolation wall 6 includes a first sub-layer 61 and a second sub-layer 62 which are stacked, and the orthographic projection of the first sub-layer 61 on the array substrate 1 is located within the orthographic projection range of the second sub-layer 62 on the array substrate 1; please refer again to Figure 4 , a third sublayer 63 is further provided on the side of the first sublayer facing the array substrate 1. The material of the anti-peeping isolation wall 6 includes a light-shielding and reflective metal material, and the second electrode layer 5 overlaps the side wall of the anti-peeping isolation wall 6. While achieving anti-peeping, the resistance of the second electrode layer 5 can also be reduced, thereby reducing the power consumption of the display panel.

[0096] Preferably, see again Figure 3 , along the direction away from the array substrate 1, the partition structure 8 includes a first portion 81 and a second portion 82 which are stacked, and the orthographic projection of the first portion 81 on the array substrate 1 is located within the projection range of the second portion 82 on the array substrate 1. Please refer again Figure 4 A third portion 83 is further provided on the side of the first portion 81 facing the array substrate 1 . The first portion 81 and / or the second portion 82 include a conductive material, and the third portion 83 includes a conductive material.

[0097] Specifically, the first portion 81 and the first sublayer 61 both include an aluminum metal layer; the second portion 82 and the second sublayer 62 both include a titanium metal layer; and the third portion 83 and the third sublayer 63 both include a molybdenum metal layer.

[0098] The partition structure 8 and the anti-peeping isolation wall 6 are both composed of the above-mentioned two layers of metal or three layers of metal. The partition structure 8 and the anti-peeping isolation wall 6 are formed using the same process and the same material, thereby simplifying the manufacturing process of the partition structure 8 and the anti-peeping isolation wall 6.

[0099] The partition structure 8 is made of the above-mentioned metal material, which can realize the electrical connection of the second electrode layer 5. The anti-peeping isolation wall 6 is made of the above-mentioned metal material, which can divide the pixels and achieve a better light shielding effect. Therefore, the anti-peeping isolation wall 6 has a higher anti-peeping accuracy and can realize more angles of anti-peeping according to needs.

[0100] Preferably, the orthographic projection of the partition structure 8 on the array substrate 1 surrounds the orthographic projection of the light emitting layer 4 on the array substrate 1. The partition structure 8 can enclose the pixels, thereby making it easier to independently package the pixels and also improving the anti-peeping effect of the display panel.

[0101] In one possible implementation, see Figure 5 , within the same pixel opening 71 , the number of the anti-peeping isolation wall 6 is one.

[0102] Preferably, the width of the orthographic projection of the anti-peeping isolation wall 6 on the array substrate 1 is smaller than the width of the orthographic projection of the partition structure 9 on the array substrate 1. The widths of the orthographic projections of the anti-peeping isolation wall 6 and the partition structure 9 on the array substrate 1 are set differently, and the width of the orthographic projection of the anti-peeping isolation wall 6 on the array substrate 1 is smaller than the width of the orthographic projection of the partition structure 9 on the array substrate 1. In this way, the width of the anti-peeping isolation wall 6 is made narrower than the width of the partition structure 9 without affecting the anti-peeping effect, which can increase the effective light-emitting area of ​​the light-emitting layer 4, thereby improving the display quality of the display panel.

[0103] Preferably, the width L of the orthographic projection of the anti-peeping isolation wall 6 on the array substrate 1 is in the range of 2μm-25μm, for example, the width L may be 2μm, 5μm, 10μm, 15μm, 20μm, 23μm or 25μm, etc. If the width L is set too large, the effective light-emitting area of ​​the light-emitting layer 4 covered by the anti-peeping isolation wall 6 will be increased, thereby reducing the effective light-emitting area of ​​the light-emitting layer 4, thereby affecting the display quality of the display panel; if the width L is set too small, it will affect the anti-peeping effect of the display panel. Therefore, by reasonably setting the width L, the display quality of the display panel can be improved without affecting the anti-peeping effect of the display panel.

[0104] The width L of the orthographic projection of the anti-peeping isolation wall 6 on the array substrate 1 is related to the size of the pixel, the material of the pixel, and the anti-peeping angle. When the size of the pixel, the material of the pixel, etc. are constant, the larger the anti-peeping angle, the larger the width L. In this way, in this embodiment, the width L of the anti-peeping isolation wall 6 can be set to different sizes, so that the display panel can have more anti-peeping angles, thereby improving the anti-peeping effect of the display panel.

[0105] In one possible implementation, see again Figure 5 , in the same pixel opening 71, the number of the privacy barrier 6 is one, and along the extending direction A of the privacy barrier 6, the center line of the positive projection of the privacy barrier 6 on the array substrate 1 ( Figure 5 The dashed line passing through the anti-peeping isolation wall 6 in the figure) and the center line of the positive projection of the first electrode 2 exposed by the pixel opening 71 on the array substrate 1 ( Figure 5The dashed line passing through the first electrode 2 in the figure coincides with the dashed line in the figure.

[0106] The orthographic projection shape of the pixel on the array substrate 1 can be circular, square, or diamond, etc. Figure 5 The shape of the pixel is only a schematic diagram. When the number of the anti-peeping isolation wall 6 is one, the anti-peeping isolation wall 6 divides the corresponding pixel into two parts evenly. In this way, the clarity of the picture displayed by the display panel at a normal viewing angle is more uniform, thereby improving the display quality of the display panel at a normal viewing angle.

[0107] In some embodiments, please refer again to Figure 5 , the orthographic projection of the anti-peeping isolation wall 6 on the array substrate 1 passes through the orthographic projection of the first electrode 2 exposed by the pixel opening 71 on the array substrate 1. The anti-peeping isolation wall 6 completely divides the corresponding pixel, and the anti-peeping isolation wall 6 extends to connect with the partition structure 8. In this way, the anti-peeping isolation wall 6 can divide a pixel into two light-emitting units, thereby further improving the shielding effect of the anti-peeping isolation wall 6 on the light of the corresponding pixel at the anti-peeping angle, and further improving the anti-peeping effect of the display panel.

[0108] In other embodiments, see Figure 6 Along the length direction of the anti-peeping isolation wall 6 , there is a gap D between the orthographic projection of the first end and / or the second end of the anti-peeping isolation wall 6 on the array substrate 1 and the orthographic projection of the partition structure 8 on the array substrate 1 .

[0109] Along the direction A in which the anti-peeping isolation wall 6 extends, one end of the anti-peeping isolation wall 6 is defined as the first end, and the other end is defined as the second end. In this way, the first end and / or the second end of the anti-peeping isolation wall 6 is not connected to the partition structure 8, and the anti-peeping isolation wall 6 can still block the light of the corresponding pixel at the anti-peeping angle.

[0110] Preferably, see again Figure 5 The orthographic projection shape of the anti-peeping isolation wall 6 on the array substrate 1 is a rectangle. In this way, on the one hand, it is easier to set the anti-peeping isolation wall 6, and on the other hand, it is easier to make the anti-peeping isolation wall 6 evenly divide the corresponding pixels.

[0111] In one possible implementation, see Figure 7 In the same pixel opening 71, the number of the anti-peeping isolation walls 6 is multiple. According to the size of the pixel, the anti-peeping angle, etc., multiple anti-peeping isolation walls 6 can be set in the pixel opening 71 while setting the partition structure 8, such as Figure 6Two anti-peeping walls 6 are arranged in one pixel opening 71. In this way, the corresponding pixel can be divided into multiple parts by multiple anti-peeping walls 6 in the same pixel opening 71, so that the anti-peeping accuracy of the display panel can be further improved, so that the display panel has more anti-peeping angles, and then the display panel can better meet the anti-peeping needs of users.

[0112] Preferably, the orthographic projections of the plurality of anti-peep walls 6 on the array substrate 1 are parallel to each other. In this way, the plurality of anti-peep walls 6 can evenly divide the corresponding pixels into a plurality of parts, and the light emitted by the pixels of the plurality of different parts is more uniform, thereby improving the display quality of the display panel at a normal viewing angle.

[0113] Preferably, see Figure 8 In the same pixel opening 71, the spacing W between the orthographic projections of adjacent anti-peeping isolation walls 6 on the array substrate 1 ranges from 2um to 20um. For example, the spacing W can be 2um, 5um, 8um, 12um, 15um, 18um or 20um. If the spacing W is set too small, the luminous effect of the entire pixel may be affected; if the spacing W is set too large, the anti-peeping effect of the display panel may be affected. Therefore, a reasonable setting of the spacing W will not affect the luminous effect of the entire pixel, and can also improve the anti-peeping effect of the display panel.

[0114] In one possible implementation, see Fig. 9 Along the direction away from the array substrate 1 , a light emitting material layer 10 and a second electrode material layer 11 are sequentially provided on the side of the anti-peeping isolation wall 6 away from the array substrate 1 .

[0115] When setting the light-emitting layer 4 and the second electrode layer 5, a light-emitting material layer 10 and a second electrode material layer 11 are sequentially formed on the side of the anti-peek isolation wall 6 away from the array substrate 1. The light-emitting material layer 10 is arranged on the same layer as the light-emitting layer 4, and the second electrode material layer 11 is arranged on the same layer as the second electrode layer 5. In this embodiment, there is no need to remove the light-emitting material layer 10 and the second electrode material layer 11 on the side of the anti-peek isolation wall 6 away from the array substrate 1, thereby reducing the corresponding process and further reducing the cost of preparing the display panel.

[0116] Optionally, see Fig.10 The display panel further includes an encapsulation layer 9 located on a side of the second electrode layer 5 away from the array substrate 1 , and the encapsulation layer 9 further extends to a side of the anti-peep isolation wall 6 and the partition structure 8 away from the array substrate 1 .

[0117] Along the direction away from the array substrate 1, the encapsulation layer 9 includes a first inorganic encapsulation layer 91, an organic encapsulation layer 92, and a second inorganic encapsulation layer 93 stacked in sequence. The anti-peeping isolation wall 6 and the partition structure 8 both include a side close to the array substrate 1, a side away from the array substrate 1, and a side surface. The first inorganic encapsulation layer 91 includes a plurality of independent encapsulation units 911. The encapsulation unit 911 extends from the side of the second electrode layer 5 away from the array substrate 1 to the side of the anti-peeping isolation wall 6 and the partition structure 8, and extends from the side of the anti-peeping isolation wall 6 and the partition structure 8 to the side of the anti-peeping isolation wall 6 and the partition structure 8 away from the array substrate 1, and two adjacent encapsulation units 911 have a spacing on the side of the partition structure 8 away from the array substrate 1. In this way, each encapsulation unit 911 can independently encapsulate a light-emitting device, so that the light-emitting devices are independent of each other, thereby improving the reliability of the display panel encapsulation, and further optimizing the optical performance of the display panel.

[0118] In one possible implementation, see Fig.11 The present application also provides a method for preparing a display panel, the method comprising:

[0119] S10: providing an array substrate 1.

[0120] The array substrate 1 may include a plurality of drive units, each of which may include one or more semiconductor switch devices. The semiconductor switch device may be formed by the cooperation of a plurality of film layers in the array substrate 1, for example, the semiconductor switch device may be a thin film transistor (TFT) formed by the cooperation of a plurality of film layers.

[0121] S11 : forming a first electrode layer 5 on one side of the array substrate 1 , wherein the first electrode layer 5 includes a plurality of first electrodes 2 arranged at intervals.

[0122] S12 : forming an insulating layer 3 on a side of the first electrode 2 away from the array substrate 1 ; an orthographic projection of the insulating layer 3 on the array substrate 1 is located within an orthographic projection of the first electrode 2 on the array substrate 1 .

[0123] The insulating layer 3 only covers a portion of the first electrode 2 , and the insulating layer 3 can prevent the first electrode 2 from being connected to the second electrode layer through the anti-peeping isolation wall 6 to form a short circuit.

[0124] S13 : forming an anti-peeping isolation wall 6 on a side of the insulating layer 3 away from the array substrate 1 ; the orthographic projection of the anti-peeping isolation wall 6 on the array substrate 1 is located within the orthographic projection of the first electrode 2 on the array substrate 1 .

[0125] S14 : forming a light emitting layer 4 on a side of the first electrode 2 away from the array substrate 1 and forming a second electrode layer 5 on a side of the light emitting layer 4 away from the array substrate 1 .

[0126] An insulating layer 3 is formed on the side of the first electrode 2 away from the array substrate 1, a light-emitting layer 4 is formed on the side of the first electrode 2 away from the array substrate 1, and a second electrode layer 5 is formed on the side of the light-emitting layer 4 away from the array substrate 1. The first electrode 2 is an anode, the second electrode layer 5 is a cathode layer, the first electrode 2, the light-emitting layer 4 and the second electrode layer 5 form corresponding pixels, and the array substrate 1 applies voltage to the first electrode 2 and the second electrode layer 5 to drive the pixels to emit light. The anti-peeping isolation wall 6 can divide the corresponding pixels and block the lateral light emitted by the pixels, so as to play an anti-peeping role for the side view of the display panel.

[0127] Since the anti-peeping isolation wall 6 has a higher anti-peeping precision, the anti-peeping isolation wall 6 of a corresponding width can be set according to the anti-peeping angle requirements, so that more viewing angles of the display panel can be protected from peeping.

[0128] Preferably, see Fig.12 The step of forming an anti-peeping isolation wall 6 on a side of the pixel defining layer 7 away from the array substrate 1 includes:

[0129] S131 : forming a pixel defining layer 7 on a side of the first electrode layer away from the array substrate 1 , wherein the pixel defining layer 7 includes a pixel opening 71 exposing at least a portion of the first electrode 2 .

[0130] See also Fig.13 , a plurality of first electrodes 2 arranged at intervals are formed on one side of the array substrate 1, and then a pixel defining layer 7 is formed on the side of the first electrode layer away from the array substrate 1. The number of pixel openings 71 of the pixel defining layer 7 can be multiple, and one pixel opening 71 corresponds to one light-emitting device, and adjacent first electrodes 2 are isolated from each other by the pixel defining layer 7. A portion of the pixel defining layer 7 is also formed on the first electrode 2, and the orthographic projection of the pixel defining layer 7 located in the pixel opening 71 on the array substrate 1 is located within the orthographic projection of the pixel opening 71 on the array substrate 1, that is, the pixel defining layer 7 located in the pixel opening 71 only covers a portion of the first electrode 2.

[0131] S132: An anti-peep isolation wall 6 and a partition structure 8 are formed on the same layer as the pixel defining layer 7 on the side away from the array substrate 1; the orthographic projection of the partition structure 8 on the array substrate 1 is located between the orthographic projections of two adjacent pixel openings 71 on the array substrate 1, and at least part of the second electrode layer 5 extends from the pixel opening 71 to the side of the pixel defining layer 7 away from the array substrate 1 and is in electrical contact with the partition structure 8.

[0132] A pixel defining layer 7 is also disposed in the pixel opening 71, and the pixel defining layer 7 in the pixel opening 71 is located on the side of the first electrode 2 away from the array substrate 1, and an anti-peeping isolation wall 6 is disposed on the side of the pixel defining layer 7 in the pixel opening 71 away from the array substrate 1. Thus, the anti-peeping isolation wall 6 is also located in the pixel opening 71, and the anti-peeping isolation wall 6 can divide the corresponding pixels and block the lateral light emitted by the pixels, thereby playing an anti-peeping role for the side view of the display panel.

[0133] The insulating layer 3 is provided at the same layer as the pixel defining layer 7. The insulating layer 3 is formed while the pixel defining layer 7 is formed. Therefore, there is no need to form the insulating layer 3 separately, thereby reducing the process of the display panel and further reducing the production cost of the display panel.

[0134] See also Fig.14 When forming the light-emitting layer 4 and the second electrode layer 5, the partition structure 8 can disconnect the light-emitting layer 4 and the second electrode layer 5 of the adjacent light-emitting device, and make at least part of the second electrode layer 5 extend from the pixel opening 71 to the side of the pixel defining layer 7 away from the array substrate 1 to be in electrical contact with the partition structure 8, and the partition structure 8 can connect the adjacent second electrode layer 5 or connect the second electrode layer 5 to other circuits. In this way, the patterning design of the light-emitting layer 4 and the second electrode layer 5 can be realized without using a precise mask, thereby reducing the manufacturing difficulty of the display panel.

[0135] Then, an encapsulation layer 9 can be provided on the side of the second electrode layer 5 away from the array substrate 1. In the direction away from the array substrate 1, the encapsulation layer 9 includes a first inorganic encapsulation layer 91, an organic encapsulation layer 92, and a second inorganic encapsulation layer 93 stacked in sequence. The anti-peeping isolation wall 6 and the partition structure 8 both include a side close to the array substrate 1, a side away from the array substrate 1, and a side surface. The first inorganic encapsulation layer 91 includes a plurality of independent encapsulation units 911. The encapsulation unit 911 extends from the side of the second electrode layer 5 away from the array substrate 1 to the side of the anti-peeping isolation wall 6 and the partition structure 8, and extends from the side of the anti-peeping isolation wall 6 and the partition structure 8 to the side of the anti-peeping isolation wall 6 and the partition structure 8 away from the array substrate 1, and two adjacent encapsulation units 911 have a spacing on the side of the partition structure 8 away from the array substrate 1. In this way, each encapsulation unit 911 can independently encapsulate a light-emitting device, so that the light-emitting devices are independent of each other, thereby improving the reliability of the display panel encapsulation, and further optimizing the optical performance of the display panel.

[0136] In a possible implementation, the present application further provides an electronic device, the electronic device including the display panel described in the present application. The electronic device may include a device with image processing capabilities, such as a server, a personal computer, a laptop computer, etc. The electronic device may include a device with image processing capabilities, such as a server, a personal computer, a laptop computer, etc. Since the electronic device includes the display panel in the present application, the anti-peeping effect of the electronic device is better.

[0137] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0138] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A display panel, characterized in that: The display panel comprises: An array substrate; A first electrode layer located at one side of the array substrate, the first electrode layer comprising a plurality of first electrodes arranged at intervals; an insulating layer located on a side of the first electrode away from the array substrate; an orthographic projection of the insulating layer on the array substrate being located within an orthographic projection of the first electrode on the array substrate; an anti-peeping isolation wall located on a side of the insulating layer away from the array substrate; the orthographic projection of the anti-peeping isolation wall on the array substrate is located within the orthographic projection of the first electrode on the array substrate; A light emitting layer is located on a side of the first electrode away from the array substrate, and a second electrode layer is located on a side of the light emitting layer away from the array substrate.

2. The display panel according to claim 1, characterized in that: The display panel further comprises a pixel defining layer located on a side of the first electrode layer away from the array substrate, the pixel defining layer comprising a pixel opening exposing at least a portion of the first electrode, and the light emitting layer and the second electrode layer are at least partially located in the pixel opening; Preferably, the insulating layer and the pixel defining layer are arranged in the same layer.

3. The display panel according to claim 2, characterized in that: The display panel further comprises a partition structure located on a side of the pixel defining layer away from the array substrate, the partition structure encloses to form a partition opening, the partition opening is connected to the pixel opening, and the second electrode layer overlaps the side wall of the partition structure; Preferably, the orthographic projection of the anti-peeping isolation wall on the array substrate is located within the orthographic projection range of the isolation opening on the array substrate; Preferably, the orthographic projection of the partition structure on the array substrate is located between the orthographic projections of two adjacent pixel openings on the array substrate, and at least a portion of the second electrode layer extends from the pixel opening to a side of the pixel defining layer away from the array substrate and is in electrical contact with the partition structure; Preferably, the second electrode layer is also overlapped with the side wall of the anti-peep isolation wall; Preferably, the partition structure is arranged at the same level as the anti-peep isolation wall; Preferably, the width of the orthographic projection of the anti-peeping isolation wall on the array substrate is smaller than the width of the orthographic projection of the partition structure on the array substrate; Preferably, the distance from the side of the partition structure away from the array substrate to the array substrate is equal to or smaller than the distance from the side of the anti-peeping isolation wall away from the array substrate to the array substrate; Preferably, along the direction in which the privacy-prevention isolation wall extends, there is a gap between the orthographic projection of the first end and / or the second end of the privacy-prevention isolation wall on the array substrate and the orthographic projection of the partition structure on the array substrate; Preferably, the orthographic projection of the anti-peeping isolation wall on the array substrate passes through the orthographic projection of the first electrode on the array substrate; Preferably, the orthographic projection shape of the anti-peep isolation wall on the array substrate is a rectangle; Preferably, along a direction perpendicular to the array substrate, the cross-sectional shape of the anti-peeping isolation wall is a regular trapezoid or a column; Preferably, along a direction perpendicular to the array substrate, the cross-sectional shape of the anti-peeping isolation wall is an inverted trapezoid; Preferably, along a direction away from the array substrate, the privacy protection isolation wall comprises a first sub-layer and a second sub-layer which are stacked, and an orthographic projection of the first sub-layer on the array substrate is located within an orthographic projection range of the second sub-layer on the array substrate; Preferably, the material of the anti-peep isolation wall includes a light-shielding and reflective metal material; Preferably, the anti-peep isolation wall includes an aluminum metal layer located on the side of the insulating layer away from the array substrate, and a titanium metal layer located on the side of the aluminum metal layer away from the array substrate; or the anti-peep isolation wall includes a molybdenum metal layer located on the side of the insulating layer away from the array substrate, an aluminum metal layer located on the side of the molybdenum metal layer away from the array substrate, and a titanium metal layer located on the side of the aluminum metal layer away from the array substrate.

4. The display panel according to claim 1, characterized in that: Along the direction away from the array substrate, a light emitting material layer and a second electrode material layer are sequentially provided on a side of the anti-peeping isolation wall away from the array substrate.

5. The display panel according to claim 1, characterized in that: The display panel further comprises a packaging layer located on a side of the second electrode layer away from the array substrate, and the packaging layer further extends to a side of the anti-peeping isolation wall and the partition structure away from the array substrate.

6. The display panel according to claim 2, characterized in that: In the same pixel opening, the number of the anti-peeping isolation wall is one; Preferably, the width of the orthographic projection of the anti-peeping isolation wall on the array substrate is in the range of 2 μm to 25 μm; Preferably, along the extending direction of the anti-peeping isolation wall, a center line of an orthographic projection of the anti-peeping isolation wall on the array substrate coincides with a center line of an orthographic projection of the first electrode on the array substrate.

7. The display panel according to claim 2, characterized in that: In the same pixel opening, the number of the anti-peeping isolation walls is multiple; Preferably, the orthographic projections of the plurality of anti-peep isolation walls on the array substrate are parallel to each other; Preferably, within the same pixel opening, the spacing between the orthographic projections of adjacent privacy protection walls on the array substrate is in the range of 2um-20um.

8. The display panel according to claim 3, characterized in that: Along a direction away from the array substrate, the partition structure includes a first portion and a second portion which are stacked, and an orthographic projection of the first portion on the array substrate is located within a projection range of the second portion on the array substrate; Preferably, the first portion and / or the second portion comprises a conductive material; Preferably, the first portion comprises an aluminum metal layer; Preferably, the second portion comprises a titanium metal layer; Preferably, a third portion is further provided on a side of the first portion facing the array substrate, and the third portion comprises a conductive material; Preferably, the third portion comprises a molybdenum metal layer; Preferably, the orthographic projection of the partition structure on the array substrate surrounds the orthographic projection of the light-emitting layer on the array substrate.

9. A method for preparing a display panel, characterized in that: The method comprises: Providing an array substrate; forming a first electrode layer on one side of the array substrate, wherein the first electrode layer includes a plurality of first electrodes arranged at intervals; An insulating layer is formed on a side of the first electrode away from the array substrate; an orthographic projection of the insulating layer on the array substrate is located within an orthographic projection of the first electrode on the array substrate; An anti-peeping isolation wall is formed on a side of the insulating layer away from the array substrate; the orthographic projection of the anti-peeping isolation wall on the array substrate is located within the orthographic projection of the first electrode on the array substrate; forming a light-emitting layer on a side of the first electrode away from the array substrate, and forming a second electrode layer on a side of the light-emitting layer away from the array substrate; Preferably, the step of forming an anti-peeping isolation wall on a side of the insulating layer away from the array substrate comprises: forming a pixel defining layer on a side of the first electrode layer away from the array substrate, wherein the pixel defining layer comprises a pixel opening exposing at least a portion of the first electrode; An anti-peep isolation wall and a partition structure are formed on the same layer on the side of the pixel defining layer away from the array substrate; the orthographic projection of the partition structure on the array substrate is located between the orthographic projections of two adjacent pixel openings on the array substrate, and at least a portion of the second electrode layer extends from the pixel opening to the side of the pixel defining layer away from the array substrate and is in electrical contact with the partition structure.

10. An electronic device, characterized in that: The electronic device comprises the display panel according to any one of claims 1 to 8.

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