Semiconductor device package with internal magnetic shield for Hall sensor

Abstract

The invention relates to a semiconductor device package with an internal magnetic shield for a Hall sensor. Described examples include: a thermal sheet (Figure 3, 321) coupled to a package substrate (307) and configured to conduct current between terminals (310) of the package substrate; a first magnetic shield (313) mounted to the top surface of the package substrate and including a die mounting area; a semiconductor die (305) flip-chip mounted to the die mounting area; a second magnetic shield (315) mounted to the package substrate and having a cantilevered portion extending over a portion of the semiconductor die containing the Hall element; wire bonds or bonded electrical connections (325) between the bonding pads of the semiconductor die and the leads on the package substrate; and a molding compound (323) covering the electrical connector, the semiconductor die, the first magnetic shield and the second magnetic shield while a portion of the thermal sheet is exposed, thereby forming a thermal pad (322) for a semiconductor device package (300).

Description

Technical Field

[0001] The present disclosure generally relates to a semiconductor device package having a semiconductor die including a Hall sensor. Background Art

[0002] Semiconductor devices for magnetic sensing include Hall effect sensors with circuit systems. Magnetic sensing can be used for motor control, position sensing, automation, current sensing and other applications. Hall effect sensors integrated in semiconductor devices can be formed by doping regions to include carriers that are sensitive to magnetic fields. When current is applied to the Hall sensor, a voltage proportional to the magnetic field is output by the Hall sensor. The Hall sensor is most sensitive to magnetic fields that are perpendicular to the plane in the Hall sensor.

[0003] Hall effect current sensing is increasingly used in control and power systems for high voltage motors. There is an increasing need for sensing of currents greater than 100 amps. Solutions for semiconductor devices with Hall sensors for these applications currently involve expensive, combined and / or bulky semiconductor packages. Examples include package-embedded solutions, where a packaged Hall sensor semiconductor device is placed in a second module with a magnetic core, and the assembly is again packaged. Other known solutions use custom semiconductor packages for the Hall sensors. The non-standard footprint for packaged Hall sensors increases assembly costs.

[0004] One aspect of Hall sensors is the need for magnetic shielding. Because Hall sensors use the magnetic field caused by current flowing through a metal conductor to sense current, stray magnetic fields in the environment can adversely affect the sensing and cause errors in the current measurement. To improve performance, magnetic shields and magnetic concentrators are used. Magnetic concentrators can improve Hall sensor performance by better aligning the magnetic field to be sensed with the plane of the Hall sensor.

[0005] Magnetic shielding materials used in semiconductor processes may include magnetic materials. These magnetic materials may not be easily integrated into semiconductor dies using semiconductor device processing, making it expensive to form magnetic shields during the manufacture of semiconductor dies in semiconductor processes. A reliable and robust semiconductor device package that integrates a Hall current sensor device with a magnetic shield at a low cost is needed. Summary of the invention

[0006] In the described examples, a method of forming a semiconductor device package includes: forming a package substrate having a board side surface and an opposing top surface, and having a heat sheet coupled to the package substrate, the heat sheet being configured to conduct current between terminals of the package substrate; mounting a first magnetic shield to the package substrate, the first magnetic shield including a die mounting area facing the board side surface, the die mounting area being exposed from the package substrate and the heat sheet; mounting a semiconductor die having a Hall element on the die mounting area, the semiconductor die being flip-chip mounted and facing away from the board side surface of the package substrate; mounting a second magnetic shield mounted to the packaging substrate and the heat sheet, the second magnetic shield having a cantilever portion, the cantilever portion extending above the portion of the semiconductor die containing the Hall element, while the bonding pad on the semiconductor die remains exposed from the second magnetic shield; forming an electrical connection with a wire bond or a bond between the bonding pad of the semiconductor die and the lead on the packaging substrate; and covering the electrical connection, the semiconductor die and a portion of the packaging substrate, the first magnetic shield and the second magnetic shield with a molding compound, while a portion of the heat sheet is exposed from the molding compound, thereby forming a thermal pad for packaging the semiconductor device.

[0007] In another described example, an apparatus includes: a package substrate having a board side surface and an opposing top surface, and a heat sheet coupled to the package substrate, the heat sheet being configured to conduct current between terminals of the package substrate. A first magnetic shield is mounted to the top surface of the package substrate, the first magnetic shield including a die mounting area facing the board side surface, the die mounting area being in an opening exposed from the package substrate and the heat sheet. A semiconductor die having a Hall element is mounted to the die mounting area, the semiconductor die being flip-chip mounted and facing away from the board side surface of the package substrate. A second magnetic shield is mounted to the package substrate and the heat sheet, the second magnetic shield having a base portion and having a cantilever portion extending above a portion of the semiconductor die including the Hall element, while bonding pads on the semiconductor die remain exposed from the second magnetic shield. Electrical connections are formed by wire bonds or ribbon bonds between bonding pads of the semiconductor die and leads on the package substrate. A molding compound covers the electrical connectors, the semiconductor die, a portion of the package substrate, the first magnetic shield, and the second magnetic shield, while a portion of the heat sheet is exposed from the molding compound to form a thermal pad for a semiconductor device package.

[0008] In another described example, a Hall current sensor device includes: a lead frame having a first set of leads in a high voltage section and a second set of leads in a low voltage section electrically isolated from the high voltage section, the lead frame having a board side surface and an opposing top surface; a heat sheet coupled to the first set of leads of the high voltage section, the heat sheet being configured to conduct current between terminals formed by the first set of leads of the high voltage section; a first magnetic shield mounted to the top surface of the lead frame and including a die mounting area in an opening exposed from the lead frame and from the heat sheet; a semiconductor die having a Hall element mounted to the die mounting area, the semiconductor die being flip-chip mounted and facing away from the die the board side surface of the lead frame; a second magnetic shield mounted to the heat sheet, the second magnetic shield having a base portion and having a cantilever portion extending above the portion of the semiconductor die containing the Hall element, while a bonding pad on the semiconductor die remains exposed from the second magnetic shield; an electrical connector, which includes a wire bond or a ribbon bond between the bonding pad of the semiconductor die and the second set of leads on the low voltage section of the lead frame; a molding compound covering the electrical connector, the semiconductor die, a portion of the lead frame, the first magnetic shield and the second magnetic shield, while a portion of the heat sheet is exposed from the molding compound, thereby forming a thermal pad for semiconductor device packaging. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A-1B Semiconductor wafers and individual semiconductor dies are illustrated separately. Figure 1C The application of the Hall sensor for the arrangement is explained in a block diagram.

[0010] Figure 2 A semiconductor device package that may be used with the arrangement is illustrated in a projection view.

[0011] Figure 3 An arranged semiconductor device package is illustrated in cross-section.

[0012] Figure 4A-4AA 4B-4BB, 4C-4CC, 4D-4DDD, 4E-4EE, and 4F illustrate, in a series of plan and side views, selected steps for forming a semiconductor device package of an example arrangement.

[0013] Figure 5 An example semiconductor device package of the arrangement is illustrated in a projection view from the board side.

[0014] Figure 6 An example method for forming an arrangement is illustrated in a flow chart. DETAILED DESCRIPTION

[0015] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated.The figures are not necessarily drawn to scale.

[0016] Elements are described herein as being “coupled.” The term “coupled” encompasses directly connected elements and indirectly connected elements, as well as elements that are electrically connected even through coupled intervening elements or lines.

[0017] The term "semiconductor die" is used herein. A semiconductor die may be a discrete semiconductor device such as a bipolar transistor, several discrete devices such as a pair of power FET switches fabricated together on a single semiconductor die, or a semiconductor die may be an integrated circuit having multiple semiconductor devices such as multiple capacitors in an A / D converter. A semiconductor die may include passive devices such as resistors, inductors, filters, sensors, or active devices such as transistors. A semiconductor die may be an integrated circuit having hundreds or thousands of transistors coupled to form a functional circuit such as a microprocessor or memory device.

[0018] The term "semiconductor device package" is used herein. The semiconductor device package has at least one semiconductor die electrically coupled to a terminal, and has a package body that protects and covers the semiconductor die. In some arrangements, multiple semiconductor dies may be packaged together. For example, a power metal oxide semiconductor (MOS) field effect transistor (FET) semiconductor die and a logic semiconductor die (e.g., a gate driver die or a controller die) may be packaged together to form a single packaged electronic device. Additional components such as passive devices may be included in the packaged electronic device. The semiconductor die is mounted to a package substrate that provides conductive leads; a portion of the conductive leads forms a terminal for the packaged device. The semiconductor die may be mounted to a package substrate with the device side surface facing away from the substrate and the back side surface facing and mounted to a die pad of the package substrate. In a wire-bonded semiconductor device package, bonding wires couple the conductive leads of the package substrate to bonding pads on the semiconductor die. The semiconductor device package may have a package body formed by a thermosetting epoxy resin in a molding process or by using an epoxy resin, a plastic, or a resin that is liquid at room temperature and subsequently cured. The package body may provide a hermetic package for the packaged device. The package body may be formed in a mold using an encapsulation process, however, portions of the leads of the substrate are not covered during encapsulation, these exposed lead portions providing terminals for the semiconductor device package.

[0019] The term "package substrate" is used herein. A package substrate is a substrate arranged to receive a semiconductor die and to support the semiconductor die in a completed semiconductor device package. A package substrate that can be used with the arrangement includes a conductive lead frame, which can be formed of copper, aluminum, stainless steel, steel, and alloys (e.g., alloy 42 and copper alloy). The lead frame can be provided in a strip or array. The conductive lead frame can be provided as a panel with a strip or array of unit device portions in rows and columns. The semiconductor die can be placed on the corresponding unit device portion within the strip or array. The semiconductor die can be placed on the die mounting area for each packaged device, and a die attach or die adhesive can be used to mount the semiconductor die to the die mounting area. In a wire bonding package, bonding wires can couple bonding pads on the semiconductor die to leads of the lead frame. The lead frame can have a plated portion in an area designated for wire bonding, for example, a silver plating can be used. After the bond wires are in place, a portion of the package substrate, the semiconductor die, and at least a portion of the die pad may be covered with a protective material such as a molding compound.

[0020] In an example arrangement, a lead frame having isolated lead portions may be used. The lead frame has a high voltage portion having a first set of leads configured for coupling to a high voltage signal or supply (e.g., at a voltage greater than 20 volts). The lead frame has a low voltage portion having a second set of leads configured for coupling to a low voltage signal (e.g., a logic level signal at a voltage less than 20 volts). The high voltage portion and the low voltage portion are electrically isolated from each other.

[0021] When encapsulating semiconductor devices, a molding compound may be used to partially cover the encapsulation substrate, the semiconductor die, and the electrical connections from the semiconductor die to the encapsulation substrate. This may be referred to as an "encapsulation" process, but some parts of the encapsulation substrate are not covered in the molding compound during encapsulation, for example, the terminals and leads are exposed from the molding compound. Encapsulation is typically a compression molding process, in which thermosetting molding compounds such as epoxy resins may be used. Room temperature solid or powder molding compounds may be heated to a liquid state, and then molding may be performed by pressing the liquid molding compound into a mold. Transfer molding may be used. Unit molds formed to surround individual devices may be used, or block molding may be used to simultaneously form packages of several devices from the molding compound. The device may be arranged in an array of several, hundreds, or even thousands of devices molded together in rows and columns. After molding, in a sawing operation, individual packaged devices are cut off from each other by cutting through the molding compound and the encapsulation substrate in the sawing lanes formed between the devices. Portions of the encapsulation substrate leads are exposed from the molding compound encapsulation to form the terminals of the packaged semiconductor device.

[0022] The term "scribe lane" is used herein. A scribe lane is a portion of a semiconductor wafer between semiconductor dies. The term "slice lane" is sometimes used in the relevant literature. Once semiconductor processing is completed and the semiconductor device is completed, the semiconductor device is separated into individual semiconductor dies by cutting the semiconductor wafer along the scribe lane. The separated dies can then be removed and processed individually for further processing. This process of removing dies from the wafer is called "singling" or sometimes "slicing". The scribe lanes are arranged on four sides of the semiconductor die, and when the dies are singulated from each other, rectangular semiconductor dies are formed.

[0023] The term "saw lanes" is used herein. Saw lanes are areas between molded electronic devices that are used to allow a saw, such as a mechanical blade, laser, or other cutting tool, to pass between the molded electronic devices to separate the devices from one another. This process is another form of singulation. When the molded electronic devices are provided in the form of strips and one device is adjacent to another device along the strip, the saw lanes are parallel and perpendicular to the length of the strip. When the molded electronic devices are provided in the form of an array of devices in rows and columns, the saw lanes include two sets of parallel saw lanes that are perpendicular to each other, and thus the saw will traverse the molded electronic devices in two different directions to cut the packaged electronic devices in the array apart from each other.

[0024] The term "quad flat no-lead" or "QFN" is used herein for a type of electronic device package. A QFN package has conductive leads that extend coextensively with the sides of a molded package body, and in a quad package, the leads are located on four sides. Alternative flat no-lead packages may have leads on both sides or only on one side. These may be referred to as "small outline no-lead" or "SON" packages. Leadless packaged electronic devices may be surface mounted to a board. Leaded packages may be used with an arrangement in which the leads extend away from the package body and are shaped to form a portion for soldering to a board. A dual in-line package (DIP) may be used with the arrangement. A small outline package (SOP) may be used with the arrangement. A small outline no-lead (SON) package may be used, and a small outline transistor (SOT) package is a leaded package that may be used with the arrangement. The leads for leaded packages are arranged to be mounted to a board for solder. The leads may be shaped to extend toward the board and form a mounting surface. Gull-wing leads, J-shaped leads, and other lead shapes may be used. A small outline integrated circuit (SOIC) package with leads may be used with the arrangement. A wide SOIC package may be used with the arrangement. A dual in-line package (DIP) may be used. In a DIP, the ends of the leads in a pin-shaped portion may be inserted into conductive holes formed in a circuit board, and solder is used to couple the leads to the conductors within the holes.

[0025] The term "magnetic material" is used herein. Magnetic materials that can be used for the arrangement include iron oxide Fe2O3, and available examples include nickel ferrite (NiFe), nickel zinc ferrite (NiZnFe) and manganese zinc ferrite (MnZnFe). Ferrites are ferrimagnetic and become magnetized in the presence of a magnetic field. The term "magnetic shield" is used herein. In the arrangement, a magnetic shield is formed by integrating a magnetic layer of soft ferrite material above or below a semiconductor die of one or more Hall sensors contained in a semiconductor device package. The integrated magnetic shield prevents stray magnetic fields from affecting the Hall element sensors on the semiconductor die. The current flowing through the lead frame in the semiconductor device package generates a local magnetic field, and the Hall sensor uses the local magnetic field to measure the current. The integrated magnetic shield prevents external magnetic fields from introducing unwanted errors into the current measurement.

[0026] The term "cantilever portion" is used herein. In an example arrangement, a magnetic shield within a semiconductor device package has a cantilever portion extending from a substrate in a horizontal direction, the cantilever portion being unsupported along its length and extending over a Hall element on a semiconductor die, while a portion of the semiconductor die is not covered by the cantilever portion of the magnetic shield.

[0027] The term "heat sheet" is used herein. A heat sheet is a conductive material that conducts heat. In the described arrangement, the heat sheet is used to carry a senseable current. The heat sheet is mounted to and electrically coupled to the high voltage portion of the lead frame, and forms part of the current path between one or more input terminals and one or more output terminals, the output terminals being configured to couple to the high voltage at the input terminals and carry current. The heat sheet in the described arrangement may be a "C" shaped conductor in plan view. The heat sheet carries current to a location within the semiconductor package near the semiconductor die that includes the Hall element. The Hall element operates by sensing the magnetic field generated by the current flowing through the heat sheet. In the example arrangement, a copper heat sheet that is thicker than the lead frame is used, and the copper heat sheet has a board side surface that is exposed from the molding compound body of the semiconductor device package for transferring heat from the semiconductor device package.

[0028] Figure 1A-1B Steps for forming a semiconductor die, such as for use with an arrangement for wire bonding, are described. Figure 1A, a semiconductor wafer 101 is shown having an array of semiconductor die 105 arranged in rows and columns. The semiconductor die 105 are formed in a semiconductor manufacturing facility using manufacturing processes including ion implantation for carrier doping, annealing, oxidation, dielectric and conductor deposition, photolithography, patterning, etching, chemical mechanical polishing (CMP), plating, and other processes for manufacturing semiconductor devices. Devices are formed on the device side surfaces of the semiconductor die. Slice streets 103 and 104 that are perpendicular to each other and run in parallel groups across the semiconductor wafer 101 separate the rows and columns of the completed semiconductor die 105 and provide areas for segmenting the wafer to separate the semiconductor die 105 from each other.

[0029] Figure 1B A single semiconductor die 105 is illustrated having a bonding pad 102, which is a conductive pad electrically coupled to a device (not shown for simplicity) formed in the semiconductor die 105. The semiconductor die 105 is separated from the semiconductor wafer 101 by wafer singulation or using scribe streets 103, 104 (see FIG. 1 ). Figure 1A ) from each other. Wafer singulation can be accomplished by mechanical sawing or by laser cutting along scribe lines. Figure 1B The semiconductor die 105 shown in FIG. 1 includes a Hall element (not shown) or more than one Hall element. In an example arrangement, the Hall element is configured as a current sensor.

[0030] Figure 1C 1 is a circuit block diagram of an example semiconductor device 100 that may be used in an arrangement. The example semiconductor device 100 is a Hall current sensor. The semiconductor device 100 includes an isolation barrier 112 that uses electrical isolation to isolate high voltage signals (signals at voltages of 20V to 100 volts or more) from a semiconductor die 105 within a package and to isolate the high voltage signals ( Figure 1C IN+, IN-) and a low voltage signal (e.g., a logic level voltage signal between 0.5 and 20 volts, for example, coupled to or output by the semiconductor die 105) . Figure 1C The signal in VOUT) is electrically isolated.

[0031] refer to Figure 1CIn the device 100, in an example application, the input IN+ may be coupled to a first node and may receive a signal carrying a current labeled "I", for example, the node at IN+ may be coupled to a high voltage signal or a high voltage supply, and the output IN- may be coupled to a second node, and the output IN- outputs a current I. The semiconductor die 105 within the semiconductor device package 100 includes at least one Hall element 108. The circuit system required to control and monitor the Hall element 108 is provided, and the circuit system includes a Hall element bias circuit 107, a temperature compensation and offset cancellation circuit 113, a precision amplifier 109, and an output amplifier 111. Other circuits that increase device reliability and performance (e.g., overvoltage, overcurrent) and a temperature sensor with corresponding control and output signals may be provided in the semiconductor die 105.

[0032] In operation, the output amplifier 111 drives an output VOUT that corresponds to the magnitude of the current I or changes voltage as the current I changes. The magnetic field generated by the current I is sensed by the Hall element 108, and the voltage VOUT corresponding to the magnitude of the magnetic field is output by the semiconductor die 105. In the system, a calibration scheme can be used to determine the value of the current I based on the voltage appearing at the output VOUT. An isolation barrier 112 is shown, which is formed by using a packaging substrate having an isolation portion to mount the semiconductor die 105 within the magnetic field occurring due to the current I, while keeping the semiconductor die 105 electrically isolated from the high voltage signals at the input IN+ and output IN- that supply the current I. The semiconductor die 105 can be made of a material that cannot withstand the high voltage applied at the terminal IN+, and can be made of silicon, and can operate at a lower voltage, such as 10 volts or less. This aspect of the arrangement reduces the cost of the Hall current sensor and allows the semiconductor die 105 to be formed using conventional semiconductor processing. Although in Figure 1C In the illustrated example of , a single Hall element 108 is shown, but in an alternative arrangement of differential sensing using an amplifier similar to precision amplifier 109, two Hall elements spaced apart may be used. This alternative arrangement allows common noise reduction to be achieved by removing common noise sensed by the two Hall elements from the output signal using differential sensing. In one example, common noise suppression is achieved by differential sensing to remove noise appearing at the two Hall elements.

[0033] Figure 2 A semiconductor device package 200 that may be used in an example arrangement is illustrated in a projection view. The semiconductor device package has a molding compound 223 forming the body of the device package, and terminals 210. Figure 2In the embodiment, a sixteen lead width small outline integrated circuit (SOIC) package 200 is shown. Using a standard pin semiconductor device package for a Hall element sensor with the described arrangement reduces the cost for mounting the device to a system board or module (compared to the custom packages used in some previous Hall sensor solutions). In the described arrangement, a standard footprint semiconductor device package can be used. Although Figure 2 The example SOIC package 200 shown in FIG. 1 includes terminals 210 that are external leads configured for surface mounting to a board using surface mount technology (SMT), but leadless packages such as quad flat no-lead (QFN) packages may also be used. Other standard semiconductor package footprints such as dual in-line package (DIP) packages may be used. Due to the use of an integral heat sheet, as explained below, the semiconductor device package of the example arrangement may be thicker than a standard semiconductor device package, but the use of a standard footprint for the package enables assembly using standard tools and equipment.

[0034] Figure 3 An example semiconductor device package 300 incorporating an arrangement is illustrated in cross-section. Figure 3 In the embodiment of the present invention, the lead frame 307 is used with terminals 310 extending outside the molding compound 323 forming the package body. The lead frame 307 is an isolated lead frame including a high voltage section 3071 and a low voltage section 3072. The internal heat sheet 321 is mounted to the board side of the lead frame 307 in the high voltage section 3071 and is formed of a thermal conductor and an electrical conductor such as copper or a copper alloy. The heat sheet 321 is electrically coupled to the high voltage section 3071 of the lead frame 307 and forms a low resistance current path to carry the current I from the input portion to the output portion of the high voltage section 3071 of the lead frame 307 (see FIG. 1 ). Figure 1C The heat sheet 321 is a heat sheet 321 formed to carry the current I to a position near the semiconductor die 305. From a plan view, the heat sheet 321 can be a C, U, V, D or similar shape, wherein the portion for carrying the current I is close to the semiconductor die 305 in the semiconductor device package 300. For the high voltage section 3071 of the lead frame 307, the heat sheet 321 forms a heat sink 321 extending from the input (see FIG. Figure 1C IN+ in) to the output (see Figure 1C The thermal pad 322 may be configured to provide a serial path from the semiconductor device package 300 to the board or module thermal path to conduct the current for the signal to be monitored, which may be a high current greater than one ampere and up to greater than 100 amperes. The thermal pad 321 may also have an external thermal pad 322 exposed from the molding compound 323. The thermal pad 322 is configured to transfer heat from the semiconductor device package 300 to the board or module thermal path to distribute thermal energy from the semiconductor device package 300 during operation.

[0035] The semiconductor device package 300 includes a semiconductor die 305 mounted in a “flip chip” orientation with the bond pads and device side surface facing the board side 326 of the semiconductor device package 300. The semiconductor die 305 includes a Hall element (not visible) or more than one Hall element placed near a heat slug 321 so that a magnetic field corresponding to a current I flowing through the heat slug 321 can be sensed by the Hall element within the semi-custom die 305. However, the semiconductor die is electrically isolated from the heat slug 321 and the high voltage section of the lead frame 307.

[0036] An electrical insulating layer 317 such as a polyimide or a laminate such as a bismaleimide triazine (BT) resin laminate or a glass reinforced epoxy (FR4) laminate is used to provide electrical isolation between the backside surface of the semiconductor die 305 and the first magnetic shield 313. The first magnetic shield 313 faces the top side 328 of the semiconductor device package 300 and provides a die mounting area spaced apart from the heat sheet 321 to carry the semiconductor die 305. Electrical connections such as bond wires 325 or ribbon bonds connect bonding pads (not shown, but see e.g., Figure 1B The second magnetic shield 315 has a portion that extends in a cantilever manner to cover the Hall element (not visible) within the semiconductor die 305, so that the Hall element has magnetic shields 315, 313 above the device-side surface of the semiconductor die 305 and the back-side surface of the semiconductor die 305 to prevent stray magnetic fields from affecting the Hall element within the semiconductor die 305 and introducing errors into the measurement made by the current sensor.

[0037] Figure 4A-4AA 4B-4BB, 4C-4CC, 4D-4DDD, 4E-4EE and 4F illustrate selected steps for forming an arrangement in a series of plan and side views. Figure 4A , a plan view of a portion 330 of a lead frame 307 illustrates an example heat sheet 321 mounted on a high voltage section 3071 of the lead frame 307. Leads 331 are shown forming a low voltage section 3072 of the lead frame 307. It should be noted that the lead frame 307 is Figure 4A 3071, and the heat slug 321 is rotated so that the heat slug 321 faces upward and above the lead frame 307, which orientation is used in the assembly steps as will be further described below. As previously mentioned, although the heat slug 321 has a "C" shape in the illustrated example, other shapes can be used for the heat slug 321. The heat slug 321 provides a low resistance path to carry current from the lead frame 307 in the high voltage section 3071 through the heat slug 321. The lead frame portion 330 is the portion of the lead frame 307 that is within the boundaries of the package body, and the external leads (see, e.g. Figure 3310 in the figure) is not shown in this part 330. In the example assembly process, the lead frame 307 is arranged in a strip, grid or array with multiple unit lead frames, which are temporarily connected together by tie bars formed by the lead frame material and support the leads during assembly. Multiple packaged semiconductor devices are formed at the same time to increase processing volume and reduce costs. The completed packaged devices are then cut to form individual semiconductor device packages.

[0038] Figure 4AA To correspond to Figure 4A , and shows a lead frame 307 with a heat slug 321 mounted thereto. The heat slug 321 and lead frame 307 may be provided as an assembly by a lead frame supplier, alternatively, the heat slug 321 may be mounted to the lead frame 307 in a first part of the assembly process. The heat slug 321 is electrically coupled to a high voltage section 3071 of the lead frame 307 and forms a low resistance current conduction path between one or more input terminals and one or more output terminals. A welding or brazing operation may be used to mount the heat slug 321 to the lead frame 307, alternatively, solder may be used.

[0039] Figure 4B Shown as seen from the top side after additional processing steps Figure 4A-4AA A plan view of the lead frame 307 and the heat sink 321. Figure 4B In the example arrangement, the first magnetic shield 313 is mounted to the top or upper side of the heat sheet 321. In this example arrangement, the first magnetic shield has an "I" shape from a plan view and is formed of a magnetic material. Example magnetic materials that can be used for the arrangement include nickel ferrite NiFe, nickel zinc ferrite NiZnFe, and manganese zinc ferrite MnZnFe. The first magnetic shield 313 is mounted to the heat sheet 321 so that a portion of the first magnetic shield 313 extends into the opening between the heat sheet 321 and the low voltage section 3072 of the lead frame 307, and a die mounting area is provided in the opening spaced apart from the heat sheet 321. In the example process, a die attach film (DAF) (not shown) is used to mount the first magnetic shield to the heat sheet 321, and alternatives include die attach materials that are dispensed and cured as liquids, pastes, or gels. The die attach material is insulating to isolate the first magnetic shield from other elements.

[0040] Figure 4BB Explanation in side view Figure 4B The first magnetic shield 313, the heat sheet 321 and the lead frame 307, wherein the lead frame assembly is relative to Figure 4BThe heat sheet 321 is rotated so the top side of the heat sheet 321 now faces downward and the first magnetic shield 313 is shown at the bottom of the element. This orientation is used to show the die mounting area 314 of the first magnetic shield 313, which is on the board side of the first magnetic shield 313 and is exposed from the low voltage section 3072 of the lead frame 307 and from the heat sheet 321. When the semiconductor device package is mounted to a board, the die mounting area 314 will face the board and the semiconductor die mounted to the first magnetic shield 313 will be oriented facing downward (toward the board surface of the package) or in a flip chip orientation, as described below.

[0041] Figure 4C Another plan view shows the Figure 4B Components. Figure 4C , the lead frame portion 330 is shown viewed from the board side, such that the first magnetic shield 313 is shown above the heat sheet 321, and the die mounting area 314 is shown facing the viewer. A semiconductor die 305 including at least one Hall element 308 is shown mounted on the die mounting area 314 of the first magnetic shield 313. The semiconductor die 305 is formed by a polyimide layer (in Figure 4C Invisible, see Figure 4CC The semiconductor die 305 is spaced apart and electrically isolated from the first magnetic shield 313 by an insulating material such as BT resin or FR4 (corresponding side view in FIG. 1 ) or an insulating substrate material such as BT resin or FR4. The semiconductor die 305 can be mounted using a die attach film (DAF) or die attach material that is dispensed and subsequently cured.

[0042] Figure 4CC for Figure 4C A side view of the components shown in . Figure 4CC , the elements are shown with the plate side of the lead frame 307 facing upward so that the heat sheet 321 is shown above the lead frame 307. The semiconductor die 305 with the Hall element 308 is shown on the die mounting area 314 of the first magnetic shield 313. The semiconductor die is spaced apart from the leads 331 of the low voltage section 3072 and from the heat sheet 321 in the opening between these elements. An isolation layer 317, which can be, for example, a polyimide layer or BT resin or FR4 laminate, is shown between the backside surface of the semiconductor die 305 and the first magnetic shield 313. Thus, the semiconductor die is electrically isolated from the first magnetic shield 313. The Hall element is adjacent to a portion of the heat sheet 321 so that, in operation, current flowing through the heat sheet 321 generates a magnetic field that can be sensed by the Hall element 308.

[0043] Figure 4D The plan view from the board side of the lead frame 307 and heat sink 321 is shown after additional processing steps. Figure 4C-4CC Components. Figure 4D, the second magnetic shield 315 is shown mounted to the first magnetic shield 313 and extending over the Hall element 308 on the semiconductor die 305 mounted to the die mounting area 314 of the first magnetic shield 313. The second magnetic shield 315 does not cover the entire device side surface of the semiconductor die 305, which enables a wire bonding operation as shown below to connect the semiconductor die 305 to the leads 331 of the low voltage section 3072 of the lead frame 307. The second magnetic shield 315 can be mounted using a DAF or die attach material. The second magnetic shield 315 can be mounted to the first magnetic shield, but the semiconductor die 305 is not in electrical or physical contact with the second magnetic shield 315. However, the cantilever portion of the second magnetic shield 315 extends over the device side of the semiconductor die 305 and covers the Hall element 308 within the semiconductor die 305.

[0044] Figure 4DD Corresponding to Figure 4D Side view of Figure 4D The element comprises a second magnetic shield 315, in Figure 4DD 305, the element is oriented with the plate side of the lead frame 307 facing upward. The second magnetic shield 315 has a base portion 318 and a cantilever portion 316, which forms an "L" shape in a cross-sectional view. The base portion 318 of the second magnetic shield 315 is mounted on the first magnetic shield 313, for example, using DAF or a die attach material, and the cantilever portion 316 of the second magnetic shield 315 extends over a portion of the heat sheet 321 and over the Hall element 308 on the semiconductor die 305. The first magnetic shield 313 and the second magnetic shield 315 are arranged above and below the semiconductor die 305 and provide magnetic shielding for the Hall element 308.

[0045] Figure 4DDD repeat Figure 4D However, curve 342 is added, which illustrates the path of the current flowing through the heat slug 321 with a dashed arrow. The current comes from the input terminal labeled “I INPUT ” signal, the input terminal is coupled to the heat sheet 321 and the output terminal of the high voltage section 3071 of the lead frame 307 to form a current path for the current 342, which flows to the output terminal as marked “I OUTPUT In operation, current 342 will flow through the heat sheet 321 at a location near the Hall element 308 on the semiconductor die 305, and the Hall element will sense a magnetic field caused by and proportional to the current 342. The first magnetic shield 313 and the second magnetic shield 315 are positioned above and below the semiconductor die 305 and shield the Hall element 308 from stray magnetic fields, thereby reducing errors.

[0046] Figure 4E A plan view showing the Figure 4D Components. Figure 4E , the view is from the board side of the lead frame 307 at the device side surface of the semiconductor die 305. Figure 4E , semiconductor die 305 is shown with electrical connections, such as bond wires 325 formed to leads 331 of low voltage sections 3072 of lead frame 307. The electrical connections can be formed using a ball bonding process (e.g., a ball-needle wire bonding tool). Alternatively, a ribbon bond can be used to couple semiconductor die 305 to leads 331.

[0047] In the example ball needle wire bonding process, a capillary with a bonding wire extending through an opening is used. A flame or an electron arc can be used to form a ball at the end of the extended bonding wire. The capillary uses mechanical force and acoustic vibration to push the molten ball onto the conductive bonding pad on the semiconductor die, and a ball bond is formed between the bonding wire and the bonding pad. When the capillary is removed from the bonding pad, the bonding wire is allowed to extend from the ball bond in an arc shape. The capillary moves over the lead and forms a pin bond by pushing the bonding wire onto the lead using mechanical force and acoustic vibration energy. The capillary moves a short distance from the pin bond and cuts the bonding wire, leaving a small tail. This ball needle operation is automated and fast, and many wire bonds can be formed in a few seconds, allowing for fast processing volume. Copper, gold, silver, and aluminum bonding wires can be used. In the example process, copper bonding wires are used. When copper is used, an oxygen-deficient atmosphere can be used in the wire bonding tool to reduce oxidation of the copper bonding wire.

[0048] Figure 4EE Explanation in side view Figure 4E Components. Figure 4E , the element is shown oriented with the plate side of the lead frame 307 facing upward. Bond wires 325 are shown between bonding pads (not visible) on the semiconductor die 305 and leads 331 of the low voltage section 3072 of the lead frame 307. The second magnetic shield 315 is shown with the base 318 and cantilever portion 316 extending above the device side surface of the semiconductor die 305 but not covering the device side surface to allow the wire bonder to reach the bonding pads for the wire bonding process. The Hall element 308 has the second magnetic shield 315 above it and the first magnetic shield 313 below it (when the element is in Figure 4EE When oriented in the neutral direction, i.e. with the plate side facing upwards), magnetic shielding from stray magnetic fields is provided.

[0049] Figure 4F Illustrated in side view, after the molding process Figure 4E The components of the package body are formed from the molding compound 323. The molding compound 323 is shown in a transparent view to expose other components. Figure 4EThe portion 330 of the lead frame 307 is shown with the lead frame 307 and other elements oriented such that the board side of the lead frame 307 faces upward. The molding compound 323 is shown formed over the semiconductor die 305, the first magnetic shield 313, the second magnetic shield 315, portions of the leads 331 of the low voltage section 3072 of the lead frame 307, and portions of the high voltage section 3071 of the lead frame 307, and covers a majority of the heat sheet 321, while the board side surface of the heat sheet 321 is exposed from the molding compound 323 to form the thermal pad 322. In an example transfer molding process, as shown in FIG. Figure 4E The lead frame 303 shown in is placed in the mold sleeve after wire bonding. Electronic molding compound (EMC) can be used as molding compound 323, which can be molded from a solid ice ball shaped block or solid powder at room temperature (which is placed in a molding tool and heated to a liquid state). In one example, an epoxy resin molding compound with a solid filler is used, and the filler increases the strength and heat dissipation of the molding compound. After the molding compound becomes liquid, a mechanical plunger is used to force the molding compound through a slide into the mold sleeve, and the molding compound surrounds the lead frame 307 and other components, wherein portions of the leads extend from the molding compound to form terminals, and thermal pads are exposed from the molding compound. The molding compound is cured and becomes solid, and the molding compound 323 is a thermosetting material and will remain solid after molding to protect the components of the semiconductor device package.

[0050] Figure 5 The completed semiconductor device package 300 is illustrated in a projection view as viewed from the board side. Figure 5 3, semiconductor die 305 is shown mounted to a first magnetic shield with a Hall element 308 placed adjacent a portion of a heat sheet 321. A low voltage section 3072 of a lead frame 307 is shown with leads 331 extending from a molding compound 323 to form a terminal 310. A high voltage section 3071 of the lead frame 308 is shown with leads extending from the molding compound 323 to form terminals 332, 334 for a high voltage signal at terminal 332, (IN+) (and at terminal 334, (IN-)). The heat sheet 321 is shown with a second magnetic shield 315 mounted so that a cantilevered portion of the second magnetic shield extends over the Hall element 308 of the semiconductor die 305. Wire bonds 325 are shown between the semiconductor die 305 and the leads 331 of the lead frame 307. The high voltage section 3071 of the lead frame is connected to and electrically coupled to the heat slug 321 to provide a current path through the heat slug 321 from the IN+ terminal 332 to the IN- terminal 334 (see Figure 4DDD 342 in FIG. 342). The semiconductor die 305 is positioned between the first magnetic shield 313 and the second magnetic shield 315 so that the Hall element 308 has magnetic shields above and below it.

[0051] Figure 5 and Figure 3The example semiconductor device package 300 shown in FIG. 1 is a wide SOIC package with sixteen terminals, however, the first magnetic shield and the second magnetic shield can be used with the package substrate of the Hall sensor semiconductor device and other package types (e.g., leadless packages and packages of various widths) to form a Hall current sensor in a standard package footprint. The use of a heat sheet in the arrangement can cause the finished semiconductor device package 300 to have a thickness greater than the standard package thickness, however, the board layout required to mount the package can still be in the standard package footprint, thereby reducing board design costs and simplifying assembly.

[0052] Figure 6 The steps for forming an arranged semiconductor device package are illustrated in a flow chart.

[0053] exist Figure 6 In step 601, the method begins by forming a package substrate having a board side surface and an opposing top surface, and having a heat sheet coupled to the package substrate, the heat sheet being configured to conduct current between terminals of the package substrate. (See, e.g., Figure 4A and Figure 4AA , heat sheet 321 and package substrate, lead frame 307. )

[0054] At step 603, the method continues by mounting a first magnetic shield to the package substrate, the first magnetic shield including a die attach area facing the board side surface, the die attach area being exposed from the package substrate and the heat sheet. (See e.g. Figure 4B and Figure 4BB , having a first magnetic shield 313 and a lead frame 307 mounted to a package substrate).

[0055] At step 605, the method continues by mounting a semiconductor die having a Hall element on the die attach area, the semiconductor die being flip-chip mounted and facing away from the board side surface of the package substrate. (See, e.g. Figure 4C-4CC The semiconductor bare chip 305 and the Hall element 308 in FIG.

[0056] At step 607, the method continues by mounting a second magnetic shield to the package substrate and the heat sink, the second magnetic shield having a cantilevered portion extending over the portion of the semiconductor die containing the Hall element, while the bond pads on the semiconductor die remain exposed from the second magnetic shield. (See e.g. Figure 4D-4DDD , having a second magnetic shield 315 mounted on the lead frame 307).

[0057] At step 609, the method continues by forming wire bonds or tape bonds between bonding pads of the semiconductor die and leads on the package substrate. (See e.g. Figure 4E-4EE , with wire bonds 325).

[0058] At step 611, the method ends by covering the electrical connector, at least one semiconductor die, and a portion of the package substrate, the first magnetic shield, and the second magnetic shield with a molding compound, while a portion of the heat slug remains exposed from the molding compound, thereby forming a thermal pad for a semiconductor device package. (See, e.g., Figure 4F Molding material 323 in.

[0059] Use of the arrangement provides a packaged semiconductor device including one or more Hall sensors with an integral magnetic shield. The packaged semiconductor device is a current sensor configured for use in high power or high current applications (e.g., currents greater than one ampere and up to 100 amperes or more). The arrangement is formed using existing methods, materials, and tools for manufacturing the device and is cost effective. The magnetic shield is formed from readily available magnetic materials. Use of the arrangement provides an economical and robust integrated Hall current sensor device for high power applications by providing a magnetic shield integrated into a semiconductor package and positioned above a semiconductor device die using materials compatible with typical semiconductor packaging processes and methods. The packaged semiconductor device can be used with a variety of semiconductor package types, including leaded, SOIC, and leadless packages including QFN and SON packages.

[0060] Modifications to the described arrangements are possible, and other alternative arrangements are possible, within the scope of the claims.

Claims

1. A method for forming a semiconductor device package, comprising: forming a package substrate having a board side surface and an opposing top surface and having a heat slug coupled to the package substrate, the heat slug configured to conduct current between terminals of the package substrate; mounting a first magnetic shield to the package substrate, the first magnetic shield including a die mounting area facing the board side surface, the die mounting area being exposed from the package substrate and the heat sheet; Mounting a semiconductor die having a Hall element on the die mounting area, the semiconductor die being flip-chip mounted and facing away from the board side surface of the package substrate; mounting a second magnetic shield to the package substrate and the heat sheet, the second magnetic shield having a cantilevered portion extending over a portion of the semiconductor die containing the Hall element while bond pads on the semiconductor die remain exposed from the second magnetic shield; forming an electrical connection with a wire bond or a tape bond between the bonding pad of the semiconductor die and a lead on the package substrate; as well as The electrical connectors, the semiconductor die, and portions of the package substrate, the first magnetic shield, and the second magnetic shield are covered with a molding compound with a portion of the heat sheet exposed from the molding compound to form a thermal pad for the semiconductor device package. 2 . The method of claim 1 , wherein mounting the semiconductor die having the Hall element on the die attach area further comprises forming an insulating layer on the die attach area before mounting the semiconductor device die. The method according to claim 2 , wherein the insulating layer is polyimide. 4 . The method according to claim 2 , wherein the insulating layer is a bismaleimide triazine BT resin laminate or a glass reinforced epoxy resin (FR4) laminate. The method of claim 1 , wherein the first magnetic shield comprises a magnetic material. 6 . The method according to claim 5 , wherein the magnetic material is nickel ferrite (NiFe), nickel zinc ferrite (NiZnFe), or manganese zinc ferrite (MnZnFe).

7. The method of claim 1, wherein the first magnetic shield has an "I" shape in a plan view.

8. The method of claim 1, wherein the second magnetic shield has a rectangular base and the cantilevered portion extends from the rectangular base.

9. The method of claim 8, wherein the second magnetic shield has an "L" shape in a cross-sectional view.

10. The method of claim 1, wherein the heat sheet is copper or a copper alloy.

11. The method of claim 1 , wherein the packaging substrate is an isolated lead frame having a high voltage section and a low voltage section, the high voltage section having a first set of terminals coupled to the heat sheet, the low voltage section having a second set of terminals spaced apart and electrically isolated from the high voltage section.

12. The method of claim 11, wherein the isolated lead frame is copper, aluminum, stainless steel, steel, or alloys thereof.

13. The method of claim 12, wherein the isolated lead frame is copper or a copper alloy.

14. An apparatus comprising: a package substrate having a board side surface and an opposing top surface, and a heat sheet coupled to the package substrate, the heat sheet configured to conduct current between terminals of the package substrate; a first magnetic shield mounted to the top surface of the packaging substrate, the first magnetic shield including a die mounting area facing the board side surface, the die mounting area being in an opening exposed from the packaging substrate and the heat sheet; a semiconductor die having a Hall element mounted to the die mounting area, the semiconductor die being flip-chip mounted and facing away from the board-side surface of the package substrate; a second magnetic shield mounted to the package substrate and the heat sheet, the second magnetic shield having a base portion and having a cantilevered portion extending over a portion of the semiconductor die containing the Hall element, while bond pads on the semiconductor die remain exposed from the second magnetic shield; wire bonds or electrical connections with bonds between bonding pads of the semiconductor die and leads on the package substrate; as well as A molding compound covers the electrical connector, the semiconductor die, a portion of the package substrate, the first magnetic shield, and the second magnetic shield, with a portion of the heat sheet exposed from the molding compound to form a thermal pad for a semiconductor device package.

15. The apparatus of claim 14, wherein the first magnetic shield and the second magnetic shield comprise a magnetic material.

16. The apparatus of claim 15, wherein the magnetic material comprises nickel ferrite (NiFe), nickel zinc ferrite (NiZnFe), or manganese zinc ferrite (MnZnFe).

17. The apparatus of claim 14, wherein the package substrate comprises a lead frame having a first set of leads in a high voltage section coupled to the heat slug, and a second set of leads in a low voltage section coupled to the semiconductor die through the electrical connections.

18. The apparatus of claim 17, wherein the first set of leads of the high voltage section of the lead frame and the heat sheet are configured to carry current to a portion of the heat sheet proximate a Hall sensor on the semiconductor die.

19. A Hall current sensor device, comprising: a lead frame having a first set of leads in a high voltage section and a second set of leads in a low voltage section electrically isolated from the high voltage section, the lead frame having a board side surface and an opposing top surface; a heat sheet coupled to the first set of leads of the high voltage section, the heat sheet configured to conduct current between terminals formed by the first set of leads of the high voltage section; a first magnetic shield mounted to the top surface of the lead frame and including a die mounting area in an opening exposed from the lead frame and from the heat sheet; a semiconductor die having a Hall element mounted to the die mounting area, the semiconductor die being flip-chip mounted and facing away from the board side surface of the lead frame; a second magnetic shield mounted to the heat sheet, the second magnetic shield having a base portion and having a cantilevered portion extending over a portion of the semiconductor die containing the Hall element, while bond pads on the semiconductor die remain exposed from the second magnetic shield; an electrical connection comprising wire bonds or ribbon bonds between the bond pads of the semiconductor die and the second set of leads on the low voltage section of the lead frame; A molding compound covers the electrical connector, the semiconductor die, a portion of the lead frame, the first magnetic shield, and the second magnetic shield, with a portion of the heat sheet exposed from the molding compound to form a thermal pad for a semiconductor device package. 20 . The Hall current sensor device of claim 19 , wherein the first magnetic shield and the second magnetic shield comprise nickel ferrite (NiFe), nickel zinc ferrite (NiZnFe), or manganese zinc ferrite (MnZnFe).

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